Data Sheet

Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MC9S08GW64
Rev. 3, 1/2011
MC9S08GW64 Series
MC9S08GW64
Covers: MC9S08GW64 and
MC9S08GW32
8-Bit HCS08 Central Processor Unit (CPU)
– New version of S08 core with same performace as traditional S08 and
lower power
– Up to 20 MHz CPU at 3.6 V to 2.15 V and up to 10 MHz CPU at 3.6 V
to 1.8 V, across temperature range of –40 C to 85 C
– HC08 instruction set with added BGND instruction
– Support for up to 48 interrupt/reset sources
On-Chip Memory
– Flash read/program/erase over full operating voltage and temperature
– Random-access memory (RAM)
– Security circuitry to prevent unauthorized access to RAM and flash
contents
Power-Saving Modes
– Two low power stop modes and reduced power wait mode
– Low power run and wait modes allow peripherals to run while voltage
regulator is in standby
– Peripheral clock gating register can disable clocks to unused modules,
thereby reducing currents
– Very low power external oscillator that can be used in stop2 or stop3
modes to provide accurate clock source to real time counter
– 6 s typical wakeup time from stop3 mode
Clock Source Options
– Oscillator (XOSC1) — Loop-control Pierce oscillator; Crystal or
ceramic resonator of 32.768 kHz; Clock source for iRTC or ICS
– Oscillator (XOSC2) — Loop-control Pierce oscillator; Crystal or
ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz;
optional clock source for ICS
– Internal Clock Source (ICS) — Internal clock source module
containing a frequency-locked-loop (FLL) controlled by internal or
external reference (XOSC1, XOSC2); precision trimming of internal
reference allows 0.2% resolution and 2% deviation over temperature
and voltage; supporting CPU/bus frequencies from 1 MHz to 20 MHz
System Protection
– Watchdog computer operating properly (COP) reset with option to run
from dedicated 1 kHz internal clock source or bus clock
– Low-voltage warning with interrupt
– Low-voltage detection with reset or interrupt
– Illegal opcode and illegal address detection with reset
– Flash block protection
Development Support
– Single-wire background debug interface
– Breakpoint capability to allow single breakpoint setting during
in-circuit debugging (plus 3 more breakpoints in breakpoint unit)
– Breakpoint (BKPT) debug module containing three comparators (A, B,
and C) with ability to match addresses in 64 KB space. Each
80-LQFP
Case 917A
14  14
comparator can be used as hardware breakpoint. Full mode,
Comparator A compares address and Comparator B compares data.
Supports both tag and force breakpoints
Peripherals
– LCD — up to 440 or 836 LCD driver with internal charge pump and
option to provide an internally regulated LCD reference that can be
trimmed for contrast control
– ADC16 — two analog-to-digital converters; 16-bit resolution; one
dedicated differential per ADC; up to 16-ch; up to 2.5 s conversion
time for 12-bit mode; automatic compare function; hardware
averaging; calibration registers; temperature sensor; internal bandgap
reference channel; operation in stop3; fully functional from 3.6 V to
1.8 V
– PRACMP —three rail to rail programmable reference analog
comparator; up to 8 inputs; on-chip programmable reference generator
output; selectable interrupt on rising, falling, or either edge of
comparator output; operation in stop3
– SCI — four full duplex non-return to zero (NRZ); LIN master extended
break generation; LIN slave extended break detection; wakeup on
active edge; SCI0 designed for AMR operation; TxD of SCI1 and SCI2
can be modulated with timers and RxD can recieved through
PRACMP;
– SPI— three full-duplex or single-wire bidirectional; double-buffered
transmit and receive; master or slave mode; MSB-first or LSB-first
shifting; SPI0 designed for AMR opeartion
– IIC — up to 100 kbps with maximum bus loading; multi-master
operation; programmable slave address; interrupt driven byte-by-byte
data transfer; supporting broadcast mode and 10-bit addressing;
supporting SM BUS functionality; can wake from stop3
– FTM — 2-channel flextimer module; selectable input capture, output
compare, or buffered edge- or center-aligned PWM on each channel
– IRTC — independent real-time clock, independent power domain, 32
bytes RAM, 32.768 kHz input clock optional output to ICS, hardware
calendar, hardware compensation due to crystal or temperature
characteristics, tamper detection and indicator
– PCRC — 16/32 bit programmable cyclic redundancy check for
high-speed CRC calculation
– MTIM — two 8-bit and one 16-bit timers; configurable clock inputs
and interrupt generation on overflow
– PDB — programmable delay block; optimized for scheduling ADC
conversions
– PCNT — position counter; working in stop3 mode without waking
CPU; can be used to generate waveforms like timer
Input/Output
– 57 GPIOs including one output-only pin
– Eight KBI interrupts with selectable polarity
– Hysteresis and configurable pullup device on all input pins;
configurable slew rate and drive strength on all output pins.
Package Options
– 80-pin LQFP, 64-pin LQFP
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2010-2011. All rights reserved.
64-LQFP
Case 840F
10  10
Table of Contents
1
2
3
Devices in the MC9S08GW64 Series. . . . . . . . . . . . . . . . . . . .3
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .10
3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .10
3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .11
3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .12
3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .23
3.8 External Oscillator (XOSCVLP) Characteristics . . . . . .26
3.9 Internal Clock Source (ICS) Characteristics . . . . . . . . .27
3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4
5
3.10.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . .
3.10.2 Timer (TPM/FTM) Module Timing . . . . . . . . . .
3.10.3 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11 Analog Comparator (PRACMP) Electricals . . . . . . . . .
3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .
3.13 VREF Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .
3.14 LCD Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15 FLASH Specifications . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Device Numbering System . . . . . . . . . . . . . . . . . . . . .
Package Information and Mechanical Drawings . . . . . . . . . .
29
30
31
34
34
39
40
40
41
41
41
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current.
Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Rev
Date
Description of Changes
1
5/26/2010
Initial public release
2
10/29/2010
Completed all the TBDs.
Updated the voltage output data in the Table 20.
Changed the classification marking of |IInT| to C in the Table 8.
3
1/28/2011
Updated Table 7.
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual
(MC9S08GW64RM)
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
MC9S08GW64 Series MCU Data Sheet, Rev. 3
2
Freescale Semiconductor
Devices in the MC9S08GW64 Series
1
Devices in the MC9S08GW64 Series
Table 1 summarizes the feature set available in the MC9S08GW64 series of MCUs.
Table 1. MC9S08GW64 Series Features by MCU and Package
Feature
Package
MC9S08GW64
80-pin
LQFP
MC9S08GW32
64-pin
LQFP
80-pin
LQFP
64-pin
LQFP
FLASH
65,536 Bytes
32,768 Bytes
RAM
4,032 Bytes
2,048 Bytes
ADC01
Single-ended
Channels
7-ch
7-ch
7-ch
7-ch
ADC0 Differential
Channels2
1
0
1
0
ADC1
Single-ended
Channels
7-ch
7-ch
7-ch
7-ch
ADC1 Differential
Channels
1
1
1
1
BKPT
yes
yes
ICS
yes
yes
IIC
yes
yes
IRQ
yes
yes
IRTC
yes
yes
KBI
8-ch
8-ch
MTIM8
2
2
MTIM16
yes
yes
PCNT
yes
yes
PCRC
yes
yes
PDB
yes
yes
PRACMP
3
3
SCI
4
4
SPI
3
3
FTM
2-ch
2-ch
LCD
836
440
824
428
836
440
824
428
VREFO
yes
yes
yes
yes
XOSC
I/O pins3
2
57
2
45
57
45
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
3
Devices in the MC9S08GW64 Series
1
There are two 16-bit ADC modules, so two parallel conversions at two channels can be made
simultaneously.
2
Each differential channel consists of two pins (DADPx and DADMx).
3
The I/O pins include one output-only pin.
The block diagram in Figure 1 shows the structure of the MC9S08GW64 series MCUs.
MC9S08GW64 Series MCU Data Sheet, Rev. 3
4
Freescale Semiconductor
VREG
VSS2
S08 Core V6
16-bit MTIM3
Port A, F:
MTIMCLK
8-bit MTIM1
Port A, F:
MTIMCLK
BKPT
Port A, F:
MTIMCLK
SPI0
Port B:
MOSI0 MISO0
SCLK0 SS0
SPI1
Port C, G:
MOSI1 MISO1
SCLK1 SS1
SPI2
Port A, D:
MOSI2 MISO2
SCLK2 SS2
CPU
BKGD/MS
INT
RESETB
SIM
SCI0
Port B:
RxD0
TxD0
SCI1
Port B, C:
RxD1
TxD1
SCI2
Port A, B:
RxD2
TxD2
SCI3
Port C, G:
RxD3
TxD3
FLASH
GW64 64 KB
GW32 32 KB
RAM
GW64 4 KB
GW32 2 KB
Internal Clock Source
REF CLK
IRCLK
PRACMP0
Port A, G, H:
CMPP0/1/2/3/4/5/6
CMPOUT0
PRACMP1
Port A, G, H:
CMPP0/1/2/3/4/5/6
CMPOUT1
PRACMP2
Port A, G, H:
CMPP0/1/2/3/4/5/6
CMPOUT2
Clock Check & Select
XTAL2
XOSC2
EXTAL2
CLKO
XTAL1
XOSC1
EXTAL1
CLKO
VBAT
TAMPER1
TAMPER2
PCNT
Independent
RTC
The RTC is in a separate
power domain
PTC0/MOSI1/LCD2
PTC1/MISO1/LCD3
PTC2/SCLK1/LCD4
PTC3/SS1/LCD5
PTC4/FTMCH0/RxD1/LCD6
PTC5/FTMCH1/TxD1/LCD7
PTC6/PCNTCH0/RxD3/LCD8
PTC7/PCNTCH1/TxD3/LCD9
Port A, B:
SDA
SCL
IIC
COP
LVD
PTB0/KBIP0/TxD1/EXTAL2
PTB1/KBIP1/RxD1/XTAL2
PTB2/KBIP2/MOSI0/MISO0/RxD0
PTB3/KBIP3/MISO0/MOSI0/TxD0
PTB4/KBIP4/SCLK0/SCL
PTB5/KBIP5/SS0/SDA
PTB6/KBIP6/RxD2/LCD0
PTB7/KBIP7/TxD2/LCD1
2-Channel FTM Port A, C, F:
FTMCH[0:1]
FTMCLK
8-bit MTIM2
PCRC
Port A
ADC0
Port B
Port B, D:
KBIP[7:0]
LCD
Port D
Port A,F,G,H:
AD[15:2]
DADP/M[0]
VREFO
VDD
VSS1
KBI
trig[0]
sel[0]
VDDA/VSSA
VREFH/VREFL
AD[15]
PTA0/MOSI2/PCNTCH0/SCL/AD2
PTA1/MISO2/PCNTCH1/SDA/AD3
PTA2/SCLK2/FTMCH0/PCNT0/CMPP0
PTA3/SS2/FTMCH1/PCNT1/CMPP1
PTA4/MTIMCLK/RxD2/PCNT2/CMPP2
PTA5/FTMCLK/TxD2/EXTRIG/IRQ
PTA6/CMPOUT0/CLKOUT/BKGD/MS
Port A:
EXTRIG
Port A, C, G, H:
PCNT0 PCNT1 PCNT2
PCNTCH0 PCNTCH1
PTD0/KBIP0/MOSI2/LCD10
PTD1/KBIP1/MISO2/LCD11
PTD2/KBIP2/SCLK2/LCD12
PTD3/KBIP3/SS2/LCD13
PTD4/KBIP4/LCD14
PTD5/KBIP5/CLKOUT/LCD15
PTD6/KBIP6/LCD16
PTD7/KBIP7/LCD17
Port E
ADC1
PDB
trig[1:0]
sel[1:0]
PTE0/LCD18
PTE1/LCD19
PTE2/LCD20
PTE3/LCD21
PTE4/LCD22
PTE5/LCD23
PTE6/LCD24
PTE7/LCD25
Port F
Port A,F,G,H:
AD[15:2]
DADP/M[1]
AD[15]
trig[1]
sel[1]
PTF0/LCD26
PTF1/LCD27
PTF2/LCD28
PTF3/LCD29
PTF4/LCD30
PTF5/LCD31
PTF6/MTIMCLK/AD4/LCD32
PTF7/FTMCLK/AD5/LCD33
Port G
VDDA/VSSA
VREFH/VREFL
PTG0/MOSI1/AD6/LCD34
PTG1/MISO1/AD7/LCD35
PTG2/SCLK1/AD8/LCD36
PTG3/SS1/AD9/LCD37
PTG4/CMPOUT1/RxD3/AD10/LCD38
PTG5/CMPOUT2/TxD3/AD11/LCD39
PTG6/CMPP3/AD12/PCNT0/LCD40
PTG7/CMPP4/AD13/PCNT1/LCD41
Port H
VDDA/VSSA
VREFH/VREFL
Port C
Devices in the MC9S08GW64 Series
PTH0/CMPP5/AD14/PCNT2/LCD42
PTH1/RTCCLKOUT/CMPP6/AD15/LCD43
Port B, C, D, E, F, G, H:
LCD[0:43]
Figure 1. MC9S08GW64 Series Block Diagram
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
5
Pin Assignments
2
Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
80 LQFP
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PTC7/PCNTCH1/TxD3/LCD9
PTC6/PCNTCH0/RxD3/LCD8
PTC5/FTMCH1/TxD1/LCD7
PTC4/FTMCH0/RxD1/LCD6
PTC3/SS1/LCD5
PTC2/SCLK1/LCD4
PTC1/MISO1/LCD3
PTC0/MOSI1/LCD2
PTB7/KBIP7/TxD2/LCD1
PTB6/KBIP6/RxD2/LCD0
PTB5/KBIP5/SS0/SDA
PTB4/KBIP4/SCLK0/SCL
PTB3/KBIP3/MISO0/MOSI0/TxD0
PTB2/KBIP2/MOSI0/MISO0/RxD0
RESET
PTB1/KBIP1/RxD1/CMPP6/XTAL2
PTB0/KBIP0/TxD1/EXTAL2
VSS
VDD
PTA6/CMPOUT0/CLKOUT/BKGD/MS
VDDA
VREFH
VSSA
VREFL
DADP0
DADM0
VREFO
DADP1
DADM1
VBAT
EXTAL1
XTAL1
TAMPER1
TAMPER2
PTA0/MOSI2/PCNTCH0/SCL/AD2
PTA1/MISO2/PCNTCH1/SDA/AD3
PTA2/SCLK2/FTMCH0/PCNT0/CMPP0
PTA3/SS2/FTMCH1/PCNT1/CMPP1
PTA4/MTIMCLK/RxD2/PCNT2/CMPP2
PTA5/FTMCLK/TxD2/EXTRIG/IRQ
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PTE6/LCD24
PTE7/LCD25
PTF0/LCD26
PTF1/LCD27
PTF2/LCD28
PTF3/LCD29
PTF4/LCD30
PTF5/LCD31
PTF6/MTIMCLK/AD4/LCD32
PTF7/FTMCLK/AD5/LCD33
PTG0/MOSI1/AD6/LCD34
PTG1/MISO1/AD7/LCD35
PTG2/SCLK1/AD8/LCD36
PTG3/SS1/AD9/LCD37
PTG4/CMPOUT1/RxD3/AD10/LCD38
PTG5/CMPOUT2/TxD3/AD11/LCD39
PTG6/CMPP3/AD12/PCNT0/LCD40
PTG7/CMPP4/AD13/PCNT1/LCD41
PTH0/CMPP5/AD14/PCNT2/LCD42
PTH1/RTCCLKOUT/AD15/LCD43
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
VCAP1
VCAP2
VLL1
VLL2
VLL3
VSS
PTE5/LCD23
PTE4/LCD22
PTE3/LCD21
PTE2/LCD20
PTE1/LCD19
PTE0/LCD18
PTD7/KBIP7/LCD17
PTD6/KBIP6/LCD16
PTD5/KBIP5/CLKOUT/LCD15
PTD4/KBIP4/LCD14
PTD3/KBIP3/SS2/LCD13
PTD2/KBIP2/SCLK2/LCD12
PTD1/KBIP1/MISO2/LCD11
PTD0/KBIP0/MOSI2/LCD10
This section shows the pin assignments for the MC9S08GW64 series devices.
Figure 2. MC9S08GW64 Series in 80-Pin LQFP Package
MC9S08GW64 Series MCU Data Sheet, Rev. 3
6
Freescale Semiconductor
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VCAP1
VCAP2
VLL1
VLL2
VLL3
VSS
PTE5/LCD23
PTE4/LCD22
PTD7/KBIP7/LCD17
PTD6/KBIP6/LCD16
PTD5/KBIP5/CLKOUT/LCD15
PTD4/KBIP4/LCD14
PTD3/KBIP3/SS2/LCD13
PTD2/KBIP2/SCLK2/LCD12
PTD1/KBIP1/MISO2/LCD11
PTD0/KBIP0/MOSI2/LCD10
Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64 LQFP
PTC7/PCNTCH1/TxD3/LCD9
PTC6/PCNTCH0/RxD3/LCD8
PTC5/FTMCH1/TxD1/LCD7
PTC4/FTMCH0/RxD1/LCD6
PTB7/KBIP7/TxD2/LCD1
PTB6/KBIP6/RxD2/LCD0
PTB5/KBIP5/SS0/SDA
PTB4/KBIP4/SCLK0/SCL
PTB3/KBIP3/MISO0/MOSI0/TxD0
PTB2/KBIP2/MOSI0/MISO0/RxD0
RESET
PTB1/KBIP1/RxD1/CMPP6/XTAL2
PTB0/KBIP0/TxD1/EXTAL2
VSS
VDD
PTA6/CMPOUT0/CLKOUT/BKGD/MS
VREFO
DADP1
DADM1
VBAT
EXTAL1
XTAL1
TAMPER1
TAMPER2
PTA0/MOSI2/PCNTCH0/SCL/AD2
PTA1/MISO2/PCNTCH1/SDA/AD3
PTA2/SCLK2/FTMCH0/PCNT0/CMPP0
PTA3/SS2/FTMCH1/PCNT1/CMPP1
PTA4/MTIMCLK/RxD2/PCNT2/CMPP2
PTA5/FTMCLK/TxD2/EXTRIG/IRQ
VDDA/VREFH
VSSA/VREFL
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PTE6/LCD24
PTE7/LCD25
PTF0/LCD26
PTF1/LCD27
PTF6/MTIMCLK/AD4/LCD32
PTF7/FTMCLK/AD5/LCD33
PTG0/MOSI1/AD6/LCD34
PTG1/MISO1/AD7/LCD35
PTG2/SCLK1/AD8/LCD36
PTG3/SS1/AD9/LCD37
PTG4/CMPOUT1/RxD3/AD10/LCD38
PTG5/CMPOUT2/TxD3/AD11/LCD39
PTG6/CMPP3/AD12/PCNT0/LCD40
PTG7/CMPP4/AD13/PCNT1/LCD41
PTH0/CMPP5/AD14/PCNT2/LCD42
PTH1/RTCCLKOUT/AD15/LCD43
Figure 3. MC9S08GW64 Series in 64-Pin LQFP Package
Table 2. Pin Availability by Package Pin-Count
80
64
Port Pin
Default func
Alt 1
Alt 2
1
1
PTE6
PTE6
LCD24
2
2
PTE7
PTE7
LCD25
3
3
PTF0
PTF0
LCD26
4
4
PTF1
PTF1
LCD27
5
PTF2
PTF2
LCD28
6
PTF3
PTF3
LCD29
Alt3
Alt4
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
7
Pin Assignments
Table 2. Pin Availability by Package Pin-Count (continued)
80
64
Port Pin
Default func
Alt 1
7
PTF4
PTF4
LCD30
8
PTF5
PTF5
LCD31
Alt 2
Alt3
Alt4
9
5
PTF6
PTF6
MTIMCLK
AD4
LCD32
10
6
PTF7
PTF7
FTMCLK
AD5
LCD33
11
7
PTG0
PTG0
MOSI1
AD6
LCD34
12
8
PTG1
PTG1
MISO1
AD7
LCD35
13
9
PTG2
PTG2
SCLK1
AD8
LCD36
14
10
PTG3
PTG3
SS1
AD9
LCD37
15
11
PTG4
PTG4
CMPOUT1
RxD3
AD10
LCD38
16
12
PTG5
PTG5
CMPOUT2
TxD3
AD11
LCD39
17
13
PTG6
PTG6
CMPP3
AD12
PCNT0
LCD40
18
14
PTG7
PTG7
CMPP4
AD13
PCNT1
LCD41
19
15
PTH0
PTH0
CMPP5
AD14
PCNT2
LCD42
20
16
PTH1
PTH1
RTCCLKOUT
AD15
LCD43
VDDA
VDDA
VREFH
VREFH
VSSA
VSSA
VREFL
VREFL
25
DADP0
DADP0
26
DADM0
DADM0
21
17
22
23
24
18
27
19
VREFO
VREFO
28
20
DADP1
DADP1
29
21
DADM1
DADM1
30
22
VBAT
VBAT
31
23
EXTAL1
EXTAL1
32
24
XTAL1
XTAL1
33
25
TAMPER11
TAMPER1
34
26
TAMPER2
TAMPER2
35
27
PTA0
PTA0
MOSI2
PCNTCH0
SCL
AD2
36
28
PTA1
PTA1
MISO2
PCNTCH1
SDA
AD3
37
29
PTA2
PTA2
SCLK2
FTMCH0
PCNT0
CMPP0
38
30
PTA3
PTA3
SS2
FTMCH1
PCNT1
CMPP1
39
31
PTA4
PTA4
MTIMCLK
RxD2
PCNT2
CMPP2
40
32
PTA52
PTA5
FTMCLK
TxD2
EXTRIG
IRQ
41
33
PTA63
BKGD/MS
CMPOUT0
CLKOUT
BKGD/MS
MC9S08GW64 Series MCU Data Sheet, Rev. 3
8
Freescale Semiconductor
Pin Assignments
Table 2. Pin Availability by Package Pin-Count (continued)
80
64
Port Pin
Default func
Alt 1
Alt 2
Alt3
42
34
VDD
VDD
43
35
VSS
VSS
44
36
PTB0
45
37
46
47
PTB0
KBIP0
TxD1
EXTAL2
PTB11
PTB1
KBIP1
RxD1
CMPP6
XTAL2
38
RESET
RESET
39
PTB2
PTB2
KBIP2
MOSI0
MISO0
RxD0
48
40
PTB3
4
PTB3
KBIP3
MISO0
MOSI0
TxD0
49
41
PTB43
PTB4
KBIP4
SCLK0
SCL
50
42
PTB5
3
PTB5
KBIP5
SS0
SDA
51
43
PTB6
PTB6
KBIP6
RxD2
LCD0
52
44
PTB7
PTB7
KBIP7
TxD2
LCD1
53
PTC0
PTC0
MOSI1
LCD2
54
PTC1
PTC1
MISO1
LCD3
55
PTC2
PTC2
SCLK1
LCD4
56
PTC3
PTC3
SS1
LCD5
57
45
PTC4
PTC4
FTMCH0
RxD1
LCD6
58
46
PTC5
PTC5
FTMCH1
TxD1
LCD7
59
47
PTC6
PTC6
PCNTCH0
RxD3
LCD8
60
48
PTC7
PTC7
PCNTCH1
TxD3
LCD9
61
49
PTD0
PTD0
KBIP0
MOSI2
LCD10
62
50
PTD1
PTD1
KBIP1
MISO2
LCD11
63
51
PTD2
PTD2
KBIP2
SCLK2
LCD12
64
52
PTD3
PTD3
KBIP3
SS2
LCD13
65
53
PTD4
PTD4
KBIP4
LCD14
66
54
PTD5
PTD5
KBIP5
CLKOUT
67
55
PTD6
PTD6
KBIP6
LCD16
68
56
PTD7
PTD7
KBIP7
LCD17
69
PTE0
PTE0
LCD18
70
PTE1
PTE1
LCD19
71
PTE2
PTE2
LCD20
72
PTE3
PTE3
LCD21
73
57
PTE4
PTE4
LCD22
74
58
PTE5
PTE5
LCD23
75
59
VSS
VSS
76
60
VLL3
VLL3
Alt4
LCD15
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
9
Electrical Characteristics
Table 2. Pin Availability by Package Pin-Count (continued)
80
64
Port Pin
Default func
77
61
VLL2
VLL2
78
62
VLL1
VLL1
79
63
VCAP2
VCAP2
80
64
VCAP1
VCAP1
Alt 1
Alt 2
Alt3
Alt4
1
TAMPER0 pin is dedicatedly used for Battery Removal Tamper and not exposed on any SoC pins.
PTA5 is with double drive strength.
3
PTA6 is an output-only pin when it is configured as GPIO.
4
PTB2, PTB3 and PTB4 are compatible with 5 V devices with a pullup device.
2
3
Electrical Characteristics
3.1
Introduction
This section contains electrical and timing specifications for the MC9S08GW64 sries of microcontrollers available at the time
of publication.
3.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 3. Parameter Classifications
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
3.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 4 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
MC9S08GW64 Series MCU Data Sheet, Rev. 3
10
Freescale Semiconductor
Electrical Characteristics
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, either VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled.
Table 4. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to +3.8
V
Maximum current into VDD
IDD
120
mA
Digital input voltage
VIn
–0.3 to VDD + 0.3
V
Instantaneous maximum current
Single pin limit (applies to all port pins except PTA5
and PTB1)1, 2, 3
ID
 25
mA
Instantaneous maximum current
Single pin limit (applies to PTA5 and PTB1)1,2,3
ID
 50
mA
Tstg
–55 to 150
C
Storage temperature range
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2 All functional non-supply pins are internally clamped to V
SS and VDD.
3 Power supply must maintain regulation within operating V
DD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
3.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and
it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine
the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of
unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.
Table 5. Thermal Characteristics
Rating
Symbol
Value
Unit
Operating temperature range
(packaged)
TA
TL to TH
–40 to 85
C
Maximum junction temperature
TJ
95
C
JA
61
C/W
Thermal resistance
Single-layer board
80-pin LQFP
64-pin LQFP
70
Thermal resistance
Four-layer board
80-pin LQFP
64-pin LQFP
JA
48
C/W
52
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
11
Electrical Characteristics
The average chip-junction temperature (TJ) in C can be obtained from:
TJ = TA + (PD  JA)
Eqn. 1
where:
TA = Ambient temperature, C
JA = Package thermal resistance, junction-to-ambient, C/W
PD = Pint PI/O
Pint = IDD  VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O  Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected)
is:
PD = K  (TJ + 273C)
Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = PD  (TA + 273C) + JA  (PD)2
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively
for any value of TA.
3.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be taken to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification, ESD stresses were performed for the human body model (HBM), the machine model (MM) and the
charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless instructed otherwise in the device specification.
Table 6. ESD and Latch-up Test Conditions
Model
Description
Symbol
Value
Unit
R1
1500

C
100
pF
Number of pulses per pin
—
3
Series resistance
R1
0

Storage capacitance
C
200
pF
Number of pulses per pin
—
3
Human
Series resistance
Body Model
Storage capacitance
Charge
Device
Model
Latch-up
Minimum input voltage limit
–2.5
V
Maximum input voltage limit
7.5
V
MC9S08GW64 Series MCU Data Sheet, Rev. 3
12
Freescale Semiconductor
Electrical Characteristics
Table 7. ESD and Latch-Up Protection Characteristics
Rating1
No.
Symbol
Min
Max
Unit
1
Human body model (HBM)
VHBM
2000
—
V
2
Machine Model (MM)
VMM
±200
—
V
3
Charge device model (CDM)
VCDM
500
—
V
ILAT
1002
—
mA
4
Latch-up current at TA = 85C
(applies to all pins except pin
31EXTAL1 and pin 30 XTAL1 in
80-pin package, applies to all pins
except pin 23 EXTAL1 and pin 24
XTAL1 in 64-pin package)
Latch-up current at TA = 85C
(applies to pin 31EXTAL1 and pin
30 XTAL1 in 80-pin package,
applies to pin 23 EXTAL1 and pin
24 XTAL1 in 64-pin package)
ILAT
623
—
mA
1
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
2 These pins meet JESD78A Class II (section 1.2) Level A (section 1.3) requirement of 100mA.
3
This pin meets JESD78A Class II (section 1.2) Level B (section 1.3) characterization to 62mA.
3.6
DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table 8. DC Characteristics
Num C
1
2
Characteristic
Condition
Min
3.6
V
VOH
VDD >1.8 V
ILoad = –0.6 mA
VDD – 0.5
—
—
V
VDD > 2.7 V
ILoad = –10 mA
VDD – 0.5
—
—
VDD > 1.8 V
ILoad = –3 mA
VDD – 0.5
—
—
VDD >1.8 V
ILoad = –0.5 mA
VDD – 0.5
—
—
VDD > 2.7 V
ILoad = –2.5 mA
VDD – 0.5
—
—
VDD > 1.8 V
ILoad = –1 mA
VDD – 0.5
—
—
—
—
100
Operating Voltage
C Output high
voltage
P
1.8
All non-LCD pins
low-drive strength
All non-LCD pins
high-drive strength
C
3
C Output high
voltage
All LCD/GPIO pins
low-drive strength
P
All LCD/GPIO pins
high-drive strength
VOH
C
4
D Output high
current
Typ1
Symbol
Max total IOH for all ports
IOHT
Max
Unit
V
mA
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
13
Electrical Characteristics
Table 8. DC Characteristics (continued)
Num C
5
Characteristic
C Output low
voltage
All non-LCD pins
low-drive strength
P
Symbol
Condition
Min
Typ1
Max
Unit
VOL
VDD > 1.8 V
ILoad = 0.6 mA
—
—
0.5
V
VDD > 2.7 V
ILoad = 10 mA
—
—
0.5
VDD > 1.8 V
ILoad = 3 mA
—
—
0.5
VDD > 1.8 V
ILoad = 0.5 mA
—
—
0.5
VDD > 2.7 V
ILoad = 3 mA
—
—
0.5
VDD > 1.8 V
ILoad = 1 mA
—
—
0.5
—
—
100
mA
VDD  2.7 V
0.70 x VDD
—
—
V
VDD 1.8 V
0.85 x VDD
—
—
VDD  2.7 V
—
—
0.35 x VDD
VDD 1.8 V
—
—
0.30 x VDD
0.06 x VDD
—
—
mV
All non-LCD pins
high-drive strength
C
6
C Output low
voltage
All LCD/GPIO pins
low-drive strength
P
All LCD/GPIO pins
high-drive strength
VOL
C
Max total IOL for all ports
IOLT
V
7
D Output low
current
8
P Input high
C voltage
all digital inputs
P Input low
C voltage
all digital inputs
10
C Input
hysteresis
all digital inputs
Vhys
11
P Input
leakage
current
all input only pins
(per pin)
|IIn|
VIn = VDD or VSS
—
0.025
1
A
12
P Hi-Z
(off-state)
leakage
current
all input/output
(per pin)
|IOZ|
VIn = VDD or VSS
—
0.025
1
A
13
C Total
leakage
current2
Total leakage current for all
pins
|IInT|
VIn = VDD or VSS
—
—
2
A
14
P Pullup,
Pulldown
resistors
all digital inputs, when
enabled
RPU,
RPD
17.5
—
52.5
k
15
P Pullup,
Pulldown
resistors
all digital inputs, when
enabled
RPU,
RPD
17.5
—
52.5
k
16
D DC injection Single pin limit
current 3, 4, Total MCU limit, includes
5
sum of all stressed pins
IIC
–0.2
—
0.2
mA
–5
—
5
mA
17
C Input Capacitance, all pins
CIn
—
—
8
pF
18
C RAM retention voltage
VRAM
—
0.6
1.0
V
19
C iRTC RAM retention voltage
ViRAM
—
1.05
—
V
9
6
VIH
VIL
VIN < VSS, VIN > VDD
20
C POR re-arm voltage
VPOR
0.9
1.4
2.0
V
21
D POR re-arm time
tPOR
10
—
—
s
MC9S08GW64 Series MCU Data Sheet, Rev. 3
14
Freescale Semiconductor
Electrical Characteristics
Table 8. DC Characteristics (continued)
Num C
1
2
3
4
5
6
7
Characteristic
Symbol
Condition
Min
Typ1
Max
Unit
2.11
2.16
2.22
V
2.16
2.23
2.27
1.80
1.85
1.91
1.86
1.92
1.99
2.36
2.46
2.56
2.52
2.49
2.71
2.10
2.16
2.23
2.15
2.23
2.26
22
Low-voltage High range — VDD falling
C detection
High range — VDD rising
threshold
VLVDH
23
Low-voltage Low range — VDD falling
C detection
Low range — VDD rising
threshold
VLVDL
24
Low-voltage VDD falling, LVWV = 1
C warning
VDD rising, LVWV = 1
threshold
VLVWH
25
C
Low-voltage VDD falling, LVWV = 0
warning
VDD rising, LVWV = 0
VLVWL
26
C Low-voltage inhibit reset/recover
hysteresis
Vhys
—
80
—
mV
27
P Bandgap Voltage Reference7
VBG
1.15
1.17
1.19
V
V
V
V
Typical values are measured at 25C. Characterized, not tested
Total leakage current is the sum value for all GPIO pins. This leakage current is not distributed evenly across all pins but
characterization data shows that individual pin leakage current maximums are less than 250nA.
All functional non-supply pins, except for PTB2 are internally clamped to VSS and VDD.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure that external VDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is
present, or if clock rate is very low (which would reduce overall power consumption).
POR will occur below the minimum voltage.
Factory trimmed at VDD = 3.0 V, Temp = 25C
TBD
Figure 4. Non LCD pins I/O Pullup Typical Resistor Values
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
15
Electrical Characteristics
Figure 5. Non LCD pins I/O Pulldown Typical Resistor Values
Figure 6. Typical Low-Side Driver (Sink) Characteristics(Non LCD pins) — Low Drive (PTxDSn = 0)
MC9S08GW64 Series MCU Data Sheet, Rev. 3
16
Freescale Semiconductor
Electrical Characteristics
Figure 7. Typical Low-Side Driver (Sink) Characteristics(Non LCD pins) — High Drive (PTxDSn = 1)
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
17
Electrical Characteristics
Figure 8. Typical High-Side (Source) Characteristics (Non LCD pins)— Low Drive (PTxDSn = 0)
MC9S08GW64 Series MCU Data Sheet, Rev. 3
18
Freescale Semiconductor
Electrical Characteristics
Figure 9. Typical High-Side (Source) Characteristics(Non LCD pins) — High Drive (PTxDSn = 1)
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
19
Electrical Characteristics
Figure 10. Typical Low-Side Driver (Sink) Characteristics(LCD/GPIO pins) — Low Drive (PTxDSn = 0)
MC9S08GW64 Series MCU Data Sheet, Rev. 3
20
Freescale Semiconductor
Electrical Characteristics
Figure 11. Typical Low-Side Driver (Sink) Characteristics(LCD/GPIO pins) — High Drive (PTxDSn = 1)
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
21
Electrical Characteristics
Figure 12. Typical High-Side (Source) Characteristics (LCD/GPIO pins)— Low Drive (PTxDSn = 0)
MC9S08GW64 Series MCU Data Sheet, Rev. 3
22
Freescale Semiconductor
Electrical Characteristics
Figure 13. Typical High-Side (Source) Characteristics(LCD/GPIO pins) — High Drive (PTxDSn = 1)
3.7
Supply Current Characteristics
This section includes information about power supply current in various operating modes.
Table 9. Supply Current Characteristics
Num
C
Parameter
Symbol
Bus
Freq
1
C
Run supply current
FEI mode, all modules on, running
from Flash
RIDD
20 MHz
Run supply current
FEI mode, all modules off, running
from Flash
RIDD
T
2
C
T
3
T
T
4
T
T
Run supply current
LPRS=0, all modules off, running
from Flash
Run supply current
LPRS=1, all modules off; running
from Flash
2 MHz
3
20 MHz
2 MHz
RIDD
VDD
(V)
16 kHz
FBILP
3
3
16 kHz
FBELP
RIDD
16 kHz
FBILP
16 kHz
FBELP
3
Typ1
Max
Unit
Temp
(C)
17.4
20.5
mA
–40 to 85C
2.6
—
10.5
—
mA
–40 to 85C
1.6
—
158
—
A
–40 to 85C
148
—
160
—
A
–40 to 85C
23
—
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
23
Electrical Characteristics
Table 9. Supply Current Characteristics
Num
C
5
T
T
6
C
C
7
T
T
8
T
T
9
Parameter
Run supply current
LPRS=1, all modules off; running
from RAM
Wait mode supply current,
all modules off
Symbol
Bus
Freq
VDD
(V)
Typ1
Max
Unit
Temp
(C)
RIDD
16 kHz
FBILP
3
137
—
A
–40 to 85C
8
—
5.4
7.5
mA
–40 to 85C
1.1
—
16 kHz
FBELP
WIDD
3
2 MHz
WIDD
Wait mode supply current
LPRS = 0, all modules off
WIDD
Wait mode supply current
LPRS = 1, all modules off
Stop2 mode supply current
20 MHz
S2IDD
16 kHz
FBILP
3
131
—
A
–40 to 85C
16 kHz
FBELP
3
123
—
A
–40 to 85C
16 kHz
FBILP
3
159
—
A
–40 to 85C
16 kHz
FBELP
3
5.6
—
A
–40 to 85C
N/A
3
330
1000
–40 to 25C
1622
—
70C
6000
—
—
—
—
—
70C
—
—
85C
474
1100
–40 to 25C
2608
—
70C
9000
—
—
—
—
—
70C
—
—
85C
C
N/A
2
C
10
C
Stop3 mode supply current
No clocks active
S3IDD
N/A
N/A
3
2
C
1
nA
nA
85C
–40 to 25C
85C
–40 to 25C
Typical values are measured at 25C. Characterized, not tested.
Table 10. Stop Mode Adders (VDD=3V, VDDA=VDD)
Temperature (C)
Num
C
Parameter
1
C
LPO
2
C
ERREFSTEN
3
Condition
RANGE = HGO = 0
1
Units
-40
25
70
85
100
100
150
175
nA
600
737
830
863
nA
—
73
80
92
A
C
IREFSTEN
4
C
LVD1
LVDSE = 1
110
112
112
113
A
5
C
PRACMP1
Not using the bandgap (BGBE = 0),
PRG enabled
30
35
40
55
A
MC9S08GW64 Series MCU Data Sheet, Rev. 3
24
Freescale Semiconductor
Electrical Characteristics
Table 10. Stop Mode Adders (continued)(VDD=3V, VDDA=VDD)
Temperature (C)
Num
Parameter
Condition
25
70
85
264
286
296
298
A
1.4
1.65
2.01
2.27
A
C
VREFO
7
C
IRTC
8
C
ADC1
ADLPC = ADLSMP = 1
Not using the bandgap (BGBE = 0),
single conversion
78.1
88.5
92.6
93.6
A
9
C
LCD
VIREG enabled for Contrast control, 1/8
Duty cycle, 8x24 configuration for
driving 192 Segments, 32Hz frame rate,
No LCD glass connected.
0.67
0.88
3.74
7.16
A
10
C
PCNT1
32KHz clock, without PWM output
33
47
67
77
nA
C
1
32KHz clock, with PWM output
40
50
63
77
nA
PCNT
Not using the bandgap (BGBE = 0), in
tight regulation mode
Units
-40
6
11
1
C
Not available in stop2 mode.
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
25
Electrical Characteristics
3.8
External Oscillator (XOSCVLP) Characteristics
Reference Figure 14 and Figure 15 for crystal or resonator circuits.
Table 11. XOSCVLP and ICS Specifications (Temperature Range = –40 to 85C Ambient)
Num
1
2
3
4
5
6
C
Characteristic
Symbol
Min
Typ1
Max
Unit
flo
fhi
fhi
32
1
1
—
—
—
38.4
16
8
kHz
MHz
MHz
C Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
High range (RANGE = 1), high gain (HGO = 1)
High range (RANGE = 1), low power (HGO = 0)
D Load capacitors
Low range (RANGE=0), low power (HGO=0)
Other oscillator settings
RF
D Feedback resistor
Low range, low power (RANGE=0, HGO=0)2
Low range, high gain (RANGE=0, HGO=1)
High range (RANGE=1, HGO=X)
D Series resistor —
Low range, low power (RANGE = 0, HGO = 0)2
Low range, high gain (RANGE = 0, HGO = 1)
High range, low power (RANGE = 1, HGO = 0)
High range, high gain (RANGE = 1, HGO = 1)
 8 MHz
4 MHz
1 MHz
C Crystal start-up time 4
Low range, low power
Low range, high gain
High range, low power
High range, high gain
RS
t
t
D Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)
FEE mode
See Note 2
See Note 3
C1,C2
CSTL
CSTH
fextal
FBE or FBELP mode
M
—
—
—
—
10
1
—
—
—
—
—
—
—
100
0
—
—
—
—
—
—
0
0
0
0
10
20
—
—
—
—
600
400
5
15
—
—
—
—
ms
0.03125
0
—
—
20
20
MHz
MHz
k
1
Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value.
Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE=HGO=0.
3 See crystal or resonator manufacturer’s recommendation.
4
Proper PC board layout procedures must be followed to achieve specifications.
2
MC9S08GW64 Series MCU Data Sheet, Rev. 3
26
Freescale Semiconductor
Electrical Characteristics
XOSCVLP
EXTAL
XTAL
RS
RF
C1
Crystal or Resonator
C2
Figure 14. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain
XOSCVLP
EXTAL
XTAL
Crystal or Resonator
Figure 15. Typical Crystal or Resonator Circuit: Low Range/Low Power
3.9
Internal Clock Source (ICS) Characteristics
Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85C Ambient)
Num
C
Characteristic
Symbol
Min
Typ1
Max
Unit
1
P
Average internal reference frequency — factory trimmed at
VDD = 3.6 V and temperature = 25 C
fint_ft
—
32.768
—
kHz
2
P
Average internal reference frequency - trimmed
fint_t
31.25
—
39.063
kHz
3
T
Internal reference start-up time
tIRST
—
—
6
s
4
P
DCO output frequency range - untrimmed
fdco_ut
12.8
16.8
21.33
MHz
5
P
DCO output frequency range - trimmed
fdco_t
16
—
20
MHz
C
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (using FTRIM)
fdco_res_t
—
0.1
0.2
%fdco
C
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (not using FTRIM)
fdco_res_t
—
0.2
0.4
%fdco
C
Total deviation from trimmed DCO output frequency over
voltage and temperature
fdco_t
—
+ 0.5
-1.0
2
%fdco
6
7
8
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
27
Electrical Characteristics
Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85C Ambient) (continued)
Num
9
C
C
Characteristic
Total deviation from trimmed DCO output frequency over
fixed voltage and temperature range of 0C to 70 C
Symbol
Min
Typ1
Max
Unit
fdco_t
—
0.5
1
%fdco
10
C FLL acquisition time 2
tAcquire
—
—
1
ms
11
C Long term jitter of DCO output clock (averaged over 2-ms
interval) 3
CJitter
—
0.02
0.2
%fdco
1
Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value.
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as
the reference, this specification assumes it is already running.
3
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in the crystal oscillator frequency increase the CJitter
percentage for a given interval.
2
Figure 16. Deviation of DCO Output from Trimmed Frequency (20 MHz, 3.0 V)
3.10
AC Characteristics
This section describes timing characteristics for each peripheral system.
MC9S08GW64 Series MCU Data Sheet, Rev. 3
28
Freescale Semiconductor
Electrical Characteristics
3.10.1
Control Timing
Table 13. Control Timing
Symbol
Min
Typ1
Max
Unit
Bus frequency (tcyc = 1/fBus)
fBus
dc
—
20
MHz
D
Internal low power oscillator period
tLPO
700
—
1300
s
3
D
External reset pulse width2
textrst
100
—
—
ns
4
D
Reset low drive
trstdrv
34 x tcyc
—
—
ns
D
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes
tMSSU
—
—
ns
D
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes 3
tMSH
—
—
s
D
IRQ pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
1.5 x tcyc
—
—
—
—
ns
Keyboard interrupt pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
1.5 x tcyc
—
—
—
—
ns
Port rise and fall time — Non-LCD Pins
Low output drive (PTxDS = 0) (load = 50 pF)5, 6
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
—
—
16
23
—
—
Port rise and fall time — Non-LCD Pins
High output drive (PTxDS = 1) (load = 50 pF)5, 6
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
—
—
5
9
—
—
—
6
10
Num
C
1
D
2
5
6
7
8
D
9
Rating
500
100
ns
C
10
1
2
3
4
5
6
C
tVRR
Voltage Regulator Recovery time
ns
us
Typical values are based on characterization data at VDD = 3.0 V, 25C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD
rises above VLVD.
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40C to 85C.
Except for LCD pins in Open Drain mode.
textrst
RESET PIN
Figure 17. Reset Timing
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
29
Electrical Characteristics
tIHIL
IRQ/KBIPx
IRQ/KBIPx
tILIH
Figure 18. IRQ/KBIPx Timing
3.10.2
Timer (TPM/FTM) Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 14. TPM Input Timing
No.
C
Function
Symbol
Min
Max
Unit
1
D
External clock frequency
fTCLK
0
fBus/4
Hz
2
D
External clock period
tTCLK
4
—
tcyc
3
D
External clock high time
tclkh
1.5
—
tcyc
4
D
External clock low time
tclkl
1.5
—
tcyc
5
D
Input capture pulse width
tICPW
1.5
—
tcyc
tTCLK
tclkh
TCLK
tclkl
Figure 19. Timer External Clock
tICPW
FTMCHn
FTMCHn
tICPW
MC9S08GW64 Series MCU Data Sheet, Rev. 3
30
Freescale Semiconductor
Electrical Characteristics
3.10.3
SPI Timing
Table 15 and Figure 20 through Figure 23 describe the timing requirements for the SPI system1,2.
Table 15. SPI Timing
No.
C
—
Function
Symbol
Min
Max
Unit
fBus/2048
0
fBus/2
fBus/4
2
4
2048
—
tcyc
tcyc
12
1
—
—
tSPSCK
tcyc
12
1
—
—
tSPSCK
tcyc
tcyc –30
tcyc – 30
1024 tcyc
—
ns
ns
30
30
—
—
ns
ns
0
25
—
—
ns
ns
Hz
D
Operating frequency
Master
Slave
fop
1
D
SPSCK period
Master
Slave
2
Enable lead time
Master
Slave
tLead
D
D
Enable lag time
Master
Slave
tLag
3
4
D
Clock (SPSCK) high or low time
Master
Slave
D
Data setup time (inputs)
Master
Slave
tSU
5
6
Data hold time (inputs)
Master
Slave
tHI
D
D
Slave access time
ta
—
1
tcyc
7
D
Slave MISO disable time
tdis
—
1
tcyc
8
9
D
Data valid (after SPSCK edge)
Master
Slave
—
—
60
60
ns
ns
10
D
Data hold time (outputs)
Master
Slave
0
0
—
—
ns
ns
11
D
Rise time
Input
Output
tRI
tRO
—
—
tcyc – 25
25
ns
ns
12
D
Fall time
Input
Output
tFI
tFO
—
—
tcyc – 25
25
ns
ns
tSPSCK
tWSPSCK
tv
tHO
1.There is 20 pF load on the SPI ports.
2.There are three types of SPI ports in MC9S08GW64 Series. They are ports for AMR, ports shared with LCD pads
and normal ports. This timing is for normal ports condition.
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
31
Electrical Characteristics
SS1
(OUTPUT)
1
2
SPSCK
(CPOL = 0)
(OUTPUT)
11
3
4
4
12
SPSCK
(CPOL = 1)
(OUTPUT)
5
MISO
(INPUT)
6
MS BIN2
BIT 6 . . . 1
9
LSB IN
9
MOSI
(OUTPUT)
10
BIT 6 . . . 1
MSB OUT2
LSB OUT
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 20. SPI Master Timing (CPHA = 0)
SS1
(OUTPUT)
1
2
12
11
11
12
3
SPSCK
(CPOL = 0)
(OUTPUT)
4
SPSCK
(CPOL = 1)
(OUTPUT)
4
5
MISO
(INPUT)
6
MSB IN2
9
MOSI
(OUTPUT) PORT DATA
BIT 6 . . . 1
LSB IN
10
MASTER MSB OUT2
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 21. SPI Master Timing (CPHA =1)
MC9S08GW64 Series MCU Data Sheet, Rev. 3
32
Freescale Semiconductor
Electrical Characteristics
SS
(INPUT)
1
12
11
11
12
3
SPSCK
(CPOL = 0)
(INPUT)
2
4
4
SPSCK
(CPOL = 1)
(INPUT)
8
7
MISO
(OUTPUT)
9
SLAVE LSB OUT
SEE
NOTE 1
6
5
MOSI
(INPUT)
BIT 6 . . . 1
MSB OUT
SLAVE
10
10
BIT 6 . . . 1
MSB IN
LSB IN
NOTE:
1. Not defined but normally MSB of character just received.
Figure 22. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
1
3
2
SPSCK
(CPOL = 0)
(INPUT)
4
SPSCK
(CPOL = 1)
(INPUT)
4
9
MISO
(OUTPUT)
SEE
NOTE 1
7
MOSI
(INPUT)
12
11
11
12
10
SLAVE
MSB OUT
5
BIT 6 . . . 1
8
SLAVE LSB OUT
6
MSB IN
BIT 6 . . . 1
LSB IN
NOTE:
1. Not defined but normally LSB of character just received.
Figure 23. SPI Slave Timing (CPHA = 1)
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
33
Electrical Characteristics
3.11
Analog Comparator (PRACMP) Electricals
Table 16. PRACMP Electrical Specifications
N
C
Symbol
Min
Typical
Max
Unit
1
D
Supply voltage
VPWR
1.8
—
3.6
V
2
C
Supply current (active) (PRG enabled)
IDDACT1
—
—
60
A
3
C
Supply current (active) (PRG disabled)
IDDACT2
—
—
40
A
4
C
Supply current (ACMP and PRG all
disabled)
IDDDIS
—
—
2
nA
5
D
Analog input voltage
VAIN
VSS – 0.3
—
VDD
V
6
C
Analog input offset voltage
VAIO
—
5
40
mV
7
C
Analog comparator hysteresis
VH
3.0
—
20.0
mV
8
P
Analog input leakage current
IALKG
—
—
1
nA
9
C
Analog comparator initialization delay
tAINIT
—
—
1.0
s
10
C
Programmable reference generator inputs
VIn1(VDD)
1.8
—
VDD
V
11
C
Programmable reference generator inputs
VIn2(VDD25)
1.8
—
2.75
V
12
C
Programmable reference generator setup
delay
tPRGST
—
—
—
ns
13
C
Programmable reference generator step
size
Vstep
–0.25
1
0.25
LSB
14
C
Programmable reference generator voltage
range
Vprgout
VIn/32
—
Vin
V
3.12
Characteristic
ADC Characteristics
These specs all assume seperate VDDAD supply for ADC and isolated pad segment for ADC supplies and differential inputs..
Spec’s should be de-rated for VREFH = Vbg condition.
Table 17. 16-bit ADC Operating Conditions
Num
Charact
eristic
1
Conditions
Absolute
Supply
voltage
Delta to VDD (VDD–VDDA)
3
Ground
voltage
Delta to VSS (VSS–VSSA)2
4
Ref
Voltage
High
2
2
Symb
Min
Typ1
Max
Unit
VDDA
1.8
—
3.6
V
VDDA
–100
0
100
mV
VSSA
–100
0
100
mV
VREFH
1.15
VDDA
VDDA
V
Comment
MC9S08GW64 Series MCU Data Sheet, Rev. 3
34
Freescale Semiconductor
Electrical Characteristics
Table 17. 16-bit ADC Operating Conditions
Num
Charact
eristic
5
Symb
Min
Typ1
Max
Unit
Ref
Voltage
Low
VREFL
VSSA
VSSA
VSSA
V
6
Input
Voltage
VADIN
VREFL
—
VREFH
V
7
Input
Capacit
ance
CADIN
—
8
4
10
5
pF
8
Input
Resista
nce
RADIN
—
2
5
k
9
16 bit modes
fADCK > 8MHz
4MHz < fADCK < 8MHz
fADCK < 4MHz
—
—
—
—
—
—
0.5
1
2
10
13/12 bit modes
fADCK > 8MHz
4MHz < fADCK < 8MHz
fADCK < 4MHz
—
—
—
—
—
—
1
2
5
Analog
Source
Resista
nce
Conditions
16-bit modes
8/10/12-bit modes
RAS
11
11/10 bit modes
fADCK > 8MHz
4MHz < fADCK < 8MHz
fADCK < 4MHz
—
—
—
—
—
—
2
5
10
12
9/8 bit modes
fADCK > 8MHz
fADCK < 8MHz
—
—
—
—
5
10
1.0
—
10
1.0
—
5
1.0
—
2.5
13
14
15
ADC
Convers
ion
Clock
Freq.
ADLPC = 0, ADHSC = 1
ADLPC = 0, ADHSC = 0
ADLPC = 1, ADHSC = 0
fADCK
Comment
External to MCU
k
Assumes
ADLSMP=0
MHz
Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2 DC potential difference.
1
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
35
Electrical Characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
RADIN
ADC SAR
ENGINE
+
VADIN
VAS
+
–
–
CAS
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 24. ADC Input Impedance Equivalency Diagram
Table 18. 16-bit ADC Characteristics full operating range(VREFH = VDDAD, VREFL = VSSAD, FADCK < 10MHz)
Characteristic
Supply Current
Conditions1
C
Symb
ADLPC = 1, ADHSC = 0
ADLPC = 0, ADHSC = 0
T
IDDA
ADLPC=0, ADHSC=1
Supply Current
Stop, Reset, Module Off
ADC
Asynchronous
Clock Source
ADLPC = 1, ADHSC = 0
ADLPC = 0, ADHSC = 0
C
P
IDDA
fADACK
ADLPC = 0, ADHSC = 1
Sample Time
See reference manual for sample times
Conversion
Time
See reference manual for conversion times
1
2
Min
Typ2
Max
—
215
—
—
540
—
—
610
—
—
0.072
—
—
2.4
—
—
5.2
—
—
6.2
—
Unit
Comment
A
ADLSMP = 0
ADCO = 1
A
MHz
tADACK =
1/fADACK
All accuracy numbers assume the ADC is calibrated with VREFH = VDDAD
Typical values assume VDDAD = 3.0V, Temp = 25C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
MC9S08GW64 Series MCU Data Sheet, Rev. 3
36
Freescale Semiconductor
Electrical Characteristics
Table 19. 16-bit ADC Characteristics(VREFH = VDDAD > 2.7V, VREFL = VSSAD, FADCK < 4MHz, ADHSC=1)
Conditions1
C
Symb
Min
Typ2
Max
Unit
Comment
16-bit differential mode
16-bit single-ended mode
T
TUE
—
—
16
20
24/-24
32/-20
LSB3
13-bit differential mode
12-bit single-ended mode
T
—
—
1.5
1.75
2.0
2.5
32x
Hardware
Averaging
(AVGE = %1
AVGS = %11)
11-bit differential mode
10-bit single-ended mode
T
—
—
0.7
0.8
1.0
1.25
9-bit differential mode
8-bit single-ended mode
T
—
—
0.5
0.5
1.0
1.0
16-bit differential mode
16-bit single-ended mode
T
—
—
2.5
2.5
3
3
13-bit differential mode
12-bit single-ended mode
T
—
—
0.7
0.7
1
1
11-bit differential mode
10-bit single-ended mode
T
—
—
0.5
0.5
0.75
0.75
9-bit differential mode
8-bit single-ended mode
T
—
—
0.2
0.2
0.5
0.5
16-bit differential mode
16-bit single-ended mode
T
—
—
6.0
10.0
12.0
16.0
13-bit differential mode
12-bit single-ended mode
T
—
—
1.0
1.0
2.0
2.0
11-bit differential mode
10-bit single-ended mode
T
—
—
0.5
0.5
1.0
1.0
9-bit differential mode
8-bit single-ended mode
T
—
—
0.3
0.3
0.5
0.5
16-bit differential mode
16-bit single-ended mode
T
—
—
4.0
4.0
+16/0
+16/-38
13-bit differential mode
12-bit single-ended mode
T
—
—
0.7
0.7
2.0
2.0
11-bit differential mode
10-bit single-ended mode
T
—
—
0.4
0.4
1.0
1.0
9-bit differential mode
8-bit single-ended mode
T
—
—
0.2
0.2
0.5
0.5
Characteristic
Total
Unadjusted
Error
Differential
Non-Linearity
Integral
Non-Linearity
Zero-Scale
Error
DNL
INL
EZS
LSB2
LSB2
LSB2
VADIN = VSSAD
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
37
Electrical Characteristics
Table 19. 16-bit ADC Characteristics(VREFH = VDDAD > 2.7V, VREFL = VSSAD, FADCK < 4MHz, ADHSC=1)
Conditions1
C
Symb
Min
Typ2
Max
Unit
Comment
16-bit differential mode
16-bit single-ended mode
T
EFS
—
—
+8/0
+12/0
+24/0
+24/0
LSB2
VADIN = VDDAD
13-bit differential mode
12-bit single-ended mode
T
—
—
0.7
0.7
2.0
2.5
11-bit differential mode
10-bit single-ended mode
T
—
—
0.4
0.4
1.0
1.0
9-bit differential mode
8-bit single-ended mode
T
—
—
0.2
0.2
0.5
0.5
16 bit modes
D
—
-1 to 0
—
—
—
0.5
—
—
—
—
—
13.5
13.4
13.2
13
12.6
—
—
—
—
—
—
—
—
—
—
12.39
12.34
12.13
11.94
11.4
—
—
—
—
—
Characteristic
Full-Scale
Error
Quantization
Error
Effective
Number of Bits
EQ
<13 bit modes
16 bit differential mode
Avg = 32
Avg = 16
Avg = 8
Avg = 4
Avg = 1
C
ENOB
16 bit single-ended mode
Avg = 32
Avg = 16
Avg = 8
Avg = 4
Avg = 1
Signal to Noise
plus Distortion
See ENOB
Total Harmonic
Distortion
16-bit differential mode
Avg = 32
C
16-bit single-ended mode
Avg = 32
D
16-bit differential mode
Avg = 32
C
16-bit single-ended mode
Avg = 32
D
Input Leakage
Error
all modes
D
EIL
Temp Sensor
Slope
–40C–25C
D
m
Temp Sensor
Voltage
25C
Spurious Free
Dynamic
Range
SINAD
D
Bits
SINAD = 6.02  ENOB + 1.76
THD
VTEMP25
For
ADC_DIV=1,
ADC_CLK=10
MHz.
dB
dB
—
—
—
—
—
—
91.0
96.5
—
—
—
—
SFDR
25C–125C
LSB2
dB
IIn * RAS
mV
—
1.646
—
—
1.769
—
—
966
—
IIn = leakage
current
(refer to DC
characteristics)
mV/C
mV
MC9S08GW64 Series MCU Data Sheet, Rev. 3
38
Freescale Semiconductor
Electrical Characteristics
1
All accuracy numbers assume the ADC is calibrated with VREFH=VDDAD
Typical values assume VDDAD = 3.0 V, Temp = 25 C, fADCK=2.0MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
3
1 LSB = (VREFH–VREFL)/2N
2
3.13
VREF Characteristics
Table 20. Electrical specifications
Num
C
1
P
2
3
Characteristic
Symbol
Min
Max
Unit
Supply voltage
VDD
1.80
3.60
V
P
Operating temperature range
Top
–40
85
C
C
Maximum Load
10
mA
Operation across Temperature
4
P
Voltage output room temperature
Untrimmed
1.070–1.3
V
5
P
Voltage output room temperature
Factory trimmed1
1.180–1.22
V
6
C
–40 °C
Factory trimmed
1.19–1.200
V
7
C
85 °C
Factory trimmed
1.185–1.200
V
Load Bandwidth
8
C
Load Regulation Mode = 10 at 1mA
load
9
C
Line Regulation (Power Supply
Rejection)
Mode = 10
20
100
V/mA
DC
±0.1 from room temp voltage
mV
AC
–60
dB
Power Consumption
1
10
C
Powered down Current (Stop Mode,
VREFEN = 0, VRSTEN = 0)
I
100
A
11
C
Bandgap only (Mode[1:0] 00)
I
75
A
12
C
Low Power buffer (Mode[1:0] 01)
I
125
A
13
C
Tight Regulation buffer (Mode[1:0] 10)
I
1.1
mA
14
C
Low Power and Tight Regulation
(Mode[1:0] 11)
I
1.15
mA
Factory trim is performed at the room temperature.
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
39
Electrical Characteristics
3.14
LCD Specifications
Table 21. LCD Electricals, 3-V Glass
C
Characteristic
Symbol
Min
28
D
LCD Frame Frequency
fFrame
D
LCD Charge Pump Capacitance
CLCD
D
LCD Bypass Capacitance
D
LCD Glass Capacitance
D
VIREG
HRefSel = 0
1
VIREG TRIM Resolution
D
VIREG Ripple
Max
Unit
30
58
Hz
100
100
nF
CBYLCD
100
100
nF
Cglass
2000
8000
pF
V
VIREG
HRefSel = 1
D
Typ
RTRIM
.89
1.00
1.15
1.49
1.67
1.851
1.5
%
VIREG
HRefSel = 0
.1
HRefSel = 1
.15
V
VIREG Max can not exceed VDD -0.15 V
3.15
FLASH Specifications
This section provides details about program/erase times and program-erase endurance for the FLASH memory.
Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed
information about program/erase operations, see the Memory section.
Table 22. FLASH Characteristics
C
Characteristic
Symbol
Min
Typical
Max
Unit
D
Supply voltage for program/erase
-40C to 85C
Vprog/erase
1.8
3.6
V
D
Supply voltage for read operation
VRead
1.8
3.6
V
fFCLK
150
200
kHz
tFcyc
5
6.67
s
frequency1
D
Internal FCLK
D
Internal FCLK period (1/FCLK)
P
P
P
P
D
D
2
Byte program time (random location)
Byte program time (burst
mode)2
tprog
9
tFcyc
tBurst
4
tFcyc
Page erase
time2
tPage
4000
tFcyc
Mass erase
time2
tMass
20,000
tFcyc
Byte program
Page erase
current3
current3
RIDDBP
—
4
—
mA
RIDDPE
—
6
—
mA
10,000
—
100,000
—
—
cycles
15
100
—
years
endurance4
1
C
Program/erase
TL to TH = –40C to + 85C
T = 25C
C
Data retention5
tD_ret
The frequency of this clock is controlled by a software setting.
MC9S08GW64 Series MCU Data Sheet, Rev. 3
40
Freescale Semiconductor
2
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied
for calculating approximate time to program and erase.
3
The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures
with VDD = 3.0 V, bus frequency = 4.0 MHz.
4
Typical endurance for FLASH was evaluated for this product family on the 9S12Dx64. For additional information on how
Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile
Memory.
5
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated
to 25C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please
refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
4
Ordering Information
This section contains the ordering information and the device numbering system for the MC9S08GW64 Series.
4.1
Device Numbering System
Example of the device numbering system:
MC 9 S08 GW 64
C XX
Status
(MC = Fully Qualified)
Package designator (see Table 23)
Temperature range
(C = –40C to 85C)
Memory
(9 = FLASH-based)
Core
Approximate FLASH size in KB
Family
5
Package Information and Mechanical Drawings
Table 23 provides the available package types and their document numbers. The latest package outline/mechanical drawings
are available on the MC9S08GW64 Series Product Summary pages at http://www.freescale.com.
To view the latest drawing, either:
•
•
Click on the appropriate link in Table 23, or
Open a browser to the Freescale® website (http://www.freescale.com), and enter the appropriate document number
(from Table 23) in the “Enter Keyword” search box at the top of the page.
Table 23. Package Descriptions
Pin Count
Package Type
Abbreviation
Designator
Case No.
Document No.
80
Low Quad Flat Package
LQFP
LK
917A
98ASS23237W
64
Low Quad Flat Package
LQFP
LH
840F
98ASS23234W
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Rev. 3
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