Freescale Semiconductor Data Sheet: Technical Data Document Number: MC9S08QA4 Rev. 3, 1/2009 MC9S08QA4 8-Pin DFN Case 1452-02 MC9S08QA4 Series Covers: MC9S08QA4 MC9S08QA2 Features: • 8-bit HCS08 Central Processor Unit (CPU) – Up to 20 MHz CPU at 3.6 V to 1.8 V across temperature range of –40°C to 85°C – HC08 instruction set with added BGND instruction – Support for up to 32 interrupt/reset sources • On-Chip Memory – Flash read/program/erase over full operating voltage and temperature – Random-access memory (RAM) – Security circuitry to prevent unauthorized access to RAM and flash contents • Power-Saving Modes – Two very low power stop modes – Peripheral clock enable register can disable clocks to unused modules, thereby reducing currents – Very low power real time counter for use in run, wait, and stop modes with internal clock sources • Clock Source Options – Internal Clock Source (ICS) — Internal clock source module containing a frequency-locked-loop (FLL) controlled by internal reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports bus frequencies from 1 MHz to 10 MHz • System Protection – Watchdog computer operating properly (COP) reset with option to run from dedicated 1 kHz internal clock source or bus clock – Low-voltage detection with reset or interrupt – Selectable trip points – Illegal opcode detection with reset – Illegal address detection with reset – Flash block protection • Development Support – Single-wire background debug interface 8-Pin PDIP Case 626-06 – Breakpoint capability to allow single breakpoint setting during in-circuit debugging • Peripherals – ADC — 4-channel, 10-bit resolution; 1.7 mV/°C temperature sensor; automatic compare function; internal bandgap reference channel; operation in stop3; fully functional from 3.6 V to 1.8 V – ACMP — Analog comparator with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal bandgap reference voltage; output can be tied internally to TPM input capture – TPM — One 1-channel timer/pulse-width modulator (TPM) module; selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel; ACMP output can be tied internally to input capture – MTIM — 8-bit modulo timer module with 8-bit prescaler – KBI — 4-pin keyboard interrupt module with software selectable polarity on edge or edge/level modes • Input/Output – Four GPIOs, one input-only pin and one output-only pin. – Hysteresis and configurable pullup device on all input pins; configurable slew rate and drive strength on all output pins except PTA5 • Package Options – 8-pin SOIC, PDIP, and DFN This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2008-2009. All rights reserved. 8-Pin NB-SOIC Case 751-07 Table of Contents 1 2 3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .5 3.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .5 3.4 ESD Protection and Latch-Up Immunity . . . . . . . . . . . . .6 3.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .10 3.7 Internal Clock Source (ICS) Characteristics . . . . . . . . .11 3.8 4 5 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.2 TPM/MTIM Module Timing . . . . . . . . . . . . . . . . 3.9 Analog Comparator (ACMP) Electricals . . . . . . . . . . . 3.10 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13 14 15 15 17 19 19 Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Revision Date Description of Changes 1 1/2008 Initial public release 2 2/2008 Changed the designator of the device in Table 15. 3 1/2009 Changed the condition of Run supply current measured to fBus = 1 MHz in Table 7. Fixed the error of inconsistent table number. Related Documentation Find the most current versions of all documents at: http://www.freescale.com Reference Manual (MC9S08QA4RM) Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information. MC9S08QA4 Series MCU Data Sheet, Rev. 3 2 Freescale Semiconductor MCU Block Diagram 1 MCU Block Diagram The block diagram, Figure 1, shows the structure of the MC9S08QA4 MCU. BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) BDC CPU TCLK HCS08 SYSTEM CONTROL PTA4/ACMPO/BKGD/MS COP IRQ LVD PORT A RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI PTA5//IRQ/TCLK/RESET 8-BIT MODULO TIMER MODULE (MTIM) PTA3/KBIP3/ADP3 PTA2/KBIP2/ADP2 4 8-BIT KEYBOARD INTERRUPT MODULE (KBI) ANALOG COMPARATOR (ACMP) USER FLASH (MC9S08QA4 = 4096 BYTES) (MC9S08QA2 = 2048 BYTES) ACMPO ACMP– ACMP+ PTA1/KBIP1/ADP1/ACMP– PTA0/KBIP0/TPMCH0/ADP0/ACMP+ 4 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) USER RAM (MC9S08QA4 = 256 BYTES) (MC9S08QA2 = 160BYTES) 16-BIT TIMER/PWM MODULE (TPM) TPMCH0 16 MHz INTERNAL CLOCK SOURCE (ICS) VSS VDD VOLTAGE REGULATOR VDDA VSSA VREFH VREFL NOTES: 1 Port pins are software configurable with pullup device if input port. 2 Port pins are software configurable for output drive strength. 3 Port pins are software configurable for output slew rate control. 4 IRQ contains a software configurable (IRQPDD) pullup device if PTA5 enabled as IRQ pin function (IRQPE = 1). 5 RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1). 6 PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1). 7 When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used to reconfigure the pullup as a pulldown device. Figure 1. MC9S08QA4 Series Block Diagram 2 Pin Assignments This section shows the pin assignments in the packages available for the MC9S08QA4 series. MC9S08QA4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 3 Pin Assignments Table 1. Pin Sharing Priority Priority PIN Lowest Highest 8-Pin Port Pin Alt 1 Alt 2 1 PTA51 IRQ TCLK 2 PTA4 ACMPO Alt 3 Alt 4 RESET BKGD MS 3 VDD 4 VSS 5 PTA3 KBIP3 ADP3 6 PTA2 KBIP2 ADP2 7 PTA1 KBIP1 8 PTA0 KBIP0 TPMCH0 ADP12 ACMP–2 ADP02 ACMP+2 1 Pin does not contain a clamp diode to VDD and must not be driven above VDD. The voltage measured on the internally pulled-up RESET pin will not be pulled to VDD. The internal gates connected to this pin are pulled to VDD. 2 If ACMP and ADC are both enabled, both will have access to the pin. PTA5/IRQ/TCLK/RESET 1 8 PTA0/KBIP0/TPMCH0/ADP0/ACMP+ PTA4/ACMPO/BKGD/MS 2 7 PTA1/KBIP1/ADP1/ACMP– VDD 3 6 PTA2/KBIP2/ADP2 VSS 4 5 PTA3/KBIP3/ADP3 8-Pin PDIP/SOIC PTA5/IRQ/TCLK/RESET 1 8 PTA0/KBIP0/TPMCH0/ADP0/ACMP+ PTA4/ACMPO/BKGD/MS 2 7 PTA1/KBIP1/ADP1/ACMP– VDD 3 6 PTA2/KBIP2/ADP2 VSS 4 5 PTA3/KBIP3/ADP3 8-Pin DFN Figure 2. MC9S08QA4 Series in 8-Pin Packages MC9S08QA4 Series MCU Data Sheet, Rev. 3 4 Freescale Semiconductor Electrical Characteristics 3 Electrical Characteristics 3.1 Introduction This chapter contains electrical and timing specifications for the MC9S08QA4 series of microcontrollers available at the time of publication. 3.2 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 2 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pullup resistor associated with the pin is enabled. Table 2. Absolute Maximum Ratings Rating Symbol Value Unit Supply voltage VDD –0.3 to 3.8 V Maximum current into VDD IDD 120 mA Digital input voltage VIn –0.3 to VDD + 0.3 V Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 ID ±25 mA Tstg –55 to 150 °C Storage temperature range 1 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to V SS and VDD. 3 Power supply must maintain regulation within operating V DD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). 3.3 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. MC9S08QA4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 5 Electrical Characteristics Table 3. Thermal Characteristics Rating Operating temperature range (packaged) Symbol Value Unit TA TL to TH –40 to 85 °C Thermal resistance Single-layer board 8-pin PDIP 113 θJA 8-pin NB SOIC 8-pin DFN 150 °C/W 179 Thermal resistance Four-layer board 8-pin PDIP 72 θJA 8-pin NB SOIC 8-pin DFN 87 °C/W 41 The average chip-junction temperature (TJ) in °C can be obtained from: TJ = TA + (PD × θJA) Eqn. 1 where: — — — — — TA = Ambient temperature, °C θJA = Package thermal resistance, junction-to-ambient, °C/W PD = Pint + PI/O Pint = IDD × VDD, Watts — chip internal power PI/O = Power dissipation on input and output pins — user-determined For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K ÷ (TJ + 273°C) Eqn. 2 Solving Equation 1 and Equation 2 for K gives: K = PD × (TA + 273°C) + θJA × (PD)2 Eqn. 3 where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA. 3.4 ESD Protection and Latch-Up Immunity Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the charge device model (CDM). MC9S08QA4 Series MCU Data Sheet, Rev. 3 6 Freescale Semiconductor Electrical Characteristics A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table 4. ESD and Latch-up Test Conditions Model Human Body Description Symbol Value Unit Series resistance R1 1500 Ω Storage capacitance C 100 pF Number of pulses per pin Machine 3 Series resistance R1 0 Ω Storage capacitance C 200 pF Number of pulses per pin 3 Minimum input voltage limit –2.5 V Maximum input voltage limit 7.5 V Latch-up Table 5. ESD and Latch-Up Protection Characteristics Rating1 No. 1 3.5 Symbol Min Max Unit 1 Human body model (HBM) VHBM ±2000 — V 2 Machine model (MM) VMM ±200 — V 3 Charge device model (CDM) VCDM ±500 — V 4 Latch-up current at TA = 85°C ILAT ±100 — mA Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. DC Characteristics This section includes information about power supply requirements and I/O pin characteristics. Table 6. DC Characteristics (Temperature Range = –40 to 85°C Ambient) Parameter Symbol Min Typical Max VDD 1.8 — 3.6 VLVDL (rising) — 3.6 VRAM Vpor1,2 — — VLVD 1.80 1.82 1.91 1.88 1.90 1.99 2.08 2.1 2.2 Unit Supply voltage (run, wait, and stop modes) (VDD falling) (VDD rising) Minimum RAM retention supply voltage applied to VDD V V Low-voltage detection threshold (VDD falling) (VDD rising) Low-voltage warning threshold (VDD falling) VLVW V V MC9S08QA4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 7 Electrical Characteristics Table 6. DC Characteristics (Temperature Range = –40 to 85°C Ambient) (continued) Parameter Symbol (VDD rising) Min Typical Max 2.16 2.19 2.27 Unit Power on reset (POR) re-arm voltage Vpor — 1.4 — V Bandgap voltage reference VBG 1.18 1.20 1.21 V 0.70 × VDD — — 0.85 × VDD — — — — 0.35 × VDD — — 0.30 × VDD Input high voltage (VDD > 2.3 V) (all digital inputs) Input high voltage (1.8 V ≤ VDD ≤ 2.3 V) (all digital inputs) Input low voltage (VDD > 2.3 V) (all digital inputs) Input low voltage (1.8 V ≤ VDD ≤ 2.3 V) (all digital inputs) VIH VIL V V Input hysteresis (all digital inputs) Vhys 0.06 × VDD — — V Input leakage current (per pin) VIn = VDD or VSS, all input-only pins |IIn| — 0.025 1.0 μA High impedance (off-state) leakage current (per pin) VIn = VDD or VSS, all input/output |IOZ| — 0.025 1.0 μA Internal pullup resistors3,4 RPU 17.5 — 52.5 kΩ Internal pulldown resistor (KBI) RPD 17.5 — 52.5 kΩ VDD – 0.5 — — VDD – 0.5 — — — — — — — — 60 — — 0.5 Output high voltage — low drive (PTxDSn = 0) IOH = –2 mA (VDD ≥ 1.8 V) Output high voltage — high drive (PTxDSn = 1) IOH = –10 mA (VDD ≥ 2.7 V) IOH = –6 mA (VDD ≥ 2.3 V) IOH = –3 mA (VDD ≥ 1.8 V) Maximum total IOH for all port pins VOH |IOHT| Output low voltage — low drive (PTxDSn = 0) IOL = 2.0 mA (VDD ≥ 1.8 V) V mA V Output low voltage — high drive (PTxDSn = 1) IOL = 10.0 mA (VDD ≥ 2.7 V) IOL = 6 mA (VDD ≥ 2.3 V) IOL = 3 mA (VDD ≥ 1.8 V) VOL Maximum total IOL for all port pins IOLT DC injection current 2, 5, 6, 7 VIn < VSS, VIn > VDD Single pin limit Total MCU limit, includes sum of all stressed pins IIC Input capacitance (all non-supply pins) CIn — — — — — — 0.5 0.5 0.5 — — 60 mA –0.2 –5 — — 0.2 5 mA mA — — 7 pF 1 RAM will retain data down to POR voltage. RAM data not guaranteed to be valid following a POR. This parameter is characterized and not tested on each device. 3 Measurement condition for pull resistors: V = V In SS for pullup and VIn = VDD for pulldown. 4 PTA5/IRQ/TCLK/RESET pullup resistor may not pull up to the specified minimum V . However, all ports are functionally tested IH to guarantee that a logic 1 will be read on any port input when the pullup is enabled and no DC load is present on the pin. 5 All functional non-supply pins are internally clamped to V SS and VDD. 2 MC9S08QA4 Series MCU Data Sheet, Rev. 3 8 Freescale Semiconductor Electrical Characteristics 6 Input must be current-limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 7 Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). PULLUP RESISTOR TYPICALS 85°C 25°C –40°C 35 PULLDOWN RESISTANCE (kΩ) PULLUP RESISTOR (kΩ) 40 30 25 20 1.8 2 2.2 2.4 2.6 2.8 VDD (V) 3 3.2 3.4 85°C 25°C –40°C 35 30 25 20 3.6 PULLDOWN RESISTOR TYPICALS 40 1.8 2.3 2.8 VDD (V) 3.3 3.6 Figure 3. Pullup and Pulldown Typical Resistor Values (VDD = 3.0 V) TYPICAL VOL VS IOL AT VDD = 3.0 V 1.2 1 0.15 VOL (V) 0.8 VOL (V) TYPICAL VOL VS VDD 0.2 85°C 25°C –40°C 0.6 0.4 0.2 0.1 85°C, IOL = 2 mA 25°C, IOL = 2 mA –40°C, IOL = 2 mA 0.05 0 0 0 5 10 IOL (mA) 15 1 20 2 VDD (V) 3 4 Figure 4. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0) TYPICAL VOL VS VDD TYPICAL VOL VS IOL AT VDD = 3.0 V 1 0.4 85°C 25°C –40°C 0.8 85°C 25°C –40°C 0.3 VOL (V) VOL (V) 0.6 0.4 0.2 0 0.2 IOL = 10 mA IOL = 6 mA 0.1 IOL = 3 mA 0 0 10 20 30 1 2 3 4 VDD (V) IOL (mA) Figure 5. Typical Low-Side Driver (Sink) Characteristics — High Drive (PTxDSn = 1) MC9S08QA4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 9 Electrical Characteristics TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V 1.2 85°C 25°C –40°C 85°C, IOH = 2 mA 25°C, IOH = 2 mA –40°C, IOH = 2 mA 0.2 VDD – VOH (V) VDD – VOH (V) 1 TYPICAL VDD – VOH VS VDD AT SPEC IOH 0.25 0.8 0.6 0.4 0.15 0.1 0.05 0.2 0 0 0 –5 –10 IOH (mA)) –15 –20 1 2 VDD (V) 3 4 Figure 6. Typical High-Side (Source) Characteristics — Low Drive (PTxDSn = 0) TYPICAL VDD – VOH VS VDD AT SPEC IOH 0.4 TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V 85°C 25°C –40°C 0.6 0.3 VDD – VOH (V) VDD – VOH (V) 0.8 0.4 0.2 0 0 –5 –10 –15 –20 IOH (mA) 85°C 25°C –40°C –25 0.2 IOH = –10 mA IOH = –6 mA 0.1 IOH = –3 mA 0 –30 1 2 3 4 VDD (V) Figure 7. Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1) 3.6 Supply Current Characteristics This section includes information about power supply current in various operating modes. Table 7. Supply Current Characteristics Parameter current3 Run supply fBus = 8 MHz current3 Run supply fBus = 1 MHz Symbol measured in FBE mode at measured in FBE mode at Wait mode supply current4 measured in FBE at 8 MHz Stop1 mode supply current RIDD RIDD WIDD S1IDD Stop2 mode supply current S2IDD Stop3 mode supply current S3IDD RTI adder to stop1, stop2, or stop34 — LVD adder to stop3 (LVDE = LVDSE = 1)4 — VDD (V)1 Typical2 Max T (°C) 3 3.5 mA 5 mA 85 2 2.6 mA — 85 3 490 μA 1 mA 85 2 370 μA — 85 3 1 mA 1.5 mA 85 3 475 nA 1.2 μA 85 2 470 nA — 85 3 600 nA 2 μA 85 2 550 nA — 85 3 750 nA 6 μA 85 2 680 nA — 85 3 300 nA — 85 2 300 nA — 85 3 70 μA — 85 2 60 μA — 85 MC9S08QA4 Series MCU Data Sheet, Rev. 3 10 Freescale Semiconductor Electrical Characteristics 1 3 V values are 100% tested; 2 V values are characterized but not tested. Typicals are measured at 25 °C. 3 Does not include any DC loads on port pins. 4 Most customers are expected to find that auto-wakeup from a stop mode can be used instead of the higher current wait mode. 2 3.7 Internal Clock Source (ICS) Characteristics Table 8. ICS Specifications (Temperature Range = –40 to 85°C Ambient) Symbol Min Typical1 Max Unit Internal reference start-up time tIRST — 60 100 μs Average internal reference frequency — untrimmed fint_ut 25 32.7 41.66 kHz Average internal reference frequency — trimmed fint_t 31.25 — 39.06 kHz DCO output frequency range — untrimmed fdco_ut 12.8 16.8 21.33 MHz DCO output frequency range — trimmed fdco_t 16 — 20 MHz Δfdco_res_t — ±0.1 ±0.2 %fdco Total deviation of DCO output from trimmed frequency2 At 8 MHz over full voltage and temperature range At 8 MHz and 3.6 V from 0 to 70 °C Δfdco_t — –1.0 to 0.5 ±0.5 ±2 ±1 %fdco FLL acquisition time 2,3 tAcquire — — 1.5 ms Long term jitter of DCO output clock (averaged over 2 ms interval) CJitter — 0.02 0.2 %fdco Characteristic Resolution of trimmed DCO output frequency at fixed voltage and temperature2 Data in Typical column was characterized at 3.0 V, 25 °C, or is typical recommended value. This parameter is characterized and not tested on each device. 3 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed. 1 2 MC9S08QA4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 11 Electrical Characteristics 0.250% 0.200% 0.150% 0.100% DEVIATION 0.050% 0.000% –0.050% 1.6 2.1 2.6 3.1 3.6 VDD Figure 8. Deviation of DCO Output from Trimmed Frequency (8 MHz, 25 °C) 3.8 AC Characteristics This section describes timing characteristics for each peripheral system. MC9S08QA4 Series MCU Data Sheet, Rev. 3 12 Freescale Semiconductor Electrical Characteristics 3.8.1 Control Timing Table 9. Control Timing Symbol Min Typical1 Max Unit Bus frequency (tcyc = 1/fBus) fBus 0 — 10 MHz Real-time interrupt internal oscillator period (see Table 9) tRTI 700 1000 1300 μs textrst 100 — — ns Asynchronous path2 Synchronous path3 tILIH 100 1.5 tcyc — — ns Asynchronous path2 Synchronous path3 tILIH, tIHIL 100 1.5 tcyc — — ns Port rise and fall time (load = 50 pF)4 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) tRise, tFall — — 3 30 — — ns tMSSU 500 — — ns tMSH 100 — — μs Parameter External reset pulse width 2 IRQ pulse width KBIPx pulse width BKGD/MS setup time after issuing background debug force reset to enter user or BDM modes BKGD/MS hold time after issuing background debug force reset to enter user or BDM modes5 1 Data in Typical column was characterized at 3.0 V, 25°C. This is the shortest pulse that is guaranteed to be recognized. 3 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 4 Timing is shown with respect to 20% V DD and 80% VDD levels. Temperature range –40°C to 85°C. 5 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t MSH after VDD rises above VLVD. 2 1600 1400 1200 = +3 σ = Mean = –3 σ 1000 Period (μs) 800 600 400 200 0 –40 –40 0 20 40 Temperature (°C) 60 80 100 Figure 9. Typical RTI Clock Period vs. Temperature MC9S08QA4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 13 Electrical Characteristics textrst RESET PIN Figure 10. Reset Timing tIHIL KBIPx IRQ/KBIPx tILIH Figure 11. IRQ/KBIPx Timing 3.8.2 TPM/MTIM Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 10. TPM/MTIM Input Timing Function Symbol Min Max Unit External clock frequency fTCLK 0 fBus/4 Hz External clock period tTCLK 4 — tcyc External clock high time tclkh 1.5 — tcyc External clock low time tclkl 1.5 — tcyc tICPW 1.5 — tcyc Input capture pulse width tTCLK tclkh TCLK tclkl Figure 12. Timer External Clock MC9S08QA4 Series MCU Data Sheet, Rev. 3 14 Freescale Semiconductor Electrical Characteristics tICPW TPMCHn TPMCHn tICPW Figure 13. Timer Input Capture Pulse 3.9 Analog Comparator (ACMP) Electricals Table 11. Analog Comparator Electrical Specifications Characteristic Symbol Min Typical Max Unit VDD 1.80 — 3.60 V Supply current (active) IDDAC — 20 — μA Analog input voltage VAIN VSS – 0.3 — VDD V Analog input offset voltage VAIO — 20 40 mV Analog comparator hysteresis VH 3.0 9.0 15.0 mV Analog input leakage current IALKG — — 1.0 μA Analog comparator initialization delay tAINIT — — 1.0 μs Supply voltage 3.10 ADC Characteristics Table 12. 3 V 10-Bit ADC Operating Conditions Symbol Min Typical1 Max Unit VDD 1.8 — 3.6 V Input voltage VADIN VSS — VDD V Input capacitance CADIN — 4.5 5.5 pF Input resistance RADIN — 5 7 kΩ RAS — — — — 5 10 kΩ — — 10 0.4 — 8.0 0.4 — 4.0 Characteristic Supply voltage Analog source resistance Conditions Absolute 10 bit mode fADCK > 4 MHz fADCK < 4 MHz 8 bit mode (all valid fADCK) ADC conversion clock frequency 1 High Speed (ADLPC=0) Low Power (ADLPC=1) fADCK Comment External to MCU MHz Typical values assume VDD = 3.0 V, Temp = 25°C, fADCK =1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. MC9S08QA4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 15 Electrical Characteristics SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Pad leakage due to input protection ZAS RAS ADC SAR ENGINE RADIN + VADIN VAS + – – CAS RADIN INPUT PIN RADIN INPUT PIN RADIN INPUT PIN CADIN Figure 14. ADC Input Impedance Equivalency Diagram Table 13. 3 V 10-Bit ADC Characteristics Symbol Min Typical1 Max Unit Supply current ADLPC = 1 ADLSMP = 1 ADCO = 1 IDDAD — 120 — μA Supply current ADLPC = 1 ADLSMP = 0 ADCO = 1 IDDAD — 202 — μA Supply current ADLPC = 0 ADLSMP = 1 ADCO = 1 IDDAD — 288 — μA Supply current ADLPC = 0 ADLSMP = 0 ADCO = 1 IDDAD — 532 646 μA 2 3.3 5 Characteristic ADC asynchronous clock source Conditions High speed (ADLPC=0) Low power (ADLPC=1) fADACK MHz 1.25 2 3.3 Comment tADACK = 1/fADACK MC9S08QA4 Series MCU Data Sheet, Rev. 3 16 Freescale Semiconductor Electrical Characteristics Table 13. 3 V 10-Bit ADC Characteristics (continued) Characteristic Conversion time (including sample time) Conditions Symbol Short sample (ADLSMP=0) Long sample (ADLSMP=1) tADC Short sample (ADLSMP=0) Sample time Long sample (ADLSMP=1) tADS 10-bit mode Total unadjusted error ETUE 8-bit mode 10-bit mode Differential non-linearity 10-bit mode Max — 20 — — 40 — — 3.5 — — 23.5 — — ±1.5 ±3.5 — ±0.7 ±1.5 — ±0.5 ±1.0 — ±0.3 ±0.5 — ±0.5 ±1.0 — ±0.3 ±0.5 — ±1.5 ±2.1 — ±0.5 ±0.7 0 ±1.0 ±1.5 0 ±0.5 ±0.5 — — ±0.5 — — ±0.5 0 ±0.2 ±4 0 ±0.1 ±1.2 — 1.646 — — 1.769 — — 701.2 — INL 8-bit mode 10-bit mode Zero-scale error EZS 8-bit mode 10-bit mode Full-scale error EFS 8-bit mode 10-bit mode Quantization error EQ 8-bit mode 10-bit mode Input leakage error EIL 8-bit mode Temp sensor voltage Typical1 DNL 8-bit mode Integral non-linearity Temp sensor slope Min –40°C – 25°C m 25°C – 85°C 25°C VTEMP25 Unit ADCK cycles ADCK cycles Comment See MC9S08QA4 Series Reference Manual for conversion time variances LSB2 Includes quantization LSB2 Monotonicity and no missing codes guaranteed LSB2 LSB2 VADIN = VSS LSB2 VADIN = VDD LSB2 LSB2 Pad leakage3 * RAS mV/°C mV 1 Typical values assume VDD = 3.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (V N REFH – VREFL)/2 3 Based on input pad leakage current. Refer to pad electricals. 3.11 Flash Specifications This section provides details about program/erase times and program-erase endurance for the flash memory. MC9S08QA4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 17 Electrical Characteristics Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see MC9S08QA4 Series Reference Manual. Table 14. Flash Characteristics Characteristic Symbol Min Typical Max Unit Supply voltage for program/erase –40°C to 85°C Vprog/erase 1.8 — 3.6 V Supply voltage for read operation VRead 1.8 — 3.6 V fFCLK 150 — 200 kHz tFcyc 5 — 6.67 μs Internal FCLK frequency 1 Internal FCLK period (1/FCLK) Byte program time (random location)2 tprog 9 tFcyc 2 Byte program time (burst mode) tBurst 4 tFcyc 2 tPage 4000 tFcyc time2 tMass 20,000 tFcyc Page erase time Mass erase endurance3 Program/erase TL to TH = –40°C to + 85°C T = 25°C Data retention4 tD_ret 10,000 — 100,000 — — cycles 15 100 — years 1 The frequency of this clock is controlled by a software setting. These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how Motorola defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile Memory. 4 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory. 2 MC9S08QA4 Series MCU Data Sheet, Rev. 3 18 Freescale Semiconductor Ordering Information 4 Ordering Information This section contains ordering numbers for MC9S08QA4 series devices. See below for an example of the device numbering system. Table 15. Device Numbering System Memory Package Device Number Flash RAM Type Designator Document No. MC9S08QA4 4 KB 256 bytes MC9S08QA2 2 KB 160 bytes 8 DFN 8 PDIP 8 NB SOIC FQ PA DN 98ARL10557D 98ASB42420B 98ASB42564B MC 9 S08 QA 4 C XX E RoHS compliance indicator (E = yes) Package designator (see Table 15) Status (MC = Fully qualified) Memory (9 = Flash-based) Core Temperature range (C = –40°C to 85°C) Family 5 Memory size (in KB) Mechanical Drawings The following pages contain mechanical specifications for MC9S08QA4 series package options. • • • 8-pin DFN (plastic dual in-line pin) 8-pin NB SOIC (narrow body small outline integrated circuit) 8-pin PDIP (plastic dual in-line pin) MC9S08QA4 Series MCU Data Sheet, Rev. 3 Freescale Semiconductor 19 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 firstname.lastname@example.org Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 email@example.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Document Number: MC9S08QA4 Rev. 3 1/2009 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. 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