AN-928: Understanding High Speed DAC Testing and Evaluation (Rev. B)

AN-928
APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Understanding High Speed DAC Testing and Evaluation
by Justin Munson
SCOPE
This application note describes the test methods used by the
Analog Devices, Inc., High Speed Converters group to
characterize the performance of high speed digital-to-analog
converters (DAC). This application note should be used as a
reference when evaluating a high speed DAC in conjunction with
the appropriate device data sheet. For further information,
contact the High Speed Converters group.
The DPG2 provides up to 512 MB of RAM to allow for
complex waveform generation. There is also the capability to
synchronize up to four DPG2s together using a HSC-DACDPG-CLKDIS board, along with one Samtec HQCD-03015.00-TED-TEU-1 cable for each DPG2.
PC
DYNAMIC TEST HARDWARE SETUP
DATA
CLOCKS
DATA
CLOCKS
FPGA
DELAY
EVALUATION BOARD
CONNECTOR
CMOS
CLOCK INPUT
06902-102
SDRAM
SDRAM
USB CONTROLLER
The typical hardware setup for testing alternating current (ac)
conditions such as spurious-free dynamic range (SFDR),
intermodulation distortion (IMD), and noise spectral density
(NSD) is shown in Figure 1. The basic setup for the dynamic
testing includes a sine source for the DAC clock, low noise
power supplies, a spectrum analyzer, and a data pattern
generator. Various types of pattern generators can be used to
drive either CMOS or LVDS data into the DACs, ranging from
arbitrary waveform generators (AWG) to field programmable
gate arrays (FPGA). Analog Devices also provides a data pattern
generator to aid in the bench evaluation.
Figure 2. DPG2 Block Diagram
CLOCK SOURCE
EITHER USE PULSE GENERATOR
OR DATA
CLOCK OUT TO CLOCK DPG
SPECTRUM
ANALYZER
PULSE
GENERATOR
DATA CLOCK OUT
DAC
PATTERN
GENERATOR
16
TxDAC®
EVALUATION
BOARD
06902-001
USB
06902-103
Figure 1. Typical AC Characterization Test Setup
DATA PATTERN GENERATOR 2 (DPG2)
The data pattern generator 2 (DPG2) is designed to simplify
the evaluation of Analog Devices high speed DAC products.
A block diagram of the DPG2 is shown in Figure 2. The DPG2
provides two channels of 16-bits each and supports both
LVDS and CMOS standards. The maximum sample rate on
each channel in LVDS mode is 1.25 GSPS and 250 MSPS in
CMOS mode.
Figure 3. DPG Board
Software is provided with the DPG2 to allow the user to
generate single- and multitone sine waves, various CMTS
waveforms, various WIFR standards, and static dc patterns
as well as to load a user-generated pattern.
Rev. B | Page 1 of 24
AN-928
Application Note
TABLE OF CONTENTS
Understanding High Speed DAC Testing and Evaluation .......... 1
Crosstalk ...................................................................................... 16
Scope .................................................................................................. 1
Sinx/x Roll-Off............................................................................ 16
Dynamic Test Hardware Setup ....................................................... 1
DC Test Definitions ....................................................................... 17
Data Pattern Generator 2 (DPG2) .................................................. 1
Full-Scale Gain............................................................................ 17
Revision History ............................................................................... 2
Gain Error ................................................................................... 17
Equipment for DAC Bench Setup .................................................. 3
Offset ............................................................................................ 17
DPG Downloader Software Suite ............................................... 3
Offset Error ................................................................................. 17
DAC Clock Signal Source ............................................................ 7
Temperature Drift ...................................................................... 18
Spectrum Analyzer ....................................................................... 7
Power Supply Rejection Ratio .................................................. 18
Digital Multimeter........................................................................ 7
Gain Matching ............................................................................ 18
Power Supplies .............................................................................. 7
Linearity ....................................................................................... 18
AC Test Definitions .......................................................................... 8
Integral Nonlinearity Error ....................................................... 18
Single-Tone, In-Band, Spurious-Free Dynamic Range ........... 8
Differential Nonlinearity Error ................................................ 18
Out-of-Band, Spurious-Free Dynamic Range .......................... 9
Monotonicity............................................................................... 18
Total Harmonic Distortion (THD) ............................................ 9
Digital Input Timing ...................................................................... 21
Two-Tone Intermodulation Distortion ..................................... 9
Setup Time .................................................................................. 21
Noise Spectral Density ............................................................... 12
Hold Time ................................................................................... 21
Adjacent Channel Leakage Ratio or Adjacent Channel Power
Ratio ............................................................................................. 15
Keep-Out Window ..................................................................... 21
REVISION HISTORY
10/13—Rev. 0 to Rev. A
Changes to Scope Section ................................................................ 1
Changes to Power Supplies Sections .............................................. 7
11/10—Rev. 0 to Rev. A
Replaced DPG with DPG2 Throughout .......................... Universal
Replaced Figures Throughout......................................................... 1
Replaced LabVIEW Executables for Vector Generation
Section with DPG Downloader Software Suite Section .............. 3
Changes to Power Supplies Section................................................ 7
3/08—Revision 0: Initial Version
Rev. B | Page 2 of 24
Application Note
AN-928
EQUIPMENT FOR DAC BENCH SETUP
This section discusses the hardware and software required to
properly characterize high speed DACs.
Analog Devices provides a DPG2 to aid in the bench evaluation.
Patterns to exercise the DAC can be generated by using the
DPG Downloader software suite provided with the DPG2.
DPG DOWNLOADER SOFTWARE SUITE
To evaluate a DAC properly, a user must be able to generate
single- and multitone continuous wave (CW) patterns, as well
as patterns for various communication standards. All of the
patterns can be generated using the DPG Downloader software.
The user interface for the DPG Downloader is shown below in
Figure 4.
The DPG Downloader can automatically determine which
evaluation board is connected and configure the correct data
port configuration via the USB cable connected to each
evaluation board. The software also detects the data clock
frequency, which is either transmitted across the data bus
connector for LVDS interfaces, or through the SMA connectors
for CMOS interfaces (J12 or J13 on the DPG2 main board).
Single Tone
Upon selecting the Single Tone option from the menu, a single
tone vector block appears as shown in Figure 5. The variables
that are adjustable for this vector are as follows:
•
Sample Rate
•
Desired Frequency
•
DAC Resolution
•
Record Length—must be divisible by 256
•
Offset—constant offset added to every code generated
•
Amplitude
•
Relative Phase— can be used if generating I and Q vectors
Multi-Tone
Upon selecting the Multi-Tone option from the menu, a multi
tone vector block appear as shown in Figure 6. The multi-tone
generation has many of the same variables as the single tone
block. The main difference between the two functions is that
the Add Tone button is selected (circled in Figure 6) to specify
the number of tones, tone spacing, and start frequency.
06902-104
All of the available waveforms that can be generated via this
software can be found under the Add Generated Waveform
pull-down menu as shown in Figure 4. A user can also load
their own generated vector via the Add Data File option
found in the top left corner. The following sections describe
the steps to generate each of the vectors in the Add Generated
Waveform menu.
Figure 4. DPG Downloader Front Panel Interface
Rev. B | Page 3 of 24
Application Note
06902-105
AN-928
06902-106
Figure 5. Single Tone Vector Generation
Figure 6. Multi-Tone Vector Generation
DC Pattern
Noise Generator
The dc pattern option allows the user to load in a constant
static value or a pattern of alternating values and zeros. The dc
pattern generator block is shown in Figure 7.
The noise generator function allows the user to generate a
pattern for various types of random noise patterns such as
Gaussian, uniform, or white noise. The noise generator block
is shown in Figure 8.
Rev. B | Page 4 of 24
AN-928
06902-107
Application Note
06902-108
Figure 7. DC Vector Generation
Figure 8. Noise Vector Generation
Rev. B | Page 5 of 24
AN-928
Application Note
Wireless Infrastructure
The cable infrastructure block is shown in Figure 9. This block
allows the user to create various CMTS vectors using the
standard pull-down menu, such as US64QAM, US256QAM,
US64QAM, and EU256QAM. The symbol rate is automatically
selected depending on which standard is chosen. The user can
also select the number of channels to be generated in the vector.
The wireless infrastructure block is shown in Figure 10. This
block allows the user to create various WIFR vectors using
the standard pull-down menu, such as WCDMA, GSM,
and CDMA2K. The carrier spacing is automatically selected
depending on which standard is chosen. As was the case with
the CIFR block, the user can select the number of carriers to
be generated.
06902-109
Cable Infrastructure
06902-110
Figure 9. Cable Infrastructure Vector Generation
Figure 10. Wireless Infrastructure Vector Generation
Rev. B | Page 6 of 24
Application Note
AN-928
Depending on the clock speed and desired performance, the
dynamic test setup uses either an Agilent E4426B ESG-AP/8644
or a Rohde & Schwarz SML01/SML02/SMA100A generator to
provide the clock for the DAC. These generators can provide
clock frequencies from several kHz to several GHz depending
on the DAC under test.
All of these sources provide very low phase noise and good jitter
performance. The phase noise, especially at offsets further away
from the carrier frequency (5 MHz to 10 MHz), has a large
impact on the overall achievable noise performance of the DAC.
Some sine sources can provide exceptional noise performance at
lower frequencies and worse performance at higher frequencies or
vice versa. For more information on the impact of the phase
noise of the sine source on the noise performance of the DAC,
see the Noise Spectral Density section.
SPECTRUM ANALYZER
The 3458A offers up to 8.5 digits of resolution and various
range settings (5 ranges for dc volts: 0.1 V to 1000 V and
8 ranges for dc current: 100 nA to 1 A), making it ideal for
measuring the offset of the DAC or DAC segments in the nA
to µA region. The Agilent 3458A can be used to measure the
direct current out of the DAC, or an external current to voltage
converter (I-V) circuit can be used to measure voltage rather
than current. The I-V circuit used for dc testing is shown in
Figure 11. The overall gain of this circuit is 100; a 20 mA full-scale
(FS) current converts to a 2 V signal.
R19
100kΩ
0.1µF
IOUTX
4 OP27
–V
R15
33kΩ
2 U2
6
3 +V
7
0.1µF
+15V
To analyze the dynamic performance of the DAC, a spectrum
analyzer is employed. The two analyzers used by Analog
Devices to characterize the DACs are the Agilent E4443A PSA
spectrum analyzer and the Rohde & Schwarz FSEA30 spectrum
analyzer.
The harmonic distortion of the analyzer is also important when
measuring the spurious performance of the DAC. The harmonic
performance of the analyzer depends on several settings: the
settings of the RF attenuation, resolution BW, and reference
level, as well as the setting of the input level of the CW signal
being measured. If the spurious performance of the DAC is
lower than the HD2 and HD3 of the analyzer for a specified
setting, external methods must be employed to properly measure
the performance of the part. For more information about
optimizing the spectrum analyzer for harmonic measurements,
see the Single-Tone, In-Band, Spurious-Free Dynamic Range
section.
DIGITAL MULTIMETER
A digital multimeter (DMM) measures the majority of the
direct current (dc) parameters for the DAC. The Agilent 3458A
is a good choice when trying to measure direct current
parameters with precise accuracy.
+15V
R16
100kΩ
R17
49.9kΩ
C28
4700pF
7
3 +V
6
2 U3
–V
AD811
4 C31
0.1µF
–15V
R18
49.9kΩ
S4
R21
R20 652kΩ
47kΩ
Figure 11. I-V Converter Circuit
POWER SUPPLIES
It is important to provide clean, quiet power supplies to
optimize the alternating current (ac) performance and lower
the power supply rejection ratio (PSRR) for DACs.
Two solutions can be employed on a DAC evaluation board:
direct power using an Agilent E3631A programmable triple
output power supply or regulated power supplies using the
ADP3333, ADP3338, and ADP3339 LDO regulators. The ADP
series regulators provide very low noise and well regulated
sources for a variety of supply voltages.
The typical application circuit for the ADP3339 is shown in
Figure 12.
ADP3339
VIN
OUT
IN
1µF
10µH
OUT
22µF
+
1µF
VOUT
0.1µF
GND
06902-011
The Agilent PSA has many features that make it ideal for DAC
dynamic testing, including adjacent channel power ratio
(ACPR) measurement capability, channel power measurement
used to measure noise spectral density (NSD), phase noise
measurement capability, demodulation functions, and optional
personalities for various wireless communication standards.
The PSA also has an optional internal preamplifier to aid in
measuring NSD. For more information on this function, see the
Noise Spectral Density section.
C30
0.1µF
–15V
06902-010
DAC CLOCK SIGNAL SOURCE
Figure 12. ADP3339 Typical Application Circuit
Another option to supply power to a high speed converter is
to use dc-to-dc converters in place of the linear regulators. If
proper care is taken with power supply decoupling, dc-to-dc
converters can provide the same level of spectral purity with
greater efficiency than linear regulators. For more information
on this topic, see the AN-1213 Application Note, Powering the
AD9788 800 MSPS TxDAC Digital-to-Analog Converter Using
the ADP2105 Synchronous Step-Down DC-to-DC Regulator for
Increased Efficiency.
Rev. B | Page 7 of 24
AN-928
Application Note
AC TEST DEFINITIONS
AC testing is usually made with the analog signal at about 0 dBm,
which for most of the DACs in the portfolio is done using an
analog full-scale value of approximately 20 mA. For DACs with
adjustable full-scale currents via either an external resistor or
internal gain adjust DAC, testing is performed at various gain
values to determine how the performance of the parts scales
with the analog output power. Testing is also performed with
respect to temperature and analog supply voltage. Consult the
specific device data sheet to determine the test conditions under
which the ac testing is performed.
REF 0dBm
PEAK LOG 10dB/
ATTEN 30dB
MKR1 20.06MHz
–79.57dBm
1
The spurious-free dynamic range (SFDR) is the difference, in
dBc, between the peak amplitude of the output signal and the
peak spurious signal over the specified Nyquist bandwidth.
Typically, the dominating spur is a harmonic, usually the
second or third harmonic of the input signal. The major
problem that arises when measuring the SFDR for a DAC is
optimizing the spectrum analyzer to measure the true harmonic
performance of the DAC and not of the spectrum analyzer itself.
In Figure 13, RF attenuation is set to 30 dB. Note that it is
obvious that RF attenuation is too high, which causes the mixer
level internal to the analyzer to be too low. This setting causes
the signal-to-noise ratio of the input signal to be unnecessarily
reduced.
Setting RF attenuation to 20 dB (see Figure 14) causes the
analyzer to add unwanted distortion to the measurement and
causes over-loading of the input mixer stage. This means that
the true harmonic performance of the DAC is not being
measured.
STOP 50.00MHz
SWEEP 2.313s (601pts)
Figure 13. DAC Output with 30 dB RF Attenuation
REF 0dBm
PEAK LOG 10dB/
ATTEN 20dB
MKR1 20.06MHz
–71.46dBm
1
START 100kHz
RES BW 5.1kHz
VBW 5.1kHz
STOP 50.00MHz
SWEEP 2.313s (601pts)
Figure 14. DAC Output with 20 dB RF Attenuation
Optimization of RF attenuation is especially key when
measuring spurious performance in the 80 dBc to 100 dBc
range. At these levels, the spurious performance of the DAC is
usually better than the spurious performance of the analyzer
itself at the specified RF attenuation setting. One way to ensure
that the analyzer is measuring the true performance of the DAC
converter is to use a notch filter between the converter output
and the spectrum analyzer as shown in Figure 15. Using a notch
filter allows the user to bring the RF attenuation level down to
zero (because the signal level out of the notch is attenuated by
almost 60 dB) and to bring the reference level down to zoom in
closer to the actual harmonics.
MINI-CIRCUITS
ADT1-1WT
1:1
IOUT
CMOS
DAC
Rev. B | Page 8 of 24
RDIFF
= 100Ω
6dB
ATTENTUATION
NOTCH
FILTER
SPECTRUM
ANALYZER
IOUT
Figure 15. SFDR Measurement Configuration Using a Notch Filter
06902-014
RF attenuation is the key parameter when measuring the
harmonics of a DAC, especially in the presence of a full-scale
single-tone sine wave. Figure 13 and Figure 14 show the DAC
synthesizing a 10 MHz sine wave, with two different settings for
RF attenuation.
VBW 5.1kHz
06902-013
Several controls on the spectrum analyzer can be used to try to
optimize the measurement: RF attenuation, reference level, and
sweep time. RF attenuation, the most critical parameter, optimizes the input level into the first mixer stage of the spectrum
analyzer to avoid overloading the mixer stage and causing
unwanted distortion. The reference level controls the IF gain
stage after the mixer. This is coupled to the RF attenuation, but
changing the reference level does not affect the signal level at
the input of the mixer, only on the display. The final parameter
is the sweep generator, which is controlled by the resolution
bandwidth and sweep time. These parameters optimize the time
it takes to take the measurement and have an effect on how
accurately one can measure the true noise floor of the DAC.
START 100kHz
RES BW 5.1kHz
06902-012
SINGLE-TONE, IN-BAND, SPURIOUS-FREE
DYNAMIC RANGE
Application Note
AN-928
Before using the notch filter to measure the harmonics, it is
necessary to calibrate out the loss in the filter at the frequency
of the harmonics. This can be done by applying a 0 dBm sine
wave at the frequency of each harmonic into the 6 dB pad and
the notch filter and then recording the loss at the output of the
notch filter. This value can then be factored out of the measured
harmonic value to determine the actual amplitude for each
harmonic. Figure 16 shows the output of the 6 dB pad and
10 MHz notch filter with a 0 dBm 20 MHz signal applied to the
input. The overall loss through the pad and the notch filter is
6.01 dBm, so there is little or no loss in the notch filter itself at
the frequency of the harmonic.
REF 0dBm
PEAK LOG 10dB/
ATTEN 20dB
SPAN 5MHz
SWEEP 6.029s (601pts)
Figure 16. Calibration of Loss in the 6 dB Pad and Notch Filter
Figure 17 shows the converter output with the notch filter in place.
The actual harmonic value measured is −87.5 dB. Once the 6 dB
attenuation is added back in, the actual level of the highest spur is
−81.5 dB. Without the notch filter and 20 dB RF attenuation, this
spur measures at −71.5 dB, which is a difference of 10 dB, caused by
distortion in the analyzer not by the DAC itself.
REF –30dBm
PEAK LOG 10dB/
ATTEN 0dB
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured fundamental.
2F1±F2 and 2F2±F1
The terms 2F1±F2 and 2F2±F1 represent the third-order intermodulation distortion (IMD) products of the DAC when
synthesizing two coherent tones. The third-order IMD performance is the worst-case ratio of the peak value of each term to the
peak value of one of the two input tones. The minus terms in the
third-order IMD products are very important; depending on the
spacing of the two tones, the intermodulation products fall very
close to the desired signals. This necessitates a very steep and often
expensive band-pass filter if the intermodulation products are too
high. The typical spacing for two tones for IMD testing is 1 MHz.
06902-015
VBW 1kHz
For converters with interpolation filters, this range is between
the Nyquist frequency of the input data rate and the Nyquist
frequency of the DAC update rate. Typically, energy in this
band is rejected by the interpolation filters. This specification,
therefore, defines how well the interpolation filters work and
the effect of other parasitic coupling paths on the DAC output.
TWO-TONE INTERMODULATION DISTORTION
MKR1 19.967MHz
–6.01dBm
1
CENTER 20MHz
RES BW 1kHz
within the band that starts at the Nyquist frequency of the input
data rate and ends at the frequency of the DAC output sample rate.
MKR1 20.06MHz
–87.55dBm
3F1±2F2 and 3F2 ±2F1
The terms 3F1±2F2 and 3F2±2F1 represent the fifth-order IMD
products of the DAC. Because these terms are usually smaller in
amplitude than the third-order IMD products, and are further
away from the desired signals, they do not usually represent
such a significant impact on performance. Figure 18 through
Figure 21 show a typical DAC two-tone output spectrum and its
IMD products. To adequately measure the IMD products, it is
necessary to reduce the frequency span and change both the
reference level and RF attenuation because they are not visible
with the spectrum analyzer settings in the presence of the two
tones, as can be seen in Figure 18.
REF 0dBm
AVG LOG 10dB/
ATTEN 30dB
MKR2 70.997MHz
–10.358dBm
2
1
START 100kHz
RES BW 5.1kHz
VBW 5.1kHz
STOP 50.00MHz
SWEEP 2.313s (601pts)
06902-016
1
Figure 17. SFDR Measurement with a Notch Filter
CENTER 70.500MHz
RES BW 3kHz
Out-of-band SFDR is the difference, in dBc, between the peak
amplitude of the output signal and the peak spurious signal
MARKER 1
MARKER 2
Rev. B | Page 9 of 24
TRACE:
1
1
VBW 3kHz
TYPE:
FREQ
FREQ
SPAN 2MHz
SWEEP 847.3ms (601pts)
X-AXIS:
69.993MHz
70.997MHz
AMPLITUDE:
–11.25dBm
–10.36dBm
06902-017
OUT-OF-BAND, SPURIOUS-FREE DYNAMIC RANGE
Figure 18. Typical Two-Tone Output Spectrum (FOUT = 70, 71 MHz)
AN-928
Application Note
REF –30dBm
AVG LOG 10dB/
REF –30dBm
AVG LOG 10dB/
MKR1 71.997MHz
–10.358dBm
ATTEN 10dB
MKR2 68.993MHz
–80.041dBm
ATTEN 10dB
1
2
2
MARKER 1
MARKER 2
TRACE:
1
1
TYPE:
FREQ
FREQ
CENTER 68.500MHz
RES BW 3kHz
SPAN 2MHz
SWEEP 847.3ms (601pts)
X-AXIS:
71.997MHz
72.997MHz
AMPLITUDE:
–77.83dBm
–96.79dBm
MARKER 1
MARKER 2
TRACE:
1
1
VBW 3kHz
SPAN 2MHz
SWEEP 847.3ms (601pts)
TYPE:
FREQ
FREQ
06902-019
VBW 3kHz
06902-018
CENTER 72.500MHz
RES BW 3kHz
1
X-AXIS: AMPLITUDE:
67.993MHz –98.36dBm
68.993MHz –80.04dBm
Figure 20. .2F1-F2 and 3F1-2F2
Figure 19. 2F2-F1 and 3F2-2F1
Table 1. Typical IMD Calculation
Fundamental Amplitude
−11.25
−10.36
Third Order IMD Amplitudes
−77.8
−80
400MHz
Fifth Order IMD Amplitudes
−96.8
−98.4
IMD (dBc)
66.55 (3rd)
85.55 (5TH)
6dBm
DUAL POWER SUPPLY
5V
GND
AGILENT ESG/HP8644B
VOLTAGE REGULATORS
VOLTAGE REGULATORS
CLK IN
DAC1
FMOD
AD9779
DATA PATTERN
GENERATOR (DPG)
DAC2
SPI
PARALLEL
PORT
RHODE & SCHWARZ FSEA30
AGILENT PSA
Figure 21. Single-Tone and Two-Tone AC Test Setup
Rev. B | Page 10 of 24
06902-020
PAD AND NOTCH
FILTER INSERTED
HERE FOR SFDR
MEASUREMENTS.
PC
Application Note
AN-928
400MHz
6dBm
DUAL POWER SUPPLY
5V
GND
AGILENT ESG/HP8644B
VOLTAGE REGULATORS
VOLTAGE REGULATORS
CLK IN
DAC1
FMOD
AD9779
DATA PATTERN
GENERATOR (DPG)
DAC2
SPI
PC
RHODE & SCHWARZ FSEA30
AGILENT PSA
Figure 22. NSD AC Test Set
Rev. B | Page 11 of 24
06902-021
PARALLEL
PORT
AN-928
Application Note
Noise spectral density (NSD) is the converter noise power per
unit of bandwidth. This is usually specified in dBm/Hz in the
presence of a 0 dBm full-scale signal. If the signal power is less
than or greater than 0 dBm, it is necessary to specify the NSD in
dBc/Hz and specify the output signal power. To characterize the
NSD for a converter, with respect to clock frequency and FOUT,
the setup shown in Figure 22 is used.
For a spectrum analyzer, which contains an internal preamp,
the band-passed signal can be applied directly to the input of
the spectrum analyzer, and the NSD can be directly measured
as shown in Figure 23. The NSD number shown has the gain
of the internal preamp factored out. To calculate the correct
NSD number from this value, the loss in the filter must be
factored in as
NSD = −160 + 1.25 = −158.75 dBm/Hz
A band-pass filter at a specified frequency is used to isolate a
section of the DAC noise floor and knock down the signal level
going into the spectrum analyzer. The internal preamp of the
spectrum analyzer is used to ensure that the noise floor of the
DAC is above the noise floor of the analyzer. If the spectrum
analyzer does not have an internal preamp, an external low
noise amplifier (LNA) can be used to achieve the same results.
An appropriate LNA for these measurements is the Mini-Circuits
ZFL-500LN.
As with the SFDR measurements, it is first necessary to calibrate
the filter path to be able to factor the loss in the filter out of the
measured NSD results. Typically, the NSD performance is
measured using a 70 MHz band-pass filter, but it is important to
check a few sections of the noise floor with various band-pass
filters to ensure that the noise floor is flat over the entire
Nyquist band.
Figure 23 shows the output of a 70 MHz band-pass filter with a
0 dBm, 70 MHz sine wave input. Because the loss through the
filter is approximately 1.25 dB, this value needs to be factored
out of the measured NSD numbers.
REF 0dBm
PEAK LOG 10dB/
ATTEN 20dB
MKR1 70.000MHz
–1.25dBm
1
REF –40dBm
AVG LOG 10dB/
ATTEN 0dB
CHANNEL POWER =
–100.01 dBm/1.000MHz
PSD = –160.01dBm/Hz
CENTER 70.000MHz
RES BW 10kHz
VBW 100kHz
SPAN 10MHz
SWEEP 291.9 ms (601pts)
06902-023
NOISE SPECTRAL DENSITY
Figure 23. Measured NSD Using Internal Preamp
For a spectrum analyzer that does not contain an internal
preamp, an external LNA can accomplish the same result as
the internal preamp. Before using the LNA in the measurement path, the actual gain of the LNA must be calibrated. To
determine the gain of the LNA, a −30 dBm 70 MHz sine wave
is applied to the input of the LNA and the output of the LNA is
measured with a spectrum analyzer. In this case, the gain of the
LNA is approximately 29 dB, as shown in Figure 24.
REF 0dBm
PEAK LOG 10dB/
ATTEN 20dB
MKR1 70.000MHz
–0.95dBm
VBW 1kHz
SPAN 5MHz
SWEEP 6.029 s (601pts)
Figure 23. 70 MHz Band-Pass Filter Output
(FOUT = 70 MHz, 0 dBm)
CENTER 70.000MHz
RES BW 1kHz
VBW 1kHz
SPAN 5MHz
SWEEP 6.029 s (601pts)
06902-024
CENTER 70.000MHz
RES BW 1kHz
06902-022
1
Figure 24. Output of LNA with −30 dBm 70 MHz Sine Wave Input Signal
Rev. B | Page 12 of 24
Application Note
AN-928
The measured NSD using the band-pass filter followed by the
LNA is shown in Figure 25. The actual NSD is calculated as
follows:
NSD = (−130.5) – (29) + (1.25) = −158.25 dBm/Hz
REF –40dBm
AVG LOG 10dB/
ATTEN 0dB
CHANNEL POWER =
–70.48dBm/1.000MHz
PSD = –130.48dBm/Hz
Referring to the phase noise plots for each sine source (see
Figure 27, Figure 28, and Figure 29), note that the main difference is at the 1 MHz and 5 MHz offsets. The close-in phase
noise does not appear to vary much and does not have a
significant impact on the performance. This means that the
noise performance of the sine source itself is the largest limiting
factor on the overall achievable noise performance in the DAC.
MKR1 100Hz
CARRIER POWER 5.09dBm ATTEN 2.00dB
REF –70.00dBc/Hz
1100351.75dBc/Hz
1
2
3
VBW 100kHz
SPAN 10MHz
SWEEP 291.9 ms (601pts)
Figure 25. Measured NSD Using External LNA
A major factor in the degradation in NSD performance for a
DAC is the sine source used to clock the part. Figure 26 shows
the NSD for the AD9783 running at 400 MSPS with respect to
FOUT using three different sine sources (Rohde & Schwarz
SMA100A, Agilent ESG, and Rohde & Schwarz SML02).
50Hz
FREQUENCY OFFSET
MARKER 1
MARKER 2
MARKER 3
MARKER 4
TRACE:
2
2
2
2
TYPE:
SPOT FREQ
SPOT FREQ
SPOT FREQ
SPOT FREQ
X-AXIS:
100Hz
100kHz
1MHz
5MHz
5MHz
06902-027
CENTER 70.000MHz
RES BW 10kHz
06902-025
4
VALUE:
–104.49dBc/Hz
–124.44dBc/Hz
–144.83dBc/Hz
–146.78dBc/Hz
Figure 27. Phase Noise Performance at 400 MSPS for
the Agilent E4426B ESG Sine Source
–140
CARRIER POWER 5.11dBm ATTEN 2.00dB
REF –70.00dBc/Hz
–144
–148
SML02
NSD (dBm/Hz)
–152
1
ESG
–156
SMA100
–160
2
–164
–168
–172
3
4
0
20
40
60
80
100
120
140
160
180
200
FOUT (MHz)
50Hz
FREQUENCY OFFSET
Figure 26. AD9783 NSD vs FOUT for Various Sine Sources at 400 MSPS
MARKER 1
MARKER 2
MARKER 3
MARKER 4
TRACE:
2
2
2
2
TYPE:
SPOT FREQ
SPOT FREQ
SPOT FREQ
SPOT FREQ
X-AXIS:
100Hz
100kHz
1MHz
5MHz
5MHz
VALUE:
–98.67dBc/Hz
–124.77dBc/Hz
–146.25dBc/Hz
–149.16dBc/Hz
Figure 28. Phase Noise Performance at 400 MSPS for
the Rohde & Schwarz SML02 Sine Source
Rev. B | Page 13 of 24
06902-028
–180
06902-026
–176
AN-928
Application Note
The Rohde & Schwarz SML02 proves inferior to both the
Agilent ESG and the Rohde & Schwarz SMA100A at all of the
offset frequencies. This is most likely because the maximum
frequency for the SML02 is 2.2 GSPS, thus the performance
drops off significantly when running close to the maximum
specified frequency. The major difference between the ESG and
SMA100A occurs at the 5 MHz offset. This is similar to the
results at 400 MSPS.
CARRIER POWER 5.10dBm ATTEN 2.00dB
REF –70.00dBc/Hz
1
2
CARRIER POWER –2.56dBm ATTEN 0dB
REF –70.00dBc/Hz
1
3
50Hz
FREQUENCY OFFSET
MARKER 1
MARKER 2
MARKER 3
MARKER 4
TRACE:
2
2
2
2
TYPE:
SPOT FREQ
SPOT FREQ
SPOT FREQ
SPOT FREQ
5MHz
X-AXIS:
100Hz
100kHz
1MHz
5MHz
06902-029
4
VALUE:
–103.66dBc/Hz
–124.90dBc/Hz
–147.17dBc/Hz
–152.35dBc/Hz
2
Figure 29. Phase Noise Performance at 400 MSPS for
the Rohde & Schwarz SMA100A Sine Source
3
4
Sine Source
Agilent E4426B ESG
Rohde & Schwarz
SML02
Rohde & Schwarz
SMA100A
100 Hz
−104.5
Offset
100 kHz
1 MHz
−124.4
−144.8
5 MHz
−146.8
−98.7
−124.8
−146.3
−149.2
−103.7
−124.9
−147.2
−152.4
Figure 30 shows the NSD measured using the AD9739 and the
same three sine sources. Here, the NSD is measured at 2.1
GSPS; the phase noise of each sine source is measured at 2.1
GSPS to determine if there is any degradation or improvement at
the higher operating frequency.
50Hz
FREQUENCY OFFSET
MARKER 1
MARKER 2
MARKER 3
MARKER 4
TRACE:
2
2
2
2
TYPE:
SPOT FREQ
SPOT FREQ
SPOT FREQ
SPOT FREQ
5MHz
X-AXIS:
100Hz
100kHz
1MHz
5MHz
06902-031
Table 2. Sine Source Phase Noise Summary at 400 MSPS
VALUE:
–120.52dBc/Hz
–78.13dBc/Hz
–139.16dBc/Hz
–141.58dBc/Hz
Figure 31. Phase Noise Performance at 2.1 GSPS for
the Rohde & Schwarz SML02 Sine Source
CARRIER POWER –2.47dBm ATTEN 0dB
REF –70.00dBc/Hz
MKR4 5MHz
1100351.75dBc/Hz
1
–140
–144
2
–148
ESG
SML02
–156
3
4
–160
–164
SMA100
–168
50Hz
–172
MARKER 1
MARKER 2
MARKER 3
MARKER 4
0
100
200
300
400
500
600
700
800
900 1000 1100
FOUT (MHz)
06902-030
–176
–180
FREQUENCY OFFSET
Figure 30. NSD vs. FOUT for Various Sine Sources at 2.1 GSPS
The Rohde & Schwarz SML02 at 2.1 GSPS provides the worst
noise performance for the AD9739, whereas at 400 MSPS, the
Agilent E4426B ESG provides the worst noise performance for
the AD9783. As with the AD9783, the phase noise plots support
the lower performing NSD performance.
Rev. B | Page 14 of 24
TRACE:
2
2
2
2
TYPE:
SPOT FREQ
SPOT FREQ
SPOT FREQ
SPOT FREQ
X-AXIS:
100Hz
100kHz
1MHz
5MHz
5MHz
VALUE:
–94.06dBc/Hz
–123.63dBc/Hz
–143.61dBc/Hz
–145.92dBc/Hz
Figure 33. Phase Noise Performance at 2.1 GSPS for
the Agilent E4426B ESG Sine Source
06902-032
NSD (dBm/Hz)
–152
Application Note
AN-928
CARRIER POWER –2.35dBm ATTEN 0dB
REF –70.00dBc/Hz
MKR4 5MHz
–149.50dBc/Hz
Table 6. ACLR Settings for CDMA2000 IF < 1GHz
1
Carrier
1st Adjacent Channel
2nd Adjacent Channel
Carrier
1st Adjacent Channel
2nd Adjacent Channel
3
MARKER 1
MARKER 2
MARKER 3
MARKER 4
TRACE:
2
2
2
2
TYPE:
SPOT FREQ
SPOT FREQ
SPOT FREQ
SPOT FREQ
X-AXIS:
100Hz
100kHz
1MHz
5MHz
5MHz
06902-033
4
FREQUENCY OFFSET
Channel Bandwidth
1.228 MHz
30 kHz
30 kHz
Table 7. ACLR Settings for TDSCDMA
2
50Hz
Offset (MHz)
0
0.885
1.25
Offset (MHz)
0
0.750
1.98
Channel Bandwidth
1.228 MHz
30 kHz
30 kHz
Figure 33 and Figure 34 show typical ACLR performance for
WCDMA and CDMA2000. The WCDMA data shows the
AD9736 running at 491.52 MSPS. The CDMA2000 data shows
the AD9779 running at 122.88 MSPS, 4× interpolation, FDAC/4
modulation.
VALUE:
–91.46dBc/Hz
–124.41dBc/Hz
–142.43dBc/Hz
–149.50dBc/Hz
Figure 32. Phase Noise Performance at 2.1 GSPS for
the Rohde & Schwarz SMA100A Sine Source
REF –28.46dBm
AVG LOG 10dB
ATTEN 2dB
Table 3. Sine Source Phase Noise Summary at 2.1 GSPS
100 Hz
−94.1
Offset
100 kHz
1 MHz
−123.6
−143.6
5 MHz
−145.9
−78.1
−120.5
−139.2
−141.5
−91.2
−124.4
−142.4
−149.5
Because the noise performance of the sine source can vary
significantly over the entire operating frequency range, care
must be taken when choosing the correct sine source for a given
application when NSD is a critical parameter.
ADJACENT CHANNEL LEAKAGE RATIO OR
ADJACENT CHANNEL POWER RATIO
The adjacent channel leakage (power) ratio is a ratio, in dBc,
between the measured power within a channel relative to its
adjacent channels. Various standards require different channel
bandwidths and adjacent channel spacing as defined in Table 4
through Table 7.
CENTER 200.00MHz
RES BW 30kHz
VBW 300kHz
SPAN 33.84MHz
SWEEP 109.8 ms (601pts)
RMS RESULTS
LOWER
UPPER
dBc
dBm
dBc
dBm
CARRIER PWR OFFSET FREQ REF BW
5.000MHz
3.840MHz –78.59 –94.50 –78.29 –94.21
–15.92dBm/
10.000 MHz 3.840MHz –79.62 –95.53 –79.95 –95.87
3.84000MHz
15.000 MHz 3.840MHz –79.45 –95.36 –79.96 –95.88
06902-034
Sine Source
Agilent E4426B
Rohde & Schwarz
SML 02
Rohde & Schwarz
SMA100A
Figure 33. AD9736 Typical WCDMA Performance
REF –43.16dBm
AVG LOG 10dB
ATTEN 2dB
Table 4. ACLR Setting for WCDMA
Carrier
1st Adjacent Channel
2nd Adjacent Channel
3rd Adjacent Channel
4th Adjacent Channel
Offset (MHz)
0
5
10
15
20
Channel Bandwidth
3.84 MHz
3.84 MHz
3.84 MHz
3.84 MHz
3.84 MHz
Table 5. ACLR Settings for CDMA2000 IF > 1 GHz
Offset (MHz)
0
1.6
3.2
Channel Bandwidth
1.228 MHz
1.228 MHz
1.228 MHz
Rev. B | Page 15 of 24
CENTER 127.255MHz
RES BW 1kHz
RMS RESULTS
CARRIER PWR OFFSET FREQ
750.0MHz
–19.63dBm/
1.980MHz
1.22880MHz
VBW 10kHz
REF BW
30MHz
30MHz
SPAN 5MHz
SWEEP 14.59 s (601pts)
LOWER
UPPER
dBc
dBm
dBc
dBm
–86.07 –105.70 –84.86 –104.49
–14.88 –34.51 –91.17 –110.80
Figure 34. AD9779 Typical CDMA2000 Performance
06902-035
Carrier
1st Adjacent Channel
2nd Adjacent Channel
AN-928
Application Note
CROSSTALK
REF –30dBm
PEAK LOG 10dB
1 MKR1
Crosstalk is the measure of any feedthrough from one converter
to another on a multichannel DAC. Crosstalk can be measured
using one of the following two methods:
•
TRACE: 1
TYPE: FREQ
X-AXIS: 61.3MHz
AMPLITUDE:
–85.04dBc/Hz
Drive each DAC with a distinct frequency tone and check
each channel for the appearance of the other tone.
REF 0dBm
PEAK LOG 10dB
1 MKR1
ATTEN 22dB
TRACE: 1
TYPE: FREQ
X-AXIS: 61.3MHz
AMPLITUDE:
–0.33dBc/Hz
MKR2
TRACE: 1
TYPE: FREQ
X-AXIS: 121.8MHz
AMPLITUDE:
–77.15dBc/Hz
MKR4
TRACE: 1
4
TYPE: FREQ
X-AXIS: 339.2MHz
AMPLITUDE:
–17.97dBc/Hz
MKR3
TRACE: 1
TYPE: FREQ
X-AXIS: 278.0MHz
AMPLITUDE:
–70.80dBc/Hz
3
2
MKR3
TRACE: 1
TYPE: FREQ
X-AXIS: 278.0MHz
AMPLITUDE:
–89.55dBc/Hz
MKR2
TRACE: 1
TYPE: FREQ
X-AXIS: 121.8MHz
AMPLITUDE:
–87.81dBc/Hz
Drive one DAC with a distinct tone and the other DACs
with 0 and look for the appearance of the tone on the
spectrum of idle DACs.
Figure 35 and Figure 36 show the crosstalk measurement using
the second method. Not only does the fundamental signal feed
through but the harmonics and images do also. Because
crosstalk results can also be affected by coupling mechanisms
on the evaluation board, care must be taken to ensure that what
is measured is due to the converter itself and not to the
evaluation board.
MKR4
TRACE: 1
4
TYPE: FREQ
X-AXIS: 339.2MHz
AMPLITUDE:
–71.17dBc/Hz
3
2
EXT REF
AC COUPLED: UNSPECIFIED BELOW 20MHz
START 100kHz
VBW 5.1kHz
STOP 399.0MHz
RES BW 5.1kHz
SWEEP 18.49 s (601pts)
06902-037
•
ATTEN 10dB
Figure 36. Feedthrough of DAC1 onto DAC2 with 0 Applied to DAC2
SINX/X ROLL-OFF
All DAC converters have an inherent sinx/x roll-off that affects
the amplitude of the signal being synthesized as it gets closer to
the Nyquist frequency. It is important to characterize this rolloff to determine how the decrease in signal amplitude affects
the ac performance. To measure this effect, simply generate
various full-scale sine waves out of the DAC and measure the
fundamental amplitude as the output frequency increases.
Figure 37 shows this measurement for the AD9783 running at
600 MSPS. This part also has an analog mix mode that can
generate tones in the second and third Nyquist zones; thus, the
amplitude response in mix mode is also shown.
0
–0.5
06902-036
–1.0
Figure 35. Output of DAC1 for a 60 MHz Sine Wave Input
Note that, in Figure 35 and Figure 36, the markers are on the
following spurs:
Fundamental tone: 60 MHz
Second harmonic: 120 MHz
FDAC minus the second harmonic: 280 MHz
First image of DAC (FDAC − FOUT): 340 MHz
NORMAL MODE
–1.5
–2.0
–2.5
–3.0
MIX MODE
–3.5
–4.0
–4.5
–5.0
0
60
120
180
240
300
360
420
480
540
600
FOUT (MHz)
Figure 37. AD9783 Amplitude Response in Normal and Mix Modes
Rev. B | Page 16 of 24
06902-038
1.
2.
3.
4.
AMPLITUDE (dBm)
EXT REF
AC COUPLED: UNSPECIFIED BELOW 20MHz
START 100kHz
VBW 5.1kHz
STOP 399.0MHz
RES BW 5.1kHz
SWEEP 18.49 s (601pts)
Application Note
AN-928
DC TEST DEFINITIONS
The dc test definitions in this section assume binary data inputs.
OFFSET
FULL-SCALE GAIN
The offset of a converter is the measured output current with all
the input bits set to 0. For IOUTA (or, for some converter pinouts,
IOUTP), 0 mA is expected when all inputs are set to 0. For IOUTB
(or, for some converter pinouts, IOUTN), 0 mA is expected when
all the inputs are set to 1.
The full scale of a converter is the measured output current with
all the input bits set to 1. For IOUTA (or, for some converter
pinouts, IOUTP), full scale is expected when all inputs are set to 1.
For IOUTB (or, for some converter pinouts, IOUTN), full scale is
expected when all the inputs are set to 0.
OFFSET ERROR
GAIN ERROR
Offset error is the deviation of the output current from the ideal
zero. Figure 39 shows the effect on the DAC transfer function
when an offset error is present.
Gain error is the difference between the actual and ideal output
span. The actual output span is determined by the output when
all inputs are set to 1, minus the output when all inputs are set
to 0. Figure 39 shows the effect on the DAC transfer function
when a gain error is present.
3-BIT DAC TRANSFER FUNCTION
OFFSET ERROR
IDEAL RELATIONSHIP
FULL SCALE
7/8
1 LSB
5/8
OFFSET
ERROR
4/8
3/8
SCALE-FACTOR ERROR
GAIN
ERROR
2/8
1/8
0
000
001
010
011
100
101
110
111
0
1/8
2/8
3/8
4/8
5/8
6/8
7/8
1
DIGITAL INPUT CODE AND FRACTIONAL VALUE
Figure 38. Effect of Offset and Gain Errors on the Ideal Transfer Function
Rev. B | Page 17 of 24
06902-039
NORMALIZED ANALOG OUTPUT
6/8
AN-928
Application Note
TEMPERATURE DRIFT
GAIN MATCHING
Temperature drift is the maximum change over the entire
operating temperature range TMIN to TMAX. For offset and gain
drift, the drift is reported in ppm of full-scale range per °C. For
reference drift, the drift is reported in ppm per °C. The drift in
ppm per °C is usually calculated from the maximum measured
value. A typical reference drift plot is shown in Figure 39.
Gain matching is the ratio of the gain of one DAC to the gain
of the other DAC. This measurement is only valid for parts with
multiple DACs and is calculated by
VREF (V)
GAIN _ DAC1
× 100
There are two types of linearity: differential nonlinearity (DNL)
and integral nonlinearity (INL). In order to calculate either the
INL or DNL of a converter, it is necessary to first reconstruct the
entire transfer function of the converter by measuring the
output current for each digital input code. Measuring all of the
codes for a converter, especially 14-bit or 16-bit converters, can
be a long, painstaking process that is not entirely necessary if
the converter has segmentation.
1.208
1.206
1.202
–40 –30 –20 –10
0
10
20
30
40
50
60
70
80
90
TEMPERATURE (°C)
06902-040
1.204
Figure 39. Typical Reference Drift Plot
In this case, the maximum measured value occurs at 85°C, so
the drift is calculated from this value. The data for this curve is
shown in Table 8.
Table 8. Reference Drift Data
VREF
1.20508
1.204974
1.204714
1.204352
1.203768
1.203126
1.202425
1.20508
17.62552
PPM from Maximum
0
−88.035
−303.092
−604.217
−1088.733
−1621.428
−2203.190
ppm _ from _ max =
Take, for example, the AD9779, which is a 16-bit 1GSPS DAC.
The AD9779 consists of a PMOS current source array divided
into 63 equal current sources that make up the six most
significant bits (MSBs). The remaining 10 bits are a binary
weighted fraction of the MSB current sources (LSBs).
The entire transfer function can be reconstructed by taking only
73 measurements, rather than 65,535 measurements, which is a
significant savings in test time. Some other converters, such as
the AD9786, a 16-bit 500 MSPS DAC, are segmented into
MSBs, ISBs, and LSBs. The AD9786 has 127 equal current
sources that make up the seven most significant bits. The next
four bits (ISBs) consist of 15 equal current sources whose value
is 1/16 of an MSB current source. The remaining five bits
(LSBs) are a binary weighted fraction of the ISBs. In this case,
the ramp can be reconstructed by taking only 147 measurements,
rather than 65,535 measurements.
INTEGRAL NONLINEARITY ERROR
INL error is the maximum deviation of the actual analog output
from the ideal output, determined by a straight line drawn from
zero to full scale. An illustration of how an INL error manifests
itself using the ideal transfer curve and measured data is shown
in Figure 40 for a 3-bit DAC.
PPM from max is calculated by
(VREF − VREFMAX )
× 1e 6
VREFMAX
DIFFERENTIAL NONLINEARITY ERROR
Finally, PPM/°C is calculated by
PPM / °C =
GAIN _ DAC1 − GAIN _ DAC2
LINEARITY
1.210
Temperature
85
65
45
25
0
−20
−40
Maximum
PPM/°C
GainMatch =
DNL error is the measure of the variation in analog value,
normalized to full scale, associated with one LSB change. An
illustration of how a DNL error manifests using the ideal transfer
curve and measured data is shown in Figure 41 for a 3-bit DAC.
(PPMMAX − PPMMIN )
125°C
POWER SUPPLY REJECTION RATIO
Power supply rejection ratio (PSRR) is the maximum change in
the full-scale output as the supplies are varied from minimum
to maximum specified voltages.
MONOTONICITY
A DAC is considered monotonic if the output either increases
or remains constant as the digital input increases. If the analog
output decreases at any point during the digital input sequence,
the converter is nonmonotonic.
Rev. B | Page 18 of 24
Application Note
AN-928
FULL SCALE
1.25
7/8
1.00
6/8
0.75
ERROR (LSBs)
–INL
5/8
4/8
0.50
0.25
0
3/8
2/8
–0.25
1/8
–0.50
0
001
010
011
100
101
110
111
16384
24576
32768
40960
49152
57344
65536
CODE
06902-041
0
000
8192
06902-043
+INL
Figure 42. Typical INL Plots for the AD9786
Figure 40. INL Measurements
FULL SCALE
0.3
7/8
0.2
6/8
ERROR (LSBs)
0.1
5/8
–DNL = 1LSB
MONOTONIC
4/8
0
-0.1
3/8
+INL
-0.3
0
000
001
010
011
100
101
110
111
06902-042
1/8
0
8192
16384
24576
32768
40960
49152
57344
CODE
Figure 43. Typical DNL Plots for the AD9786
Figure 41. DNL Measurements
Rev. B | Page 19 of 24
65536
06902-044
-0.2
2/8
AN-928
Application Note
100MHz
6dBm
DUAL POWER SUPPLY
5V
GND
AGILENT ESG/HP8644B
VOLTAGE REGULATORS
VOLTAGE REGULATORS
CLK IN
DAC1
FMOD
AD9779
DAC2
SPI
I-V CONVERTER
OP AMP
CIRCUITRY
PC
PARALLEL
PORT
1.998765V
HP3458A MULITIMETER
Figure 44. DC Measurement Test Setup
Rev. B | Page 20 of 24
06902-045
DATA PATTERN
GENERATOR (DPG)
Application Note
AN-928
DIGITAL INPUT TIMING
This time is also usually defined as a minimum time. As is the
case with the setup time, the hold time can be positive or
negative, as shown in Figure 45 through Figure 47.
SETUP TIME
The setup time for a DAC is the amount of time before the
clock latching edge at which the data needs to be stable. This
time is usually defined as a minimum specification. The setup
time can be either positive or negative depending on where the
keep-out window occurs with respect to the latching edge of the
clock, as shown in Figure 45 through Figure 47.
KEEP-OUT WINDOW
The keep-out window for a DAC is the total window around the
latching clock edge, which includes both setup and hold times.
For a more detailed description of the setup and hold measurements for high speed CMOS input DACs, refer to the AN-748
Application Note, Set-Up and Hold Measurements in High Speed
CMOS Input DACs.
HOLD TIME
The hold time for a DAC is the amount of time the data must be
stable after the latching edge for the data to be acquired accurately.
INPUT CLOCK
tS
06902-046
tH
INPUT DATA
Figure 45. Setup and Hold Times Symmetric to the Latching Clock Edge (tS and tH Are Both Positive)
INPUT CLOCK
tS
06902-047
tH
INPUT DATA
Figure 46. Setup and Hold Times Are Delayed from the Latching Clock Edge (tS Is Negative and tH Is Positive)
INPUT CLOCK
tH
06902-048
tS
INPUT DATA
Figure 47. Setup and Hold Times Are Advanced in Time from the Latching Clock Edge (tS Is Positive and tH Is Negative)
Rev. B | Page 21 of 24
AN-928
Application Note
NOTES
Rev. B | Page 22 of 24
Application Note
AN-928
NOTES
Rev. B | Page 23 of 24
AN-928
Application Note
NOTES
©2008–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
AN06902-0-10/13(B)
Rev. B | Page 24 of 24
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