Data Sheet

UBA20271/2
350 V and 600 V Power ICs for dimmable compact fluorescent
lamps
Rev. 2.1 — 12 October 2011
Product data sheet
1. General description
The UBA20271/2 are high-voltage power ICs intended to drive and control higher
powered self ballasted Compact Fluorescent Lamp (CFL) lighting applications. The
UBA20271/2 operate from 120 V and 230 V. The module includes a half-bridge power
circuit of two NMOST power FETs. In addition, a controller circuit is included that has
advanced features for dimming and a lamp current controlled boost feature. The boost
feature is used for boosting cold (amalgam) CFL.
The controller contains a half-bridge drive function for CFL, a high-voltage level-shift
circuit with integrated bootstrap diode. In addition, the controller contains an oscillator
function, a current control function both for preheat and burn, a timer function and
protection circuits. The UBA20271/2 are supplied via a dV/dt current charge supply circuit
from the half-bridge circuit.
Remark: Mains voltages noted are AC.
2. Features and benefits
2.1 Half-bridge features
 UBA20271: Two internal 350 V, 1.0  max 5.0 A NMOST half-bridge power FETs
 UBA20272: Two internal 600 V, 3.0 , max 2.7 A NMOST half-bridge power FETs
 Integrated high-voltage level-shift function with integrated bootstrap diode
2.2 Preheat and ignition features





Coil saturation protection during ignition
Adjustable saturation protection level
Adjustable preheat time
Adjustable preheat current
Ignition lamp current detection
2.3 Lamp boost features
 Adjustable boost timing
 Fixed boost current ratio of 1.5
 Gradually boost to burn transition timing
2.4 Dim features
 Continuously variable dimming function for standard phase cut dimmers
UBA20271/2
NXP Semiconductors
350 V and 600 V Power ICs for dimmable compact fluorescent lamps
 Natural dimming curve by logarithmic correction
 Adjustable Minimum Dimming Level (MDL)
 Controlled lamp ON/OFF
2.5 Protection





OverCurrent Protection (OCP) in boost and burn state
Capacitive Mode Protection (CMP)
OverPower Protection (OPP)
Power-down function
OverTemperature Protection (OTP)
2.6 Other features
 Current controlled operating in boost and burn state
 External power-down function
 Lamp flicker suppression
3. Applications
 Dimmable compact fluorescent lamps for power levels from 5 W to 20 W directly
operating from 230 V (UBA20272) and 120 V (UBA20271) mains voltage.
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
UBA20271T/N1
SO20
Plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
UBA20272T/N1
SO20
Plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
UBA20271_UBA20272
Product data sheet
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Rev. 2.1 — 12 October 2011
© NXP B.V. 2011. All rights reserved.
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16 FS
18 DHS
SUPPLY
DIVIDE BY 2
LOGIC
REFERENCE
VOLTAGES
HS
driver
LEVEL
SHIFTER
DRIVER
LOGIC
17 HBO
19 HBO
LS
driver
TEMPERATURE
SENSOR
160° 120° 80°
5 V DIGITAL
GHS
GLS
20 HBO
1 SLS
2 SLS
5 V ANALOG
CAPACITIVE MODE DETECTOR
STATE LOGIC
NXP Semiconductors
BOOTSTRAP
5. Block diagram
UBA20271_UBA20272
Product data sheet
VDD
6
3 SLS
VDD(stop)
Vth(capm)SLS
RESET
PREHEAT CURRENT SENSOR
COUNTER
5V
CB 14
LOGIC
Vph(SLS)
LOGIC
PREHEAT/
BOOST TIMER
RESET STATE
START-UP STATE
PREHEAT STATE
IGNITION STATE
HOLD STATE
BOOST STATE
BURN STATE
POWER-DOWN STATE
INDUCTOR SATURATION/
OVERCURRENT DETECTOR
Vth(ocp)SLS
4 LSAT
25 μA
6 μA
IGNITION CURRENT DETECTOR
LOGIC
1 μA
60 μA
Vth(det)ign(CSI)
SGND 15
5 PGND
REFERENCE
CURRENT
VOLTAGE
CONTROLLED OSCILLATOR
1.27 V
LOGIC
BOOST ENABLE
BOOST
AMPLIFIER
FREQUENCY
CONTROL
VLD
12 DCI
VT(hec1)
DCI
I
3 of 33
© NXP B.V. 2011. All rights reserved.
LAMP
CURRENT
SENSOR
V
Fig 1.
Vth(start)
(DCI)
Votp(CSI)
DSR
DCI
25 μA
8
10
11
9
CF
CI
CSI
MDL
Block diagram UBA20271/2
LEVEL SHIFT
DIMMER
CONTROL
001aam772
UBA20271/2
Vth(bst)
(DCI)
OTA
7
RREF
START ENABLE
Vclamp
(CSI)
350 V and 600 V Power ICs for dimmable compact fluorescent lamps
Rev. 2.1 — 12 October 2011
All information provided in this document is subject to legal disclaimers.
CP 13
UBA20271/2
NXP Semiconductors
350 V and 600 V Power ICs for dimmable compact fluorescent lamps
6. Pinning information
6.1 Pinning
SLS
1
20 HBO
SLS
2
19 HBO
SLS
3
18 DHS
LSAT
4
17 HBO
PGND
5
VDD
6
RREF
7
14 CB
CF
8
13 CP
MDL
9
12 DCI
CI 10
11 CSI
UBA20271/2
16 FS
15 SGND
001aam784
Fig 2.
Pin configuration UBA20271/2 (SO20)
6.2 Pin description
Table 2.
UBA20271_UBA20272
Product data sheet
Pin description
Symbol
Pin
Description
SLS
1,2,3
source low-side switch[1]
LSAT
4
coil saturation level input
PGND
5
power ground[3]
VDD
6
low voltage supply
RREF
7
internal reference current input
CF
8
voltage controlled oscillator capacitor
MDL
9
minimum dimming level input
CI
10
voltage controlled oscillator input integrating capacitor
CSI
11
current feedback sense input
DCI
12
dimming level input
CP
13
preheat timing capacitor
CB
14
boost timing capacitor
SGND
15
signal ground[3]
FS
16
floating supply voltage
HBO
17,19,20
half-bridge output[2]
DHS
18
high-voltage supply
[1]
SLS pins are internally connected
[2]
HBO pins are internally connected
[3]
PGND and SGND are internally connected
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Rev. 2.1 — 12 October 2011
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UBA20271/2
NXP Semiconductors
350 V and 600 V Power ICs for dimmable compact fluorescent lamps
7. Functional description
The UBA20271/2 are ICs with integrated half-bridge MOSFETs in self ballasted
high-power CFL and their derivatives. The UBA20271/2 are equipped with variable
dimming functionality that has a logarithmic corrected natural dimming function. This
function enables a less sensitive brightness control of the lamp at low dim levels.
The UBA20271/2 are rated up to a maximum continuous rectified mains voltage of 350 V
or 500 V, respectively and lamp power-up to 20 W. The UBA20271/2 include all the
necessary functions for preheat, ignition, boost, and on-state operation of the lamp and
includes a linear dimming feature. In addition, several protection measures are included
that safeguard the functioning of the CFL and controller. The controller states are shown
in Figure 3.
VDD = 0
RESET STATE
VDD < VDD(rst)
HOLD = 0
VDD > VDD(rst)
VDD < VDD(rst)
START-UP STATE
POWER-DOWN STATE
VCP < Vth(rel)CP
(1)
PREHEAT STATE
(2)
HOLD STATE
(3)
HOLD = 1
preheat time
completed
IGNITION STATE
(4)
Ignition_Detected
BOOST AND BURN
STATES
(6)
(5)
001aam665
(1) VDD > VDD(start) AND Vi(DCI) > Vth(start)DCI AND (HOLD = 0 OR VCP < Vth(rel)CP)
(2) VDD < VDD(stop) OR Vi(DCI) < Vth(start)DCI  Vth(hys)DCI
(3) (End of ignition time AND HOLD = 0) OR VDD < VDD(stop) OR Vi(DCI) < Vth(start)DCI  Vth(hys)DCI
(4) End of ignition AND HOLD = 1
(5) VCP < Vth(pd)CP OR overcurrent fault time > 1⁄10 tph OR fbridge(max) detected in capacitive mode
(6) VDD < VDD(stop) OR Vi(DCI) < Vth(start)DCI  Vth(hys)DCI
Fig 3.
UBA20271_UBA20272
Product data sheet
State diagram
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Rev. 2.1 — 12 October 2011
© NXP B.V. 2011. All rights reserved.
5 of 33
UBA20271/2
NXP Semiconductors
350 V and 600 V Power ICs for dimmable compact fluorescent lamps
7.1 Lamp start-up cycle
7.1.1 Reset state
The UBA20271/2 are in a reset state while the supply voltage on the VDD pin is lower than
the VDD(rst) level. In the reset state, a part of the internal supply is turned off, all registers,
counters and timers are undefined. In addition, the hold state latch is reset and both the
high and low-side transistor are non-conductive. During power-up, the low voltage supply
capacitor on the VDD pin is charged via an external start-up resistor. When the voltage on
the VDD pin is higher than the VDD(rst) level, the start-up state is entered. The UBA20271/2
enters the reset state when the supply voltage on the VDD pin drops lower than VDD(rst).
7.1.2 Start-up state
Start-up is achieved by charging the low voltage supply capacitor on the VDD pin via an
external start-up resistor. At start-up the High-Side (HS) transistor is non-conductive and
the Low-Side (LS) is conductive to enable charging of the bootstrap capacitor. This
capacitor supplies the HS driver and level shifter circuit connected between the FS and
HBO pin. A DC reset circuit is incorporated in the ICs HS driver. This circuit ensures that
lower than the lockout voltage on the FS pin the output voltage (VGHS  VHBO) is zero.
As the start-up state is entered, the circuit only starts oscillating when the low voltage
supply (VDD) reaches the value of VDD(start) AND Vi(DCI) > Vth(start)DCI. The circuit starts
oscillating at fbridge(max).
The circuit enters the preheat state as soon as the capacitor on the CP pin is charged to a
voltage level higher than Vth(CP)max. To remain oscillating, the VDD voltage must remain
higher than VDD(stop) and lower than the upper limit VDD(clamp). In addition, the typical
voltage level on the DCI pin must be higher than Vth(start)DCI  Vth(hys)DCI = 0.24 V.
An UnderVoltage LockOut (UVLO) is implemented on the DCI pin to create a guaranteed
turn-off for multiple lamps when the lamps are at low dim levels. The UVLO also
guarantees that there is a preheat phase when the dim level is turned up again.
The typical turn-on level on the DCI pin is set to lower than Vth(start)DCI = 0.36 V, else it
would increase the turn-on hysteresis of the lamp. This level enables the UBA20271/2 to
perform a stable ignition of the lamp when there is already sufficient power from the
dimmer at lower dim levels.
During the start-up state, the voltage on the CF pin is at zero and the CB pin is close to
zero. The voltage on the CP pin rises to higher than Vth(CP)max level during the start-up
state. See Figure 9.
7.1.3 Preheat state
Starting at fbridge(max), the frequency decreases by charging capacitor CCI via an output
current circuit controlled by the preheat current sensor circuit. This state continues until
the momentary value of the voltage across sense resistor RSLS reaches the internally
fixed preheat voltage level (SLS pin). At this level, the current of the preheat current
sensor reaches a charge and discharge balanced state on capacitor CCI to set the
frequency.
UBA20271_UBA20272
Product data sheet
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Rev. 2.1 — 12 October 2011
© NXP B.V. 2011. All rights reserved.
6 of 33
UBA20271/2
NXP Semiconductors
350 V and 600 V Power ICs for dimmable compact fluorescent lamps
The preheat time consists of eight saw-toothed pulses at the CP pin. Preheat begins as
soon as the capacitor on the CP pin is charged to a voltage higher than Vth(CP)max. During
the preheat time, the current feedback sensor circuit (input CSI pin) is disabled. To
increase noise immunity, an internal filter of 30 ns is included at the SLS pin.
If during preheat, the level on the DCI pin drops lower than Vth(start)DCI  Vth(hys)DCI
= 0.24 V or the VDD pin drops lower than VDD(stop), the preheat state is immediately
stopped. The circuit then enters the hold state delaying a new preheat cycle. A fixed
voltage drop on the preheat capacitor CCP and a fixed discharge current on the CP pin
sets the delay time.
A new preheat cycle starts after the CP pin level slowly discharges. This condition
continues until VCP < Vth(rel)CP and recharges higher than Vth(CP)max provided
VDD > VDD(start) AND Vi(DCI) > Vth(start)DCI. See Figure 5.
f
(kHz)
100
start frequency
CFL ignition
A
B
C
preheat frequency
100 %
boost bottom ~22 kHz
time (s)
preheat
ignition
boost
transition
burn
001aam764
Fig 4.
CFL frequency from start to burn state
7.1.4 Ignition state
Directly after the preheat state has been completed, the ignition state is entered. In the
ignition state, the frequency sweeps down due to charging of the capacitor CCI on the CI
pin with an internally fixed current. See Figure 4. During this continuous decrease in
frequency, the circuit approaches the resonant frequency of the resonant tank L2, C5.
This results in a high voltage across the lamp to ignite the lamp. The current sensor circuit
which monitors the voltage over resistor RCSI detects lamp ignition. See Figure 11.
If the voltage on the CSI pin is above the typical ignition detection threshold voltage level
of 0.6 V, lamp ignition is detected. The system then changes from ignition state to the
boost or burn state. If no ignition is detected, the frequency decreases further to the
minimum half-bridge frequency fbridge(min). To prevent continuous ignition attempts and
over-heating of the application due to lamp damage, the UBA20271/2 only attempts to
ignite the lamp twice after power-up. The ignition attempt counter is incremented when the
lamp ignition threshold voltage on the CSI pin is not exceeded at the end of the ignition
enabling time. If a second ignition attempt also exceeds the ignition time-out period, the IC
enters the power-down state. See Figure 5.
UBA20271_UBA20272
Product data sheet
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Rev. 2.1 — 12 October 2011
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7 of 33
UBA20271/2
NXP Semiconductors
350 V and 600 V Power ICs for dimmable compact fluorescent lamps
voltage
(V)
5V
2nd failed
ignition
attempt
1st failed
ignition
attempt
VCP
Vth(CP)max
Vth(CP)min
discharge
to 0 V
Vth(rel)CP
startup
time
1st preheat
time
tph
HOLD STATE
2nd preheat
time
ten(ign)
td(restart)
tph
1st ignition
enabling time
restart
delay time
2nd
startup
POWER DOWN STATE
ten(ign)
2nd ignition
enabling time
0V
time (s)
001aan537
Fig 5.
Retry cycle
7.1.5 Boost state and transition to burn state
When ignition is detected by measuring lamp current on the CSI pin, the circuit enters the
boost state. Figure 7 shows the boost and burn state in more detail. In the boost state, the
nominal burn state lamp current can be increased with a fixed boost ratio of 1.5:1. This
boosts up the slow luminescence increase of a cold amalgam CFL lamp, provided
VDCI > Vth(bst)DCI. If the IC is at a temperature (Tj(bp)bst) before entering the boost state, the
burn state is bypassed.
A boost timing circuit is included to determine the boost time and transition to burn time.
The circuit consists of a clock generator comprising CCB, Rext(RREF) and a 64-step counter.
When the timer is not operating, CCB is discharged to lower than the Vth(CB)min level of
1.1 V. This voltage, about 0.6 V, is still higher than the level at which the comparator on
CCB detects if the CB pin is shorted to ground.
The boost time consists of 63 saw-toothed pulses at the CB pin and automatically
followed by the transition time at the CP pin. The 32 saw-tooth pulses form the transition
time from boost to burn enabling a smooth transition between the current controlled boost
and burn state. The total transition time is approximately four times the preheat time as
shown in Figure 6.
UBA20271_UBA20272
Product data sheet
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Rev. 2.1 — 12 October 2011
© NXP B.V. 2011. All rights reserved.
8 of 33
UBA20271/2
NXP Semiconductors
350 V and 600 V Power ICs for dimmable compact fluorescent lamps
voltage
(V)
5V
VCP
Vth(CP)max 4.5 V
1
32
Vth(CP)min 3.8 V
Vth(CB)max 3.6 V
VCB
Vth(CB)min 1.1 V
1
2
61
62
63
0.6 V
ignition
boost
0V
transition
burn
time (s)
001aam765
Fig 6.
Boost timing
In the boost state, the lamp current feedback control circuit operates the same as in the
burn state. This action is used to improve lamp stability. Lamp current boosted by a fixed
ratio of 1.5 compared to the burn state, boosts up the slow luminescence increase of a
cold CFL lamp. In the boost to burn transition time there is a slow 15-step ratio decrease
from 1.5 to 1. For the transition to burn time, the preheat timer is reused and the boost
ratio is gradually decreased in 15 steps from 1.5 to 1. The steps occur within 32
saw-toothed pulses on the CP pin. The 32 saw-toothed pulses form the transition time
from boost to burn to enable a smooth transition between the current controlled boost and
burn state. Given the application values of CCB and Rext(RREF) a boost time of more than
300 s is possible. In addition to boost bypass at temperature Tj(bp)bst ( 80 C), there is a
temperature protection function during the boost state of Tj(end)bst ( 120 C). If the IC
temperature passes this level during boost, the transition timer is immediately started in
order to enter the burn state faster. This action effectively reduces the boost time. See
Figure 4 [B].
The current boost in the boost state does not start when Vi(DCI) is lower than Vth(bst)DCI.
Current boost ends when Vi(DCI) is lower than Vth(bst)DCI  Vth(bst)hys(DCI) without a boost
transition. See Figure 4 [A].
Remark: If the CB pin is shorted to ground, the boost function is disabled. During such
conditions, the bottom frequency fbridge(min) is 1.8 times higher than the boost bottom
frequency fbridge(bst)min.
7.1.6 Burn state
After the boost state, or when the boost state is bypassed burn state starts. The lamp
current sensor circuit is still enabled. See Figure 4 [A]. The CSI pin (current sense input)
measures the RMS voltage across sense resistor RCSI. It then passes through a
Double-Sided Rectifier (DSR) circuit and fed towards an Operational Transconductor
Amplifier (OTA). When the RMS voltage on the CSI pin reaches the internal reference
level, the lamp current sensor circuit takes over the control of the lamp current. The
UBA20271_UBA20272
Product data sheet
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© NXP B.V. 2011. All rights reserved.
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UBA20271/2
NXP Semiconductors
350 V and 600 V Power ICs for dimmable compact fluorescent lamps
internal current output of the OTA is transferred via an integrator on the CI pin to the input
of the Voltage Controlled Oscillator (VCO). The VCO regulates the frequency and as a
result, the lamp current.
BOOST AND BURN
STATES
Vi(DCI) > Vth(bst)DCI AND boost
boost timer running
(2)
00
burn select
01
boost
Boost_ratio = 1
Boost_ratio = 1.5
(3)
temp < (Tj(otp) - Tj(otp)hys
(1)
Vi(CSI) = Votp(CSI)
(66 % level)
Vi(CSI) = Vclamp(CSI)
(100 % level)
(4)
temp > (Tj(otp)
10
burn
(5)
11
boost transition
001aam668
(1) Temp > Tj(bp)bst OR Boost_Disable
(2) Temp < Tj(bp)bst AND NOT Boost_Disable
(3) NOT (Boost OR Boost transition)
(4) Temp > Tj(end)bst OR Boost timer ended OR (Boost_ratio = 1.5 AND VDCI < Vth(bst)DCI - Vth(bst)hys(DCI))
(5) Boost_Transition timer ended OR VDCI < Vth(bst)DCI  Vth(bst)hys(DCI) OR Temp > Tj(otp)
Fig 7.
Boost and burn state machine
7.1.7 Hold state
The hold state is a special state to reduce lamp flicker at deep dim levels, on or near dim
and ignition threshold level. See Figure 3.
The hold state is entered following:
• a failed ignition attempt
• or when the low supply voltage VDD is lower than VDD(stop) in the ignition or preheat
state
• or when VDCI < Vth(start)DCI  Vth(hys)DCI in the ignition or preheat state
A repeated aborted preheat or ignition cycle due to a drop in DCI voltage that is lower than
Vth(start)DCI  Vth(hys)DCI or a drop in supply voltage that is lower than VDD(stop) in preheat or
ignition state does not increment the ignition attempt counter. The UBA20271/2 enters the
hold state only delaying a new preheat cycle by the same time delay and mechanism. As
shown in Figure 5 hold state retention time.
UBA20271_UBA20272
Product data sheet
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UBA20271/2
NXP Semiconductors
350 V and 600 V Power ICs for dimmable compact fluorescent lamps
When CP is lower than Vth(rel)CP, the IC is released from the hold state and moves to the
start-up state. See Figure 3. Alternatively, the hold state ends when the supply voltage is
lower than VDD(rst) and the IC is reset.
With a 470 nF capacitor on the CP pin, the typical hold state retention delay is between
1.0 seconds and 1.7 seconds. However, it depends on where the preheat cycle is cut off
on the rising or falling edge of the preheat timing. The retention time for a failed ignition
always starts from the top of the rising edge on the CP pin. See Figure 5. In the hold state,
a latch is set (hold state latch = 1), the oscillator is stopped, transistor HS is
non-conductive and transistor LS conducting. The voltage on pin VDD alternates between
VDD(start) and VDD(stop) as long as the voltage on the CP pin has not reached Vth(rel)CP. See
Figure 5.
The alternating supply voltage is a result of the current drawn by the IC supply pin VDD.
The supply current is less than 220 A, when the supply voltage VDD is increasing
between VDD(stop) and VDD(start). The supply current is typically 2 mA when VDD is
decreasing between VDD(start) and VDD(stop). More current is drawn during the decreasing
slope of VDD as the internal analog supply is turned on when VDD > VDD(start). This
condition enables comparators in the IC to monitor the voltage on the CP pin and whether
the supply voltage VDD decreases lower than VDD(stop).
7.2 Oscillation and timing
7.2.1 Oscillation
The internal oscillator is a VCO circuit which generates a sawtooth waveform between the
Vth(CF)max level and 0 V. Capacitor CCF, resistor Rext(RREF), and the voltage at the CI pin
determine the frequency of the sawtooth. Rext(RREF) and CCF determine the minimum and
maximum switching frequencies. Their ratio is internally fixed. There are two ratios, the
ratio between fbridge(max) and fbridge(min) is 2.5 and the ratio between fbridge(max) and
fbridge(bst)min is 4.6. The sawtooth frequency is twice the half-bridge frequency.
Transistors HS (Q1) and LS (Q2) are brought into conduction with a duty cycle of
approximately 50 %. Figure 8 provides an overview of the oscillator signal and driver
signals. The oscillator starts oscillating at fbridge(max). The non-overlap time between the
gate drive signals VGLS and VGHS is tno.
UBA20271_UBA20272
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Rev. 2.1 — 12 October 2011
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UBA20271/2
NXP Semiconductors
350 V and 600 V Power ICs for dimmable compact fluorescent lamps
voltage
(V)
VCF
0
tdch
V(GHS-HBO)
0
VGLS
tno
tno
0
VHBO
0
time (s)
001aam766
Fig 8.
Sawtooth, gate driver and half-bridge output signals
7.2.2 Combined timing circuit
A combined timing circuit is included to determine the preheat time, ignition enabling time
and overcurrent time, see Figure 9. The circuit consists of a clock generator defined by
CCP and Rext(RREF) and a counter. When the timer is not operating, CCP is charged to 5 V.
The timing circuit starts operating following the start-up state, as soon as the low supply
voltage has reached VDD(start). Additionally the DCI input voltage is higher than Vth(start)DCI
and the voltage on pin CP must pass Vth(CP)max.The preheat time consists of eight
saw-tooth pulses on the CP pin as shown in Figure 9. The maximum ignition enabling time
following the preheat phase is two complete sawtooth (triangular) pulses. During the boost
and burn state, part of the timer is used to generate the maximum overcurrent time (more
than one half of the saw-toothed pulse). If a continuous overcurrent is detected, the timer
starts.
UBA20271_UBA20272
Product data sheet
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Rev. 2.1 — 12 October 2011
© NXP B.V. 2011. All rights reserved.
12 of 33
UBA20271/2
NXP Semiconductors
350 V and 600 V Power ICs for dimmable compact fluorescent lamps
voltage
(V)
ignition
enabling time
5V
VCP
Vth(CP)max
4.5 V
Vth(CP)min
3.8 V
CFL ignition overcurrent
ignition
time
startup
time
preheat time
0V
fault time
boost-burn
power down
time (s)
001aam768
Fig 9.
Timing diagram preheat, ignition and overcurrent
7.3 Natural linear dimming
What determines the actual internal set point level used for the current control feedback
loop is an external level applied via the DCI pin for dimming. The DCI voltage is a function
of the phase cut angle of the applied dimmer. To ensure that the external input for the
control on the DCI pin internally stays within a certain range, this input signal passes an
internal linear to logarithmic conversion circuit followed by a limiting circuit.
The linear to logarithmic conversion circuit is designed to improve dimming control by
correcting for the higher sensitivity of the human eye to small changes in low light levels.
See Figure 10. The conversion circuit also provides a natural perceived linear brightness
adjustment of the lamp.
The limiting circuit prevents the signal falling below the MDL or rising above the 100 %
reference level of Vclamp(CSI). The output of the linear to logarithmic conversion circuit is
the actual reference voltage for the lamp current control loop. See signal VLD in Figure 1
(dimmer control block). When the IC is in the burn state, the voltage is equal to the RMS
voltage on the CSI pin. When the control loop is regulating correctly, the upper limit is
clamped at the 100 % reference level. This condition prevents lamp current values that
are too high in mains overvoltage situations. See Figure 10.
The MDL level presets a minimum to which the lamp current clips at low dim levels and is
adjustable via the MDL pin. An accurate minimum dimming voltage level is set by using an
internal reference current (derived from the internal band gap reference circuit and
resistor Rext(RREF)) and an applied external resistor RMDL on the MDL pin.
UBA20271_UBA20272
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350 V and 600 V Power ICs for dimmable compact fluorescent lamps
voltage
(V)
1.2
Vi(CSI)
[VRMS]
internal
clamp
(1)
Vclamp(CSI)
1.0
100 %
0.8
0.6
VLD
0.4
midcurve
0.2
Vth(hys)DCI
MDL
0
0
0.4
0.2
VT(hec1)DCI
0.6
0.8
VT(hec2)DCI
1.0
0.9
Vth(start)DCI
1.2
1.4
1.6
Vi(DCI) (V)
voltage
(V)
VT(hec3)DCI
001aam671
(1) Vi(CSI) = VLD = f(Vi(DCI))
Fig 10. CSI voltage as a function of DCI voltage
7.4 Protection and power-down
7.4.1 Coil saturation protection
Coil saturation protection is integrated into the IC to allow for the use of small CFL lamps
and use of small coils. Saturation of these coils is detected and excessive overcurrent due
to saturation is prevented. Coil saturation protection is only enabled during the ignition
state. To limit voltages and currents in the resonant circuit when there is no ignition or
delayed ignition, a cycle-by-cycle control mechanism is used to prevent coil saturation.
This control also limits the high peak current and dissipation in the half-bridge power
transistors.
Coil saturation is detected by monitoring the voltage across the RSLS resistor. A trigger is
generated when this voltage exceeds the Vth(sat)SLS level. When saturation is detected, a
fixed current Io(sat)CF is injected into the CCF capacitor to shorten the switching cycle of
the half-bridge. The injected current is maintained until the end of the switching cycle. This
action immediately increases the half-bridge switching frequency. Furthermore, in each
successive cycle that coil saturation is detected, capacitor CCI is discharged to enable an
ignition time-out detection in the ignition state.
Coil saturation protection is triggered when the voltage on the SLS pin exceeds Vth(sat)SLS.
The voltage VSLS on the SLS pin is also used to set the preheat current. The value of
external resistor RSLS determines this voltage. With an internal reference source current
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350 V and 600 V Power ICs for dimmable compact fluorescent lamps
and external resistor RLSAT connected to the LSAT pin, a more secure setting of the
threshold level Vth(sat)SLS is possible. When resistor RLSAT is not mounted, the Vth(sat)SLS
level is internally clamped at 2.5 V. CLSAT parallel to RLSAT is obligatory for stability
reasons even when RLSAT is not mounted.
7.4.2 OverCurrent Protection (OCP)
OCP is active in the burn and boost states (not during boost transition). When the peak
absolute value of the voltage across the current sense resistor on the SLS pin exceeds
the OCP reference level Vth(ocp)SLS, overcurrent is detected. A current Io(CP) is then sunk
from the capacitor connected to the CP pin for the next full cycle. If the overcurrent is
absent at the end of this cycle, this current is disabled. Instead a current, equal to Io(CP), is
sourced to CP. If the overcurrent occurs in more than half the number of cycles, there is a
net discharging of the capacitor connected to the CP pin. When the voltage, on the CP pin
drops lower than Vth(CP)min, the IC enters power-down mode. In a continuous overcurrent
condition, the overcurrent time-out of tfault(oc) takes about 1⁄10 tph. The IC then enters the
power-down mode. The Vth(ocp)SLS level corresponds with the Vth(sat)SLS level during the
ignition state.
7.4.3 OverPower Protection (OPP)
OPP is active in boost and burn state. The lamp current is limited and regulated to its
nominal designed lamp current in case overvoltage situations on the mains supply occur.
Overpower begins when the DCI voltage, that regulates the lamp current is exceeding the
maximum DCI input range. Internally the DCI voltage is clamped to the maximum input
voltage level VT(hec3)DCI see Figure 10. The DCI clamp level is independent of any supply
voltage fluctuations.
7.4.4 Capacitive Mode Protection (CMP)
CMP is active in the ignition, burn and boost states and during boost transition. The signal
across resistor RSLS also provides information about the switching behavior of the
half-bridge. When conditions are normal, the current flows from the source of the LS
transistor to the half-bridge when the LS transistor is switched on. This results in a
negative voltage on the SLS pin. As the circuit yields to capacitive mode, the voltage
decreases and eventually reverses polarity. The protection prevents this condition from
happening by checking if the voltage on the SLS pin is higher than Vth(capm)SLS.
If the voltage across resistor RSLS is higher than the Vth(capm)SLS threshold when the LS
transistor is switched on, the circuit assumes that it is in capacitive mode. When
capacitive mode is detected, the currents from the OTA are disabled and the capacitive
mode sink current, Io(sink)CI, is enabled. This sink current discharges the capacitor/resistor
circuitry on the CI pin and as a result gradually increase the half-bridge frequency.
Discharge continues for the remainder of the current switching cycle, so the total current
on CI is equal to the sink current. If capacitive mode persists, the action is repeated until
capacitive mode is not detected. If capacitive mode is no longer detected, the OTA starts
regulating again.
If the conditions causing the capacitive mode persist, the OTA regulates the system back
towards capacitive mode with the protection system taking control. The system operates
on the edge of capacitive mode. During boost and burn state, if the load on the half-bridge
continues to be capacitive at higher frequencies, CMP then eventually drives the
half-bridge to the maximum frequency fbridge(max). From this point, the IC enters
power-down mode.
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350 V and 600 V Power ICs for dimmable compact fluorescent lamps
7.4.5 Power-down mode
Power-down mode starts when:
• a continuous overcurrent exceeds the maximum overcurrent time-out tfault(oc).Or over
a longer period when an overcurrent occurs in more than half the number of cycles
Vth(CP)min is reached.
• during the boost or the burn state fbridge(max) is reached due to capacitive mode
detection
• two consecutive failed lamp ignition attempts occur
In power-down mode, the oscillator is stopped and the HS transistor is non-conductive
while the LS transistor is conductive. The VDD supply is internally clamped. The circuit is
released from power-down mode by lowering the low voltage supply lower than VDD(rst)
(mains switch reset).
An option exists to set the IC in power-down mode via external logic. The external
power-down option is only available when the IC is in the boost or burn state. To enable
the external power-down option, the CP pin is used. When pin CP, is connected via a
10 k resistor to either the PGND or SGND the voltage on pin CP is pulled down lower
than Vth(pd)CP. This results in the IC entering power-down mode.
Remark: Do not connect the CP pin directly to the SGND or PGND pin. Connect the
SGND or PGND pin via a series 10 kresistor otherwise excessive currents flow during
reset and start-up. Excessive current prevent the IC from starting up.
7.4.6 OverTemperature Protection (OTP)
The OTP circuit is designed to prevent the IC from overheating in hazardous
environments. The circuit is triggered when the IC temperature exceeds the maximum
temperature value Tj(otp). OTP changes the lamp current to the level that corresponds to
Votp(CSI) level. This condition remains until the IC temperature reduces by 20 C
(=Tj(otp)hys) and returns to the DCI controlled level.
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350 V and 600 V Power ICs for dimmable compact fluorescent lamps
8. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
Rext(RREF)
external resistance on pin RREF
fixed nominal value
33 k
30
36
k
SR
slew rate
on pins HBO with
respect to GND
4
+4
V/ns
P = 0.8 W
General
Tamb
ambient temperature
40
85
C
Tj
junction temperature
40
+150
C
Tstg
storage temperature
55
+150
C
UBA20272: Tj < Tjmax;
high-side;
IDM = IDHS = IHBO)
-
2.7
A
low-side;
IDM = IHBO = Io(SLS)
-
2.7
A
UBA20271: Tj < Tjmax;
high-side;
IDM = IDHS = IHBO)
-
5.0
A
low-side; 
IDM = IHBO = Io(SLS)
-
5.0
A
UBA20272: Tj = Tjmax;
high-side; P = 0.5 W;
ID = IDHS = IHBO
-
0.31
A
low-side;
ID = IHBO = Io(SLS)
-
0.31
A
UBA20271: Tj = Tjmax;
P = 0.5 W; high-side;
ID = IDHS = IHBO
-
0.54
A
low-side;
ID = IHBO = Io(SLS)
-
0.54
A
0
200
A
UBA20272: operating
-
500
V
during 1 second
-
600
V
UBA20271: operating
at Tamb = 25 C
-
350
V
operating at
Tamb = 25 C
-
340
V
with respect to HBO
Currents
IDM
peak drain current
peak drain current
ID
off-state current
off-state current
Ii(CF)
input current on pin CF
Voltages
VDHS
voltage on pin DHS
voltage on pin DHS
VFS
voltage on pin FS
0.3
+14
V
VDD
supply voltage
0.3
+14
V
Vi(CSI)
input voltage on pin CSI
5
+5
V
Vi(DCI)
input voltage on pin DCI
0
5
V
Vi(SLS)
input voltage on pin SLS
6
+6
V
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350 V and 600 V Power ICs for dimmable compact fluorescent lamps
Table 3.
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VCI
VMDL
Conditions
Min
Max
Unit
voltage on pin CI
0
3.5
V
voltage on pin MDL
0
5
V
all pins, except pins 16,
17, 18, 19 and 20
2000
+2000
V
pins 16, 17, 18, 19 and
20
1000
+1000
V
400
+400
V
-
-
-
ESD
electrostatic discharge voltage
VESD
human body model:
charged device model:
all pins
[1]
Latch-up
[1]
In accordance with SNW-FQ-303: all pins.
9. Thermal characteristics
Table 4.
Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
Rth(j-a)
thermal resistance from junction to
ambient
in free air; SO20 package on
JEDEC 2S 2P board
56
K/W
10. Characteristics
Table 5.
Characteristics
VDD = 13 V; VFS - VHBO = 13 V; Tamb = 25 C; settings according to default setting in Table 6, all voltages referenced to GND,
positive currents flow into the IC, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
high-side switch = off;
low-side switch = on
5.7
6.2
6.7
V
Start-up state (VDD)
VDD(rst)
reset supply voltage
VDD(stop)
stop supply voltage
9.6
10.0
10.4
V
VDD(start)
start supply voltage
11.9
12.4
12.9
V
VDD(hys)
hysteresis of supply
voltage
2.2
2.4
2.6
V
VDD(clamp)
clamp supply voltage
Iclamp(VDD) = 5 mA
13.0
13.4
13.8
V
IDD(clamp)
clamp supply current
VDD = 14 V
20
30
-
mA
IDD(startup)
start-up supply current VDD = 9 V
-
190
220
A
IDD(pd)
power-down supply
current
VDD = 9 V
-
190
220
A
IDD
supply current
default setting; VDCI = 1.4 V
-
1.6
2.0
mA
[1]
VCI = Vclamp(CI), VCB = 0 V
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350 V and 600 V Power ICs for dimmable compact fluorescent lamps
Table 5.
Characteristics …continued
VDD = 13 V; VFS - VHBO = 13 V; Tamb = 25 C; settings according to default setting in Table 6, all voltages referenced to GND,
positive currents flow into the IC, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
UBA20271; 300 V on
high-voltage pins
-
-
30
A
UBA20272; 500 V on
high-voltage pins
-
-
30
A
2.7
3.0
3.3
V
-
80
-
mV
High-voltage supply (DHS, HBO and FS)
Ileak
leakage current
Voltage controlled oscillator
Output pin IC
VCI(max)
maximum voltage on
pin CI
Vhr(CI)
headroom voltage on
pin CI
Vclamp(CI) = Vhr(CI)) + VCI(max);
burn and boost state
Voltage controlled oscillator
Output pin CF
fbridge(max)
maximum bridge
frequency
CCF = 100 pF; VCI = 0 V
[2]
88
100
112
kHz
fbridge(bst)min
minimum boost bridge
frequency
CCF = 100 pF;
VCI = Vclamp(CI)
[2]
21
22
23
kHz
fbridge(min)
minimum bridge
frequency
CCF = 100 pF;
VCI = Vclamp(CI) ; VCB = 0 V
[2]
38
40
42
kHz
tno
non-overlap time
VHBO rising edge
1.3
1.5
1.7
s
VHBO falling edge
1.3
1.5
1.7
s
Vth(CF)max
maximum threshold
voltage on pin CF
CCF = 100 pF;
VCI = Vclamp(CI) ; VCB = 0 V
2.40
2.50
2.60
V
Io(bst)CF
boost output current
on pin CF
VCF = 1.5 V; VCI = Vclamp(CI)
12.3
11.8
11.3
A
Io(CF)min
minimum output
current on pin CF
VCF = 1.5 V; VCB = 0 V;
VCI = Vclamp(CI)
-22.8
-21.8
-20.8
A
Io(CF)max
maximum output
current on pin CF
VCF = 1.5 V; VCB = 0 V
-67.0
-60.0
-53.0
A
on-state resistance
UBA20272:
high-side IDHS = 1.1 A;
Tj = 25 C
-
3.0
3.6

on-state resistance
UBA20271:
high-side IDHS = 1.1 A;
Tj = 25 C
-
1.0
1.3

on-state resistance
UBA20272:
low-side IHBO = 1.1 A;
Tj = 25 C
-
3.0
3.6

on-state resistance
UBA20271:
low-side IHBO = 1.1 A;
Tj = 25 C
-
1.0
1.3
W
Power transistors
Ron
Ron
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350 V and 600 V Power ICs for dimmable compact fluorescent lamps
Table 5.
Characteristics …continued
VDD = 13 V; VFS - VHBO = 13 V; Tamb = 25 C; settings according to default setting in Table 6, all voltages referenced to GND,
positive currents flow into the IC, unless otherwise specified.
Symbol
Parameter
Ron(150)/Ron(25) on-state resistance
ratio (150 C to 25 C)
Conditions
Min
Typ
Max
Unit
RON at Tj = 150 C /
RON at Tj = 25 C
-
1.7
-
bootstrap diode; IFS = 5 mA;
(VF = VDD -VFS)
1.3
1.7
2.1
V
Vi(SLS) = 0.4 V
-
-
1
A
0.57
0.60
0.63
V
Bootstrap diode
VF
forward voltage
Preheat current sensor
Input: pin SLS
II(SLS)
input current on pin
SLS
Vph(SLS)
preheat voltage on pin
SLS
[3]
Output: pin CI
Io(source)CI
source output current
on pin CI
VCI = 2.0 V; Vi(SLS) < 0.6 V
10.6
9.6
8.6
A
Io(sink)CI
sink output current on
pin CI
VCI = 2.0 V; Vi(SLS) > 0.6 V
26
29
32
A
Preheat timer, ignition timer, overcurrent fault timer
Pin CP
tph
preheat time
CCP = 470 nF;
Rext(RREF) = 33 k
-
0.93
-
s
ten(ign)
ignition enable time
CCP = 470 nF;
Rext(RREF) = 33 k
-
0.22
-
s
tfault(oc)
overcurrent fault time
CCP = 470 nF;
Rext(RREF) = 33 k;
initial voltage VCP = 5.0 V
-
0.10
-
s
Io(CP)
output current on pin
CP
VCP = 4.1 V; source () and
sink (+)
5.5
5.9
6.3
A
Vth(CP)min
minimum threshold
voltage on pin CP
-
3.8
-
V
Vth(CP)max
maximum threshold
voltage on pin CP
-
4.5
-
V
Vhys(CP)
hysteresis voltage on
pin CP
0.6
0.7
0.8
V
Ipu(CP)
pull-up current on pin
CP
VCP = 3.8 V
-
60
-
A
Vth(pd)CP
power-down threshold
voltage on pin CP
burn state, pin CP connected
to SGND via 10 k
-
1.0
-
V
Vth(rel)CP
release threshold
voltage on pin CP
hold state, VDCI = 1.4 V
-
2.7
-
V
tbst
boost time
CCB = 470 nF; Tj < 80 C
-
148
-
s
Io(CB)
output current on pin
CB
VCB = 2.35 V; source () and
sink (+)
0.8
1.0
1.2
A
Boost timer
Pin CB
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350 V and 600 V Power ICs for dimmable compact fluorescent lamps
Table 5.
Characteristics …continued
VDD = 13 V; VFS - VHBO = 13 V; Tamb = 25 C; settings according to default setting in Table 6, all voltages referenced to GND,
positive currents flow into the IC, unless otherwise specified.
Symbol
Parameter
Vth(CB)min
Conditions
Min
Typ
Max
Unit
minimum threshold
voltage on pin CB
-
1.1
-
V
Vth(CB)max
maximum threshold
voltage on pin CB
-
3.6
-
V
Vhys(CB)
hysteresis voltage on
pin CB
2.3
2.5
2.7
V
Tj(bp)bst
boost bypass junction
temperature
Tj sensed at end ignition time
65
80
95
C
Tj(end)bst
boost end junction
temperature
Tj during boost time
105
120
135
C
Idet(dis)bst
boost disable detection VCB = 0 V
current
-30
-25
-20
A
tt(bst-burn)
transition time from
boost to burn
CCP = 470 nF; Tj < 80 C
-
3.6
-
s
lamp current boost
ratio
VCSI in boost state versus
VCSI in burn state;
VDCI = 1.34 V
1.4
1.5
1.6
Pin CSI
NLCBR
Coil saturation protection and overcurrent detection
Input: pin SLS
Vth(sat)SLS
saturation threshold
voltage on pin SLS
ignition state; RLSAT = 47 k
1.10
1.18
1.25
V
Vth(ocp)SLS
overcurrent protection
threshold voltage on
pin SLS
boost state and burn state;
RLSAT = 47 k
1.10
1.18
1.25
V
tleb
leading edge blanking
time
detection disabled first part of
GLS time
-
800
-
ns
Io(sink)CI
sink output current on
pin CI
VCI = 2.0 V; ignition state;
Vi(SLS) > Vth(sat)SLS; cycle
clocked
26
29
32
A
Isource(LSAT)
source current on pin
LSAT
VLSAT = 1.2 V
26.3
25.0
23.7
A
Vclamp(LSAT)
clamp voltage on pin
LSAT
RLSAT = ;
2.3
2.5
2.7
V
saturation output
current difference on
pin CF
VCF = 1.5 V; ignition state;
low side switch = on
-
160
-
A
Input: pin LSAT
Output: pin CF
Io(sat)CF
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350 V and 600 V Power ICs for dimmable compact fluorescent lamps
Table 5.
Characteristics …continued
VDD = 13 V; VFS - VHBO = 13 V; Tamb = 25 C; settings according to default setting in Table 6, all voltages referenced to GND,
positive currents flow into the IC, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
0.55
0.60
0.65
V
685
885
1085
ns
15
5
0
mV
26
29
32
A
input resistance on pin Vi(CSI) = 1 V
CSI
Vi(CSI) = 1 V
1
-
-
M
40
50
60
k
input voltage on pin
CSI
controlled feedback RMS
voltage at minimum dim
level; Vi(DCI) = 0 V;
Rext(RREF) = 33 k;
RMDL = 2.0 k
44
50
56
mV
controlled feedback RMS
voltage at mid scale of lin log
curve in burn state;
Vi(DCI) = 0.9 V;
Rext(RREF) = 33 k
-
215
-
mV
voltage rectification range for
linear operation
2.5
-
+2.5
V
clamping voltage on
pin CSI
100 % light output;
Vi(DCI)  1.34 V
-
1.0
-
V
Vi(DCI)
input voltage on pin
DCI
minimum voltage set by MDL
pin resistor
VT(hec2)DCI
-
1.34
V
Ri(DCI)
input resistance on pin Vi(CSI) = 1 V
DCI
1
-
-
M
Vth(bst)DCI
boost threshold
voltage on pin DCI
1.00
1.05
1.10
V
Vth(bst)hys(DCI)
hysteresis boost
threshold voltage on
pin DCI
80
100
120
mV
Ignition current detection
Input: pin CSI
Vth(det)ign(CSI)
ignition detection
threshold voltage on
pin CSI
tw(det)ign(min)
minimum ignition
detection pulse width
Vth(det)ign(CSI) = 0.75 V square
pulse
Capacitive mode detection
Input: pin SLS
Vth(capm)SLS
[4]
capacitive mode
threshold voltage on
pin SLS
Output: pin CI
Io(sink)CI
sink output current on
pin CI
VSLS > Vth(capm)SLS;
VCI = 2.0 V; ignition state or
boost and burn state
Lamp current sensor and dimming control
Input: pin CSI
Ri(CSI)
Vi(CSI)
Vclamp(CSI)
Input: pin DCI
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350 V and 600 V Power ICs for dimmable compact fluorescent lamps
Table 5.
Characteristics …continued
VDD = 13 V; VFS - VHBO = 13 V; Tamb = 25 C; settings according to default setting in Table 6, all voltages referenced to GND,
positive currents flow into the IC, unless otherwise specified.
Symbol
Parameter
Vth(start)DCI
Conditions
Min
Typ
Max
Unit
start threshold voltage
on pin DCI
-
0.35
-
V
Vth(hys)DCI
hysteresis threshold
voltage on pin DCI
80
100
120
mV
VT(hec1)DCI
human eye correction
1 transition voltage on
pin DCI
Vi(CSI) = 0 V; VMDL = 0 V
-
0.17
-
V
VT(hec2)DCI
human eye correction
2 transition voltage on
pin DCI
Rext(RREF) = 33 k;
RMDL = 2.0 k;
Vi(CSI) = Vclamp(CSI)
-
0.44
-
V
VT(hec3)DCI
human eye correction
3 transition voltage on
pin DCI
Vi(CSI) = 1 V
-
1.34
-
V
Votp(CSI)
overtemperature
protection voltage on
pin CSI
RMS voltage;
Rext(RREF) = 33 k;
RMDL = 2.0 k;
Vi(DCI) = 1.5 V;
Tj > Tj(otp)  Tj(otp)hys
380
400
420
mV
output current on pin
CI
burn state; source () and
sink (+); VCI = 2.0 V
85
95
105
A
-26.3
-25.0
-23.7
A
-
50
-
mV
Output: pin CI
Io(CI)
Input: pin MDL
Isource(MDL)
source current on pin
MDL
VMDL
voltage on pin MDL
Rext(RREF) = 33 k;
RMDL = 2.0 k
Temperature protection
Tj(otp)
overtemperature
protection junction
temperature
145
160
175
C
Tj(otp)hys
hysteresis
overtemperature
protection junction
temperature
10
20
30
C
[1]
For the default setting, see Table 6.
[2]
Switching frequency of the half-bridge output HBO. The sawtooth frequency on pin CF is twice as high.
[3]
Data sampling of Vph(SLS) is performed at the end of the conduction period of the low-side power MOSFET, in preheat state.
[4]
Data sampling of Vth(capm)SLS is performed at the start of conduction of the low-side power MOSFET, in all states with oscillator active.
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350 V and 600 V Power ICs for dimmable compact fluorescent lamps
11. Application information
11.1 Design equations
All equations are only valid for Rext(RREF) = 33 k
11.1.1 CCP related timing equations:
• Preheat time:
C CP
t ph = --------------   16  V hys  CP  + 5 – V th  CP max 
I o  CP 
(1)
• Ignition enabling time:
C CP
t en  ign  = --------------  4  V hys  CP 
I o  CP 
(2)
• Overcurrent fault time:
C CP
t fault  oc  = --------------   5 – V th  CP min 
I o  CP 
(3)
• Transition to burn time:
C CP
t t  bst – burn  = --------------   64  V hys  CP  + 5 – V th  CP max 
I o  CP 
(4)
• Restart delay time
C CP
t d  restart  = --------------------------   V th  CP max – V th  rel CP 
I restart  CP 
(5)
Where: Irestart(CP) = 0.5 A (typical)
11.1.2 CCB related timing equations:
• Boost time:
C CB
t bst = --------------   126  V hys  CB  + V th  CB min – 0.6 
I o  CB 
(6)
11.1.3 CCF related frequency equations:
• Maximum bridge frequency:
0.5
f bridge  max  = ---------------------------------------------------------------------------+
C
C CF
par
-------------------------- V th  CF max + t dch
I o  CF max
(7)
• Minimum bridge frequency with disabled boost:
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350 V and 600 V Power ICs for dimmable compact fluorescent lamps
0.5
f bridge  min  = ---------------------------------------------------------------------------C CF + C par
---------------------------  V th  CF max + t dch
I o  CF min
(8)
• Minimum bridge frequency with enabled boost
0.5
f bridge  bst min = ---------------------------------------------------------------------------C CF + C par
---------------------------  V th  CF max + t dch
I o  bst CF
(9)
Where: Cpar = 4.7 [pF] and tdch = 0.4 [s] (typical)
11.1.4 RSLS related preheat current:
V ph  SLS 
I ph  M  = -------------------R SLS
V ph  SLS 
I ph  RMS   ------------------------R SLS  3
(10)
11.1.5 RMDL related MDL:
• MDL threshold voltage:
V MDL = R MDL  I source  MDL 
(11)
11.1.6 RLSAT related saturation and overcurrent threshold level
• Saturation threshold voltage
V th  sat SLS = V th  ocp SLS = R LSAT  I source  LSAT 
D5
D6
(12)
DHS 18
FS
C3
C17
R5
L2
14
16
13
C12
R1
D1
L1
C1
D2
C2
C9
D3
D4
C10
R2
C4
RSLS
C8
R9
R7
C11
C13
C5
R3
R4
HBO 20
VDD
6
D8
D7
RCSI
R10
D9
C14
R11
C8
10
HBO 19
CFL
C7
CCP
CP
GHS
HBO 17
R6
CCB
CB
GLS
SLS 1
SLS
2
SLS
3 UBA20271/2
CSI
11
DCI
12
5
15
C6
PGND
9
7
8
4
CI
C15
C16
MDL
RMDL
RREF
RREF
CF
LSAT
SGND
CCF
RLSAT
CLSAT
001aam783
Fig 11. Application diagram
Detailed in Table 6 is a list of typical application components. See Figure 11.
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350 V and 600 V Power ICs for dimmable compact fluorescent lamps
Table 6.
Typical components for a 230 V mains application
Reference Component
UBA20271
UBA20271_UBA20272
Product data sheet
Description
UBA20272
R1
10
10
R2, R3
110 k
220 k
R4
22 k
22 k
R5, R6
110 k
330 k
R7, R10
100 k
100 k
R8
560 
1 k
R9
1 k
1 k
R11
39 k
39 k
RREF
33 k; 1 %
33 k; 1 %
RSLS
1
1.2 
RMDL
1 k
1 k
RCSI
8.2 
8.2 
Adjust for nominal lamp
current
RLSAT
100 k
100 k
RLSAT depends on the
LSAT rating of the lamp
inductor
C1, C2
22 nF; 400 V
22 nF; 630 V
C3
3.3 nF; 1000 V
3.3 nF; 1000 V
C4
22 F; 250 V
10 F; 400 V
C5
6.8 nF; 1000 V
4.7 nF; 1000 V
C6, C14
470 nF
470 nF
C7
100 pF
100 pF
C8
22 nF; 400 V
47 nF; 400 V
C9
560 pF; 500 V
560 pF; 500 V
C10
not mounted
not mounted
C11
4.7 nF
4.7 nF
C12
100 nF
100 nF
C13
470 nF
470 nF
C15
220 nF
220 nF
C16
not mounted
not mounted
C17
22 nF; 250 V
22 nF; 400 V
CCB
150 nF
150 nF
CCP
470 nF
470 nF
CCF
100 pF; 2 %
100 pF; 2 %
CLSAT
1 nF
1 nF
D1 to D4
1N4007
1N4007
D5, D6
1N4937
1N4937
D7
BZX84JC12
BZX84JC12
D8
1N4148
1N4148
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Rev. 2.1 — 12 October 2011
2 W fusible resistor
lamp capacitor
VDD charge pump
capacitor
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350 V and 600 V Power ICs for dimmable compact fluorescent lamps
Table 6.
Typical components for a 230 V mains application …continued
Reference Component
L1
UBA20271_UBA20272
Product data sheet
Description
UBA20271
UBA20272
4.7 mH
4.7 mH
mains filter inductor;
ISAT = 300 mA
lamp inductor
L2
1000/4/4 H
2000/2/2 H
D9
1N4148
1N4148
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12. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
HE
y
v M A
Z
11
20
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
10
e
bp
detail X
w M
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.3
0.1
2.45
2.25
0.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.01
0.019 0.013
0.014 0.009
0.51
0.49
0.30
0.29
0.05
0.419
0.043
0.055
0.394
0.016
inches
0.1
0.012 0.096
0.004 0.089
0.043
0.039
0.01
0.01
Z
(1)
0.9
0.4
0.035
0.004
0.016
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT163-1
075E04
MS-013
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 12. Package outline SOT163-1 (SO20)
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350 V and 600 V Power ICs for dimmable compact fluorescent lamps
13. Abbreviations
Table 7.
UBA20271_UBA20272
Product data sheet
Abbreviations
Acronym
Description
CFL
Compact Fluorescent Lamp
CMP
Capacitive Mode Protection
DSR
Double-Sided Rectifier
ESD
ElectroStatic Discharge
HS
High-Side
LS
Low-Side
MDL
Minimum Dimming Level
OCP
OverCurrent Protection
OPP
OverPower Protection
OTA
Operational Transconductance Amplifier
OTP
OverTemperature Protection
RMS
Root Mean Square
SR
Slew Rate
UVLO
UnderVoltage LockOut
VCO
Voltage Controlled Oscillator
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14. Revision history
Table 8.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
UBA20271_UBA20272 v.2.1
20111012
Product data sheet
-
UBA20271_UBA20272 v.2
Modifications:
•
•
•
minor text changes.
Figure 1 changed.
Figure 2 changed.
UBA20271_UBA20272 v.2
20110816
Product data sheet
-
UBA20271_UBA20272 v.1
UBA20271_UBA20272 v.1
20110816
Preliminary data sheet
-
-
UBA20271_UBA20272
Product data sheet
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15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
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350 V and 600 V Power ICs for dimmable compact fluorescent lamps
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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350 V and 600 V Power ICs for dimmable compact fluorescent lamps
17. Contents
1
2
2.1
2.2
2.3
2.4
2.5
2.6
3
4
5
6
6.1
6.2
7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.2
7.2.1
7.2.2
7.3
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
8
9
10
11
11.1
11.1.1
11.1.2
11.1.3
11.1.4
11.1.5
11.1.6
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Half-bridge features . . . . . . . . . . . . . . . . . . . . . 1
Preheat and ignition features . . . . . . . . . . . . . . 1
Lamp boost features . . . . . . . . . . . . . . . . . . . . . 1
Dim features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Other features. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Lamp start-up cycle . . . . . . . . . . . . . . . . . . . . . 6
Reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Start-up state . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Preheat state . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ignition state . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Boost state and transition to burn state . . . . . . 8
Burn state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Hold state . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Oscillation and timing . . . . . . . . . . . . . . . . . . . 11
Oscillation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Combined timing circuit . . . . . . . . . . . . . . . . . 12
Natural linear dimming . . . . . . . . . . . . . . . . . . 13
Protection and power-down . . . . . . . . . . . . . . 14
Coil saturation protection . . . . . . . . . . . . . . . . 14
OverCurrent Protection (OCP) . . . . . . . . . . . . 15
OverPower Protection (OPP) . . . . . . . . . . . . . 15
Capacitive Mode Protection (CMP) . . . . . . . . 15
Power-down mode . . . . . . . . . . . . . . . . . . . . . 16
OverTemperature Protection (OTP) . . . . . . . . 16
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17
Thermal characteristics . . . . . . . . . . . . . . . . . 18
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 18
Application information. . . . . . . . . . . . . . . . . . 24
Design equations . . . . . . . . . . . . . . . . . . . . . . 24
CCP related timing equations: . . . . . . . . . . . . . 24
CCB related timing equations: . . . . . . . . . . . . . 24
CCF related frequency equations: . . . . . . . . . . 24
RSLS related preheat current: . . . . . . . . . . . . . 25
RMDL related MDL: . . . . . . . . . . . . . . . . . . . . . 25
RLSAT related saturation and overcurrent
threshold level . . . . . . . . . . . . . . . . . . . . . . . . 25
12
13
14
15
15.1
15.2
15.3
15.4
16
17
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
29
30
31
31
31
31
32
32
33
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 12 October 2011
Document identifier: UBA20271_UBA20272
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