RT3662AC Dual-Output PWM Controller with 3 Integrated Drivers for AMD SVI2 Mobile CPU Power Supply General Description Features RT3662AC is a dual-output PWM controller with 3 integrated drivers, and it is compliant with AMD SVI2 Voltage Regulator Specification to support both CPU core (VDD) and Northbridge portion of CPU (VDDNB). The RT3662AC features CCRCOT (Constant Current Ripple Constant On-Time) with G-NAVP (Green-Native AVP), which is Richtek's proprietary topology. G-NAVP makes it an easy setting controller to meet all AMD AVP (Adaptive Voltage Positioning) VDD/VDDNB requirements. The droop is easily programmed by setting the DC gain of the error amplifier. With proper compensation, the load transient response can achieve optimized AVP performance. The controller also uses the interface to issue VOTF Complete and to send digitally encoded voltage and current values for the VDD/VDDNB domains. The RT3662AC can operate in diode emulation mode to enhance the light load efficiency. And it provides the current gain adjustment capability by pin setting. RT3662AC provides power good indication, thermal indication (VRHOT_L), and it features complete fault protection functions including over current, over voltage and under voltage. 2/1-Phase (VDD) + 1/0-Phase (VDDNB) PWM Controller 3 Embedded MOSFET Drivers G-NAVPTM Topology Support Dynamic Load-Line and Zero Load-Line Diode Emulation Mode at Light Load Condition SVI2 Interface to Comply with AMD Power Management Protocol Adjustable Current Gain Capability DVID Enhancement 0.5% DAC Accuracy Differential Remote Voltage Sensing Build-in ADC for Pin Setting Programming, Thermal Indication and VOUT, IOUT Reporting Fast Transient Response Power Good Indicator Thermal Indicator (VRHOT_L) OVP, UVP and UVLO Over Current Protection Applications AMD SVI2 Mobile CPU Laptop Computer Marking Information RT3662AC GQW YMDNN RT3662ACGQW : Product Number YMDNN : Date Code Simplified Application Circuit RT3662AC VRHOT_L PHASE1 SVC To CPU Copyright © 2016 Richtek Technology Corporation. All rights reserved. April 2016 PHASE2 MOSFET PHASE_NB MOSFET VVDD SVD SVT DS3662AC-01 MOSFET VVDDNB is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT3662AC Pin Configurations Ordering Information RT3662AC (TOP VIEW) PHASE2 LGATE2 BOOT1 UGATE1 PHASE1 LGATE1 PVCC LGATE_NB PHASE_NB UGATE_NB Package Type QW : WQFN-40L 5x5 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) Note : 40 39 38 37 36 35 34 33 32 31 Richtek products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. UGATE2 BOOT2 PGOOD RGND COMP FB ISEN2P VSEN ISEN1P ISEN1N 1 30 2 29 3 28 27 4 5 26 GND 6 25 7 24 8 41 23 22 9 21 10 BOOT_NB EN VIN COMP_NB FB_NB ISENP_NB ISENN_NB TSEN_NB VDDIO SVT VRHOT_L TSEN SET1 IMON VREF_PINSET IMON_NB VCC PWROK SVC SVD 11 12 13 14 15 16 17 18 19 20 WQFN-40L 5x5 Functional Pin Description Pin No. Pin Name Pin Function 1 UGATE2 Upper Gate Driver Output of Phase 2 for VDD Controller. Connect this pin to the gate input of high side MOSFET. 2 BOOT2 Bootstrap Supply of VDD Controller for Phase 2 High Side MOSFET. This pin powers high side MOSFET driver. 3 PGOOD Power Good Indicator for the VDD and VDDNB Controller. This pin is an open drain output. 4 RGND Return Ground of VDD and VDDNB Controllers. This pin is the common negative input of output voltage differential remote sense of VDD and VDDNB controllers. 5 COMP Error Amplifier Output Pin of the VDD Controller. 6 FB Output Voltage Feedback Input of VDD Controller. This pin is the negative input of the error amplifier for the VDD controller. 7 ISEN2P Positive Current Sense Input of Phase 2 for VDD Controller. 8 VSEN VDD Controller Voltage Sense Input. This pin is connected to the terminal of VDD controller output voltage. 9 ISEN1P Positive Current Sense Input of Phase 1 for VDD Controller. 10 ISEN1N Common Negative Current Sense Input of Phase1 and Phase 2 for VDD Controller. 11 VRHOT_L Thermal Indicator. This pin is an open drain output. (Active low) Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS3662AC-01 April 2016 RT3662AC Pin No. Pin Name Pin Function 12 TSEN This Pin Provides Two Functions: Platform Setting, Platform can use this pin to set frequency of VDD and VDDNB Controllers, initial offset and per-phase OCP threshold of VDD Controller. The other function is thermal sense input for VRHOT indicator. Connect the NTC network for thermal sensing to this pin. 13 SET1 Platform Setting Pin. Platform can use this pin to set the AI gain of VDD and VDDNB Controllers, VDDNB Voltage Reporting Compensation bit1~bit3 and VDD Controller QRTH. 14 IMON Current Monitor Output for the VDD Controller. This pin outputs a voltage proportional to the output current. 15 This Pin Provides Two Functions: The 3.2V power supply for pin setting function divided resistors. The other function is fixed 0.8V output reference VREF_PINSET voltage, and the voltage is only used to offset the output voltage of IMON and IMON_NB pins. Connect a RC circuit from this pin to GND. The recommended resistor is from 3.9 to 10, and the capacitor is 0.47F. 16 IMON_NB Current Monitor Output for the VDDNB Controller. This pin outputs a voltage proportional to the output current. 17 VCC Controller Power Supply. Connect this pin to 5V and place a decoupling capacitor 2.2F at least. The decoupling capacitor is as close controller as possible. 18 PWROK System Power Good Input. If PWROK is low, the SVI interface is disabled and VR returns to BOOT-VID state with initial load-line slope and initial offset. If PWROK is high, the SVI interface is running and the DAC decodes the received serial VID codes to determine the output voltage. 19 SVC Serial VID Clock Input. 20 SVD Serial VID Data Input. This pin is a serial data line. 21 SVT Serial VID Telemetry Output from VR. This pin is a push-pull output. 22 VDDIO Processor Memory Interface Power Rail and Serves as the Reference for PWROK, SVD, SVC and SVT. This pin is used by the VR to reference the SVI pins. 23 TSEN_NB This Pin Provides Two Functions: Platform Setting, Platform can use this pin to set initial offset, BOOT VID, Voltage Reporting Compensation bit0 and perphase OCP threshold of VDDNB Controller. The other function is thermal sense input for VRHOT indicator. Connect the NTC network for thermal sensing to this pin. 24 ISENN_NB Negative Current Sense Input for VDDNB Controller. 25 ISENP_NB Positive Current Sense Input for VDDNB Controller. 26 FB_NB Output Voltage Feedback Input of VDDNB Controller. This pin is the negative input of the error amplifier for the VDDNB controller. 27 COMP_NB Error Amplifier Output Pin of the VDDNB Controller. 28 VIN VIN Input Pin. Connect a low pass filter to this pin. 29 EN Controller Enable Input Pin. 30 BOOT_NB Bootstrap Supply of VDDNB Controller for High Side MOSFET. This pin powers high side MOSFET driver. 31 UGATE_NB Upper Gate Driver Output of VDDNB Controller. Connect this pin to the gate input of high side MOSFET. Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3662AC-01 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT3662AC Pin No. Pin Name Pin Function 32 PHASE_NB Switch Nodes of High Side Driver for VDDNB Controller. Connect this pin to high side MOSFET Source together with the low side MOSFET Drain and the inductor. 33 LGATE_NB Lower Gate Driver Output of VDDNB Controller. Connect this pin to the gate input of low side MOSFET. 34 PVCC Driver Power Supply. Connect this pin to GND by the 2.2F ceramic capacitor at least. The decoupling capacitor is as close controller as possible. 35 LGATE1 Lower Gate Driver Output of Phase 1 for VDD Controller. Connect this pin to the gate input of low side MOSFET. 36 PHASE1 Phase 1 Switch Nodes of High Side Driver for VDD Controller. Connect this pin to high side MOSFET Source together with the low side MOSFET Drain and the inductor. 37 UGATE1 Upper Gate Driver Output of Phase 1 for VDD Controller. Connect this pin to the gate input of high side MOSFET. 38 BOOT1 Bootstrap Supply of VDD Controller for Phase 1 High Side MOSFET. This pin powers high side MOSFET driver. 39 LGATE2 Lower Gate Driver Output of Phase 2 for VDD Controller. Connect this pin to the gate input of low side MOSFET. 40 PHASE2 Phase 2 Switch Nodes of High Side Driver for VDD Controller. Connect this pin to high side MOSFET Source together with the low side MOSFET Drain and the inductor. 41 (Exposed Pad) GND Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS3662AC-01 April 2016 RT3662AC VRHOT_L PGOOD VCC EN PWROK VDDIO SVT SVD SVC TSEN_NB TSEN IMONI_NB IMONI ISENN_NB SET1 VSEN Function Block Diagram UVLO GND MUX RGND SVI2 Interface Configuration Registers Control Logic ADC From Control Logic DAC Soft Start& Slew Rate Control VSET + ERROR AMP AI_VDD, AI_VDDNB QR_TH TONSET OFFSET PHOCP_TH VDDNB Voltage Reporting Compensation Offset Cancellation - FB - COMP PWM CMP ISEN1N - 0.75 x AI_VDD IB1 PWM1 BOOTx PWM2 Driver UGATEx PHASEx LGATEx RAMP TONSET + 1.867m - Current Balance IB2 + ISEN2P TON GEN QR_TH 1.867m + VIN + + ISEN1P Loop Control Protection Logic - VSEN IMONI IMON IB1 Driver POR IB2 OV/UV VREF_PINSET PVCC From Control Logic + RGND OCP_SPIKE DAC OC To Protection Logic - VIN Soft Start& Slew Rate Control VSET_NB + ERROR AMP Offset Cancellation - + - + FB_NB PWM CMP TON GEN COMP_NB TONSET 1.867m ISENP_NB + ISENN_NB - PWM _NB BOOT_NB Driver UGATE_NB PHASE_NB LGATE_NB RAMP 0.75 x AI_VDDNB + VREF_PINSET - IMON_NB IMONI_NB ISENN_NB OV/UV + OC_NB OCP_SPIKE_NB Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3662AC-01 April 2016 - To Protection Logic is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT3662AC Operation The RT3662AC adopts G-NAVPTM (Green Native Error Amplifier AVP) which is Richtek's proprietary topology derived from finite DC gain of EA amplifier with current mode control, making it easy to set the droop to meet all AMD CPU requirements of AVP (Adaptive Voltage Positioning). The G-NAVPTM controller is one type of current mode constant on-time control with DC offset Error amplifier generates COMP/COMP_NB signal by the difference between VSET/VSET_NB and FB/FB_NB. cancellation. The approach can not only improve DC offset problem for increasing system accuracy but also provide fast transient response. When current feedback signal reaches COMP signal, it generates an on-time width to achieve PWM modulation. voltage ripple and current ripple to achieve accurate output voltage. Offset Cancellation This block cancels the output offset voltage from UVLO Detect the VCC pin voltage for under voltage lockout protection and power on reset operation. MUX and ADC The MUX supports the inputs from SET1, TSEN, TSEN_NB, IMONI, IMONI_NB, ISENN_NB and VSEN. The ADC converts these analog signals to digital codes for reporting or performance adjustment. SVI2 Interface/Configuration Registers/Control Logic The SVI2 interface uses the SVC, SVD, and SVT pins to communicate with CPU. The configuration registers save the digital data from ADC output for reporting or performance adjustment. The Control Logic controls the ADC timing and generates the digital code of the VID for VDD/VDDNB voltage. Loop Control Protection Logic Loop control protection logic detects EN and UVLO signals to initiate the soft-start function, and the PGOOD and VRHOT_L will be controlled after the soft-start is finished. When VRHOT indication event occurs, the VRHOT_L pin voltage will be pulled low. Current Balance Each phase current sense signal is sent to the current balance circuit which adjusts the on-time of each phase to optimize current sharing. PWM CMP The PWM comparator compares COMP signal (COMP/COMP_NB) and current feedback signal to generate a signal for TONGEN. TONGEN This block generates an on-time pulse which high interval is based on the on-time setting. RAMP The Ramp generator is designed to improve noise immunity and reduce jitter. OC/OV/UV Output voltage and output current are sensed for over current, over voltage and under voltage protection. DAC The DAC receives VID codes from the SVI2 control logic to generate an internal reference voltage (VSET/VSET_NB) for controller. Soft-Start and Slew-Rate Control This block controls the slew rate of the internal reference voltage when output voltage changes. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 is a registered trademark of Richtek Technology Corporation. DS3662AC-01 April 2016 RT3662AC Table 1. Serial VID Codes SVID [7:0] Voltage (V) SVID [7:0] Voltage (V) SVID [7:0] Voltage (V) SVID [7:0] Voltage (V) 0000_0000 1.55000 0010_0111 1.30625 0100_1110 1.06250 0111_0101 0.81875 0000_0001 1.54375 0010_1000 1.30000 0100_1111 1.05625 0111_0110 0.81250 0000_0010 1.53750 0010_1001 1.29375 0101_0000 1.05000 0111_0111 0.80625 0000_0011 1.53125 0010_1010 1.28750 0101_0001 1.04375 0111_1000 0.80000 0000_0100 1.52500 0010_1011 1.28125 0101_0010 1.03750 0111_1001 0.79375 0000_0101 1.51875 0010_1100 1.27500 0101_0011 1.03125 0111_1010 0.78750 0000_0110 1.51250 0010_1101 1.26875 0101_0100 1.02500 0111_1011 0.78125 0000_0111 1.50625 0010_1110 1.26250 0101_0101 1.01875 0111_1100 0.77500 0000_1000 1.50000 0010_1111 1.25625 0101_0110 1.01250 0111_1101 0.76875 0000_1001 1.49375 0011_0000 1.25000 0101_0111 1.00625 0111_1110 0.76250 0000_1010 1.48750 0011_0001 1.24375 0101_1000 1.00000 0111_1111 0.75625 0000_1011 1.48125 0011_0010 1.23750 0101_1001 0.99375 1000_0000 0.75000 0000_1100 1.47500 0011_0011 1.23125 0101_1010 0.98750 1000_0001 0.74375 0000_1101 1.46875 0011_0100 1.22500 0101_1011 0.98125 1000_0010 0.73750 0000_1110 1.46250 0011_0101 1.21875 0101_1100 0.97500 1000_0011 0.73125 0000_1111 1.45625 0011_0110 1.21250 0101_1101 0.96875 1000_0100 0.72500 0001_0000 1.45000 0011_0111 1.20625 0101_1110 0.96250 1000_0101 0.71875 0001_0001 1.44375 0011_1000 1.20000 0101_1111 0.95625 1000_0110 0.71250 0001_0010 1.43750 0011_1001 1.19375 0110_0000 0.95000 1000_0111 0.70625 0001_0011 1.43125 0011_1010 1.18750 0110_0001 0.94375 1000_1000 0.70000 0001_0100 1.42500 0011_1011 1.18125 0110_0010 0.93750 1000_1001 0.69375 0001_0101 1.41875 0011_1100 1.17500 0110_0011 0.93125 1000_1010 0.68750 0001_0110 1.41250 0011_1101 1.16875 0110_0100 0.92500 1000_1011 0.68125 0001_0111 1.40625 0011_1110 1.16250 0110_0101 0.91875 1000_1100 0.67500 0001_1000 1.40000 0011_1111 1.15625 0110_0110 0.91250 1000_1101 0.66875 0001_1001 1.39375 0100_0000 1.15000 0110_0111 0.90625 1000_1110 0.66250 0001_1010 1.38750 0100_0001 1.14375 0110_1000 0.90000 1000_1111 0.65625 0001_1011 1.38125 0100_0010 1.13750 0110_1001 0.89375 1001_0000 0.65000 0001_1100 1.37500 0100_0011 1.13125 0110_1010 0.88750 1001_0001 0.64375 0001_1101 1.36875 0100_0100 1.12500 0110_1011 0.88125 1001_0010 0.63750 0001_1110 1.36250 0100_0101 1.11875 0110_1100 0.87500 1001_0011 0.63125 0001_1111 1.35625 0010_0110 1.11250 0110_1101 0.86875 1001_0100 0.62500 0010_0000 1.35000 0100_0111 1.10625 0110_1110 0.86250 1001_0101 0.61875 0010_0001 1.34375 0100_1000 1.10000 0110_1111 0.85625 1001_0110 0.61250 0010_0010 1.33750 0100_1001 1.09375 0111_0000 0.85000 1001_0111 0.60625 0010_0011 1.33125 0100_1010 1.08750 0111_0001 0.84375 1001_1000 0.60000 0010_0100 1.32500 0100_1011 1.08125 0111_0010 0.83750 1001_1001 0.59375 Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3662AC-01 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT3662AC SVID [7:0] Voltage (V) SVID [7:0] Voltage (V) SVID [7:0] Voltage (V) SVID [7:0] Voltage (V) 0010_0101 1.31875 0100_1100 1.07500 0111_0011 0.83125 1001_1010 0.58750 0010_0110 1.31250 0100_1101 1.06875 0111_0100 0.82500 1001_1011 0.58125 1001_1100 0.57500 1011_0101 * 0.41875 1100_1110 * 0.26250 1110_0111* 0.10625 1001_1101 0.56875 1011_0110 * 0.41250 1100_1111 * 0.25625 1110_1000* 0.10000 1001_1110 0.56250 1011_0111 * 0.40625 1101_0000 * 0.25000 1110_1001* 0.09375 1001_1111 0.55625 1011_1000 * 0.40000 1101_0001 * 0.24375 1110_1010* 0.08750 1010_0000 0.55000 1011_1001 * 0.39375 1101_0010 * 0.23750 1110_1011* 0.08125 1010_0001 0.54375 1011_1010 * 0.38750 1101_0011 * 0.23125 1110_1100* 0.07500 1010_0010 0.53750 1011_1011 * 0.38125 1101_0100 * 0.22500 1110_1101* 0.06875 1010_0011 0.53125 1011_1100 * 0.37500 1101_0101 * 0.21875 1110_1110* 0.06250 1010_0100 0.52500 1011_1101 * 0.36875 1101_0110 * 0.21250 1110_1111* 0.05625 1010_0101 0.51875 1011_1110 * 0.36250 1101_0111 * 0.20625 1111_0000* 0.05000 1010_0110 0.51250 1011_1111 * 0.35625 1101_1000 * 0.20000 1111_0001* 0.04375 1010_0111 0.50625 1100_0000 * 0.35000 1101_1001 * 0.19375 1111_0010* 0.03750 1010_1000 * 0.50000 1100_0001 * 0.34375 1101_1010 * 0.18750 1111_0011* 0.03125 1010_1001 * 0.49375 1100_0010 * 0.33750 1101_1011 * 0.18125 1111_0100* 0.02500 1010_1010 * 0.48750 1100_0011 * 0.33125 1101_1100 * 0.17500 1111_0101* 0.01875 1010_1011 * 0.48125 1100_0100 * 0.32500 1101_1101 * 0.16875 1111_0110* 0.01250 1010_1100 * 0.47500 1100_0101 * 0.31875 1101_1110 * 0.16250 1111_0111* 0.00625 1010_1101 * 0.46875 1100_0110 * 0.31250 1101_1111 * 0.15625 1111_1000* 0.00000 1010_1110 * 0.46250 1100_0111 * 0.30625 1110_0000* 0.15000 1111_1001* OFF 1010_1111 * 0.45625 1100_1000 * 0.30000 1110_0001* 0.14375 1111_1010* OFF 1011_0000 * 0.45000 1100_1001 * 0.29375 1110_0010* 0.13750 1111_1011* OFF 1011_0001 * 0.44375 1100_1010 * 0.28750 1110_0011* 0.13125 1111_1100* OFF 1011_0010 * 0.43750 1100_1011 * 0.28125 1110_0100* 0.12500 1111_1101* OFF 1011_0011 * 0.43125 1100_1100 * 0.27500 1110_0101* 0.11875 1111_1110* OFF 1011_0100 * 0.42500 1100_1101 * 0.26875 1110_0110* 0.11250 1111_1111* OFF * Indicates TOB is 80mV for this VID code; unconditional VR controller stability required at all VID codes Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 is a registered trademark of Richtek Technology Corporation. DS3662AC-01 April 2016 RT3662AC Table 2. SET1 Pin Setting for VDD Controller AI Gain Ratio and VDDNB Voltage Reporting Offset SET1 Pin Setting Voltage RD VSET1_DIV 3.2 RU RD AI_VDD VDDNB_RPT_OFS [3:1] bits Min Typical Max Unit 0 23 47 mV 000 50 74 97 mV 001 100 124 147 mV 010 150 174 197 mV 200 224 247 mV 250 274 297 mV 101 300 324 347 mV 110 350 374 397 mV 111 400 424 447 mV 000 450 474 497 mV 001 500 524 547 mV 010 551 574 597 mV 601 624 648 mV 651 674 698 mV 101 701 724 748 mV 110 751 774 798 mV 111 801 824 848 mV 000 851 874 898 mV 001 901 924 948 mV 010 951 974 998 mV 1001 1024 1048 mV 1051 1074 1098 mV 101 1101 1125 1148 mV 110 1151 1175 1198 mV 111 1201 1225 1248 mV 000 1251 1275 1298 mV 001 1301 1325 1348 mV 010 1351 1375 1398 mV 1401 1425 1448 mV 1451 1475 1498 mV 101 1501 1525 1548 mV 110 1552 1575 1598 mV 111 Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3662AC-01 April 2016 25% 50% 100% 0LL 011 100 011 100 011 100 011 100 is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT3662AC Table 3. SET1 Pin Setting for VDDNB Controller AI Gain Ratio, VDD Controller QR Threshold SET1 Pin Setting Voltage RU RD VSET1_IR 80μ RU RD AI_VDDNB QR Threshold (VDD) Min Typical Max Unit 0 49 97 200 249 297 300 349 397 25mV 400 449 497 Disable 601 650 698 701 750 798 801 850 898 1001 1050 1098 1101 1150 1198 25mV 1201 1250 1298 Disable 1401 1450 1498 1501 1550 1598 Disable 25% 20mV 50% 20mV 25mV mV Disable 100% 20mV 0LL 20mV 25mV Table 4. TSEN Pin Setting for the Frequency of VDD/VDDNB Controller, VDD Controller Initial Offset and PHOCP Setting Ratio TSEN Pin Setting Voltage RD VTSEN_DIV 3.2 RU RD Min Typical Max Unit 0 23 47 mV 50 74 97 mV 200 224 247 mV 250 274 297 mV 400 424 447 mV 450 474 497 mV 601 624 648 mV 651 674 698 mV 801 824 848 mV 851 874 898 mV 1001 1024 1048 mV 1051 1074 1098 mV 1201 1225 1248 mV 1251 1275 1298 mV 1401 1425 1448 mV 1451 1475 1498 mV PHOCP_TH = OCP_SPIKE × (PHOCP Setting Ratio) / M Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 VDD PHOCP Frequency Initial Offset Setting Ratio (VDD/VDDNB) (VDD) (Percentage of OCP_SPIKE) 25mV 0mV 300kHz 25mV 50mV 25mV 0mV 400kHz 25mV 50mV 150% 200% 150% 200% 150% 200% 150% 200% 150% 200% 150% 200% 150% 200% 150% 200% (M : Phase Number) is a registered trademark of Richtek Technology Corporation. DS3662AC-01 April 2016 RT3662AC Table 5. TSEN_NB Pin Setting for VDDNB Controller Initial Offset, Voltage Reporting Offset and PHOCP Setting Ratio TSEN_NB Pin Setting Voltage RD VTSEN_NB_DIV 3.2 RU RD Initial Offset (VDDNB) Min Typical Max Unit 0 23 47 mV 50 74 97 mV 100 124 147 mV 150 174 197 mV 200 224 247 mV 250 274 297 mV 300 324 347 mV 350 374 397 mV 400 424 447 mV 450 474 497 mV 500 524 547 mV 551 574 597 mV 601 624 648 mV 651 674 698 mV 701 724 748 mV 751 774 798 mV 801 824 848 mV 851 874 898 mV 901 924 948 mV 951 974 998 mV 1001 1024 1048 mV 1051 1074 1098 mV 1101 1125 1148 mV 1151 1175 1198 mV 1201 1225 1248 mV 1251 1275 1298 mV 1301 1325 1348 mV 1351 1375 1398 mV 1401 1425 1448 mV 1451 1475 1498 mV 1501 1525 1548 mV 1552 1575 1598 mV Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3662AC-01 April 2016 25mV (PS0) VDDNB_RPT _OFS [0] 0 1 0 0mV (PS0) 1 0 25mV (PS0) 1 0 50mV (PS0) 1 0 Fixed 1.5V (PS2) 1 0 Fixed 1.35V (PS2) 1 0 Fixed 1.25V (PS2) 1 0 0mV (PS2) 1 VDDNB PHOCP Setting Ratio (Percentage of OCP_SPIKE_NB) 150% 200% 150% 200% 150% 200% 150% 200% 150% 200% 150% 200% 150% 200% 150% 200% 150% 200% 150% 200% 150% 200% 150% 200% 150% 200% 150% 200% 150% 200% 150% 200% is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT3662AC Table 6. VDDNB Voltage Reporting Offset Table VDDNB_RPT_OFS [3:0] VDDNB Voltage Reporting Offset (VDDNB_RPT_OFS) (Bits) 0000 DIMON_NB x 1/128 0001 DIMON_NB x 2/128 0010 DIMON_NB x 3/128 0011 DIMON_NB x 4/128 0100 DIMON_NB x 5/128 0101 DIMON_NB x 6/128 0110 DIMON_NB x 7/128 0111 DIMON_NB x 8/128 1000 DIMON_NB x 9/128 1001 DIMON_NB x 10/128 1010 DIMON_NB x 11/128 1011 DIMON_NB x 12/128 1100 DIMON_NB x 13/128 1101 DIMON_NB x 14/128 1110 DIMON_NB x 15/128 1111 DIMON_NB x 16/128 DIMON_NB VIMON_NB 0.8 255 (Bits) 0.8 DIMON_NB : VDDNB Current Reporting Digital Code Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 is a registered trademark of Richtek Technology Corporation. DS3662AC-01 April 2016 RT3662AC Absolute Maximum Ratings (Note 1) VCC to GND ------------------------------------------------------------------------------------------------- 0.3V to 6.5V PVCC to GND ----------------------------------------------------------------------------------------------- 0.3V to 6V RGND to GND ----------------------------------------------------------------------------------------------- 0.3V to 0.3V BOOTx to PHASEx ----------------------------------------------------------------------------------------- 0.3V to 6V PHASEx to GND DC -------------------------------------------------------------------------------------------------------------- 0.3V to 32V < 20ns --------------------------------------------------------------------------------------------------------- 8V to 38V UGATEx to PHASEx DC -------------------------------------------------------------------------------------------------------------- 0.3V to 6V < 20ns --------------------------------------------------------------------------------------------------------- 5V to 7.5V LGATEx to GND DC -------------------------------------------------------------------------------------------------------------- 0.3V to 6V <20ns ---------------------------------------------------------------------------------------------------------- 2.5V to 7.5V Other Pins ---------------------------------------------------------------------------------------------------- 0.3V to (VCC + 0.3V) Power Dissipation, PD @ TA = 25C WQFN-40L 5x5 ---------------------------------------------------------------------------------------------- 3.63W Package Thermal Resistance (Note 2) WQFN-40L 5x5, JA ---------------------------------------------------------------------------------------- 27.5C/W WQFN-40L 5x5, JC---------------------------------------------------------------------------------------- 6C/W Lead Temperature (Soldering, 10 sec.)---------------------------------------------------------------- 260C Junction Temperature -------------------------------------------------------------------------------------- 150C Storage Temperature Range ----------------------------------------------------------------------------- 65C to 150C ESD Susceptibility (Note 3) HBM (Human Body Model) ------------------------------------------------------------------------------- 2kV Recommended Operating Conditions (Note 4) Supply Voltage, VCC--------------------------------------------------------------------------------------- 4.5V to 5.5V Supply Voltage, PVCC------------------------------------------------------------------------------------- 4.5V to 5.5V Supply Voltage, VIN ---------------------------------------------------------------------------------------- 4.5V to 26V Ambient Temperature Range ---------------------------------------------------------------------------- 40C to 85C Junction Temperature Range ---------------------------------------------------------------------------- 40C to 125C Electrical Characteristics (VCC = 5V, TA = 25C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit 4.5 5 5.5 V -- 9 15 mA Input Power Supply Supply Voltage VCC Supply Current IVCC EN = 3V, Not Switching Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3662AC-01 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT3662AC Parameter Symbol Min Typ Max Unit -- 5 -- A 4.5 5 5.5 V VBOOTX = 5V, Not Switching -- 150 -- A VPOR_r PVCC POR Rising -- 3.85 4.1 V VPOR_f PVCC POR Falling 3.4 3.65 -- V 100 200 350 mV 0.795 0.8 0.805 V VDAC = 1.0000 to 1.5500 (No Load, CCM Mode) VDAC = 0.8000 to 1.0000 0.5 0 0.5 %SVID 5 0 5 mV VDAC = 0.3000 to 0.8000 8 0 8 mV VDAC = 0.2500 to 0.3000 80 0 80 mV IRGND EN = 3V, Not switching 150 200 250 A SR SetVID Fast 7.5 10 15 mV/s 4 -- 4 mV Shutdown Current ISHDN PVCC Supply Voltage VPVCC PVCC Supply Current IPVCC Test Conditions EN = 0V Driver Power On Reset (Driver POR) Driver POR Threshold Driver POR Hysteresis VPOR_Hys Reference and DAC Reference Voltage Output DC Accuracy VREF VFB Reference and DAC RGND Current Slew Rate Dynamic VID Slew Rate Error Amplifier Input Offset VEAOFS DC Gain ADC RL = 47k 70 80 -- dB Gain-Bandwidth Product GBW CLOAD = 5pF -- 5 - MHz Output Voltage Range VCOMP IEA,SRC / IEA,SNK RLOAD = 47k 0.3 -- 3.6 V -- 5 -- mA 0.4 -- 0.4 mV EA Source/Sink Current Current Sense Amplifier Input Offset Voltage VOSCS Impedance at Neg. Input RISENxN 1 -- -- M Impedance at Pos. Input RISENxP 1 -- -- M Input range VISEN_IN VDAC = 1.1V, (ISENxP ISENxN) 40 -- 40 mV Current Sense Gain Error AISEN_Err VDAC = 1.1V 2 -- 2 % VIH_EN 2 -- -- VIL_EN -- -- 0.8 ILEK_EN 1 -- 1 EN and Logic Inputs EN Threshold Leakage Current of EN SVC, SVD, PWROK Hysteresis of SVC, SVD, PWROK VIH_SVI Respect to VDDIO 70 -- 100 VIH_SVI Respect to VDDIO 0 -- 35 VHYS_SVI Respect to VDDIO 10 -- -- Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 14 V A % % is a registered trademark of Richtek Technology Corporation. DS3662AC-01 April 2016 RT3662AC Parameter Symbol Test Conditions Min Typ Max Unit 0.1 -- 30 MHz SVI2 Bus SVC Frequency f SVC (Note 5) Thermal Management VRHOT Indicator Threshold VTH_VRHOT 2.16 2.2 2.24 V VRHOT Indicator Hysteresis VHYS_VRHOT 50 75 100 mV 150 175 200 ns -- 250 400 ns -- 80 -- A 3.9 4.1 4.3 V -- 200 -- mV 1.8 1.85 1.9 V 0.3 1 3 s 600 500 400 mV 0.5 3 7 s 73.15 77 80.85 A 8 14 20 s 0.1 0.5 1 s 0 -- 0.2 V 2 -- -- s 0 -- 0.2 V TON Setting On-Time Setting TON Minimum Off Time TOFF VIN = 19V,VDAC = 1V, [PSI0_L:PSI1_L] = 11 (Note 6) VDAC = 1V ITSEN VCC = 5V VUVLO VCC Falling edge ITSEN TSEN Source Current Protection Under Voltage Lockout Threshold Under Voltage Lockout Hysteresis Over Voltage Protection Threshold VUVLO VOVP Delay of OVP TOVP VSEN Rising above Threshold Under Voltage Protection Threshold VUVP Respect to VID Voltage Delay of UVP TUVP OCP_SPIKE Threshold IOCP_SPIKE OCP_SPIKE Trigger Delay Delay of Per Phase OCP VSEN Falling below Threshold DCR = 1.1m, KAG = 0.6, RIMON = 8.433k TOCPSPIKE _DLY TPHOCP VRHOT_L and PGOOD Output Low Voltage at VRHOT_L VVRHOT_L VRHOT_L Assertion Time TVRHOTL Output Low Voltage at PGOOD VPGOOD IVRHOT_L = 4mA IPGOOD = 4mA PGOOD Threshold VTH_PGOOD Respect to BOOT VID -- 300 -- mV PGOOD Delay Time TPGOOD 60 110 160 s Maximum Reported Current (FFh = OCP_SPIKE) -- 100 -- %IDD_ SPIKE _OCP Minimum Reported Current (00h) -- 0 -- %IDD_ SPIKE _OCP IDDSPIKE Current Accuracy -- -- 3 % BOOT VID to PGOOD High Current Report Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3662AC-01 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 15 RT3662AC Parameter Symbol Test Conditions Min Typ Max Unit Maximum Reported Voltage (0_00h) -- 3.15 -- V Minimum Reported Voltage (1_F8h) -- 0 -- V Voltage Accuracy 2 -- 2 LSB Voltage Report Switching Time UGATEx Rise Time tUGATEr 3nF Load -- 8 -- ns UGATEx Fall Time tUGATEf 3nF Load -- 8 -- ns LGATEx Rise Time tLGATEr 3nF Load -- 8 -- ns LGATEx Fall Time tLGATEf 3nF Load -- 4 -- ns UGATEx Turn-On Propagation Delay TUGATEpdh Output Unloaded -- 20 -- ns LGATEx Turn-On Propagation Delay TLGATEpdh Output Unloaded -- 20 -- ns RUGATEsr 100mA Source Current -- 1 -- IUGATEsr VUGATE VPHASE = 2.5V -- 2 -- A RUGATEsk 100mA Sink Current -- 1 -- UGATEx Driver Sink Current IUGATEsk VUGATE VPHASE = 2.5V -- 2 -- A LGATEx Driver Source Resistance RLGATEsr 100mA Source Current -- 1 -- LGATEx Driver Source Current ILGATEsr VLGATE = 2.5V -- 2 -- A LGATEx Driver Sink Resistance RLGATEsk 100mA Sink Current -- 0.5 -- LGATEx Driver Sink Current VLGATE = 2.5V -- 4 -- A Output UGATEx Driver Source Resistance UGATEx Driver Source Current UGATEx Driver Sink Resistance ILGATEsk Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. JA is measured at TA = 25C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. JC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Min. SVC frequency defined in electrical spec. is related with different application. As min. SVC < 1MHz, VR can’t support telemetry reporting function. As min. SVC < 400kHz, VR can’t support telemetry reporting function and VOTF complete function. Note 6. TON[PSI0_L:PSI1_L=00,01,10] = 0.8 * TON[PSI0_L:PSI1_L=11] Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 16 is a registered trademark of Richtek Technology Corporation. DS3662AC-01 April 2016 RT3662AC Typical Application Circuit 4.7 28 VIN RT3662AC VIN 2.2 22 VDDIO VDDIO 1μF VREF COMP 4.7 17 5V 68k 324k 8 270pF 41.2k 10k VVDD_SENSE Reserved RGND 4 0 34 5V 4.02k 1.8k BOOT1 13 187k 12 38 SET1 UGATE1 37 TSEN PHASE1 LGATE1 RNTC 10 2.2 0.1μF 35 1 180 300 487 1.5k 0.47μF LOAD POSCAP : 470μF/4.5m x 3 2.26k ISEN1P 9 23 TSEN_NB MLCC : 22μF x 14 1 RNTC 24k VVDD 0.36μH/1.1m 36 3.3nF 187k 33k 10 10μF x 2 100k/ = 4485 14k VSS_SENSE VIN PVCC 2.2μF 300 39pF 5 FB 6 VCC 2.2μF 37.4k VSEN 0.1μF ISEN1N 10 VIN 100k/ = 4485 BOOT2 2 2.2 15 VREF_PINSET 8.699k 1 10μF x 2 UGATE2 1 VREF 0.1μF 0.1μF 0.36μH/1.1m PHASE2 40 39 LGATE2 1 3.9 1.5k 0.47μF 3.3nF 0.47μF RNTC 15.8k 390 14 100k/ = 4485 11.755k RNTC 12.78k 4.75k 16 100k/ = 4485 56pF 3.3V 4.7k 4.7k 270pF 27 FB_NB 26 59k 10k 11 18 VRHOT_L BOOT_NB 30 PWROK UGATE_NB 31 PGOOD PHASE_NB 19 SVC LGATE_NB 20 SVD 3 21 SVT Enable VSS_SENSE Reserved VIN 10k To CPU VVDDNB_SENSE IMON_NB COMP_NB VDDIO 2.26k ISEN2P 7 IMON 29 EN 41 (Exposed Pad) 2.2 0.1μF 10 VVDDNB 0.36μH/1.1m 32 33 1 768 0.47μF LOAD 3.3nF POSCAP : 470μF/4.5m ISENP_NB 25 Reserved GND 10 10μF x 2 MLCC : 22μF x 6 ISENN_NB 24 0.1μF Timing Diagram LGATEx 1.5V 1.5V 1.5V 1.5V UGATEx tUGATEpdh Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3662AC-01 April 2016 tLGATEpdh is a registered trademark of Richtek Technology Corporation. www.richtek.com 17 RT3662AC Typical Operating Characteristics CORE VR Power On from EN Boot VID = 0.8V CORE VR Power Off from EN VDD (500mV/Div) VDD (500mV/Div) Boot VID = 0.8V EN (3V/Div) EN (3V/Div) PGOOD (3V/Div) PGOOD (3V/Div) UGATE1 (20V/Div) UGATE (20V/Div) Time (500μs/Div) Time (200μs/Div) CORE VR Thermal Monitoring CORE VR OCP_SPIKE ILoad = 60A to 90A ILoad (16A/Div) TSEN (1V/Div) PGOOD (3V/Div) LGATE (10V/Div) VRHOT_L (1V/Div) UGATE (30V/Div) Time (10ms/Div) Time (10μs/Div) CORE VR OVP CORE VR UVP VID = 1.1V VID = 1.1V VDD (500mV/Div) VDD (800mV/Div) PGOOD (3V/Div) PGOOD (3V/Div) UGATE (30V/Div) LGATE (10V/Div) UGATE (30V/Div) LGATE (10V/Div) Time (10μs/Div) Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 18 Time (10μs/Div) is a registered trademark of Richtek Technology Corporation. DS3662AC-01 April 2016 RT3662AC CORE VR Dynamic VID Up CORE VR Dynamic VID Up VDD VDD (400mV/Div) SVD (2V/Div) SVD (2V/Div) SVT (2V/Div) SVT (2V/Div) VID = 0.4V to 1V, ILoad = 3.9A VDD (200mV/Div) VID = 1V to 1.06875V, ILoad = 19.5A Time (20μs/Div) Time (10μs/Div) CORE VR Dynamic VID Up CORE VR Dynamic VID Up VDD VDD SVD (2V/Div) SVD (2V/Div) SVT (2V/Div) SVT (2V/Div) VDD (200mV/Div) VID = 1V to 1.1V, ILoad = 19.5A VDD (200mV/Div) VID = 1V to 1.2V, ILoad = 19.5A Time (10μs/Div) Time (10μs/Div) CORE VR Dynamic VID Up CORE VR Load Transient VDD (30mV/Div) ILoad (20A/Div) VDD SVD (2V/Div) VDD SVT (2V/Div) VDD (300mV/Div) VID = 1V to 1.4V, ILoad = 19.5A Time (10μs/Div) Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3662AC-01 April 2016 fLoad = 10kHz, ILoad = 20A to 55A Time (5μs/Div) is a registered trademark of Richtek Technology Corporation. www.richtek.com 19 RT3662AC NB VR Thermal Monitoring CORE VR Load Transient ILoad (20A/Div) TSEN_NB (1V/Div) VDD (30mV/Div) VRHOT_L (1V/Div) fLoad = 10kHz, ILoad = 55A to 20A Time (5μs/Div) Time (10ms/Div) NB VR Power Off from EN NB VR Power On from EN Boot VID = 0.8V Boot VID = 0.8V VDDNB (500mV/Div) EN (3V/Div) VDDNB (500mV/Div) EN (3V/Div) PGOOD (3V/Div) PGOOD (3V/Div) UGATE_NB (20V/Div) UGATE_NB (20V/Div) Time (500μs/Div) Time (200μs/Div) NB VR OCP_SPIKE NB VR OVP VID = 1.1V ILoad = 15A to 40A ILoad (20A/Div) VDDNB (800mV/Div) PGOOD (3V/Div) UGATE_NB (30V/Div) PGOOD (3V/Div) UGATE_NB (30V/Div) LGATE_NB (10V/Div) LGATE_NB (10V/Div) Time (10μs/Div) Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 20 Time (10μs/Div) is a registered trademark of Richtek Technology Corporation. DS3662AC-01 April 2016 RT3662AC NB VR UVP NB VR Dynamic VID Up VID = 1.1V VDDNB (500mV/Div) VDDNB (400mV/Div) PGOOD (3V/Div) SVD (2V/Div) UGATE_NB (30V/Div) SVT (2V/Div) LGATE_NB (10V/Div) VID = 0.4V to 1V, ILoad = 1.2A Time (10μs/Div) Time (20μs/Div) NB VR Dynamic VID Up NB VR Dynamic VID Up VDDNB VDDNB SVD (2V/Div) SVD (2V/Div) SVT (2V/Div) SVT (2V/Div) VDDNB (200mV/Div) VID = 1V to 1.06875V, ILoad = 6A VDDNB (200mV/Div) VID = 1V to 1.1V, ILoad = 6A Time (10μs/Div) Time (10μs/Div) NB VR Dynamic VID Up NB VR Dynamic VID Up VDDNB VDDNB SVD (2V/Div) SVD (2V/Div) SVT (2V/Div) SVT (2V/Div) VDDNB (200mV/Div) VID = 1V to 1.2V, ILoad = 6A Time (10μs/Div) Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3662AC-01 April 2016 VDDNB (300mV/Div) VID = 1V to 1.4V, ILoad = 6A Time (10μs/Div) is a registered trademark of Richtek Technology Corporation. www.richtek.com 21 RT3662AC NB VR Load Transient VDDNB (20mV/Div) VDDNB (20mV/Div) ILoad (10A/Div) fLoad = 10kHz, ILoad = 7A to 17A Time (5μs/Div) Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 22 NB VR Load Transient ILoad (10A/Div) fLoad = 10kHz, ILoad = 17A to 7A Time (5μs/Div) is a registered trademark of Richtek Technology Corporation. DS3662AC-01 April 2016 RT3662AC Application Information Power Ready (POR) Detection Boot VID During start-up, the RT3662AC will detect the voltage at the voltage input pins: VCC, PVCC and EN. When VCC > 4.3V and PVCC > 3.85V, the IC will recognize the power state of system to be ready (POR = high) and wait for enable command at the EN pin. After POR = When EN goes high, both VDD and VDDNB output begin to soft-start to the Boot VID in CCM. Table 7 shows the Boot VID setting. The Boot VID is determined by the SVC and SVD input states at EN rising edge and it is in the internal register. The digital soft-start circuit high and VEN > 2V, the IC will enter start-up sequence for both VDD and VDDNB rail. If the voltage of VCC and EN pin drop below low threshold, the IC will enter power down sequence and all the functions will be disabled. Normally, connecting system power to the EN pin is recommended. The SVID will be ready in 2ms (max) ramps up the reference voltage at a controlled slew rate to reduce inrush current during start-up. When all the output voltages are above power good threshold (300mV below Boot VID) at the end of soft-start, the controller asserts power good (PGOOD) after a time delay. after the chip has been enabled. All the protection latches (OVP, OCP, UVP) will be cleared only after POR = low. The condition of VEN = low will not clear these latches. Table 7. 2-Bit Boot VID Code + CMP VCC 4.3V + PVCC 3.85V CMP + CMP EN 2V POR Chip EN - Figure 1. Power Ready (POR) Detection Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3662AC-01 April 2016 Initial Startup VID (Boot VID) SVC SVD VDD/VDDNB Output Voltage (V) 0 0 1.1 0 1 1.0 1 0 0.9 1 1 0.8 Start-Up Sequence After EN goes high, the RT3662AC starts up and operates according to the initial settings. Figure 2 shows the simplified sequence timing diagram. The detailed operation is described in the following. is a registered trademark of Richtek Technology Corporation. www.richtek.com 23 RT3662AC T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 VIN VDDIO PVCC, VCC SVID Send Byte SVC SVID Send Byte SVD VOTF Complete VOTF Complete SVT EN PWROK CCM Boot VID CCM VDD/ VDDNB VID CCM Boot VID CCM CCM VID CCM CCM PGOOD Figure 2. Simplified Sequence Timing Diagram Description of Figure 2 : T0: When the VIN power is ready, the RT3662AC will wait for VCC and PVCC POR. send a VOTF Complete if the VID is greater than BOOT VID and reaches target VID. T1: VDDIO power is ready, and the BOOT VID can be set by SVC pin and SVD pin, and latched at EN rising edge. SVT is driven high by the RT3662AC. T7: The PWROK pin goes low and the SVI2 interface stops running. All output voltages go back to the Boot VID in CCM. T2: The enable signal goes high and all output voltages ramp up to the Boot VID in CCM. The soft-start slew rate is 2.5mV/s. T8: The PWROK pin goes high again and the SVI2 interface starts running. The RT3662AC waits for SVID command from processor. T3: All output voltages are within the regulation limits and the PGOOD signal goes high. T9: A valid SVID command transaction occurs between the processor and the RT3662AC. T4: The PWROK pin goes high and the SVI2 interface starts running. The RT3662AC waits for SVID command T10: The action is same with T6. The RT3662AC starts VID on-the-Fly transition and send a VOTF Complete if from processor. the VID up and reaches target VID. T5: A valid SVID command transaction occurs between the processor and the RT3662AC. T11: The enable signal goes low and all output voltages enter soft-shutdown mode. The soft-shutdown slew rate is 2.5mV/s. T6: The RT3662AC starts VOTF (VID on-the-Fly) transition according to the received SVID command and Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 24 is a registered trademark of Richtek Technology Corporation. DS3662AC-01 April 2016 RT3662AC Power-Down Sequence SVI2 Wire Protocol If the voltage at the EN pin falls below the enable falling threshold, the controller is disabled. The voltage at the The RT3662AC complies with AMD's Voltage Regulator Specification, which defines the Serial VID Interface 2.0 PGOOD pin will immediately go low when EN pin signal goes low, and the controller executes soft-shutdown operation. The internal digital circuit ramps down the reference voltage at the same slew rate as that of in soft-start, making VDD and VDDNB output voltages gradually decrease in CCM. The Boot VID information stored in the internal register is cleared at POR. This event forces the RT3662AC to check the SVC and SVD inputs for a new boot VID when the EN voltage goes high again. (SVI2) protocol. With SVI2 protocol, the processor directly controls the reference voltage level of each individual controller channel and determines which controller operates in power saving mode. The SVI2 interface is a three-wire bus that connects a single master to one or above slaves. The master initiates and terminates SVI2 transactions and drives the clock, SVC, and the data, SVD, during a transaction. The slave drives the telemetry, SVT during a transaction. The AMD processor is always the master. The voltage PGOOD The PGOOD is open-drain logic output. It provides the power good signal when VDD and VDDNB output voltage are within the regulation limits and no protection is triggered. The pin is typically tied to 3.3V or 5V power source through a pull-high resistor. During shutdown state (EN = low) and the soft-start period, the PGOOD voltage is pulled low. After a successful soft-start and VDD and VDDNB output voltages are within the regulation limits, the PGOOD is released high. The voltage at the PGOOD pin will be pulled low when any of the following events occurs : over-voltage protection, under-voltage protection, over-current protection, and logic low EN voltage. If one rail triggers protection, the PGOOD will be pull low. regulator controller (RT3662AC) is always the slave. The RT3662AC receives the SVID code and acts accordingly. The SVI protocol supports 20MHz high speed mode I2C, which is based on SVD data packet. Table 8 shows the SVD data packet. A SVD packet consists of a “Start” signal, three data bytes after each byte, and a “Stop” signal. The 8-bit serial VID codes are listed in Table1. After the RT3662AC has received the stop sequence, it decodes the received serial VID code and executes the command. The controller has the ability to sample and report voltage and current for the VDD and VDDNB domains. The controller reports this telemetry serially over the SVT wire which is clocked by the processor driven SVC. A bit TFN at SVD packet along with the VDD and VDDNB domain selector bits are used by the processor to change the telemetry functionality. The telemetry bit definition is listed in Figure 3. The detailed SVI2 specification is outlined in the AMD Voltage Regulator and Voltage Regulator Module (VRM) and Serial VID Interface 2.0 (SVI2) Specification. Table 8. SVD Data Packet Bit Time 1:5 Description Always 11000b 8 VDD domain selector bit, if set then the following two data bytes contain the VID, the PSI state, and the load-line slope trim and offset trim state for VDD. VDDNB domain selector bit, if set then the following two data bytes contain the VID, the PSI state, and the load-line slope trim and offset trim state for VDDNB. Always 0b 10 PSI0_L 6 7 11 : 17 19 VID Code bits [7:1] VID Code bit [0] Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3662AC-01 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 25 RT3662AC Bit Time Description 20 PSI1_L 21 TFN (Telemetry Functionality) 22 : 24 Load Line Slope Trim [2:0] 25 : 26 Offset Trim [1:0] Voltage and Current Mode Selection Bit Time…… START 1 2 3 VDDNB Voltage Bit in Voltage Only Mode; Current Bit in Voltage and Current Mode VDD Voltage Bits 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 STOP SVC SVT Figure 3. Telemetry Bit Definition PWROK and SVI2 Operation VID on-the-Fly Transition The PWROK pin is an input pin, which is connected to the global power good signal from the platform. Logic high at this pin enables the SVI2 interface, allowing data transaction between processor and the RT3662AC. Once the RT3662AC receives a valid SVID code, it decodes the information from processor to determine which output plane is going to move to the target VID. The internal DAC then steps the reference voltage in a After the RT3662AC has received a valid SVID code, it executes the VID on-the-Fly transition by stepping up/down the reference voltage of the required controller channel in a controlled slew rate, hence allowing the output voltage to ramp up/down to target VID. controlled slew rate, making the output voltage shift to the required new VID. Depending on the SVID code, more than one controller channel can be targeted simultaneously in the VID transition. For example, VDD and VDDNB voltages can ramp up/down at the same time. prior to the VID on-the-Fly transition, it will change to high performance mode and implement CCM operation when the controller implement VID up, and then remain in high performance mode; if the controller implement VID down in power-saving mode, it will decay down and keep in power-saving mode. The voltage at the PGOOD pin will keep high during the VID on-the-Fly transition. The RT3662AC send a VOTF complete only at the end of VID up transition. In the event of receiving a VID off code, the RT3662AC steps the reference voltage of required controller channel down to zero, hence making the required output voltage decrease to zero, and the voltage at the PGOOD pin will remain high since the VID code is valid. If the PWROK input goes low during normal operation, the SVI2 protocol stops running. The RT3662AC immediately drives SVT high and modifies all output voltages back to the Boot VID, which is stored in the internal register right after the controller is enabled. The controller does not read SVD and SVC inputs after the loss of PWROK. If the PWROK input goes high again, the SVI2 protocol resumes running. The RT3662AC then waits to decode the SVID command from processor for a new VID and acts as previously described. The SVI2 protocol is only runs when the PWROK input goes high after the voltage at the EN pin goes high. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 26 During the VID on-the-Fly transition, the RT3662AC will force CCM operation in high performance mode. If the controller channel operates in the power-saving mode Power State Transition The RT3662AC supports power state transition function in VDD and VDDNB VR for the PSI[x]_L command from AMD processor. The PSI[x]_L bit in the is a registered trademark of Richtek Technology Corporation. DS3662AC-01 April 2016 RT3662AC SVI2 protocol controls the operating mode of the RT3662AC controller channels. The default operation mode of VDD and VDDNB VR is full-phase CCM. VSS_SENSE. For VDD controller, connect FB to VDD_SENSE with a resistor to build the negative input path of the error amplifier. Connect FB_NB to When the VDD VR is in N phase configuration and receives PSI0_L = 0 and PSI1_L = 0 or 1, the VDD VR will entry 1-phase diode emulation mode. When the VDD VR receives PSI0_L = 1 and PSI1_L = 0, the VDD VR remains 1-phase diode emulation mode. In reverse, the VDD VR goes back to N phase operation in CCM upon receiving PSI0_L = 1 and PSI1_L = 1, see Table 9. When the VDDNB VR receives PSI0_L = 0 and PSI1_L = 0 or 1, it enters 1-phase diode emulation mode. If the VDDNB VR receives PSI0_L = 1 and VDDNB_SENSE with a resistor using the same way in VDD controller. Connect VSS_SENSE to RGND using separate trace as shown in Figure 4. The precision reference voltages refer to RGND for accurate remote sensing. PSI1_L = 0, it remains 1-phase diode emulation mode. The VDDNB VR will go back to 1-phase CCM operation after receiving PSI0_L = 1 and PSI1_L = 1, see Table 10. PSI0_L : PSI1_L Mode 11 2 phase CCM 10 2 01 1 phase DEM 00 11 1 phase CCM 10 1 01 VDD_SENSE VDDNB_SENSE VDD Controller FB 1 phase DEM 00 RGND Mode 11 1 phase CCM 10 01 1 phase DEM 00 Differential Remote Sense Setting The VDD and VDDNB controllers have differential, remote-sense inputs to eliminate the effects of voltage drops along the PC board traces, processor internal power routes and socket contacts. The processor contains on-die sense pins, including of VDD_SENSE, VDDNB_SENSE and VSS_SENSE. Connect RGND to Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3662AC-01 April 2016 RGND Figure 4. Differential Remote Voltage Sense Connection The RT3662AC provides the SET1 pin for platform users to set the VDD and VDDNB controller current gain ratio (AI_VDD, AI_VDDNB), VDD controller QR threshold (QR_TH) and VDDNB voltage reporting offset bit[1:3] (VDDNB_RPT_OFS). Platform designers should use resistive voltage divider on the pin, refer to Figure 5. The voltage (VREF) at VREF_PINSET pin will be pulled up to 3.2V for SET1 pin setting after power ready (POR), and then the voltage will change and fix to 0.8V with a delay time for normal operation. The divided voltage at the SET1 pin as below : PSI0_L : PSI1_L 1 VDDNB Controller VSS_SENSE Table 10. VDDNB VR Power State Full Phase Number FB_NB SET1 Pin Setting Table 9. VDD VR Power State Full Phase Number Processor VSET1_DIV 3.2 RD RU RD (1) The ADC monitors and decodes the voltage at this pin only once after power up. After ADC decoding (only once), a 80A current (when VCC = 5V) will be generated at the SET1 pin for pin setting. That is the voltage at SET1 pin described as below : R RD VSET1_IR 80 U RU RD (2) From equation (1) and (2) and Table 2 and 3, platform users can set the above described pin setting functions. is a registered trademark of Richtek Technology Corporation. www.richtek.com 27 RT3662AC VDDNB_RPT _COMP[1:3] Thermal Indicator AI_VDD, AI_VDDNB Refer to Figure 6, the RT3662AC provides the thermal indicator function. The VRHOT_L pin is an open-drain 80µA (VCC = 5V) QR_TH VREF ADC VSET1_DIV RU SET1 SET1 Register VSET1_IR RD After TSEN and TSEN_NB pin setting, a 80A current (when VCC = 5V) will be generated at the TSEN and TSEN_NB pin for thermal indicator function. And the voltage at TSEN and TSEN_NB pin as below : Figure 5. SET1 Pin Setting TSEN and TSEN_NB Pin Setting The RT3662AC provides the TSEN and TSEN_NB pins for platform users to set the pin setting functions, including the VDD and VDDNB controller switching frequency (FSW ), Initial offset, Per-phase over current protection (PHOCP) and VDDNB voltage reporting offset bit[0] (VDDNB_RPT_OFS). Platform designers should use resistive voltage divider on the pins, refer to Figure 6. The voltage (VREF) at VREF_PINSET pin will be pulled up to 3.2V for TSEN and TSEN_NB pin setting after power ready (POR), and then the voltage will change and fix to 0.8V with a delay time for normal operation. The divided voltage at the TSEN and TSEN_NB pin described as below: VTSEN_DIV 3.2 Rp2 output which is used for VR thermal indicator. When the sensed voltage at TSEN or TSEN_NB pin is less than 2.2V, the VRHOT_L signal will be pulled low to notify CPU that the temperature is over the VRHOT temperature threshold. (3) Rp1 Rp2 R R Rp2 Rp1 Rp2 VTSEN 80 A 1 NTC VREF R R p1 p2 R1 RNTC Rp1 Rp2 (5) R R Rp4 Rp3 Rp4 VTSEN_NB 80 A 2 NTC VREF R R p3 p4 R2 RNTC Rp3 Rp4 (6) Due to the VREF reference voltage cause the thermal compensation become complex. In this way, the sensed voltage related VREF will be eliminated in ADC block. The actual sensed voltage at TSEN and TSEN_NB pin described as below: R R Rp1 Rp2 VTSEN_ADC 80 A 1 NTC R1 RNTC Rp1 Rp2 R R Rp3 Rp4 VTSEN_NB_ADC 80 A 2 NTC R2 RNTC Rp3 Rp4 (7) (8) VDDIO VTSEN_NB_DIV 3.2 Rp4 Rp3 Rp4 (4) The ADC monitors and decodes the voltage at this pin only once after power up. After ADC decoding (only once), a 80A current (when VCC = 5V) will be generated at the TSEN and TSEN_NB pin for thermal indicator and protection functions. From equation (3) and (4) and Table 4 and 5, platform users can set the above described pin setting functions. VDDNB_RPT Initial _COMP[0] Offset PHOCP FSW VRHOT_L Thermal Monitor PROCHOT_L 80µA (VCC = 5V) VREF ADC 2.2V VTSEN Register RNTC Rp1 TSEN R1 VTSEN_DIV 80µA (VCC = 5V) VTSEN_NB Rp2 VREF RNTC VTSEN_NB_DIV Rp3 TSEN_NB R2 Rp4 Figure 6. TSEN and TSEN_NB Circuit Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 28 is a registered trademark of Richtek Technology Corporation. DS3662AC-01 April 2016 RT3662AC VDD Controller Current Signal Sensing Active Phase Determination Refer to Figure 7, for different RSENSE resistor, the current sense method can classify as two types. The The number of active phases is determined by the internal circuitry that monitors the ISEN2P voltage during start-up. Normally, the VDD controller operates as a 2-phase PWM controller. Pulling ISEN2P to VCC programs a 1-phase operation. At EN rising edge, VDD controller detects whether the voltage of ISEN2P is higher than “VCC 0.5V” to decide how many phases should be active and the active phase number is determined and latched. Loop Control The VDD controller adopts Richtek's proprietary GNAVPTM topology. The G-NAVPTM is based on the finite gain peak current mode with CCRCOT (Constant Current Ripple Constant On-Time) topology. The output voltage, VVDD will decrease with increasing output load current. The control loop consists of PWM modulators with power stages, current sense amplifiers and an error method1 only use RX1 for lower RSENSE application, and the method2 use RX1 and RX2 to divide the current signal for higher RSENSE application. Richtek also provide Excel based design tool to let user choose the appropriate components quickly. The current sense topology of the VDD controller is continuous inductor current sensing. Therefore, the controller has less noise sensitive. Low offset amplifiers are used for current balance, loop control and over current detection. The ISENxP and ISEN1N pins denote the positive and negative input of the current sense amplifier. In order to optimize transient performance, the recommended Req and CX will be set according to the equations as below, recommended set to 1.1. Req CX L RSENSE (9) amplifier as shown in Figure 7. Similar to the peak current mode control with finite compensator gain, the HS_FET on-time is determined by CCRCOT on-time generator. When load current increases (VCS increases), the steady state COMP voltage also increases and induces VVDD_SENSE to decrease, thus achieving AVP. A near-DC offset canceling is added to the output of EA to eliminate the inherent output offset of finite gain peak current mode controller. VIN COMP2 + CMP - CCRCOT PWM Logic HS_FET L RSENSE Driver RC LS_FET + 1.867m - Offset Canceling IMON C RIMON VREF_PINSET C2 C1 COMP FB RGND R2 R1 + EA + RX2 ISENxP ISENxN Method2 : Req (10) R X1 R X2 R X1 R X2 (11) Considering the inductance tolerance, the resistor Req has to be tuned on board by examining the transient voltage. If the output voltage transient has an initial dip below the minimum load-line requirement and the response time is too fast causing a ring back, the value of resistance should be increased. Vice versa, with a high resistance, the output voltage transient has only a small initial dip with a slow response time. Droop Setting RX1 CX VCS 0.75 x AI_VDD VVDD Method1 : Req = RX1 It is very easy to achieve Active Voltage Positioning (AVP) by properly setting the error amplifier gain due to the native droop characteristics as shown in Figure 8. This target is to have VVDD = VDAC ILOAD x RDROOP (12) VVDD_SENSE VSS_SENSE VDAC Figure 7. VDD Controller: Simplified Schematic with Voltage Loop and Current Loop Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3662AC-01 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 29 RT3662AC Then solving the switching condition VCOMP2 = VCS in Figure 7 yields the desired error amplifier gain as GI A V R2 R1 RDROOP (13) Method1 : GI RSENSE 1.867m RIMON 0.75 AI_VDD (14) Method2 : GI RSENSE R X2 1.867m RIMON 0.75 AI_VDD R X1 R X2 (15) Where GI is the current sense amplifier gain. RSENSE is the current sense resistor. If no external sense resistor VVDD 1 2 C RC (16) Where C is the capacitance of output capacitor, and RC is the ESR of output capacitor. C2 can be calculated as follows: C2 C RC R2 (17) The zero of compensator has to be placed at half of the switching frequency to filter the switching related noise. Such that, C1 1 R1 fSW (18) COMP EA + C2 C1 R2 R1 VVDD_SENSE FB RGND VSS_SENSE VDAC AV2 > AV1 Figure 9. VDD Controller: Compensation Circuit AV2 AV1 0 fP + present, it is the equivalent resistance of the inductor. RIMON is the IMON equivalent resistance. For the PHOCP accuracy, the RIMON resistor need to set in 8k to 70k. AI_VDD is the VDD controller current gain ratio set by SET1 pin setting. RDROOP is the equivalent loadline resistance as well as the desired static output impedance. The pole frequency of the compensator must be set to compensate the output capacitor ESR zero: Load Current Figure 8. VDD Controller: Error Amplifier gain (AV) Influence on VVDD Accuracy Current Balance The VDD controller implements internal current balance mechanism in the current loop. The VDD controller senses and compares per-phase current signal with average current. If the sensed current of any particular phase is larger than average current, the on-time of this phase will be adjusted to be shorter. Loop Compensation Optimized compensation of the VDD controller allows for best possible load step response of the regulator's output. A type-I compensator with one pole and one zero is adequate for proper compensation. Figure 9 shows the compensation circuit. Previous design procedure shows how to select the resistive feedback components for the error amplifier gain. Next, C1 and C2 must be calculated for compensation. The target is to achieve constant resistive output impedance over the widest possible frequency range. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 30 Initial and Dynamic Offset The VDD controller features initial and dynamic offset function. The VDD rail initial offset function can be implemented through the TSEN pin setting. And the dynamic offset can be implemented by SVI2 interface, it controlled by CPU. Consider the offset factor, the VDD output voltage described as below : VVDD VDAC ILOAD RDROOP VINI_OFS VDYN_OFS (19) VINI_OFS is the initial offset voltage set by pin setting function, and the dynamic offset voltage, VDYN_OFS, controlled by CPU, and it can be set through the SVI2 interface. is a registered trademark of Richtek Technology Corporation. DS3662AC-01 April 2016 RT3662AC Dynamic VID Enhancement Current Monitoring and Reporting During a dynamic VID event, the charging (dynamic VID up) or discharging (dynamic VID down) current causes The VDD controller provides current monitoring function via inductor current sensing. In the G-NAVPTM unwanted load-line effect which degrades the settling time performance. The RT3662AC will hold the inductor current to hold the load-line during a dynamic VID event. The VDD controller will always enter full-phase configuration when it receives dynamic VID up command; If VDD controller receives dynamic VID down command, it will hold the operating state. technology, the output voltage is dependent on output current, and the current monitoring function is achieved by this characteristic of output voltage. The equivalent output current will be sensed from inductor current sensing and mirrored to the IMON pin. The resistor connected to the IMON pin determines voltage of the IMON output. When the VID CCM down on light loading condition, the negative inductor current will be produced, and it may cause the audio noise and phase ring effect. For For Method1 current sensing : improving the problems, the controller set the dynamic VID down slew rate to 0.625mV/s, the action will reduce the negative current and phase ring effect. Ramp Compensation TM G-NAVP topology is one type of ripple based control that has fast transient response. However, ripple based control usually don't have good noise immunity. The RT3662AC provides a ramp compensation to increase noise immunity and reduce jitter at the switching node, refer to Figure 10 shows the ramp compensation. When the VDD controller takes phase shedding operation and enters diode emulation mode, the internal ramp of VDD controller will be modified for the reason of stability. W/O ramp compensation VO Noise Margin VREF VCOMP - VCS PWM With ramp compensation VO VIMON IL,SUM DCRL 1.867m RIMON 0.8 Where IL,SUM is the VDD output current, DCRL is the current sense resistance, RIMON is the IMON pin equivalent setting resistor, and the current sense gain equal to 1.867m. The ADC circuit of the VDD controller monitors the voltage variation at the IMON pin, and this voltage is decoded into digital format and stored into output current register. DIMON VIMON 0.8 255 (Bits) 0.8 When the transient load step-up becomes quite large, it is difficult for loop response to meet the energy transfer. Hence, the output voltage generate undershoot to fail specification. RT3662AC has Quick Response (QR) mechanism which is able to improve this issue. It adopts a nonlinear control mechanism which can disable interleaving function and simultaneously turn on all UGATE one pulse at instantaneous step-up transient load to restrain the output voltage drooping. The output voltage signal behavior needs to be detected so that QR mechanism can be trigged. Refer to Figure 11, the output voltage signal is via a remote sense line to connect at the VSEN pin. The QR threshold can be set by SET1 pin setting for VDD controller refers to Table 3. QR_TH CMP + + QR Pulse Generation Circuit VCOMP - VCS (21) Quick Response Noise Margin VRAMP (20) VSEN PWM Figure 11. VDD Controller : Quick Response Triggering Figure 10. Ramp Compensation Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3662AC-01 April 2016 Circuit is a registered trademark of Richtek Technology Corporation. www.richtek.com 31 RT3662AC Over-Current Protection The RT3662AC provides the over current protection function. The OCP_SPIKE threshold will be set by the current monitor resistor RIMON as below : Under-Voltage Lock Out (UVLO) For Method1 current sensing : 1.6 0.8 OCP_SPIKE DCRL 1.867m RIMON MOSFETs. When UVP is triggered by one rail, the other rail will also enter soft shutdown sequence. A 3s delay is used in UVP detection circuit to prevent false trigger. (22) For prevent the OCP false trigger, the trigger delay is requirement, refer to Electrical Characteristics. When output current is still higher than the OCP_SPIKE after the trigger delay time, the OCP will be latched, and then the VDD controller will turn off both high-side and lowside MOSFETs of all channels. During normal operation, if the voltage at the VCC pin drops below IC POR threshold, the VDD controller will trigger UVLO. The UVLO protection forces all high-side and low-side MOSFETs off by shutting down internal PWM logic drivers. A 3s delay is used in UVLO detection circuit to prevent false trigger. VDDNB Controller VDDNB Controller Disable The VDDNB controller can be disabled by connecting ISENP_NB to a voltage higher than “VCC 0.5V”. If not Per-Phase Over Current Protection The VDD controller provides per-phase over current protection (PHOCP) function in each phase. If the VDD controller force 1 phase operation by pulling ISEN2P pin to 5V, it only detected at soft-start duration when VR power on. The VDD PHOCP threshold is set by TSEN pin setting described as below : in use, ISENN_NB is recommended to be connected to VCC. When VDDNB controller is disabled, all SVID commands related to VDDNB controller will be rejected. Loop Control high-side and low-side MOSFETs to protect CPU. The VDDNB controller adopts Richtek's proprietary GNAVPTM topology. The G-NAVPTM is based on the finite gain peak current mode with CCRCOT (Constant Current Ripple Constant On-Time) topology. The output voltage, VVDDNB will decrease with increasing output load current. The control loop consists of PWM modulators with power stages, current sense amplifiers and an error amplifier as shown in Figure 12. Over-Voltage Protection (OVP) Similar to the peak current mode control with finite The OVP circuit of the VDD controller monitors the output voltage via the VSEN pin after POR. When the VSEN voltage exceeds the OVP threshold 1.85V, OVP is triggered and latched. The VDD controller will try to turn on low-side MOSFET and turn off high-side compensator gain, the HS_FET on-time is determined by CCRCOT on-time generator. When load current increases, VCS increases, the steady state COMP voltage also increases and induces VVDDNB_SENSE to decrease, thus achieving AVP. A near-DC offset canceling is added to the output of EA to eliminate the inherent output offset of finite gain peak current mode controller. PHOCP_TH OCP_SPIKE N M (23) N is the VDD PHOCP setting ratio, M is the operation phase number. If the PHOCP is triggered, the controller will turn off all MOSFET of all active phases to protect the CPU. When OVP is triggered by one rail, the other rail will also enter soft shut down sequence. A 1s delay is used in OVP detection circuit to prevent false trigger. Under-Voltage Protection (UVP) The VDD controller implements UVP of VSEN pin. If VSEN voltage is less than the internal reference by 500mV, the VDD controller will trigger UVP latch. The UVP latch will turn off both high-side and low-side Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 32 is a registered trademark of Richtek Technology Corporation. DS3662AC-01 April 2016 RT3662AC small initial dip with a slow response time. VIN + CMP - COMP2 HS_FET VVDDNB L RSENSE CCRCOT PWM Logic Driver RX1 CX RC LS_FET VCS 0.75 x AI_VDDNB + RX2 C ISENP_NB 1.867m ISENN_NB - IMON_NB RIMON_NB Offset Canceling C2 C1 COMP_NB FB_NB R2 R1 + EA + VREF_PINSET RGND Droop Setting It is very easy to achieve Active Voltage Positioning (AVP) by properly setting the error amplifier gain due to the native droop characteristics as shown in Figure 13. This target is to have VVDDNB = VDAC ILOAD x RDROOP VVDDNB_SENSE (27) Then solving the switching condition VCOMP2 = VCS in Figure 12 yields the desired error amplifier gain as VSS_SENSE VDAC Figure 12. VDDNB Controller : Simplified Schematic with Voltage Loop and Current Loop Current Sense Setting Refer to Figure 12, for different RSENSE resistor, the current sense method can classify as two types. The method1 only use RX1 for lower RSENSE application, and the method2 use RX1 and RX2 to divide the current signal for higher RSENSE application. Richtek also provide Excel based design tool to let user choose the appropriate components quickly. The current sense topology of the VDDNB controller is continuous inductor current sensing. Therefore, the controller has less noise sensitive. Low offset amplifiers are used for loop control and over current detection. The ISENP_NB and ISENN_NB pins denote the positive and negative input of the current sense amplifier. In order to optimize transient performance, the GI A V R2 R1 RDROOP Method1 : GI RSENSE 1.867m RIMON 0.75 AI_VDDNB (29) Method2 : GI RSENSE R X2 1.867m RIMON 0.75 AI_VDDNB R X1 R X2 L RSENSE Method1 : Req R X1 Method2 : Req R X1 R X2 R X1 R X2 current gain ratio set by SET1 pin setting. RDROOP is the equivalent load-line resistance as well as the desired static output impedance. VVDDNB AV2 > AV1 (24) AV2 (25) AV1 0 (26) Considering the inductance tolerance, the resistor Req has to be tuned on board by examining the transient voltage. If the output voltage transient has an initial dip below the minimum load-line requirement and the response time is too fast causing a ring back, the value of resistance should be increased. Vice versa, with a high resistance, the output voltage transient has only a Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3662AC-01 April 2016 (30) Where GI is the current sense amplifier gain. RSENSE is the current sense resistor. If no external sense resistor present, it is the equivalent resistance of the inductor. RIMON_NB is the IMON_NB equivalent resistance. For the PHOCP accuracy, the RIMON_NB resistor need to set in 8k to 70k. AI_VDDNB is the VDDNB controller recommended Req and CX will be set according to the equation as below, and recommended set to 1.1. Req CX (28) Load Current Figure 13. VDDNB Controller : Error Amplifier gain (AV) Influence on VVDDNB Accuracy Loop Compensation Optimized compensation of the VDDNB controller allows for best possible load step response of the regulator’s output. A type-I compensator with one pole and one zero is adequate for proper compensation. is a registered trademark of Richtek Technology Corporation. www.richtek.com 33 RT3662AC Figure 14 shows the compensation circuit. Previous design procedure shows how to select the resistive feedback components for the error amplifier gain. Next, VINI_OFS is the initial offset voltage set by pin setting function, and the dynamic offset voltage, VDYN_OFS, controlled by CPU, and it can be set through the SVI2 C1 and C2 must be calculated for compensation. The target is to achieve constant resistive output impedance over the widest possible frequency range. interface. The pole frequency of the compensator must be set to compensate the output capacitor ESR zero : fP 1 2 C RC (31) Where C is the capacitance of output capacitor, and RC is the ESR of output capacitor. C2 can be calculated as follows : C2 C x RC R2 (32) The zero of compensator has to be placed at half of the switching frequency to filter the switching related noise. Such that, C1 1 R1 fSW (33) During a dynamic VID event, the charging (dynamic VID up) or discharging (dynamic VID down) current causes unwanted load-line effect which degrades the settling time performance. The RT3662AC will hold the inductor current to hold the load-line during a dynamic VID event. The VDDNB controller will always enter CCM operation when it receives dynamic VID up command; If VDD controller receives dynamic VID down command, it will hold the operating state. When the VID CCM down on light loading condition, the negative inductor current will be produced, and it may cause the audio noise and phase ring effect. For improving the problems, the controller set the dynamic VID down slew rate to 0.625mV/s, the action will reduce the negative current and phase ring effect. Ramp Compensation COMP_NB C2 C1 R2 R1 VVDDNB_SENSE FB_NB + EA + Dynamic VID Enhancement RGND VSS_SENSE VDAC Figure 14. VDDNB Controller : Compensation Circuit Initial and Dynamic Offset The VDDNB controller features initial and dynamic offset function. The initial offset function can be implemented through the TSEN pin setting. And the Dynamic offset can be implemented by SVI2 interface, it controlled by CPU. Consider the offset factor, the VDDNB output voltage described as below : VVDDNB VDAC ILOAD RDROOP VINI_OFS VDYN_OFS (34) G-NAVPTM topology is one type of ripple based control that has fast transient response. However, ripple based control usually don't have good noise immunity. The RT3662AC provides a ramp compensation to increase noise immunity and reduce jitter at the switching node refer to Figure 10 shows the ramp compensation. When the VDDNB controller takes phase shedding operation and enters diode emulation mode, the internal ramp of VDDNB controller will be modified for the reason of stability. Current Monitoring and Reporting The VDDNB controller provides current monitoring function via inductor current sensing. In the G-NAVPTM technology, the output voltage is dependent on output current, and the current monitoring function is achieved by this characteristic of output voltage. The equivalent output current will be sensed from inductor current sensing and mirrored to the IMON_NB pin. The resistor connected to the IMON_NB pin determines voltage of the IMON_NB output. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 34 is a registered trademark of Richtek Technology Corporation. DS3662AC-01 April 2016 RT3662AC For Method1 current sensing : Over-Current Protection VIMON_NB IL,SUM DCRL 1.867m RIMON_NB 0.8 (35) The RT3662AC provides the over current protection function. The OCP_SPIKE_NB threshold will be set by Where IL,SUM is the VDDNB output current, DCRL is the current sense resistance, RIMON_NB is the IMON_NB pin equivalent setting resistor, and the current sense gain equal to 1.867m. The ADC circuit of the VDDNB controller monitors the voltage variation at the IMON_NB pin, and this voltage is decoded into digital format and stored into output current register. DIMON_NB VIMON_NB 0.8 0.8 255 (Bits) (36) VDDNB Voltage Reporting Offset The VDDNB controller senses the ISENN_NB voltage for voltage reporting. In Figure 15, due to the PCB trace (RPCB) from ISENN_NB to output capacitor, it will cause the voltage drop on loading, as the loading current become bigger, the drop will affect the voltage reporting seriously. Through the voltage reporting offset function, it can be improved, and the voltage reporting of VDDNB controller (VVDDNB_RPT) can be described as below : VVDDNB_RPT(d) VISENN_NB_ADC(d) VVDDNB_RPT_OFS(d) (37) VVDDNB_RPT is the VDDNB voltage reporting digital code, VISENN_NB_ADC is the ISENN_NB sensed voltage digital code and VVDDNB_RPT_OFS is the VDDNB voltage reporting offset bits. VIN BOOT_NB 30 UGATE_NB 31 PHASE_NB LGATE_NB VVDDNB RPCB 32 33 LOAD the current monitor resistor RIMON_NB as below : For Method1 current sensing : OCP_SPIKE_NB 1.6 0.8 DCRL 1.867m RIMON_NB (38) For prevent the OCP false trigger, the trigger delay is requirement, refer to Electrical Characteristics. When output current is still higher than the OCP_SPIKE_NB after the trigger delay time, the OCP will be latched, and then the VDDNB controller will turn off both high-side and low-side MOSFETs. Per-Phase Over Current Protection The VDDNB controller provides per-phase over current protection (PHOCP) function, it only detected at softstart duration when VR power on. The PHOCP threshold is set by TSEN_NB pin setting described as below : (39) PHOCP_TH OCP_SPIKE_NB N N is the VDDNB PHOCP setting ratio. If the PHOCP is triggered, the controller will turn off all high-side and low-side MOSFETs to protect CPU. Over-Voltage Protection (OVP) The OVP circuit of the VDDNB controller monitors the output voltage via the ISENN_NB pin after POR. When the ISENN_NB voltage exceeds the OVP threshold 1.85V, OVP is triggered and latched. The VDDNB controller will try to turn on low-side MOSFET and turn off high-side MOSFET of all active phases to protect the CPU. When OVP is triggered by one rail, the other rail will also enter soft shut down sequence. A 1s delay is used in OVP detection circuit to prevent false trigger. ISENP_NB 25 ISENN_NB 24 Under-Voltage Protection (UVP) Figure 15. The Description of PCB trace from ISENN_NB to Output Capacitor The VDDNB controller implements UVP of ISENN_NB pin. If ISENN_NB voltage is less than the internal reference by 500mV, the VDDNB controller will trigger UVP latch. The UVP latch will turn off both high-side and low-side MOSFETs. When UVP is triggered by one rail, the other rail will also enter soft shutdown sequence. A 3s delay is used in UVP detection circuit to prevent false trigger. Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3662AC-01 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 35 RT3662AC During normal operation, if the voltage at the VCC pin drops below IC POR threshold, the VDDNB controller will trigger UVLO. The UVLO protection forces all highside and low-side MOSFETs off by shutting down internal PWM logic drivers. A 3s delay is used in UVLO detection circuit to prevent false trigger. Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : PD(MAX) = (TJ(MAX) TA) / JA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and JA is the junction to ambient thermal resistance. The maximum power dissipation depends on the operating ambient temperature for fixed TJ(MAX) and thermal resistance, JA. The derating curve in Figure 16 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. 4.0 Maximum Power Dissipation (W)1 Under-Voltage Lock Out (UVLO) Four-Layer PCB 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 16. Derating Curve of Maximum Power Dissipation For recommended operating condition specifications, the maximum junction temperature is 125C. The junction to ambient thermal resistance, JA, is layout dependent. For WQFN-40L 5x5 package, the thermal resistance, JA, is 27.5C/W on a standard JEDEC 517 four-layer thermal test board. The maximum power dissipation at TA = 25C can be calculated by the following formula : PD(MAX) = (125C 25C) / (27.5C/W) = 3.63W for WQFN-40L 5x5 package Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 36 is a registered trademark of Richtek Technology Corporation. DS3662AC-01 April 2016 RT3662AC Outline Dimension Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 D 4.950 5.050 0.195 0.199 D2 3.250 3.500 0.128 0.138 E 4.950 5.050 0.195 0.199 E2 3.250 3.500 0.128 0.138 e L 0.400 0.350 0.016 0.450 0.014 0.018 W-Type 40L QFN 5x5 Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS3662AC-01 April 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 37