BTS4175SGA Data Sheet (467 KB, EN)

Data Sheet, Rev.1.0, April 2008
BTS4175SGA
Smart High-Side Power Switch
Automotive Power
BTS4175SGA
1
Overview 3
2
Block Diagram 5
3
3.1
3.2
3.3
Pin Configuration 6
Pin Assignment 6
Pin Definitions and Functions 6
Voltage and Current Definition 7
4
4.1
4.2
4.3
General Product Characteristics 8
Absolute Maximum Ratings 8
Functional Range 9
Thermal Resistance 9
5
5.1
5.2
5.3
5.4
Power Stage 10
Output ON-State Resistance 10
Turn ON / OFF Characteristics 10
Inductive Output Clamp 11
Electrical Characteristics Power Stage 13
6
6.1
6.2
6.3
6.4
6.5
6.6
Protection Mechanisms 14
Loss of Ground Protection 14
Undervoltage Protection 14
Overvoltage Protection 14
Reverse Polarity Protection 15
Overload Protection 15
Electrical Characteristics Protection Functions 17
7
7.1
7.2
7.2.1
7.2.2
7.3
Diagnostic Mechanism 18
ST Pin 18
ST Signal in Case of Failures 18
Diagnostic in Open Load, Channel OFF 18
ST Signal in case of Over Temperature 20
Electrical Characteristics Diagnostic Functions 21
8
8.1
8.2
Input Pin 22
Input Circuitry 22
Electrical Characteristics 22
9
9.1
Application Information 23
Further Application Information 23
10
Package Outlines 24
11
Revision History 25
Data Sheet
2
Rev.1.0, 2008-04-29
Smart High-Side Power Switch
1
BTS4175SGA
Overview
Basic Features
•
•
•
•
•
•
•
•
•
•
Fit for 12V and 24V application
One Channel device
Very Low Stand-by Current
CMOS Compatible Inputs
Electrostatic Discharge Protection (ESD)
Optimized Electromagnetic Compatibility
Logic ground independent from load ground
Very Low Leakage Current from OUT to the load in OFF state
Green Product (RoHS compliant)
AEC Qualified
PG-DSO-8-24
Description
The BTS4175SGA is a single channel Smart High-Side Power Switch. It is embedded in a PG-DSO-8-24 package,
providing protective functions and diagnostics. The power transistor is built by a N-channel power MOSFET with
charge pump. The device is monolithically integrated in Smart technology. It is specially designed to drive Relay,
R5W lamp or LED in the harsh automotive environment.
Table 1
Electrical Parameters (short form)
Parameter
Symbol
Value
Operating voltage range
VSOP
VS (AZ)
RDS(ON)
IL (nom)
IL_SCR
IS(off)
-Vs(REV)
6V .... 52V
Over voltage protection
Maximum ON State resistance at Tj = 150°C
Nominal load current
Minimum current limitation
Standby current for the whole device with load
Maximum reverse battery voltage
62V
350mΩ
1.3A
6A
18µA
52V
Diagnostic Feature
•
•
•
•
Open load in OFF
Feedback of the thermal shutdown in ON state
Feedback of the current limitation
Diagnostic feedback with open drain output
Type
Package
Marking
BTS4175SGA
PG-DSO-8-24
4175SGA
Data Sheet
3
Rev.1.0, 2008-04-29
BTS4175SGA
Overview
Protection Functions
•
•
•
•
•
•
•
Short circuit protection
Overload protection
Current limitation
Thermal shutdown
Overvoltage protection (including load dump) with external resistor
Loss of ground and loss of battery protection
Electrostatic discharge protection (ESD)
Application
•
All types of relays, lamps and resistive loads
Data Sheet
4
Rev.1.0, 2008-04-29
BTS4175SGA
Block Diagram
2
Block Diagram
VS
voltage sensor
internal
power
supply
over
temperature
driver
logic
IN
gate control
&
charge pump
E SD
protection
T
clamp for
inductive load
over current
switch off
open load detection
OUT
ST
GND
Figure 1
Data Sheet
Block diagram .emf
Block diagram for the BTS4175SGA
5
Rev.1.0, 2008-04-29
BTS4175SGA
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
GND
1
8
VS
IN
2
7
VS
OUT
3
6
VS
ST
4
5
VS
Figure 2
Pin Configuration
3.2
Pin Definitions and Functions
Pin
Symbol
Function
1
GND
Ground; Ground connection
2
IN
Input channel; Input signal. Activate the channel in case of logic high level
3
OUT
Output; Protected High side power output channel
4
ST
Diagnostic feedback; of channel. Open drain.
5, 6, 7, 8
VS
Battery voltage; Design the wiring for the simultaneous max. short circuit current
and also for low thermal resistance
Data Sheet
6
Rev.1.0, 2008-04-29
BTS4175SGA
Pin Configuration
3.3
Voltage and Current Definition
Figure 3 shows all terms used in this data sheet, with associated convention for positive values.
IS
VS
VD S
VS
IIN
IN
IL
OUT
VIN
VOU T
IST
ST
V ST
GND
R GND
I GN D
Voltage and current convention
single avec diag.vsd
Figure 3
Data Sheet
Voltage and current definition
7
Rev.1.0, 2008-04-29
BTS4175SGA
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Absolute Maximum Ratings 1)
TJ = 25°C; (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Max.
–
52
V
–
0
52
V
–
0
36
V
RECU = 20mΩ,
RCable=16mΩ/m,
LCable=1µH/m,
Voltages
VS
- VS(REV)
4.1.1
Supply voltage
4.1.2
Reverse polarity Voltage
4.1.3
Supply voltage for short circuit protection Vbat(SC)
l = 0 or 5m 2)
see Chapter 6
Input pins
4.1.4
Voltage at INPUT pins
4.1.5
Current through INPUT pins
VIN
IIN
-10
16
V
–
-5
5
mA
–
Power stage
4.1.6
Load current
| IL |
–
IL(LIM)
A
–
4.1.7
Power dissipation (DC),
PTOT
–
1.5
W
4.1.8
Inductive load switch off energy
dissipation, Single pulse
EAS
–
125
mJ
TA=85°C,
Tj <150°C
Tj=150°C,
VS=13.5V,
IL = 1A
Tj
Tstg
-40
150
°C
–
-55
150
°C
–
VESD
VESD
-1
1
kV
HBM3)
-5
5
kV
HBM3)
Currents
Temperatures
4.1.9
Junction Temperature
4.1.10
Storage Temperature
ESD Susceptibility
4.1.11
ESD Resistivity IN pin
4.1.12
ESD Resistivity all other pins
1) Not subject to production test, specified by design
2) In accordance to AEC Q100–012 and AEC Q101-006
3) ESD susceptibility HBM according to EIA/JESD 22-A 114B
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Data Sheet
8
Rev.1.0, 2008-04-29
BTS4175SGA
General Product Characteristics
4.2
Pos.
4.2.1
Functional Range
Parameter
Symbol
Limit Values
Min.
Max.
Unit
Conditions
Operating Voltage
VSOP
6
52
V
VIN = 4.5V,
RL = 47Ω,
VDS < 0.5V
VSUV
IGND
–
5.5
V
–
2
mA
VIN = 5V
IS(OFF)
–
–
15
18
µA
Tj <85°C
Tj = 150°C,
RL = 47Ω,
VIN = 0V
4.2.2
Undervoltage shutdown
4.2.3
Operating current
4.2.4
Standby current for whole device
with load
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Pos.
Thermal Resistance
Parameter
4.3.1
Junction to Soldering Point
4.3.2
Junction to Ambient:
Channel active
Symbol
RthJS
RthJA
Limit Values
Min.
Typ.
Max.
–
–
15
–
83
–
Unit
Conditions
K/W
–1)
K/W
with 6cm² cooling
area1)
1) Not subject to production test, specified by design
Data Sheet
9
Rev.1.0, 2008-04-29
BTS4175SGA
Power Stage
5
Power Stage
The power stage is built by an N-channel vertical power MOSFET (DMOS) with charge pump.
5.1
Output ON-State Resistance
The ON-state resistance RDS(ON) depends on the supply voltage as well as the junction temperature Tj. Figure 4
shows the dependencies for the typical ON-state resistance. The behavior in reverse polarity is described in
Chapter 6.4.
1000
400
900
350
800
300
Rdson (m Ω )
Rdson (m Ω )
700
250
200
150
600
500
400
300
100
200
50
100
0 1 2 3 4
14
0
12
0
10
0
80
60
40
0
20
0
-2
0
-4
0
0
Battery voltage (V)
Junction tem perature (°C)
Figure 4
5 6 7 8 9 10 11 12 13 14 15 16 17 18
Rdson.vsd
Typical ON-state resistance
A high signal (See Chapter 8) at the input pin causes the power DMOS to switch ON with a dedicated slope, which
is optimized in terms of EMC emission.
5.2
Turn ON / OFF Characteristics
Figure 5 shows the typical timing when switching a resistive load.
IN
V IN_H_min
VIN_L_max
t
V OUT
90% VS
dV/dt OFF
tON
70% VS
dV/dt ON
30% VS
t OFF
10% VS
t
Switching times.vsd
Figure 5
Data Sheet
Turn ON/OFF (resistive) timing
10
Rev.1.0, 2008-04-29
BTS4175SGA
Power Stage
5.3
Inductive Output Clamp
When switching OFF inductive loads with high side switches, the voltage VOUT drops below ground potential,
because the inductance intends to continue driving the current. To prevent the destruction of the device due to
high voltages, there is a voltage clamp mechanism implemented that keeps the negative output voltage at a certain
level (VS-VDS(AZ)). Please refers to Figure 6 and Figure 7 for details. Nevertheless, the maximum allowed load
inductance is limited.
VS
V DS
IN
LOGIC
IL
V BAT
OUT
GND
VIN
VOUT
L, RL
Output clamp.vsd
Figure 6
Output clamp
IN
t
VOUT
VS
t
VS-VDS(AZ)
tpeak
IL
t
Switching an inductance.vsd
Figure 7
Switching in inductance timing
Maximum Load inductance
During demagnetization of inductive loads, energy has to be dissipated in the BTS4175SGA. This energy can be
calculated with following equation:
V S – V DS ( AZ )
L
R L × I L -⎞
E = V DS ( AZ ) × -------- × --------------------------------------+ IL
- + ln ⎛ --------------------------------------⎝ V S – V DS ( AZ )⎠
RL
RL
Following equation simplifies under the assumption of RL = 0Ω.
Data Sheet
11
Rev.1.0, 2008-04-29
BTS4175SGA
Power Stage
VS
2
1
E = --- × LI × ⎛⎝ 1 – ------------------------------------------⎞
2
V S – V DS ( AZ ) )⎠
The energy, which is converted into heat, is limited by the thermal design of the component. See Figure 8 for the
maximum allowed energy dissipation.
1800
1600
1400
EAS(mJ)
1200
1000
800
600
400
200
0
0
0,5
1
Load current (A)
Figure 8
Data Sheet
1,5
EAS.vsd
Maximum energy dissipation single pulse, Tj,Start = 150 °C; VS = 13.5V
12
Rev.1.0, 2008-04-29
BTS4175SGA
Power Stage
5.4
Electrical Characteristics Power Stage
Electrical Characteristics: Power stage
VS = 13.5 V, Tj = -40 °C to +150 °C,(unless otherwise specified). Typical values are given at Tj = 25°C
Pos.
Parameter
Symbol
5.4.1
ON-state resistance per channel
RDS(ON)
Limit Values
Min.
Typ.
Max.
–
175
–
Unit
Conditions
mΩ
Tj=25°C1),
IL = 1A,
VIN= 5V,
See Figure 4
5.4.2
5.4.3
–
280
350
–
V
TA=85°C1),
Tj <150°C1)
IDS = 4mA2)
5
µA
VIN=0V
0.7
2
V/µs
RL=47Ω,
Vs=13.5V
See Figure 5
Nominal load current
IL(nom)
1.3
–
Drain to Source clamping Voltage
VDS(AZ)
59
63
IL(OFF)
dV/dtON
–
–
–
VDS(AZ) = VS-VOUT
Tj=150°C
A
5.4.4
Output leakage current
5.4.5
Slew rate ON
10% to 30% VOUT
5.4.6
Slew rate OFF
70% to 40% VOUT
-dV/dtOFF
–
0.9
2
V/µs
5.4.7
Turn-ON time to 90% VS
Includes propagation delay
tON
–
80
180
µs
5.4.8
Turn-OFF time to 10% VS
Includes propagation delay
tOFF
–
80
200
µs
5.4.9
Internal output pull down
RPD
200
kΩ
VOUT(OL) = 4V
1) Not subject to production test, specified by design
2) Voltage is measured by forcing IDS.
Data Sheet
13
Rev.1.0, 2008-04-29
BTS4175SGA
Protection Mechanisms
6
Protection Mechanisms
The device provides embedded protective functions. Integrated protection functions are designed to prevent the
destruction of the IC from fault conditions described in the data sheet. Fault conditions are considered as “outside”
normal operating range. Protection functions are designed for neither continuous nor repetitive operation.
6.1
Loss of Ground Protection
In case of loss of the module ground, where the load remains connected to ground, the device protects itself by
automatically turning OFF (when it was previously ON) or remains OFF, regardless of the voltage applied on IN
pin. In that case, a maximum I(OUTGND) can flow out of the output.
6.2
Undervoltage Protection
Below VSOP_min, the under voltage mechanism is met. If the supply voltage is below the under voltage mechanism,
the device is OFF (turns OFF). As soon as the supply voltage is above the under voltage mechanism, then the
device can be switched ON and the protection functions are operational.
6.3
Overvoltage Protection
There is a clamp mechanism for over voltage protection. To guarantee this mechanism operates properly in the
application, the current in the zener diode ZDAZ has to be limited by a ground resistor. Figure 9 shows a typical
application to withstand overvoltage issues. In case of supply greater than VS(AZ), the power transistor switches
ON and the voltage across logic section is clamped. As a result, the internal ground potential rises to VS - VS(AZ).
Due to the ESD zener diodes, the potential at pin IN rises almost to that potential, depending on the impedance
of the connected circuitry. Integrated resistors are provided at the IN pin to protect the input circuitry from
excessive current flow during this condition.
VS
VBAT
IN
R ST
ZD AZ
R IN
LOGIC
ST
OUT
ZD ESD
GND
R GND
Overvoltage protection single with diag.vsd
Figure 9
Data Sheet
Over voltage protection with external components
14
Rev.1.0, 2008-04-29
BTS4175SGA
Protection Mechanisms
In the case the supply voltage is in between of VS(SC) max and VDS(AZ), the output transistor is still operational and
follow the input. If the channel is in ON state, parameters are no longer warranted and lifetime is reduced
compared to normal mode. This specially impacts the short circuit robustness, as well as the maximum energy
EAS the device can handle.
6.4
Reverse Polarity Protection
In case of reverse polarity, the intrinsic body diode causes power dissipation. The current in this intrinsic body
diode is limited by the load itself. Additionally, the current into the ground path and the logical pins has to be limited
to the maximum current described in Chapter 4.1, sometimes with an external resistor. Figure 10 shows a typical
application. The RGND resistor is used to limit the current in the zener protection of the device. Resistors RIN and
RST is used to limit the current in the logic of the device and in the ESD protection stage. The recommended value
for RGND is 150Ω, for RST 0/1= 15kΩ. In case the over voltage is not considered in the application, RGND can be
replaced by a Shottky diode.
VccµC
Micro controller
(e.g. XC22xx)
RSTPU
R ST
VS
VBAT
ST
-VDS(REV)
R IN
Zdbody
IN
OUT
I L(nom)
ZDESD
GND
RGND
Reverse Polarity single with diag.vsd
Figure 10
Reverse polarity protection with external components
6.5
Overload Protection
In case of overload, or short circuit to ground, the BTS4175SGA offers two protections mechanisms.
Current limitation
At first step, the instantaneous power in the switch is maintained to a safe level by limiting the current to the
maximum current allowed in the switch IL(LIM). During this time, the DMOS temperature is increasing, which affects
the current flowing in the DMOS.
Thermal protection
At thermal shutdown, the device turns OFF and cools down. A restart mechanism is used, after cooling down, the
device restarts and limits the current to IL(SCR). Figure 11 shows the behavior of the current limitation as a function
of time.
Data Sheet
15
Rev.1.0, 2008-04-29
BTS4175SGA
Protection Mechanisms
IN
t
IL
IL(LIM)
IL(SCr)
tm
t
ST
TdST(+)
t
Current limitation with diag full . vsd
Figure 11
Data Sheet
Current limitation function of the time
16
Rev.1.0, 2008-04-29
BTS4175SGA
Protection Mechanisms
6.6
Electrical Characteristics Protection Functions
Electrical Characteristics: Protection
VS = 13.5 V, Tj = -40 °C to +150 °C. Typical values are given at Tj = 25°C
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
-VDS(REV)
–
600
–
mV
TJ = 150°C
VOUT > VS
VS(AZ)
62
–
–
V
Is = 4mA
–
–
4
–
6.5
–
9
–
–
A
Tj = -40°C,
Tj = 25°C,
Tj = 150°C
VS < 40V1),
VS > 40V1)
Reverse polarity
6.6.1
Drain source diode voltage during
reverse polarity
Overvoltage
6.6.2
Over voltage protection
Overload condition
6.6.3
Initial peak short circuit current limit IL(LIM)
(pin 5 to 3)
VS = 20V; tm = 150µs
6.6.4
Repetitive short circuit current
limitation
IL(SCR)
–
6.5
4.5
–
A
6.6.5
Thermal shutdown temperature
150
–
–
°C
–1)
6.6.6
Thermal shutdown hysteresis
TjSC
ΔTJT
–
10
–
K
– 1)
1) Not subject to production test, but specified by design
Data Sheet
17
Rev.1.0, 2008-04-29
BTS4175SGA
Diagnostic Mechanism
7
Diagnostic Mechanism
For diagnosis purpose, the BTS4175SGA provides a status pin.
7.1
ST Pin
BTS4175SGA status pin is an open drain, active low circuit. Figure 12 shows the equivalent circuitry. As long as
no “hard” failure mode occurs (Short circuit to GND / Over temperature or open load in OFF), the signal is
permanently high, and due to a required external pull-up to the logic voltage will exhibit a logic high in the
application. A suggested value for the RPU ST is 15kΩ.
.
VccµC
R PU ST
R ST
ST
Channel 0
Diagnostic
Logic
ZD ESD
GND
Figure 12
Status output circuitry
7.2
ST Signal in Case of Failures
ST pin full diag.vsd
Table 3 gives a quick reference for the logical state of the ST pin during device operation.
Table 3
ST pin truth table
Device operation
IN
OUT
ST
Normal operation
L
L
H
H
H
H
L
> V(OL)
L1)
H
H
H
L
L
H
H
L
L
Open Load channel
Over temp channel
1) L if potential at the output exceeds the Openload detection voltage
7.2.1
Diagnostic in Open Load, Channel OFF
For open load diagnosis in OFF-state, an external output pull-up resistor (ROL) is recommended. For calculation
of the pull-up resistor value, the leakage currents and the open load threshold voltage VOL(OFF) has to be taken into
account. Figure 13 gives a sketch of the situation and Figure 14 shows the typical timing diagram.
Ileakage defines the leakage current in the complete system, including IL(OFF) (see Chapter 5.4) and external
leakages e.g due to humidity, corrosion, etc... in the application.
To reduce the stand-by current of the system, an open load resistor switch SOL is recommended.
Data Sheet
18
Rev.1.0, 2008-04-29
BTS4175SGA
Diagnostic Mechanism
If the channel is OFF, the output is no longer pulled down by the load and VOUT voltage rises to nearly VS. This is
recognized by the device as open load. The voltage threshold is given by VOL(OFF). In that case, the ST signal is
switched to a logical low VSTL.
Vbat
SOL
BTS4175SGA
VS
R OL
OUT
I LOFF
OL
comp.
R PD
Ileakage
GND
VOL(OFF )
RGND
Rleakage
Open Load in OFF .vsd
Figure 13
Open load detection in OFF electrical equivalent circuit
IN
t
V OUT
VOL(OFF)
IL
t
t
ST
V ST(HIGH)
VST(LOW)
t
Diagnostic In Open load full diag.vs
Figure 14
Data Sheet
ST in open load condition
19
Rev.1.0, 2008-04-29
BTS4175SGA
Diagnostic Mechanism
7.2.2
ST Signal in case of Over Temperature
In case of over temperature, the junction temperature reaches the thermal shutdown temperature TjSC.
In that case, the ST signal is stable and remains to toggling between VST(L) and VST(H). Figure 15 gives a sketch
of the situation.
IN
t
V OUT
t
ST
t
T JSC
ΔT JSC
TJ
t
Diagnostic In Overload full toggling.vs
Figure 15
Sense signal in overtemperature condition
.
Data Sheet
20
Rev.1.0, 2008-04-29
BTS4175SGA
Diagnostic Mechanism
7.3
Electrical Characteristics Diagnostic Functions
Electrical Characteristics: Diagnostics
VS = 13.5 V, Tj = -40 °C to +150 °C, (unless otherwise specified) Typical values are given at Vs = 13.5V, Tj = 25°C
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit
Conditions
Load condition threshold for diagnostic
7.3.1
Open Load detection threshold
in OFF state1)
VOL(OFF)
–
3.0
4.0
V
VIN = 0V
7.3.1
Short circuit detection voltage
VOUT(SC)
–
2.8
–
V
–3)
Status output (open drain)
High level; Zener limit voltage
VST (HIGH)
5.4
6.1
–
V
IST = +1,6mA2),
Status output (open drain)
Low level
VST (LOW)
ST pin
7.3.2
7.3.3
Zener Limit voltage
–
–
0.6
V
IST =+1,6mA2)
Diagnostic timing
7.3.4
Status invalid after positive input tdST(+)
slope
–
120
160
µs
–3)
7.3.5
Status invalid after negative
input slope
tdST(-)
–
250
400
µs
–
1) External pull up resistor required for open load detection in OFF state
2) If ground resistor RGND is used, the voltage drop across this resistor has to be added
3) Not subject to production test, specified by design
Data Sheet
21
Rev.1.0, 2008-04-29
BTS4175SGA
Input Pin
8
Input Pin
8.1
Input Circuitry
The input circuitry is CMOS compatible. The concept of the Input pin is to react to voltage transition and not to
voltage threshold. With the Schmidt trigger, it is impossible to have the device in an un-defined state, if the voltage
on the input pin is slowly increasing or decreasing. The output is either OFF or ON but cannot be in an linear or
undefined state. The input circuitry is compatible with PWM applications. Figure 16 shows the electrical equivalent
input circuitry. The pull down current source ensures the channel is OFF with a floating input.
IN
RI
II
To driver’s logic
ESD
Input circuitry.vsd
Figure 16
Input pin circuitry
8.2
Electrical Characteristics
Electrical Characteristics: Diagnostics
VS = 13.5 V, Tj = -40 °C to +150 °C, Typical values are given at Vs = 13.5V, Tj = 25°C
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
–
–
0.8
V
–1)
2.2
–
–
V
–1)
–
0.4
–
V
–2)
1
–
25
µA
3
–
25
µA
VIN= 0,7V
VIN= 5V
2
3.5
5
kΩ
See Figure 16
INput pins characteristics
8.2.1
Low level input voltage
8.2.2
High level input voltage
8.2.3
Input voltage hysteresis
8.2.4
Low level input current
8.2.5
High level input current
8.2.6
Input resistance
VIN(L)
VIN(H)
VIN(HYS)
IIN(L)
IIN(H)
RI
1) If ground resistor RGND is used, the voltage drop across this resistor has to be added
2) Not subject to production test, specified by design
Data Sheet
22
Rev.1.0, 2008-04-29
BTS4175SGA
Application Information
9
Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
VBAT
VDD
VDD
RPUST
VBAT_SW
R IN
Vdd
ROL
Vs
OUT
Microcontroller
(e.g. XC22xx)
IN
IN
ST
OUT
RST
GND
GND
R GND
Application example single avec diag.vsd
IS
Figure 17
Application diagram with BTS4175SGA
Note: This is a very simplified example of an application circuit. The function must be verified in the real application.
9.1
•
Further Application Information
For further information you may visit http://www.infineon.com/
Data Sheet
23
Rev.1.0, 2008-04-29
BTS4175SGA
Package Outlines
10
Package Outlines
1.27
0.1
0.41 +0.1
-0.05
+0.05
-0.01
0.2
C
0.64 ±0.25
0.2 M A C x8
8
5
Index
Marking 1
4
5 -0.21)
8˚ MAX.
4 -0.21)
1.75 MAX.
0.1 MIN.
(1.5)
0.33 ±0.08 x 45˚
6 ±0.2
A
Index Marking (Chamfer)
1)
Figure 18
Does not include plastic or metal protrusion of 0.15 max. per side
PG-DSO-8-24 (Plastic Dual Small Outline Package)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pbfree finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Data Sheet
24
Rev.1.0, 2008-04-29
BTS4175SGA
Revision History
11
Revision History
Version
Date
Changes
1.0
2008-03-12
Creation of the data sheet
Data Sheet
25
Rev.1.0, 2008-04-29
Edition 2008-04-29
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2008 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
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