BTS6110-1SJA Data Sheet (1.6 MB, EN)

BTS6110-1SJA
Smart High-Side Power Switch
Data Sheet
Rev. 1.1, 2014-11-24
Automotive Power
BTS6110-1SJA
Table of Contents
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4
4.1
4.2
4.3
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage and Current Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
5
5
5
5
5.1
5.2
5.3
5.3.1
5.3.2
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCB set up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
6
7
7
7
8
6
6.1
6.2
6.3
6.4
6.5
6.6
Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Output ON-state Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Turn ON/OFF Characteristics with Resistive Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Frequency Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Timing Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Polarization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CAP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7
7.1
7.2
7.3
7.3.1
7.3.2
Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Limitation in the Power DMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
8.1
8.2
Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Load Current Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Under load Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
9
9.1
9.2
9.3
9.4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics CAP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics for the Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Diagnostic Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
11
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Data Sheet
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Rev. 1.1, 2014-11-24
Smart High-Side Power Switch
1
BTS6110-1SJA
Overview
Application
•
Side Indicator 2 x R10W + 1 x R2W
Basic Features
•
•
•
•
•
•
One channel device
Very small external reservoir capacitor of 10 µF
Electrostatic discharge protection (ESD)
Optimized electromagnetic compatibility
Green product (RoHS compliant)
AEC qualified
Package
Marking
PG-DSO-8-49
6110-SJA
Protection Functions
•
•
Overtemperature protection with limited restart
Overvoltage protection without external component
Diagnostic Functions
•
Auto-failure detection of a failed main lamp (N-1 diagnosis), signalized by frequency doubling
Description
The BTS6110-1SJA is a single 80 mΩ channel Smart High-Side Power Switch, embedded in a PG-DSO-8-49
package, providing protective functions and diagnosis. It is designed to drive lamps 2 x R10W + 1 x R2W to realize
the side indicators function for motorcycle.
Table 1
Product Summary
Parameter
Symbol
Value
Operating voltage range
VS(OP)
VS(LD)
RDS(ON)
f4
f2
IL(SC)
9 V ... 16 V
Load dump voltage
Maximum ON state resistance at TJ = 150 °C
Flasher Frequency ; normal operation
Flasher Frequency; loss of a main lamp / typical value
Minimum current limitation
65 V
200 mΩ
85 ± 15 cycles / minute 1)
f4 * 2.24
20 A
1) With external capacitor CEXT = 10µF
Data Sheet
3
Rev. 1.1, 2014-11-24
BTS6110-1SJA
Block Diagram
2
Block Diagram
Internal
Power
Supply
CAP
Capacitor
loading
Management
VS
Over voltage
clamping
Over
Temperature
Clock
Generation
+
T
Gate Control
Driver Logic
Over Current
Limiter
Load Current
Sense
Input Trigger
TEST
OUT
ESD
Block diagram single.vsd
Figure 1
BTS6110-1SJA Block Diagram
3
Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
V BAT
CVS
Vs
TEST
OUT
CEXT
CAP
+
Application example_onedash.vsd
Figure 2
Application Example
Note: This is a very simplified example of an application circuit. The function must be verified in the real application.
Table 2
Bill of Material
Reference
Value
Purpose
CVS
10 nF / min. 100V
Reduction of voltage spikes. It is mandatory to place this component
to assure correct device behavior.
CEXT
10 µF
BTS6110-1SJA energy reservoir during ON state. It is mandatory to
place this component to assure correct device behavior.
Data Sheet
4
Rev. 1.1, 2014-11-24
BTS6110-1SJA
Pin Configuration
4
Pin Configuration
4.1
Pin Assignment
CAP
1
8
VS
TEST
2
7
VS
OUT
3
6
VS
OUT
4
5
VS
pinout Single SO 8.vsd
Figure 3
Pin Configuration
4.2
Pin Definitions and Functions
Pin
Symbol
Function
1
CAP
CAPacitor; Must be connected to OUT via a reservoir capacitor
2
TEST
TEST MODE PIN; Must be connected to OUT
3, 4
OUT
OUTput; Protected high side power output channel 1)
5, 6, 7, 8
VS
Voltage Supply; Battery voltage
1) All output pins must be connected together on the PCB. PCB traces have to be designed to withstand the maximum current
which can flow.
4.3
Voltage and Current Definition
Figure 4 shows all terms used in this document, with associated convention for positive values.
+BAT
I
VS
S
VDS
VS
ITEST
IOUT
TEST
OUT
CAP
VTEST
ICAP
VCAP
VOUT
GND
voltage and current convention single
Figure 4
Data Sheet
.vsd
Voltage and Current Definition
5
Rev. 1.1, 2014-11-24
BTS6110-1SJA
General Product Characteristics
5
General Product Characteristics
5.1
Absolute Maximum Ratings
Table 3
Absolute Maximum Ratings 1)
TJ = -40 °C to +150 °C; (unless otherwise specified)
Parameter
Symbol
Values
Unit
Note /
Test Condition
Number
Min.
Typ.
Max.
-0.3
–
18
V
–
P_5.1.1
0
–
16
V
P_5.1.2
–
–
65
V
t < 120 s
TA = 25 °C
RL ≥ 6 Ω
2)
RI = 2 Ω
RL = 6 Ω
VCAP
ICAP
-0.3
–
8.0
V
–
P_5.1.4
-2
–
15
mA
–
P_5.1.5
VTEST
ITEST
-0.3
–
1
V
–
P_5.1.6
-2
–
2
mA
–
P_5.1.7
Load current
| IL |
–
–
IL(LIM)
A
–
P_5.1.8
Power dissipation
(50% duty cycle)
PTOT
–
–
1.4
W
TA = 85 °C
TJ < 150 °C
P_5.1.9
Voltage at power transistor
VDS
–
–
65
V
–
P_5.1.10
TJ
TSTG
-40
–
150
°C
–
P_5.1.11
-55
–
150
°C
–
P_5.1.12
VESD
VESD
-2
–
2
kV
3)
HBM
P_5.1.13
kV
3)
HBM
P_5.1.14
Supply Voltages
Supply voltage
Reverse polarity voltage
VS
-VS(REV)
Supply voltage for Load dump VS(LD)
protection
P_5.1.3
CAP Pin
Voltage at CAP pin
Current through CAP pin
TEST Pin
Voltage at TEST pin
Current through TEST pin
Power Stage
Temperatures
Junction temperature
Storage temperature
ESD Susceptibility
ESD susceptibility (all pins)
ESD susceptibility (OUT
versus VS)
-4
–
4
1) Not subject to production test. Specified by design.
2) VS(LD) is setup without the DUT connected to the generator per ISO 7637-1.
3) ESD susceptibility HBM according to EIA/JESD 22-A 114B
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not
designed for continuous repetitive operation.
Data Sheet
6
Rev. 1.1, 2014-11-24
BTS6110-1SJA
General Product Characteristics
5.2
Functional Range
Table 4
Functional Range TJ = -40 °C to +150 °C; (unless otherwise specified)
Parameter
Symbol
Nominal operating voltage
VNOM
VS(OP)
Extended operating voltage
Values
Min.
Typ.
Max.
9
13.5
16
8
–
24
Unit
Note /
Test Condition
Number
V
VOUT = 0 V
P_5.2.1
V
1)
P_5.2.2
8 to 18 V: RL =
6 Ω, 18 to 24 V:
RL = 12 Ω
VDS < 0.7 V
1) Not subject to production test. Specified by design.
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
5.3
Thermal Resistance
Table 5
Thermal Resistance
Parameter
Symbol
Junction to case (bottom)
Junction to ambient
RthJS
RthJA
Values
Unit
Note /
Test Condition
Number
Min.
Typ.
Max.
–
40
–
K/W
1)
P_5.3.1
–
58
–
K/W
1) 2)
P_5.3.2
1) Not subject to production test. Specified by design.
2) Specified Rthja value is according to JEDEC JESD51-2,-5,-7 at natural convection on FR4 2s2p board with thermal vias;
The product (chip + package) was simulated on a 76.4 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu,
2 x 35 µm Cu).
5.3.1
PCB set up
e = 1.27; A = 5.69; L = 1.31; B = 0.65
B
e
L
A
HLG05506
Figure 5
Data Sheet
PCB Footprint for PG-DSO-8-49
7
Rev. 1.1, 2014-11-24
BTS6110-1SJA
General Product Characteristics
5.3.2
Thermal Resistance
100
90
80
70
Zth‐ja [K/W]
60
50
40
30
20
1s0p‐footprint
1s0p‐100mm²
10
1s0p‐300mm²
1s0p‐600mm²
0
1.00E‐04
1.00E‐03
1.00E‐02
1.00E‐01
1.00E+00
1.00E+01
1.00E+02
1.00E+03
Time [s]
Figure 6
Typical Thermal Resistance for FR2 PCB
100
90
80
70
Zth‐ja [K/W]
60
50
40
30
20
1s0p‐footprint
1s0p‐100mm²
10
1s0p‐300mm²
1s0p‐600mm²
0
1.00E‐04
1.00E‐03
1.00E‐02
1.00E‐01
1.00E+00
1.00E+01
1.00E+02
1.00E+03
Time [s]
Figure 7
Data Sheet
Typical Thermal Resistance for FR4 PCB
8
Rev. 1.1, 2014-11-24
BTS6110-1SJA
Power Stage
6
Power Stage
The power stage is built using an N-channel vertical power MOSFET (DMOS) with charge pump.
6.1
Output ON-state Resistance
The ON-state resistance RDS(ON) depends on the junction temperature TJ. Figure 8 shows the dependencies in
terms of temperature for the typical ON-state resistance. The behavior in reverse polarity is described in
Chapter 7.2.
180
160
RDS(ON) [mΩ ]
140
120
100
80
60
40
-40
typical RDS(ON) with VCHI
typical RDS(ON) with VCLO
-20
0
20
40
60
temp [°C]
80
100
120
140
160
BTS6110-1EJA
Figure 8
Typical ON-state Resistance
6.2
Turn ON/OFF Characteristics with Resistive Load
A low voltage event at the OUT pin causes the power DMOS to switch ON with a dedicated slope, optimized in
terms of Electro Magnetic Emission.
Chapter 7.2 shows the typical timing when switching a resistive load.
VOUT
dV/dt ON
dV/dt OFF
t RISE
90% VS
70% VS
30% VS
tINIT
t FALL
10% VS
t
Switching times .vsd
Figure 9
Data Sheet
Switching a Resistive Load Timing
9
Rev. 1.1, 2014-11-24
BTS6110-1SJA
Power Stage
6.3
Frequency Generator
The BTS6110-1SJA is designed to manage side indicators functionality. As soon as a LOW voltage level is applied
for more than tINIT, at OUT pin, the clock generator is activated and the channel is switched ON. At t1, the device
starts diagnosis. Refer to Figure 10. In case of underload detection, the device switches OFF and operates the
failure frequency based on T2FAIL. Otherwise, the device stays ON and runs on frequency based on T4. The duty
cycle is fixed to d.
OUT
T2
NORMAL OPERATION
t
DIAGNOSTIC
OUT
MAIN LAMP BROKEN
t
tINIT
T2FAIL
T4
Figure 10
Frequency Generation Timing
6.4
Timing Output
timing_definition.vsd
The BTS6110-1SJA is dedicated to side indicators function on vehicle. The frequency f2 (resp T2FAIL period) is
tuned to be the failure indication frequency. At t1 time, the BTS6110-1SJA measures the load current. Refer to
Figure 11. Depending on the measurement results, three possible actions will be done (see Chapter 8 for the
details diagnosis definition).
If an underload is detected, it provokes immediate switch OFF to run at f2 frequency, indicating the failure. A
normal diagnosis keep the power output ON for t1 to run at f4 frequency. A short circuit will latch the device.
Data Sheet
10
Rev. 1.1, 2014-11-24
BTS6110-1SJA
Power Stage
DIAG
DIAG
t1
tINIT
IOUT
tINIT
VOUT
DIAG
DIAG
DIAG
T4
T2FAIL
T2
SHORT CIRCUIT
VOUT
DIAG
UNDERLOAD
DIAG
DIAG
NOMINAL LOAD
DIAG
T2
T2FAIL
T4
tINIT
IOUT
NOMINAL LOAD
Figure 11
Frequency Generation Timing
6.5
Output Polarization
UNDERLOAD
frequency generator diag.vsd
The BTS6110-1SJA includes from VS to OUT a pull up resistor RL(OFF). This pull-up resistor compensates the IDIRT
leakage current due to the humidity and dust at the handle bar selector. It forces supply voltage VS at the output
until a load is connected. The BTS6110-1SJA starts as soon as VDS is detected between VS and OUT by charging
the external reservoir capacitor CEXT. Refer to Figure 12.
Data Sheet
11
Rev. 1.1, 2014-11-24
BTS6110-1SJA
Power Stage
VS
CAP
VCP
Charge /Discharge
ICAP
Central Logic &
Band Gap
CLOCK
VCAP
VDS
CEXT
VS
Measurement
OUT
IDIRT
RAIN
EFFECT
RRAIN
Application_Pioggia.vsd
Figure 12
Output Polarization Circuitry
In case of leakage at the output, due to rain for example, the BTS6110-1SJA might start parasitically. To limit the
effect, a load current measurement is implemented to estimate the impedance connected at the output. An
impedance lower than RRAIN will activate the switch while an impedance above (see maximum value P_9.1.11) will
keep the device in sensing mode. Refer to Figure 13.
SELECTOR OFF + RAIN
SELECTOR ON
VOUT
12V
t
0V
VCAP
T2
VCHI
t1
VCLO
tSCAN
t
ICAP
IINIT
tINIT
ICLOAD
t
ICUNLOAD
IOUT
tSTART
ISTART
t
GATE
Cap_load_Pioggia.vsd
Figure 13
Data Sheet
t
Output Timing during Leakage
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Rev. 1.1, 2014-11-24
BTS6110-1SJA
Power Stage
6.6
CAP Pin
The BTS6110-1SJA stores the needed energy to keep the DMOS ON during T2 phase, in the capacitor CEXT. This
capacitor is loaded initially with IINT while OUT is grounded. IINT is relatively important to reduce tINIT, initialization
time. During the next successive activations, the charging / discharging currents are controlled to ICLOAD and
ICUNLOAD whom are significantly lower to improve EMC and capacitor aging.
The loading is stopped when the voltage at the capacitor VCHI is reached, and restarted by VCLO. This oscillation
provides the reference clock to the flasher functionality. In the case VS - VOUT is below VS(OP), the device doesn’t
start. Refer from Equation (1) to Equation (4) and Figure 14 and Figure 15.
(1)
t INIT
V S – 1V
V S – 1V
= C EXT × -------------------- × ln ⎛ -------------------------⎞
⎝ V S – 7 ,5V⎠
I INIT
(2)
T 2FAIL = T 4 × d f
(3)
T2
1
d = ------ = -----------------------------------T4
I CUNLOAD
1 + --------------------------I CLOAD
(4)
T 4 = C EXT × R CAP
VOUT
tINIT
T2
t
T4
I CAP
IINIT
I CLOAD
ICUNLOAD
t
VCAP
VCHI
VCLO
Cap_load. vsd
Figure 14
Data Sheet
t
Capacitor Charge and Discharge Timing
13
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BTS6110-1SJA
Protection Functions
1000
Minimum period T4 at 25°C
Nominal period T4
Maximum period T4 at 25°C
900
Maximum period T4 in ‐20…85°C
Maximum period T4 in ‐40…150°C
800
700
T4 [ms]
600
500
400
7
8
9
10
11
12
13
C [uF]
Figure 15
Normal Period T4 Dependency in Regards to Capacitor Value (typical behavior)
7
Protection Functions
The BTS6110-1SJA provides integrated protection functions. These functions are designed to prevent the
destruction of the IC from fault conditions described in the data sheet. Fault conditions are considered as “outside”
normal operating range. Protection functions are designed for neither continuous nor repetitive operation.
7.1
Overvoltage Protection
The BTS6110-1SJA is protected against overvoltage. In case of a voltage VS > VS(AZ), if the handle bar selector
switch is ON, the ZDS(AZ) will activate the power DMOS and some current will flow, limited by the load.
7.2
Reverse Polarity Protection
In case of reverse polarity, the intrinsic body diodes of the power DMOS causes power dissipation. The current in
this intrinsic body diode is limited by the load itself. Figure 16 shows the application schematic.
Data Sheet
14
Rev. 1.1, 2014-11-24
BTS6110-1SJA
Protection Functions
CAP
Internal Power
Supply
VS
ZDS(AZ)
T
+
ZDS(AZ)
VDS(REV)
LOGIC
CEXT
VBAT(REV)
OUT
I OUT(REV)
Reverse Polarity .vsd
Figure 16
Reverse Polarity Protection
7.3
Overload Protection
In case of overload, such as high inrush of cold lamp filament, or short circuit to ground, the BTS6110-1SJA offers
protection mechanisms.
7.3.1
Current Limitation
At first step, the instantaneous power in the switch is maintained to a safe value by limiting the current to IL(SC).
During this time, the DMOS temperature is increasing.
7.3.2
Temperature Limitation in the Power DMOS
The channel incorporates an absolute (TJ(SC)) and a dynamic (TJ(SW)) temperature sensor. Activation of either
sensor will cause the overheated channel to switch OFF to prevent destruction. Any protective switch OFF latches
the output until the temperature has reached an acceptable value. To ensure the lamps to be turned ON, the
DMOS restarts after cool down until t1. Figure 17 sketches the situation. The restart takes place for maximum t1
of the flasher in fault condition, around 130ms. If after this time, the device is still in restart conditions, the switch
is latched until the OUT voltage goes to HIGH again.
Data Sheet
15
Rev. 1.1, 2014-11-24
BTS6110-1SJA
Diagnostic Functions
Latch Reset: Selector
OFF -> ON
t1
VOUT
t
IOUT
LOAD CURRENT LIMITATION PHASE
LATCH
Normal Operation
IL(SC)
I L(NOM)
t
T DMOS
TJ(SC)
ΔTJ(SC)
ΔTJ(SW)
ΔTJ(SW)
TA
t
Intellilatch.vsd
Figure 17
Overload Protection
8
Diagnostic Functions
For diagnosis purpose, the BTS6110-1SJA measures the load current.
8.1
Load Current Measurement
The BTS6110-1SJA integrates a sense signal called IIS. As long as no “hard” failure mode occurs (current
limitation / overtemperature / excessive dynamic temperature increase) a proportional signal to the load current
(ratio kILIS = IL / IIS) is measured. To reduce current consumption, the diagnosis is only realized periodically. Refer
to the Figure 11. The complete sense circuit and diagnostic mechanism is described on Figure 18. In the case
VIS < VREF, the device raises an internal fault signal, to double the flashing frequency. Just before the switch ON
event, the device measures the supply voltage VS, via a voltage divider.
VS
+
+
-
0 if VIS > VREF
1 if VIS < VREF
RIS
-
OUT
S ens e s c hematic s ingle.v s d
Figure 18
Data Sheet
Diagnostic Block Diagram
16
Rev. 1.1, 2014-11-24
BTS6110-1SJA
Diagnostic Functions
8.2
Under load Current
Figure 19 shows the load current Idf_L considered as a function of the load current in the power DMOS. The blue
curve represents the typical current threshold, assuming ideal device. The red curves show the accuracy the
device provide accross full temperature range, at a defined current 1).
Idf_L
Idf_L9
Idf_L16
9
Figure 19
16
VS
Underload_new.vsd
Current Sense for Nominal Load
1) Only Idf_L9 and Idf_L16 are tested in production. The red curves between these points are specified by design.
Data Sheet
17
Rev. 1.1, 2014-11-24
BTS6110-1SJA
Electrical Characteristics
9
Electrical Characteristics
9.1
Electrical Characteristics Power Stage
Table 6
Electrical Characteristics: Power Stage
VS = 9 V to 16 V, TJ = -40 °C to +150 °C (unless otherwise specified).
Typical values are given at VS = 13.5 V, TJ = 25 °C
Parameter
ON-state resistance per
channel
Symbol
RDS(ON)_150
Values
Min.
Typ.
Max.
–
–
200
Unit
Note /
Test Condition
Number
mΩ
RL = 6 Ω
VCAP = VCHI
TJ = 150 °C
P_9.1.1
See Figure 8
ON-state resistance per
channel
RDS(ON)_25
–
80
–
mΩ
1)
Drain to source clamping
voltage
VDS(AZ) = [VS - VOUT]
VDS(AZ)
65
70
75
V
IDS = 2 mA
P_9.1.3
Output Leakage resistor
RRAIN
dV/dtON
0.04
0.4
1
kΩ
1)
P_9.1.11
0.1
0.25
0.5
V/µs
RL = 6 Ω
VS = 13.5 V
P_9.1.5
-dV/dtOFF
0.1
0.25
0.5
V/µs
See Figure 9
P_9.1.6
Turn-ON time to VOUT = 10 to tRISE
90% VS
–
70 1)
–
µs
P_9.1.7
Turn-OFF time to VOUT = 90 to tFALL
10% VS
–
70 1)
–
µs
P_9.1.8
Switch ON energy
EON
–
450
–
µJ
Switch OFF energy
EOFF
–
470
–
µJ
Slew rate
30% to 70% VS
Slew rate
70% to 30% VS
1)
TJ = 25 °C
RL = 6 Ω
VOUT = 90% VS
VS = 16 V
1)
RL = 6 Ω
VOUT = 10% VS
VS = 16 V
P_9.1.2
P_9.1.9
P_9.1.10
1) Not subject to production test, specified by design
Data Sheet
18
Rev. 1.1, 2014-11-24
BTS6110-1SJA
Electrical Characteristics
9.2
Electrical Characteristics CAP pin
Table 7
Electrical Characteristics: CAP pin
VS = 9 V to 16 V, TJ = -40 °C to +150 °C (unless otherwise specified).
Typical values are given at VS = 13.5 V, TJ = 25 °C
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note /
Test Condition
3
4.5
10
mA
Number
P_9.2.1
Load Current
Initialization Load current
IINIT
See Figure 14
VS = 9 V
Charging current
76.4
ICLOAD
µA
1)
See Figure 14
P_9.2.2
VCAP = 5.37 V
Discharging current
-74.4
ICUNLOAD
µA
1)
See Figure 14
P_9.2.3
VCAP = 5.37 V
Load current matching
ICRATIO =
|ICUNLOAD | /
ICLOAD
0.97
–
1)
See Figure 14
P_9.2.4
VCHI
VCLO
VCDIAG
6.4
V
1)
See Figure 14
P_9.2.5
V
1)
See Figure 14
P_9.2.6
5.37
V
1)
See Figure 14
P_9.2.7
2.4
V
1)
See Figure 14
P_9.2.8
Voltage Threshold
CAP voltage High threshold
CAP voltage Low threshold
CAP voltage diagnostic
threshold
CAP voltage threshold
Matching
VOSC =
VCHI - VCLO
RLOAD =
VOSC /
ICLOAD
RUNLOAD =
VOSC /
ICUNLOAD
RCAP =
RUNLOAD +
RLOAD
RCAP_USAGE
4
–
32
–
kΩ
1)
See Figure 14
P_9.2.10
–
31.6
–
kΩ
1)
See Figure 14
P_9.2.11
58
63.6
75
kΩ
58
63.6
70.3
kΩ
1) 2)
TJ = -20°C to 85°C P_9.2.19
RCAP_AMB
58
63.6
69.2
kΩ
1) 2)
TJ = +25°C
Duty Cycle
d
45
50
55
%
–
P_9.2.14
Double frequency factor
df = T2FAIL / 0.40
0.45
0.50
–
–
P_9.2.18
Initialisation Time
T4
tINIT
tSCAN
30
–
ms
– 1)2) VS = 9V
Flasher duty cycle
Device dependency
Flasher duty cycle
Device dependency
Flasher duty cycle
Device dependency
Flasher duty cycle
Device dependency
Flasher duty cycle
Device dependency
P_9.2.17
P_9.2.20
Time Generator
Impedance sensing Time
–
–
25
–
ms
–
1)2)
P_9.2.13
P_9.2.16
1) Not subject to production test, specified by design
2) With a CEXT of 10 µF
Data Sheet
19
Rev. 1.1, 2014-11-24
BTS6110-1SJA
Electrical Characteristics
9.3
Electrical Characteristics for the Protection Functions
Table 8
Electrical Characteristics: Protection
VS = 9 V to 16 V, TJ = -40 °C to +150 °C (unless otherwise specified).
Typical values are given at VS = 13.5 V, TJ = 25 °C
Parameter
Symbol
Values
Unit
Note /
Test Condition
Number
Min.
Typ.
Max.
VDS(REV)
200
600
700
mV
RL = 6 Ω
TJ = 150 °C
See Figure 16
P_9.3.1
IL(SC)
∆TJ(SW)
20
27
36
A
1)
P_9.3.2
–
80
–
K
TJ(SC)
150
1702)
2002)
°C
See Figure 17
P_9.3.3
–
30
–
K
2)
P_9.3.4
Reverse Polarity
Drain source diode voltage
during reverse polarity
Overload Condition
Load current limitation
Dynamic temperature
increase while switching
Thermal shutdown
temperature
Thermal shutdown hysteresis ∆TJ(SC)
VDS = 5 V
2)
See Figure 17
See Figure 17
P_9.3.5
1) Test at TJ = -40°C only
2) Not subject to production test, specified by design.
Data Sheet
20
Rev. 1.1, 2014-11-24
BTS6110-1SJA
Electrical Characteristics
9.4
Electrical Characteristics Diagnostic Function
Table 9
Electrical Characteristics: Diagnostics
VS = 9 V to 16 V, TJ = -40 °C to +150 °C (unless otherwise specified).
Typical values are given at VS = 13.5 V, TJ = 25 °C
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note /
Test Condition
0.782
0.924
1.067
A
Number
P_9.4.1
Load Current Underload Threshold
Load current threshold
Low battery operation
Idf_L9
Load current threshold
High battery operation
Idf_L16
Data Sheet
VS at 9 V step
See Figure 19
1.074
1.269
1.464
A
VS at 16 V step
P_9.4.2
See Figure 19
21
Rev. 1.1, 2014-11-24
BTS6110-1SJA
Package Outlines
10
Package Outlines
B
0.1
SEATING PLANE
2)
0.41+0.1
-0.06
0.2
8
5
1
4
5 -0.2 1)
M
0.64 ±0.25
6 ±0.2
A B 8x
C
0.19 +0.06
8° MAX.
1.27
4 -0.21)
1.75 MAX.
0.175 ±0.07
(1.45)
0.35 x 45°
0.2
M
C 8x
A
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Lead width can be 0.61 max. in dambar area
PG-DSO-8-16, -24, -25, -28, -31, -33, -36, -44, -49-PO V06
Figure 20
PG-DSO-8-49 (Plastic Dual Small Outline Package) (RoHS-Compliant)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant. For the
soldering of this device the appropriate temperature profile as described in J-STD-020 is to be used.
Table 10
Value
Package Classification
Purpose
MSL3
JEDEC humidity category acc. J-STD-020-D
260°C
JEDEC classification temperature acc. J-STD-020-D
Data Sheet
22
Rev. 1.1, 2014-11-24
BTS6110-1SJA
Revision History
11
Revision History
Version
Date
Changes
1.1
2014-11-24
Chapter 3 - Changed position of the Notes
Chapter 5.3 - Removed the hint for exposed pad packages in footnote of
table 5
Chapter 6.3 - Minor text change and update of Figure 10
Chatper 6.4 - Minor text change and update of Figure 11
Chatper 6.5 - Typo in text and update of Figure 12 and 13 (typo and
headline)
Chapter 7.3.2 - Typo in text corrected
Chapter 8.2 - Update of Figure 19
Chapter 9.2 - P_9.2.2 and P_9.2.3 changed test condition from VCAP VOUT = 5.37 V to VCAP = 5.37 V
Chapter 10 - Updated package drawing Figure 20
1.0
2014-02-27
Creation of the Document
Data Sheet
23
Rev. 1.1, 2014-11-24
Edition 2014-11-24
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2014 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
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characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
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