AN-1269 APPLICATION NOTE One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Designing an Inverting Power Supply Using the ADP2441/ADP2442 Synchronous Step-Down DC-to-DC Regulators by Kevin Tompsett and Ricky Yang INTRODUCTION Applications such as bipolar amplifiers, optical modules, CCD bias, and OLED displays usually require a negative output voltage from a positive input voltage. Designers of power management systems need versatile switching controllers and regulators that allow them to solve these power management challenges. The ADP2441/ADP2442 switching regulators from Analog Devices, Inc., provide synchronous buck functionality. This ranges from a 36 V input voltage down to 0.6 V output voltage at up to 1 A with a switching frequency range from 300 kHz to 1 MHz. Although targeted for synchronous step-down applications, the versatility of the ADP2441/ADP2442 allows these parts to realize an inverting buck boost topology, which can generate a negative output voltage from a positive input voltage, without additional cost, component count, or solution size. These parts utilize synchronous topology, which gives higher efficiency at a full load and lower noise at a light load operation than an asynchronous part. If higher efficiency at a low load is desired, the ADP2441 has a pulse skip mode (PSM). The ADP2442 can operate in forced constant current mode (CCM) for lower noise at low load or with PSM enabled. This application note describes how to implement the ADP2441/ADP2442 in a synchronous inverting buck boost topology to generate negative output voltages from positive input power supplies. In addition, some design challenges and possible solutions are addressed. For a faster design time, the ADIsimPower design tool can be used. This tool uses far more sophisticated design equations and methods to create a robust design that meets the requirements under all conditions almost instantaneously. It is available for download via the ADIsimPower product page or directly via ADP244x Inverting Buck Boost Designer. Rev. 0 | Page 1 of 8 AN-1269 Application Note TABLE OF CONTENTS Introduction ...................................................................................... 1 Input Capacitor Selection .................................................................5 Revision History ............................................................................... 2 Compensation Selection ...................................................................6 Buck Boost Topology Basics ........................................................... 3 Enable Signal Level Shifting .............................................................6 Implementation with the ADP2441/ADP2442.............................. 3 Reduce VOUT Over Shoot Before Start Up ......................................7 Output Voltage Setting ..................................................................... 4 Conclusion..........................................................................................8 Inductor Selection ............................................................................ 4 References ...........................................................................................8 Ramp Compensation ....................................................................... 4 Related Links ......................................................................................8 Output Capacitor Selection ............................................................. 5 REVISION HISTORY 7/14—Revision 0: Initial Version Rev. 0 | Page 2 of 8 Application Note AN-1269 BUCK BOOST TOPOLOGY BASICS IMPLEMENTATION WITH THE ADP2441/ADP2442 The simplified buck boost topology is shown in Figure 1. The topology consists of an inductor, two power switches operating out of phase from one another, and input/output capacitors. To implement the buck boost topology inverting power supply application by using the ADP2441/ADP2442 synchronous buck regulator, take into consideration some design restrictions as listed in Table 1. Figure 2 and Figure 3 show the current flow path during the on time and off time, respectively. During the on time, Switch S1 is on, S2 is off, and the current is flowing from the input capacitor, charging the inductor while the output capacitor provides energy to the load. During off time, Switch S1 is off, Switch S2 is on, and the current flows from the inductor to the load while charging the output capacitor. Note that the current flows from ground to VOUT, which results in negative output voltage. S2 RLOAD 11888-001 COUT Figure 1. Buck Boost Topology S2 COUT 11888-002 Figure 2. Current Flow Path During On Time S1 L CVCC VOUT CIN1 COUT RLOAD 11888-003 CIN VIN S2 RF2 The steady state conversion ratio can be written per Equation 1 by applying the principles of inductor voltage-second balance and capacitor charge balance on the topology. The dc inductor current value, IL, in CCM is specified in Equation 2, and the inductor ripple current, ∆IL, is shown in Equation 3. IL = I OUT 1− D −V × (1 − D ) ∆I L = OUT L × f SW FB RC1 CC1 Figure 3. Current Flow Path During Off Time VOUT −D = VIN 1− D RF1 (1) (2) (3) Rev. 0 | Page 3 of 8 VIN COMP CC2 EN CBST VIN ADP2441/ ADP2442 SW CC L1 COUT1 PGND –VOUT CVCC 2 VCC D1 COUT2 J2 H RFREQ L CSS Figure 4. Inverting Buck Boost Topology Implemented with the ADP2441/ADP2442 11888-004 VIN ADP2441/ ADP2442 4.5 V 20 V 1.2 A/1.2 A To convert the synchronous buck regulator into the buck boost topology, the inductor and output capacitor are connected similar to the buck topology. Note that the ground and the output voltage points are reversed as shown in Figure 4. RLOAD BST L CIN VOUT SYNC/ MODE/ SS/TRK S1 VCC VIN > < < FREQ L CIN VOUT Device Parameters VUVLO VMAX IOCP The minimum input voltage of the buck boost circuit must be higher than the UVLO voltage of the ADP2441/ADP2442, which has the typical value of 4.5 V to get the regulator to work. The sum of the maximum input voltage and the absolute value of the output voltage must be lower than the maximum operation input voltage of the regulators, VMAX, which has the typical value of 20 V. In addition, make sure the inductor peak current is smaller than the OCP trigger point of the regulator with accommodation for inductance tolerance. AGND S1 Voltage and Current VIN_MIN VIN_MAX + |VOUT| IL_PEAK (IL_peak not = IOUT) PGOOD VIN Table 1. Design Restrictions AN-1269 Application Note OUTPUT VOLTAGE SETTING The output voltage is set by an external resistive divider. The resistor values are calculated using RTOP = RBOTTOM × VOUT − 0.6 (4) 0.6 To limit the output voltage accuracy degradation due to the FB bias current (0.1 µA maximum) to less than 0.5% (maximum), ensure that RBOTTOM < 30 kΩ. over a wider range of duty cycle than could be achieved with the old style fixed ramp compensation that many chips use. To choose an inductor that will be current-mode stable first, choose an inductor using Equation 5. Then check that Qn calculated using Equation 8 is between 0.2 and 0.9 at both minimum and maximum VIN. Equation 8 is based on Ridley’s work in his An Accurate and Practical Small-Signal Model for Current-Mode Control paper (see the References section). Qn = 1/(π × (0.5 − D + 0.33 × fSW × L/(D × VIN)) (8) Table 2 lists the recommended resistor divider for various output voltages. where: fSW is the switching frequency. Table 2. Resistor Divider for Difference Output Voltage The peak inductor current is calculated by adding the dc component and half of the peak-to-peak inductor ripple current. RTOP ± 1% (kΩ) 10 20 47.5 10 22 28 35.7 RBOTTOM ± 1% (kΩ) 10 10 15 2.21 3 1.47 1.5 I PEAK = I AVG + The inductor value is determined by the operating frequency, input voltage, and inductor ripple current. Using a smaller inductance leads to a faster transient response, but degrades efficiency due to a larger inductor ripple current. Using a larger inductance value leads to a smaller ripple current and better efficiency, but results in a slower transient response. Taking into account this maximum peak inductor current, the application space of the ADP2441/ADP2442 in the inverting buck boost topology for common input voltages at 600 kHz switching frequency is shown in Figure 5 with the assumption that the peak-to-peak inductor ripple current is 40% of the inductor average current. 1.4 MAXIMUM OUTPUT CURRENT (A) As a guideline, the inductor ripple current (∆IL) is typically set to 30% of the maximum inductor average current, IAVG. The inductor value is calculated using the following equation: (5) where: VIN is the input voltage. D is the duty cycle: D= VOUT VOUT + VIN I AVG 1.2 VIN = 5V (ADP2441/ADP2442) VIN = 12V (ADP2441/ADP2442) VIN = 15V (ADP2441/ADP2442) 1.0 0.8 0.6 0.4 0.2 (6) 0 –30 KRP is the chosen current ripple percentage. A good rule of thumb is around 30%. IAVG is the average inductor current: I = OUT 1− D (9) The peak inductor current is also the peak current in the internal power switch, which is the sense element used to determine whether to induce current limit. To avoid premature current limit, the peak inductor current should not exceed the OCP threshold current, IOCP, of the devices. INDUCTOR SELECTION VIN × D L= K RP × I AVG × f SW I AVG × K RP 2 –25 –20 –15 –10 OUTPUT VOLTAGE (V) –5 0 11888-005 VOUT (V) −1.2 −1.8 −2.5 −3.3 −5 −12 −15 Figure 5. Application Space for Common Input Voltage at fSW = 600 kHz (7) fSW is the switching frequency. RAMP COMPENSATION The saturation current of the inductor must be larger than the peak inductor current. For ferrite core inductors with a steep saturation characteristic, the saturation current rating of the inductor should be higher than the current limit threshold for the IC. This prevents the inductor from saturating during normal operation. As with all current mode converters, the ADP2441/ADP2442 in an inverting buck boost topology require ramp compensation to assure current mode stability. The ADP2441/ADP2442 use an innovative adaptive ramp scheme that is dependent on duty cycle. This results in an ideal ramp compensation amplitude Rev. 0 | Page 4 of 8 Application Note AN-1269 OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION The output voltage of the inverting buck boost tends to be noisier than a buck converter. This is because unlike a buck converter, the output current is discontinuous in the inverting buck boost topology. The fast rise and fall times of Switch S2 result in noise spikes on the output voltage as the current in S2 is ramped up quickly from 0 to IL and back to 0. This makes it very important to use low ESR, MLCC capacitors and good layout techniques to reduce parasitic inductance. The input current is also discontinuous in the inverting buck boost topology. Therefore, the fast rise and fall times of Switch S1 result in noise spikes on the input rail as the current in S1 is ramped up quickly from 0 to IL and back to 0. This makes it very important to use low ESR, MLCC capacitors, and good layout techniques to reduce parasitic inductance. Equation 10 gives an estimated value of the minimum capacitance required to keep the output voltage ripple within an allowable range. (10) where: ∆VRIPPLE is the allowable output ripple voltage. ESR is the total equivalent series resistance of the output capacitors. IPEAK is the inductor peak current. (12) where: IAVG is the average inductor current. ESRC IN is the equivalent series resistance of the input capacitors. To achieve as low output ripple voltage as possible, MLCC capacitors that have very low ESR values are recommended. The rms current rating of the selected output capacitors should be larger than the values calculated using Equation 11. I RMS _ C OUT = (11) At least one 10 µF ceramic capacitor is recommended; place it as close to PVIN pin as possible. The rms current of the selected input capacitor should be greater than the value calculated in Equation 13. 2 D 2 × I OUT 2 ∆I 2 I RMS _ C IN = I OUT + L × D + 12 1− D (13) Although the majority of the capacitance on the input voltage rail is referenced to system ground, an additional input decoupling capacitor placed from the input voltage to the GND pin of ADP2441/ADP2442 can reduce the output voltage ripple and improve the transient response as shown in Figure 6. VIN CVCC RC1 CC1 VIN FB COMP CC2 EN BST RF1 CBST VIN ADP2441/ ADP2442 SW CC L1 COUT1 PGND –VOUT SYNC/ MODE/ SS/TRK RF2 VCC CIN1 AGND CVCC 2 VCC D1 COUT2 J2 H RFREQ L CSS Figure 6. Inverting Buck Boost Topology with Input Decoupling Capacitor from VIN to GND Pin Rev. 0 | Page 5 of 8 11888-006 2 2 I OUT × D × (1 − D ) + ∆I L × (1 − D ) + I 2 × D OUT 12 1− D I AVG × D f SW × (0.05 × VIN − I PEAK × ESRC IN ) FREQ f SW I OUT × D × ( ∆VRIPPLE − I PEAK × ESR ) C IN = PGOOD COUT ≈ Equation 12 calculates the minimum input capacitance assuming energy depletion of the input capacitor during on time is no more than 5% of the input voltage. AN-1269 Application Note Use the following design guidelines to calculate the values of the compensation network components. COMPENSATION SELECTION The control-to-output transfer function of the power stage in buck boost topology can be written in the form: • Set the cross frequency, fC, between fP and 1/3 of fZ1 fC = s s 1 − 2 × π × f × 1 + 2π × f Z1 Z2 GVD (s) = K × s 1 + 2 ×π × fP • (14) RC = f C × VOUT (19) K × f P × g m × 0.6 where: gm is the transconductance of the internal error amplifier with a typical value of 250 µS. R is the load resistor. Ri is the current sense gain with a typical value of 0.49 V/A. • 2 (1 − D ) × R 2 ×π × L × D Place the compensation zero at 1/2 of the power stage pole, fP CC1 = The transfer function GVD(s) has one right-half-plane-zero (RHPZ), fZ1; one zero, fZ2; and one pole, fP. The values of the zero and pole are: • CC2 = (15) 1 1+ D fP = 2 × π × R × COUT (20) D×L (21) (1 − D )2 × R × RC ENABLE SIGNAL LEVEL SHIFTING (16) 2 × π × RESR × COUT 2 × R × CCOUT (1 + D ) × RC Place the compensation pole at the RHPZ fZ1 The ADP2441/ADP2442 have an EN pin to enable and disable the regulator. However, in the inverting buck boost application, the IC is referenced to the negative output voltage instead of the system ground. Once the chip is enabled, pulling the enable pin to ground will not turn the IC off because the voltage from the enable pin to AGND of the IC will be equal to VOUT. (17) where: RESR is the equivalent series resistance of the output capacitor. One of the possible solutions for this issue is to use NPN and PNP transistors and several resistors to level shift the enable level as shown in Figure 7. Note that the precision enable feature of the ADP2441/ADP2442 is lost when the level shifting circuit is used. If the enable function is not needed, simply connect the EN pin to the input voltage as shown in Figure 4. VIN CVCC RF1 RC1 CC1 FB COMP ADP2441/ ADP2442 VIN EN FREQ OFF PGOOD ON CC2 VIN SW CC L1 COUT1 PGND –VOUT CVCC 2 VCC D1 COUT2 J2 H RFREQ L CSS Figure 7. EN Level Shifting Circuit for Inverting Buck Boost Topology Rev. 0 | Page 6 of 8 11888-007 EN RF2 CBST BST CIN VCC AGND CIN1 VIN SYNC/ MODE/ SS/TRK fZ2 = (18) Calculate the RC value using the equation: where: R × (1 − D ) K= Ri × (1 + D ) f Z1 = f P × f Z1 Application Note AN-1269 This issue can be seen in all buck regulators when they are used to perform the inverting buck boost topology described herein and it is very hard to eliminate the issue completely. One solution is to put a Schottky diode on the output of the converter. This diode reduces the positive voltage somewhat and prevents any silicon diodes in the ADP2441/ADP2442 regulator or any load components from turning on and causing problems. Another solution is to reduce the resistance of the feedback resistor divider until the voltage drop across the resistor divider is lower than the forward voltage of the body diode of the low-side MOSFET. Then, the shutdown current flows through the resistor divider instead of the body diode as shown in Figure 10 and the positive voltage on the PGND pin can be reduced to an acceptable value. VOUT OVER SHOOT BEFORE STARTUP When using the synchronous buck regulator as an inverting buck boost topology, one common issue is that the output voltage starts off positive before the regulator is enabled as shown in Figure 8. T 500mV 0V 2 ADP2441/ADP2442 CH2 1.0V BW M2.00ms A CH2 –2.72V 11888-008 VIN VIN CIN L SW Figure 8. VOUT Ramps Up Before Startup RTOP ADP2441/ADP2442 VIN VIN CIN SW FB COUT RBOTTOM PGND VOUT 11888-010 This positive output voltage is caused by the shutdown current of the regulator and any other chips connected to the negative rail, flowing from the PGND pin of the IC through the body diode of the low-side MOSFET and back to the system ground as shown in Figure 9. The body diode of the low-side MOSFET is that which clamps the VOUT at the forward voltage of the body diode with a typical value of around 500 mV. Figure 10. Current Flows Through the Feedback Resistor Divider Figure 11 shows the result of reducing the resistance of the resistor divider. The positive VOUT voltage decreases from 500 mV to 180 mV. T L RTOP FB COUT 180mV PGND VOUT 11888-009 0V 2 RBOTTOM Because VOUT is connected to the PGND pin of the regulator which is actually the reference point for the internal circuits like UVLO, the positive voltage shown in the PGND pin decreases the UVLO threshold voltage. The regulator may fail to start up when the input voltage is very close to the UVLO threshold voltage of the regulator, which has a typical value of 4.0 V. CH2 1.0V BW M2.00ms A CH2 –2.72V 11888-011 Figure 9. Current Flows Through Body Diode of Low Side MOSFET Figure 11. Reduce VOUT Ramp Up by Decreasing the Resistance of the Feedback Resistor Divider The drawback of this solution is that the quiescent current of the system increases because the current flowing through the feedback resistor is higher. This increased quiescent current can reduce the efficiency at light loads quite a bit, though the actual power loss is quite small. Rev. 0 | Page 7 of 8 AN-1269 Application Note CONCLUSION REFERENCES The ADP2441/ADP2442 can be used successfully in the inverting buck boost topology resulting in a simple, inexpensive, and small solution for creating a negative rail. In addition to detailing all of the necessary design equations, this application note provides a simple EN level shifting circuit when the enable/disable functionality is needed. Also, the potential start-up issue inherent with the inverting buck boost topology is avoided with two simple solutions. R. B. Ridley. An Accurate and Practical Small-Signal Model for Current-Mode Control. Ridley Engineering Inc. 1999. By following the design equations and suggestions in this application note, the system designer can ensure a robust design that satisfies all their requirements. RELATED LINKS Resources ADP2441 ADP2442 AN-1083 AN-1168 ADP244x Inverting Buck Boost Designer Description Data Sheet, 36 V, 1 A, Synchronous Step-Down DC-to-DC Regulator Data Sheet, 36 V, 1 A, Synchronous Step-Down DC-to-DC Regulator with External Clock Synchronization Application Note, Designing an Inverting Buck Boost Using the ADP2300 and ADP2301 Switching Regulators Application Note, Designing an Inverting Power Supply Using the ADP2384/ADP2386 Synchronous Step-Down DC-to-DC Regulators ADIsimPower Design Tool ©2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. AN11888-0-7/14(0) Rev. 0 | Page 8 of 8