BTS5482SF Data Sheet (2.2 MB, EN)

SPOC - BTS5482SF
SPI Power Controller
For Advanced Front Light Control
Data Sheet
Rev. 1.0, 2013-06-05
Automotive Power
SPOC - BTS5482SF
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
2.1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Assignment SPOC - BTS5482SF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
4.1
4.2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5
5.1
5.2
5.3
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
14
15
6
6.1
6.2
6.3
6.4
6.5
6.6
Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output ON-State Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Stage Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inverse Current Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Driver Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
16
18
19
20
21
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inrush State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operative State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fault State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timers and nretry counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Undervoltage restarts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loss of Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loss of VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
25
31
31
32
34
34
34
34
34
35
8
8.1
8.2
8.3
8.4
8.5
Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnosis Word at SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Load Current Sense Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch Bypass Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Open Load in OFF-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
38
39
41
41
42
9
9.1
9.2
9.3
9.4
9.5
9.6
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Protocol 8 Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
45
46
47
48
50
51
10
Application Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Data Sheet
2
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
11
Package Outlines SPOC - BTS5482SF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
12
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Data Sheet
3
Rev. 1.0, 2013-06-05
For Advanced Front Light Control
SPI Power Controller
1
SPOC - BTS5482SF
Overview
Features
•
•
•
•
•
•
•
•
•
8 bit serial peripheral interface for control and diagnosis
Integrated control for two external smart power switches
3.3 V and 5 V compatible logic pins
Very low stand-by current
Enhanced electromagnetic compatibility (EMC) for bulbs as well as
LEDs with increased slew rate
Stable behavior at under voltage
Device ground independent from load ground
Green Product (RoHS-Compliant)
AEC Qualified
PG-DSO-36-43
Description
The SPOC - BTS5482SF is a four channel high-side smart power switch in PG-DSO-36-43 package providing
embedded protective functions. It is especially designed to control standard exterior lighting in automotive
applications. In order to use the same hardware, the device can be configured to bulb or LED mode for channel 2
and channel 3. As a result, both load types are optimized in terms of switching and diagnosis behavior.
It is specially designed to drive exterior lamps up to 65W, 27W, 10W and HIDL.
Product Summary
VS
VDD
VS(LD)
IS(STB)
RDS(ON,typ)
Operating Voltage Power Switch
Logic Supply Voltage
Supply Voltage for Load Dump Protection
Maximum Stand-By Current at 25 °C
Typical On-State Resistance at Tj = 25 °C
channel 0, 1
channel 2, 3
Maximum On-State Resistance at Tj = 150 °C
RDS(ON,max)
channel 0, 1
channel 2, 3
fSCLK(max)
SPI Access Frequency
4.5 … 28 V
3.0 … 5.5 V
40 V
4.5 µA
4 mΩ
15 mΩ
8.5 mΩ
28 mΩ
5 MHz
Type
Package
Marking
SPOC - BTS5482SF
PG-DSO-36-43
BTS5482SF
Data Sheet
4
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Overview
Configuration and status diagnosis are done via SPI. The SPI is daisy chain capable. The device provides a
current sense signal per channel that is multiplexed to the diagnosis pin IS. It can be enabled and disabled via SPI
commands. An over load and over temperature flag is provided in the SPI diagnosis word. A multiplexed switch
bypass monitor provides short-circuit to VS diagnosis. In OFF-state a current source can be switched to the output
of one selected channel in order to detect an open load.
The device provides an external driver capability for two external devices. For each external driver there are two
control outputs available: one output for controlling the input and one output for diagnosis enable input. The current
sense output of the external smart power drivers can be connected to the IS pin.
The SPOC - BTS5482SF provides a fail-safe feature via limp home input pin.
The power transistors are built by N-channel vertical power MOSFETs with charge pumps.
Protective Functions
•
•
•
•
•
•
•
•
•
Reverse battery protection with external components
ReversaveTM - Reverse battery protection by self turn-on of channels 0, 1, 2 and 3
Short circuit protection
Over load protection
Thermal shutdown with latch and dynamic temperature protection
Over current tripping
Over voltage protection
Loss of ground protection
Electrostatic discharge protection (ESD)
Diagnostic Functions
•
•
•
•
•
•
•
•
Multiplexed proportional load current sense signal (IS)
Enable function for current sense signal configurable via SPI
High accuracy of current sense signal at wide load current range
Current sense ratio (kILIS) configurable for LEDs or bulbs for channel 2 and 3
Very fast diagnosis in LED mode
Feedback on over temperature and over load via SPI
Multiplexed switch bypass monitor provides short circuit to VS detection
Integrated, in two steps programmable current source for open load in OFF-state detection
Application Specific Functions
•
•
Fail-safe activation via LHI pin
Control of two additional loads with external smart power switches
Applications
•
•
•
•
High-side power switch for 12 V grounded loads in automotive applications
Especially designed for standard exterior lighting like high beam, low beam, indicator, parking light and
equivalent LED modules.
Load type configuration via SPI (bulbs or LEDs) for optimized load control
Replaces electromechanical relays, fuses and discrete circuits
Data Sheet
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Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Block Diagram
2
Block Diagram
VS
VDD
power
supply
IN1
temperature
sensor
driver
logic
IN2
IN3
clamp for
inductive
load
gate control
&
charge pump
load current
sense
over current
protection
channel 0
IS
LHI
CS
ESD
protection
current sense multiplexer
limp home
control
SPI
OUT3
OUT2
OUT1
OUT0
EDO0
ESD
protection
EDD0
EDO1
EDD1
GND
Data Sheet
3
switch bypass
monitor
external driver
control
SI
Figure 1
2
LED mode
control
SCLK
SO
1
Overview _STD_EXT.emf
Block Diagram SPOC - BTS5482SF
6
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Block Diagram
2.1
Terms
Figure 2 shows all terms used in this data sheet.
VS
IS
VS
IDD
ISO
VDD
VDD
S0
I SI
VSO
SI
I CS
V SI
I L0
CS
V DS0
OUT0
ISCLK
VCS
VOUT0
SCLK
V SCLK
I L1
VDS 1
OUT1
ILHI
V OUT1
LHI
V LHI
I L2
VDS2
OUT2
VOUT2
IIN1
VDS 3
I L3
IN1
OUT3
IIN2
VIN 1
IIN3
VIN2
V OUT3
IN2
I EDO 0
IN3
EDO0
V IN3
EDD0
I IS
IS
EDO1
VIS
EDD1
I EDD0
I EDO 1
I EDD1
VEDO 0
VEDD0
VEDO 1
VEDD1
GND
IGND
Terms_STD _EXT .emf
Figure 2
Terms
In all tables of electrical characteristics is valid: Channel related symbols without channel number are valid for each
channel separately (e.g. VDS specification is valid for VDS0 … VDS3).
All SPI register bits are marked as follows: ADDR.PARAMETER (e.g. HWCR.CL). In SPI register description, the
values in bold letters (e.g. 0) are default values.
Data Sheet
7
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment SPOC - BTS5482SF
(top view )
VS
VS
OUT0
OUT0
OUT0
OUT0
OUT3
OUT3
VS
LHI
SO
SI
SCLK
CS
GND
IN1
IN2
IN3
Figure 3
Data Sheet
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13
24
14
23
15
22
16
21
17
20
18
19
VS
VS
OUT1
OUT1
OUT1
OUT1
OUT2
OUT2
VS
n.c.
EDO0
EDD0
EDO1
EDD1
GND
IS
n.c.
VDD
Pin Configuration PG-DSO-36-43
8
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Pin Configuration
3.2
Pin Definitions and Functions
Pin
Symbol
I/O
Function
1, 2, 9, 28, 35, 36 1)
VS
–
Positive power supply for high-side power switch
19
VDD
–
Logic supply (5 V)
15, 22
GND
–
Ground connection
Power Supply Pins
Parallel Input Pins (integrated pull-down, leave unused pins unconnected)
16
IN1
I
Input signal of channel 1 (high active)
17
IN2
I
Input signal of channel 2 (high active)
18
IN3
I
Input signal of channel 3 (high active)
OUT0
O
Protected high-side power output of channel 0
OUT1
O
Protected high-side power output of channel 1
OUT2
O
Protected high-side power output of channel 2
OUT3
O
Protected high-side power output of channel 3
Power Output Pins
3, 4, 5, 6 2)
31, 32, 33, 34
29, 30
7, 8
2)
2)
2)
SPI & Diagnosis Pins
14
CS
I
Chip select of SPI interface (low active); Integrated pull up
13
SCLK
I
Serial clock of SPI interface
12
SI
I
Serial input of SPI interface (high active)
11
SO
O
Serial output of SPI interface
21
IS
O
Current sense output signal
Limp Home Pin (integrated pull-down, pull-down resistor recommended)
10
LHI
I
Limp home activation signal (high active)
External Driver Pins (integrated pull-down, leave unused external driver pins unconnected)
26
EDO0
O
External driver output for activation of external driver 0
24
EDO1
O
External driver output for activation of external driver 1
25
EDD0
O
External driver diagnosis enable signal of external driver 0
23
EDD1
O
External driver diagnosis enable signal of external driver 1
n.c.
–
not connected, internally not bonded
Not connected Pins
20, 27
1) All VS pins have to be connected.
2) All outputs pins of each channel have to be connected.
Data Sheet
9
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Electrical Characteristics
4
Electrical Characteristics
4.1
Absolute Maximum Ratings
Absolute Maximum Ratings 1)
Tj = -40 to +150 °C; all voltages with respect to ground
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit Conditions
min.
max.
-0.3
28
V
–
-0.3
5.5
V
–
–
16
channel 0, 1
0
24
channel 2, 3
0
24
Supply Voltage
VS
VDD
-Vbat(rev)
4.1.1
Power supply voltage
4.1.2
Logic supply voltage
4.1.3
Reverse polarity voltage according Figure 31
4.1.4
Supply voltage for short circuit protection (single VS(SC)
pulse)
4.1.5
Supply voltage for load dump protection with
connected loads
VS(LD)
–
40
4.1.6
Current through ground pin
–
25
4.1.7
Current through VDD pin
IGND
IDD
-25
12
TjStart = 25 °C
t ≤ 2 min. 2)
V
RECU = 20 mΩ
l = 0 or 5 m 3)
RCable = 6 mΩ/m
LCable = 1 µH/m
RCable = 16 mΩ/m
LCable = 1 µH/m
V
RI = 2 Ω 4)
t = 400 ms
mA t ≤ 2 min.
mA t ≤ 2 min.
IL
EAS
–5)
IL(Htrip)
A
6)
mJ
7)
V
Power Stages
4.1.8
Load current
4.1.9
Maximum energy dissipation
single pulse
channel 0, 1
–
180
Tj(0) = 150 °C
IL(0) = 5 A
channel 2, 3
–
45
IL(0) = 2 A
tdelay(CL)
50
–
ms
IIS
-8
8
mA t ≤ 2 min.
VIN
IIN
-0.3
5.5
V
-0.75
-2.0
0.75
2.0
mA –
VCS
ICS
VSI
ISI
VSCLK
ISCLK
-0.3
VDD + 0.3 V
-2.0
2.0
-0.3
VDD + 0.3 V
-2.0
2.0
-0.3
VDD + 0.3 V
-2.0
2.0
4.1.10 Thermal latch restart time
Diagnosis Pin
4.1.11 Current through sense pin IS
Input Pins
4.1.12 Voltage at input pins
4.1.13 Current through input pins
–
t ≤ 2 min.
SPI Pins
4.1.14 Voltage at chip select pin
4.1.15 Current through chip select pin
4.1.16 Voltage at serial input pin
4.1.17 Current through serial input pin
4.1.18 Voltage at serial clock pin
4.1.19 Current through serial clock pin
Data Sheet
10
–
mA t ≤ 2 min.
–
mA t ≤ 2 min.
–
mA t ≤ 2 min.
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Electrical Characteristics
Absolute Maximum Ratings (cont’d)1)
Tj = -40 to +150 °C; all voltages with respect to ground
(unless otherwise specified)
Pos.
Parameter
Symbol
4.1.20 Voltage at serial output pin
4.1.21 Current through serial output pin
Limit Values
Unit Conditions
min.
max.
VSO
ISO
-0.3
VDD + 0.3 V
-2.0
2.0
mA t ≤ 2 min.
VLHI
ILHI
-0.3
5.5
V
-0.75
-2.0
0.75
2.0
mA –
-0.3
VDD + 0.3 V
-1.0
1.0
-0.3
VDD + 0.3 V
-1.0
1.0
mA t ≤ 2 min.
-40
150
°C
–
–
60
K
–
-55
150
°C
–
kV
HBM 8)
–
–
–
Limp Home Pin
4.1.22 Voltage at limp home input pin
4.1.23 Current through limp home input pin
–
t ≤ 2 min.
External Driver Pins
VEDO
4.1.25 Current through external driver output
IEDO
4.1.26 Voltage at external driver diagnosis enable
VEDD
4.1.27 Current through external driver diagnosis enable IEDD
4.1.24 Voltage at external driver output
–
mA t ≤ 2 min.
–
Temperatures
Tj
∆Tj
Tstg
4.1.28 Junction temperature
4.1.29 Dynamic temperature increase while switching
4.1.30 Storage temperature
ESD Susceptibility
VESD
4.1.31 ESD susceptibility HBM
OUT pins vs. VS
other pins incl. OUT vs. GND
-4
-2
4
2
1) Not subject to production test, specified by design.
2) Device is mounted on an FR4 2s2p board according to Jedec JESD51-2,-5,-7 at natural convection; The product
(chip+package) was simulated on a 76.4 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm Cu).
Where applicable, a thermal via array under the package contacted the first inner copper layer.
3) In accordance to AEC Q100-012 and AEC Q101-006.
4) RI is the internal resistance of the load dump pulse generator.
5) No protection mechanism available. Inverse current needs to be limited by external circuitry to prevent overheating.
6) Over current protection is an integrated protection function.
7) Pulse shape represents inductive switch off: ID(t) = ID(0) × (1 - t / tpulse); 0 < t < tpulse
8) ESD resistivity, HBM according to ANSI/ESDA/JEDEC JS-001-2010
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Data Sheet
11
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Electrical Characteristics
4.2
Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.
Pos.
Parameter
4.2.1
Junction to Soldering Point
4.2.2
Junction to Ambient 1)
Symbol
1)
Limit Values
Unit
Conditions
Min.
Typ.
Max.
RthJSP
–
–
20
K/W
measured to pin 1,
2, 9, 28, 35, 36
RthJA
–
35
–
K/W
2)
1) Not subject to production test, specified by design.
2) Specified RthJA values is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The product
(chip+package) was simulated on a 76.4 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm Cu).
Where applicable, a thermal via array under the package contacted the first inner copper layer.
Data Sheet
12
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Power Supply
5
Power Supply
The SPOC - BTS5482SF is supplied by two supply voltages VS and VDD. The VS supply line is used by the power
switches. The VDD supply line is used by the SPI related circuitry and for driving the SO line. A capacitor between
pins VDD and GND is recommended as shown in Figure 31.
There is a power-on reset function implemented for the VDD logic power supply. After start-up of the logic power
supply, all SPI registers are reset to their default values. The SPI interface including daisy chain function is active
as soon as VDD is provided in the specified range independent of VS. First SPI data are the output register values
for internal channels with TER = 1.
Specified parameters are valid for the supply voltage range according VS(nor) or otherwise specified. For the
extended supply voltage range according VS(ext) device functionality (switching, diagnosis and protection functions)
are still given, parameter deviations are possible.
5.1
Power Supply Modes
The following table shows all possible power supply modes for VS, VDD and the pin LHI.
On via Limp Home Normal
operation
INx
mode
without SPI
Limp Home
mode with
SPI 1)
Power Supply Modes
Off
Off
SPI
on
Reset Off
VS
VDD
0V
0V
0V
0V
13.5 V 13.5 V 13.5 V
13.5 V
13.5 V
0V
0V
5V
5V
0V
0V
0V
5V
5V
LHI
0V
5V
0V
5V
0V
0V
5V
0V
5V
✓
✓ 2)
✓
Power stage, protection
–
–
–
–
–
✓
Limp home
–
–
–
–
–
–
✓
✓
SPI (logic)
–
–
✓
✓
reset
reset
reset
Stand-by current
–
–
–
–
✓
✓4)
–
Idle current
–
–
–
–
–
–
–
Diagnosis
–
–
–
–
–
–
–
1)
2)
3)
4)
5)
6)
7)
2)
2)
–
✓
✓5)
✓6)
✓
reset3)
–
–
✓7)
SPI read only
Channel 1, 2 and/or 3 activated according to the state of INx
SPI reset only with applied VS voltage
When INx = 0 V
When DCR.MUX = 111b and INx = 0 V
When all channels are in OFF-state and DCR.MUX ≠ 111b
Current sense disabled in limp home mode
5.1.1
Stand-by Mode and Device Wake-up Mechanisms
Stand-by mode is entered as soon as the current sense multiplexer (DCR.MUX) is in default (stand-by) position
and all input pins are not set. All error latches are cleared automatically in stand-by mode. As soon as stand-by
mode is entered, register HWCR.STB is set. To wake-up the device, the current sense multiplexer (DCR.MUX) is
programmed different to default (stand-by) position. The power-on wake up time tWU(PO) has to be considered.
Idle mode parameters are valid, when all channels are switched off, whereas the current sense multiplexer is not
in default position, and VDD supply is available.
Note: A transition from operation to stand-by mode does not reset the SPI registers. So, if VDD is present and SPI
is programmed, a changing to MUX = 111b does not reset the SPI registers. An activation of the channels via
the input pin INx will wake up the device with the former SPI register settings.
Data Sheet
13
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Power Supply
Activating one of the outputs via the input pins (INx = high) will wake-up the device out of stand-by mode. The
power stages are working without VDD supply according to the table in Chapter 5.1. The output turn-on time will
be extended by the stand-by channel wake up time tWU(STCH) as long as no other channel is active. If one channel
is active already before, channel turn-on times tON (6.6.12) can be considered.
Note: In the operation with VDD = 0 V and INx = high a switching off of all input signals will turn the device in standby mode. In stand-by mode the error latches are cleared.
Limp home (LHI = high) applied for a time longer than tLH(ac) will wake-up the device out of stand-by mode after
the power-on wake up time tWU(PO) and it is working without VDD supply. Channels 1, 2 and 3 can be activated via
the input pins INx. The error latches can be cleared by a low-high transition at the according input pin.
5.2
Reset
There are several reset triggers implemented in the device. They reset the SPI registers including the over
temperature latches to their default values. The power stages will switch off, if they are activated via the SPI
register OUTL.n. If the power stages are activated via the parallel input pins they are not affected by the reset
signals. The ERR-flags are cleared by those reset triggers. The over temperature protection and latches are
functional after a reset trigger.
Note: During a reset only the channels 1, 2 and 3 can be activated via the according input pins. The input assigned
mode is not available during a reset.
The first SPI transmission after any kind of reset contains at pin SO the read information from the standard
diagnosis, the transmission error bit TER is set.
Power-On Reset
The power-on reset is released, when VDD voltage level is higher than VDD(PO). The SPI interface can be accessed
after wake up time tWU(PO). If one of the parallel input pins INx or the LHI pin is high, the power-on reset is not
affecting the protection latches.
Reset Command
There is a reset command available to reset all register bits of the register bank and the diagnosis registers. As
soon as HWCR.RST = 1b, a reset, equivalent to power-on reset is executed. The SPI interface can be accessed
after transfer delay time tCS(td).
Limp Home Mode
The limp home mode will be activated as soon as the pin LHI is set to high for a time longer than tLH(ac). The SPI
write-registers are reset with applied VS voltage and the protection latches are cleared. The outputs OUT1 to OUT3
can be activated via the input pins also during activated limp home mode. The error latches can be cleared by a
low-high transition at the according input pin. For application example see Figure 31. The SPI interface is
operating normally, so the limp home register bit LHI as well as the error flags can be read, but any write command
will be ignored.
Data Sheet
14
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Power Supply
5.3
Electrical Characteristics
Electrical Characteristics Power Supply
Unless otherwise specified: VS = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C
typical values: VS = 13.5 V, VDD = 4.3 V, Tj = 25 °C
Pos. Parameter
Symbol
Limit Values
Unit Test Conditions
min.
typ.
max.
8
–
17
V
–
5.3.2 Extended supply voltage range for operation VS(ext)
power switch
4.51)
–
282)
V
Parameter
deviations possible
VS(UV)
5.3.4 Stand-by current for whole device with loads IS(STB)
–
3.7
–
V
5.3.1 Supply voltage range for normal operation
power switch
VS(nor)
5.3.3 Undervoltage shutdown
5.3.5 Idle current for whole device with loads, all
channels off
IS(idle)
5.3.6 Logic supply voltage
VDD
IDD
5.3.7 Logic supply current
5.3.8 Logic stand-by current
µA
–
–
–
–
4.5
28
–
14.5
–
mA
VDD = 0 V
VLHI = 0 V
2)
Tj = 25 °C
2)
Tj ≤ 85 °C
VDD = 5 V
DCR.MUX = 110
IDD(STB)
3.0
–
5.5
–
80
200
–
350
500
–
25
–
V
–
µA
3)
VLHI = 0 V
VDD = 5 V
VIS = 0 V
Chip in Idle
fSCLK = 0 Hz
VCS = 5 V
fSCLK = 5 MHz
VCS = 0 V
µA
VCS = VDD
fSCLK = 0 Hz
Chip in Stand-by
5.3.9 Operating current for whole device active
IGND
–
15
21
mA
fSCLK = 0 Hz
VLHI(L)
VLHI(H)
ILHI(L)
ILHI(H)
0
–
0.8
V
–
VDD(PO)
tWU(PO)
tWU(STCH)
tLH(ac)
LHI Input Characteristics
5.3.10 L-input level at LHI pin
5.3.11 H-input level at LHI pin
5.3.12 L-input current through LHI pin
5.3.13 H-input current through LHI pin
1.8
–
5.5
V
–
3
8
20
µA
2)
10
40
80
µA
VLHI = 5 V
–
–
2.4
V
–
–
–
200
µs
2)
–
–
200
µs
2)
5
–
200
µs
2)
VLHI = 0.6 V
Reset
5.3.14 Power-On reset threshold voltage
5.3.15 Power-On wake up time
5.3.16 Stand-by channel wake up time
5.3.17 Limp home acknowledgement time
1) Load current sense diagnosis is not available for VS < 6.0 V
2) Not subject to production test, specified by design.
3) Device in normal operation without any temperature or overcurrent latches set
Note: Characteristics show the deviation of parameter at the given supply voltage and junction temperature.
Data Sheet
15
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Power Stages
6
Power Stages
The high-side power stages are built by N-channel vertical power MOSFETs (DMOS) with charge pumps. There
are four channels implemented in the device.
6.1
Output ON-State Resistance
The on-state resistance RDS(ON) depends on the supply voltage VS as well as on the junction temperature Tj.
Figure 4 shows those dependencies. The behavior in reverse polarity mode is described in Section 7.6.
VS = 13.5 V
Tj = 25 °C
80
80
Channel 2,3 (bulb)
Channel 2,3 (LED)
Channel 0, 1 (bulb)
70
60
60
50
50
RDS(ON) [mΩ]
RDS(ON) [mΩ]
Channel 0,1 (bulb)
70
40
30
channel 2,3 (bulb)
channel 2,3 (LED)
40
30
20
20
10
10
0
0
-50
0
50
100
0
150
Figure 4
Typical On-State Resistance
6.2
Input Circuit
5
10
15
20
25
30
VS [V]
Tj [°C]
The outputs of the SPOC - BTS5482SF can be activated either via the SPI register OUTL.OUTn or via the
dedicated input pins. There are two different ways to use the input pins, the direct drive mode and the assigned
drive mode. The default setting is the direct drive mode. To activate the assigned drive mode the register bit
ICR.INCG needs to be set.
Additionally, there are two ways of using the input pins in combination with the OUTL register by programming the
ICR.COL parameter.
•
•
ICR.COL = 0b: A channel is switched on either by the according OUTL register bit or the input pin.
ICR.COL = 1b: A channel is switched on by the according OUTL register bit only, when the respective input
pin is high. In this configuration, a PWM signal can be applied to the input pin and the channel is activated by
the SPI register OUTL.
Data Sheet
16
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Power Stages
Figure 5 shows the complete input switch matrix.
OUT5
OUT4
OUT3
OUT2
OUT1
OUT0
OR
&
Gate Driver 0
OR
IN1
Gate Driver 1
&
OR
IN2
Gate Driver 2
&
IN3
OR
OR
Gate Driver 3
&
OR
&
OR
&
INCG
External Driver
Output 0
External Driver
Output 1
&
COL
InputMatrix_STD_EXT .emf
Figure 5
Input Switch Matrix
The current sink to ground ensures that the input signal is low in case of an open input pin. The zener diode
protects the input circuit against ESD pulses.
6.2.1
Input Direct Drive
This mode is the default after the device’s wake up and reset. The input pins activate the channels during normal
operation (with default setting of bit ICR.INCG), stand-by mode and limp home mode. Channel 0 and the external
drivers can be activated only via the SPI-bit OUTx.OUTn in direct drive mode. The inputs are linked directly to the
channels according to:
Table 1
Direct Drive Mode
Input Pin
Assigned channel, if ICR.INCG = 0b
IN1
Channel 1
IN2
Channel 2
IN3
Channel 3
Data Sheet
17
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Power Stages
6.2.2
Input Assigned Drive
To activate the assigned drive function the register bit ICR.INCG needs to be set. In this mode all output channels
can be activated via the input pins. Channel 2, 3 and the two external drivers are assigned to only one input pin.
The following mapping is used:
Table 2
Assigned Drive Mode
Input Pin
Assigned channel, if ICR.INCG = 1b
IN1
Channel 0
IN2
Channel 1
IN3
Channel 2, channel 3, external driver 0, external driver 1
6.3
Power Stage Output
The power stages are built to be used in high side configuration (Figure 6).
VS
VDS
Vbat
OUT
GND
VOUT
Output.emf
Figure 6
Power Stage Output
The power DMOS switches with a dedicated slope, which is optimized in terms of electromagnetic emission
(EME). Defined slew rates and edge shaping allow lowest EME during PWM operation at low switching losses.
6.3.1
Bulb and LED mode
Channel 2 and channel 3 can be configured in bulb and LED mode via the SPI registers HWCR.LEDn. During LED
mode following parameters are changed for an optimized functionality with LED loads: On-state resistance
RDS(ON), switching timings (tdelay(ON), tdelay(OFF), tON, tOFF), slew rates dV / dtON and dV / dtOFF, current protections
IL(trip) and current sense ratio kILIS.
Data Sheet
18
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Power Stages
6.3.2
Switching Resistive Loads
When switching resistive loads the following switching times and slew rates can be considered.
IN /
OUTx
tON
VOUT
tdelay (ON)
t
tOFF
tON(ris e)
tdelay(OFF)
tOFF (fall )
90% of V S
70% of V S
70%
dV /
dtON
30% of V S
dV /
dtOFF
30%
10% of V S
t
Figure 7
Switching a resistive Load
6.3.3
Switching Inductive Loads
SwitchOn.emf
When switching off inductive loads with high-side switches, the voltage VOUT drops below ground potential,
because the inductance intends to continue driving the current. To prevent the destruction of the device due to
high voltages, there is a voltage clamp mechanism implemented, which limits that negative output voltage to a
certain level (VDS(CL) (6.6.2)). See Figure 6 for details. The device provides SmartClamp functionality. To increase
the energy capability, the clamp voltage VDS(CL) increases with the junction temperature Tj and load current IL.
Please refer also to Section 7.7. When switching inductive loads, it has to be ensured that the clamp mechanism
of the device is not activated.
6.3.4
Switching high inrush loads
When switching loads with high inrush currents like e.g. high capacitive loads, it has to be ensured that in normal
operating range the maximum load current is below the current trip level of the device. If the current trip level is
touched, the device would operate under fault conditions that are considered as outside normal operating range.
In this case absolute maximum ratings are exceeded (see 4.1.8). Please refer to Section 4 and Section 7 for
further information.
6.4
Inverse Current Behavior
During inverse currents (VOUT > VS) the affected channel stays in ON- or in OFF-state. Furthermore, during applied
inverse currents no ERR-flag is set.
The functionality of unaffected channels is not influenced by inverse currents applied to other channels (except
effects due to junction temperature increase). Influences on the diagnostic function of unaffected channels are
possible only for the current sense ratio, please refer to ∆kILIS(IC) (8.5.3).
Note: No protection mechanism like temperature protection or current protection is active during applied inverse
currents. Inverse currents cause power losses inside the DMOS, which increase the overall device
temperature, which could lead to a switch off of the unaffected channels due to over temperature.
Data Sheet
19
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Power Stages
6.5
External Driver Control
Two external smart power drivers can be driven by the SPOC - BTS5482SF via the external driver control block.
For each external driver there are two control outputs available: one output for controlling the input (EDOx) and
one output for diagnosis enable input (EDDx). The current sense output of the external smart power drivers can
be connected to the IS pin. For details please refer to Figure 31.
The external driver outputs can be used only with applied VDD voltage. The external driver outputs are internally
pulled down. The external drivers can be activated via SPI-bits OUTH.OUT4 and OUTH.OUT5 or via the input pin
IN3 in assigned drive mode. The external drivers’ diagnostic enable signals can be activated via the SPI register
DCR.MUX. For being compliant to PROFET+ diagnostic functions, it is possible to configure pin EDD0 as DEN and
EDD1 as DSEL. Therefore, the bit OUTH.PRO+ needs to be set. The DSEL will be set in accordance to the
multiplexer setting DCR.MUX.
Table 3
PROFET+ Compliancy
MUX Setting
DCR.MUX
EDD0 used as DEN
EDD1 used as DSEL
100b
1
0
101b
1
1
Note: The usable duty cycle range and diagnostic timings for the external drivers depend on the external driver’s
characteristics.
Data Sheet
20
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Power Stages
6.6
Electrical Characteristics
Electrical Characteristics Power Stages
Unless otherwise specified: VS = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C
typical values: VS = 13.5 V, VDD = 4.3 V, Tj = 25 °C
Pos. Parameter
Symbol
Limit Values
Unit Test Conditions
min. typ. max.
Output Characteristics
RDS(ON)
6.6.1 On-state resistance
mΩ
–
8.5
IL = 7.5 A
1)
Tj = 25 °C
Tj = 150 °C
–
28
IL = 2.6 A
1)
Tj = 25 °C
Tj = 150 °C
–
100
IL = 0.6 A
1)
Tj = 25 °C
Tj = 150 °C
channel 0, 1
–
–
4
6
channel 2, 3
HWCR.LEDn = 0
–
–
15
21
HWCR.LEDn = 1
–
–
45
70
VDS(CL)
6.6.2 Output clamp
channel 0, 1
channel 2, 3
6.6.3 Output leakage current per channel in
stand-by
V
32
–
54
40
–
55
32
–
54
40
–
55
IL(OFFSTB)
µA
channel 0, 1
–
–
–
–
–
–
2
10
50
channel 2, 3
–
–
–
–
–
–
1
4
20
6.6.4 Output leakage current per channel in idle IL(OFFidle)
mode
channel 0, 1
channel 2, 3
Data Sheet
21
Tj = 25 °C
IL = 20 mA
1)
Tj = 150 °C
IL = 6 A
Tj = 25 °C
IL = 20 mA
1)
Tj = 150 °C
IL = 2 A
Tj = 25 °C
1)
Tj = 85 °C
1)
Tj = 105 °C
Tj = 25 °C
1)
Tj = 85 °C
1)
Tj = 105 °C
µA
–
–
–
–
–
–
60
80
530
–
–
–
–
–
–
45
50
230
OUTL.OUTn = 0
DCR.MUX = 111
OUTL.OUTn = 0
DCR.MUX ≠ 111
1)
1)
Tj = 85 °C
Tj = 105 °C
Tj = 150 °C
1)
Tj = 85 °C
1)
Tj = 105 °C
Tj = 150 °C
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Power Stages
Electrical Characteristics Power Stages (cont’d)
Unless otherwise specified: VS = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C
typical values: VS = 13.5 V, VDD = 4.3 V, Tj = 25 °C
Pos. Parameter
Symbol
6.6.5 Inverse current capability per channel
-IL(IC)
Limit Values
Unit Test Conditions
min. typ. max.
1)
A
No influences on
switching functionality of
unaffected channels, kILIS
influence according
∆kILIS(IC) (8.5.3)
channel 0, 1
6
–
–
channel 2, 3
2
–
–
0
–
0.8
V
–
1.8
–
5.5
V
–
6.6.8 L-input current
VIN(L)
VIN(H)
IIN(L)
3
8
20
µA
1)
6.6.9 H-input current
IIN(H)
10
40
80
µA
VIN = 5 V
Input Characteristics
6.6.6 L-input level
6.6.7 H-input level
Data Sheet
22
VIN = 0.6 V
DCR.MUX ≠ 111
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Power Stages
Electrical Characteristics Power Stages (cont’d)
Unless otherwise specified: VS = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C
typical values: VS = 13.5 V, VDD = 4.3 V, Tj = 25 °C
Pos. Parameter
Symbol
Limit Values
Unit Test Conditions
min. typ. max.
Timings
6.6.10 Turn-ON delay to 10% VS
tdelay(ON)
µs
1)
VS = 13.5 V
channel 0, 1
–
35
–
–
channel 2, 3
–
–
25
8
–
–
HWCR.LEDn = 0
HWCR.LEDn = 1
6.6.11 Turn-OFF delay to 90% VS
tdelay(OFF)
µs
1)
VS = 13.5 V
channel 0, 1
–
45
–
–
channel 2, 3
–
–
30
10
–
–
HWCR.LEDn = 0
HWCR.LEDn = 1
6.6.12 Turn-ON time to
90% VS including turn-ON delay
tON
µs
VS = 13.5 V
DCR.MUX ≠ 111
channel 0, 1
–
–
100
channel 2, 3
–
–
100
RL = 2.2 Ω
HWCR.LEDn = 0
RL = 6.8 Ω
–
6.6.13 Turn-OFF time to
10% VS including turn-OFF delay
–
50
tOFF
HWCR.LEDn = 1
µs
channel 0, 1
–
–
150
channel 2, 3
–
–
110
RL = 33 Ω
VS = 13.5 V
RL = 2.2 Ω
HWCR.LEDn = 0
RL = 6.8 Ω
–
6.6.14 Turn-ON rise time from 10% to
90% VS
–
50
tON(rise)
HWCR.LEDn = 1
µs
RL = 33 Ω
VS = 13.5 V
DCR.MUX ≠ 111
channel 0, 1
–
–
45
channel 2, 3
–
–
40
RL = 2.2 Ω
HWCR.LEDn = 0
RL = 6.8 Ω
–
6.6.15 Turn-OFF fall time from 90% to
10% VS
Data Sheet
–
11
tOFF(fall)
HWCR.LEDn = 1
RL = 33 Ω
µs
VS = 13.5 V
channel 0, 1
–
–
45
RL = 2.2 Ω
channel 2, 3
–
–
40
–
–
11
HWCR.LEDn = 0
RL = 6.8 Ω
HWCR.LEDn = 1
RL = 33 Ω
23
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Power Stages
Electrical Characteristics Power Stages (cont’d)
Unless otherwise specified: VS = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C
typical values: VS = 13.5 V, VDD = 4.3 V, Tj = 25 °C
Pos. Parameter
Symbol
6.6.16 Turn-ON/OFF matching
|tON tOFF|
Limit Values
Unit Test Conditions
min. typ. max.
µs
VS = 13.5 V
channel 0, 1
–
–
90
RL = 2.2 Ω
channel 2, 3
–
–
70
–
–
50
HWCR.LEDn = 0
RL = 6.8 Ω
HWCR.LEDn = 1
RL = 33 Ω
dV/ dtON
6.6.17 Turn-ON slew rate
30% to 70% VS
V/µs VS = 13.5 V
channel 0, 1
–
0.7
2.0
channel 2, 3
–
0.9
2.5
RL = 2.2 Ω
HWCR.LEDn = 0
RL = 6.8 Ω
–
2.5
6.0
-dV/
dtOFF
6.6.18 Turn-OFF slew rate
70% to 30% VS
HWCR.LEDn = 1
RL = 33 Ω
V/µs VS = 13.5 V
channel 0, 1
–
0.7
2.0
channel 2, 3
–
0.9
2.5
RL = 2.2 Ω
HWCR.LEDn = 0
RL = 6.8 Ω
–
2.5
6.0
HWCR.LEDn = 1
RL = 33 Ω
External Driver Control
6.6.19 L level external driver output voltage
VEDO(L)
VEDO(H)
–
0.4
V
VDD - –
0.4V
VDD
V
tEDO(en)
tEDO(dis)
VEDD(L)
–
–
4
µs
–
–
4
µs
0
–
0.4
V
6.6.24 H level external driver diagnosis enable
voltage
VEDD(H)
VDD - –
0.4V
VDD
V
6.6.25 External driver diagnosis enable enable
time
tEDD(en)
–
–
4
µs
6.6.26 External driver diagnosis enable disable
time
tEDD(dis)
–
–
4
µs
6.6.20 H level external driver output voltage
6.6.21 External driver output enable time
6.6.22 External driver output disable time
6.6.23 L level external driver diagnosis enable
voltage
0
IEDO = -0.5 mA
IEDO = 0.5 mA
VDD = 4.3 V
1)
CL = 20 pF
1)
CL = 20 pF
IEDD = -0.5 mA
IEDD = 0.5 mA
VDD = 4.3 V
1)
CL = 20 pF
1)
CL = 20 pF
1) Not subject to production test, specified by design.
Data Sheet
24
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Protection Functions
7
Protection Functions
SPOC - BTS5482SF provides embedded protective functions, which are designed to prevent IC destruction under
fault conditions described in this data sheet. Fault conditions are considered as “outside” normal operating range.
Protective functions are neither designed for continuous nor for repetitive operation. To provide high switching
capability and robustness, the device is managed by a state machine (Figure 8).
Legend:
OT ... Over Temperature E v ent
DT ... Dynamic Temperature E v ent
OC ... Over Current E v ent
Fault
(**)
(*) Inrush state with I L( L trip )
(**) ITC x bit and TimerInrush
will be cleared
HWCR. CL=1b or
OT /DT or
OC
LHI
HWCR .CL =1b & TimerInrush ex pired or
V S < V S(U V) (*) or
LHI & TimerInrus h ex pired
OT /DT or
OC with n re try or
OC at V D S(Vtri p )
Operative
I L(Ltrip) , no retries
(**)
TimerInrus h E xpired or
V S < VS (U V) (*)
TimerOn ex pired
Inrush
IL(Htrip) , n retry
S tartup
S tate_Diagram. emf
Figure 8
BTS5482SF state diagram
Each internal channel of BTS5482SF has its own state machine to manage the protection mechanisms. Device is
starting-up in Inrush state and depending on different conditions it will change to Operative state (normal condition)
or to Fault state (overload condition).
7.1
Inrush State
After start-up the device enters Inrush state providing high current trip level IL(Htrip) (7.10.1) with a limited number
of retries (see Figure 11). After the respective channel is in ON-state for t > tdelay(Ltrip) (7.10.2), the channel changes
to Operative state (see Chapter 7.2). In case the channels are driven in PWM (pulse width modulation) the ONtime is cumulated until tdelay(Ltrip) is reached. For a detailed description of the timers see Chapter 7.4. If a latch off
condition occurs, the device will change to Fault state (see Chapter 7.3).
7.1.1
Over Current Protection in Inrush State
The maximum load current IL is switched off in case of exceeding the over current trip level IL(Htrip) by the device
itself. Depending on the total short circuit impedance higher current over shoots may occur. A limited auto-restart
function is implemented. Please refer to following figures for details.
Data Sheet
25
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Protection Functions
Inrush
Fault
Operative
IN /
OUTx
VDS
normal
operation
over current
VDS (Vtrip )
I L(Htrip)
t
Latch off due
to nret ry(LV )
Switch off by over
current detection
IL
t
n = nretry
n=1
T
Tj(SC ) j
Tj (SC) -∆Tj
t
Tj (s tart)
t
IIS
over load removed
t
*
ERR
t
CL = 1
* ERR-flag will be reset by standard
diagnosis readout during restart
CurrentTripping_nretry.emf
Over current protection with latch due to reaching maximum number of retries nretry
Figure 9
In PWM operation the number of retries is cumulated over PWM cycles until nretry is reached. Please refer to
Figure 10 for a more detailed view.
Operative
Inrush
IN /
OUTx
IL
IL(Htrip)
Operative
Fault
Fault
Inrush
Fault
t ≥ t delay(Htrip)
startup
Switch off by over current detection
Latch off due to n retry (LV)
Latch off due to n retry (LV)
Latch off due to IL(Ltrip)
t
I L(Ltrip)
nretry
0 12 3 4
31 32
01 2 3 4
ERR
Data Sheet
31 32
t
*
* ERR-flag will be reset by standard
diagnosis readout during restart
Figure 10
5 6 7 89
CL = 1
CL = 1
t
CurrentTripping_nretry_PWM .emf
Over current protection with latch due to reaching maximum number of retries nretry in PWM
26
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Protection Functions
The ERR-flag will be set during over current shut down. It can be reset by reading the ERR-flag, unless Fault state
is reached by exceeding nretry. It will be set again with the next over current event. See figures above.
The number of restarts nretry is depending on the VDS voltage according to the following figure and Chapter 7.1.2.
IL(Htrip)
n = n retry(LV)
IL
n = n retry(MV )
no retry
IL(Vtrip)
5
10
15
20
V DS
CurrentTrippingVsVDS.emf
Figure 11
Number of retries and trip levels dependent of VDS
The retry latch is cleared by SPI command HWCR.CL = 1b. If the input pin or the bit in the SPI register OUTL is
still set, the channel will be turned-on immediately after the command HWCR.CL = 1b. To prevent degradation of
the device, channel is restarting in Operative state (Chapter 7.2).
7.1.2
Over Current Protection at high VDS
The SPOC - BTS5482SF provides an over current protection at high VDS (7.10.6). For VDS > VDS(Vtrip) and
IL > IL(Vtrip) during turn-on the channel switches off and latches immediately. For details please refer to parameter
IL(VTRIP) (7.10.5).
The current trip level IL(Vtrip) is below the current trip level IL(Htrip) at VDS = 7V.
The over current latch is cleared by SPI command HWCR.CL = 1b. If the input pin or the bit in the SPI register
OUTL is still set, the channel will be turned-on immediately after the command HWCR.CL = 1b. To prevent
degradation of the device it is recommended to wait tdelay(CL) (4.1.10) until resetting the latch and restarting in
Operative state.
Inrush
Fault
Operative
IN /
OUTx
t
VDS
VDS(Vtrip)
IL(Vtrip)
IL
high VDS over current
normal operation
t
over load
removed
t
I IS
t
ERR
CL = 1
t
CurrentTrippingHighVDS.emf
Figure 12
Data Sheet
Over current protection in case of high VDS voltages
27
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Protection Functions
7.1.3
Over Temperature Protection
Each channel has its own temperature sensor. If the temperature at the channel exceeds the thermal shutdown
temperature Tj(SC), the channel will switch off and latch to prevent destruction (also in case of VDD = 0V). After an
overcurrent event the threshold Tj(SC) will be decreased by the thermal hysteresis ∆Tj (7.10.11). In order to
reactivate the channel, the temperature must drop by at least the thermal hysteresis ∆Tj and the over temperature
latch must be cleared by SPI command HWCR.CL = 1b. When channel restarts the overtemperature threshold is
reset to Tj(SC). If the input pin or the bit in the SPI register OUTL is still set, the channel will be turned-on immediately
after the command HWCR.CL = 1b.To prevent degradation of the device it is recommended to wait tdelay(CL)
(4.1.10) until resetting the latch and restarting in Operative state.
Inrush
Fault
Operative
IN /
OUTx
t
VDS
normal
operation
over current
VDS(Vtrip )
t
IL
IL(Htrip )
Switch off by over
current detection
over load
removed
n =1
n < n retry Latch off due to
Tj
Tj(SC)
Tj (SC) - ∆Tj
t
over temperature
Tj(s tart)
t
IIS
t
ERR
*
* ERR-flag will be reset by standard
diagnosis readout during restart
Figure 13
Data Sheet
CL = 1
t
CurrentTrippingDeltaT_OT .emf
Over current protection with latch due to reaching over temperature Tj(SC)
28
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Protection Functions
Inrush
Fault
Operative
Fault
Oper.
Fault
IN /
OUTx
t < tdelay (Htrip )
IL
IL(Htrip)
IL(Ltrip)
t
Latch off due to
over current
t
Tj
Latch off due to
over temperature
Tj(SC)
Tj(s tart)
t
I IS
t
ERR
CL = 1
CL = 1
t
OverLoad.emf
Figure 14
Data Sheet
Shut Down by Over Temperature
29
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Protection Functions
7.1.4
Dynamic Temperature Protection
Additionally, each channel has its own dynamic temperature protection to improve short circuit robustness when
channels are doing automatic retries. The dynamic temperature protection will check the junction temperature of
each channel after an overcurrent event. When the junction temperature (Tj) compared to the temperature of the
reference sensor (TRef) is below the dynamic temperature threshold ∆Tj(res) the channel is restarting
(t1 in Figure 15). As soon as Tj > TRef + ∆Tj(res) the channel will be latched off and the ERR-flag will be set
(t2 in Figure 15). The latch is cleared by SPI command HWCR.CL = 1b. If the input pin or the bit in the SPI register
OUTL is still set, the channel will be turned-on immediately after the command HWCR.CL = 1b. To prevent
degradation of the device it is recommended to wait tdelay(CL) (4.1.10) until resetting the latch and restarting in
Operative state.
Inrush
Fault
Operative
IN /
OUTx
IL
IL(Htrip )
normal
operation
over load
t
t
T
Tj (SC )
Latch off due to dynamic
temperature protection
dynamic temperature
protection allows restart
TRef(2) + ∆Tj (res)
TRef(1) + ∆Tj (res)
Tj
TRef
t1
ERR
t
t2
*
* ERR-flag will be reset by standard
diagnosis readout during restart
CL = 1
t
over load removed
DynamicT_latch.emf
Figure 15
Data Sheet
Dynamic Temperature Protection with latch
30
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Protection Functions
7.2
Operative State
In this state the device allows only low current trip level IL(Ltrip) (7.10.4). Channel switches off and latches
immediately in case the trip level is reached. To change from Operative State to Inrush State the respective
channel has to be in OFF-state for tdelay(Htrip). For a detailed description see Chapter 7.4.
7.2.1
Over Current Protection in Operative State
In case of a short circuit to GND event with IL > IL(Ltrip) (7.10.4), the channel is latched off immediately and it will
change to Fault State. For more details, please refer to the figure Figure 16.
The over current latch is cleared by SPI command HWCR.CL = 1b. If the input pin or the bit in the SPI register
OUTL is still set, the channel will be turned-on immediately after the command HWCR.CL = 1b. Depending on the
state of the TimerInrush (tdelay(Htrip)) the device will either restart in Inrush or Operative state.
Inrush
Operative
Fault
Inrush
Operative
IN /
OUTx
t
IL
IL(Htrip)
I L(Ltrip)
over load
t
IIS
over load
removed
ERR
t ≥ tdelay (Ltrip )
t ≥ tdelay
(Htrip )
t ≥ tdelay
(Ltrip )
t
t
CL = 1
CurrentTrippingLowVDS.emf
Figure 16
Shut Down by Over Current in Operative State
7.2.2
Over Temperature Protection in Operative State
If the junction temperature exceeds the thermal shutdown temperature Tj(SC), the channel will switch off and latch
to prevent destruction (also in case of VDD = 0V). In order to reactivate the channel, the temperature must drop
below Tj(SC) and the over temperature latch must be cleared by SPI command HWCR.CL = 1b. If the input pin or
the bit in the SPI register OUTL is still set, the channel will be turned-on immediately after the command
HWCR.CL = 1b.To prevent degradation of the device it is recommended to wait tdelay(CL) (4.1.10) until resetting the
latch and restarting in Operative state. See Figure 14 for a detailed view.
7.2.3
Dynamic Temperature Protection in Operative State
In this State the dynamic temperature protection is not needed to protect the device. For an improved EMI
performance this function is disabled.
7.3
Fault State
In this State the respective channel is in a latched off condition due to an overload event occurred in Inrush or
Operative State. To reactivate the channel the command HWCR.CL = 1b has to be sent over SPI. After the clear
latch command the channel will change to Operative State. To restart in Inrush State the respective channel has
to be OFF for t > tdelay(Htrip). See Figure 16 and Chapter 7.4 for further details.
Data Sheet
31
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Protection Functions
7.4
Timers and nretry counter
Each state machine uses two different timers (TimerOn and TimerInrush) to control the state transitions. A counter
is used to limit the maximum number of automatic restarts (nretry).
The TimerOn controls the automatic state transition from Inrush to Operative. As soon the channel is activated in
Inrush State (SPI or IN) the TimerOn (7.10.2) is running. The behavior of this timer is shown in the table below.
Table 4
TimerOn behavior
TimerOn
OC / DT / OT = 0
OC / DT / OT = 1
ON = 0
ON = 1
ON = 0
ON = 1
Inrush State
hold
running
n.a.
reset
Operative / Fault State
reset
reset
reset
reset
In case of an overload event the TimerOn is reset to provide a higher inrush capability. Figure 17 shows the
TimerOn behavior when switching on a high inrush load. After the last overcurrent event the TimerOn is restarted.
When the timer expires (t > tdelay(Ltrip)) the Operative State is entered.
Operative
Inrush
IN /
OUTx
IL
Oper.
Fault
t ≥ tdelay (Ltrip )
startup
Switch off by over current detection
IL(Htrip)
I L(Ltrip)
nretry
Fault
0
1
Oper.
Latch off due to IL(Ltrip)
2
t
Latch off due to nretry (LV)
0
1
2
3
4
5
31 32
t
*
* ERR-flag will be reset by standard
diagnosis readout during restart
Figure 17
Fault
t ≥ tdelay (Htrip )
CL = 1
ERR
Inrush
CL = 1
t
TimerOn_Inrush.emf
Timer-ON behavior with high inrush load
In case of PWM operation the TimerOn is cumulating the ON-state time of the channel. As soon as Ʃton > tdelay(Ltrip)
the channel is entering Operative State. Figure 18 shows a high ohmic short circuit in PWM operation, where the
load current does not reach IL(Htrip). When Ʃton > tdelay(Ltrip) the Operative state is entered. Due to the lower current
trip level IL(Ltrip) the channel is latched off and the Fault State is entered.
Data Sheet
32
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Protection Functions
Inrush
IN /
OUTx
Σt ON ≥ t delay(Ltrip)
startup
IL(Htrip)
I L(Ltrip)
Inrush
tdelay(Htrip)
ITCx = 1
tON
IL
Fault
Oper.
Σt ON ≥ tdelay (Ltrip)
t
tON
Latch off due to IL(Ltrip )
t
CL = 1
ERR
t
TimerOn_high_ohmic_short.emf
Figure 18
TimerOn and TimerInrush behavior in high ohmic short condition
To reactivate the channel in Operative State the command HWCR.CL = 1b has to be sent. In case the device
needs to be restarted in Inrush State the TimerInrush has to be expired. See Figure 18. Table 5 shows the
behavior of the TimerInrush in the different states of the state machine.
Table 5
TimerInrush
TimerInrush
ITCx = 0
ITCx = 1
ON = 0
ON = 1
ON = 0
ON = 1
Inrush State
running
reset
running
reset
Operative / Fault State
running
reset
running
running
TimerInrush is needed to change from Operative or Fault to Inrush state. In standard configuration (ITCx = 0) the
TimerInrush is only running when the respective channel is deactivated. To provide some more flexibility in
software, it is possible to have the TimerInrush running when the channel is activated or in PWM operation
(ITCx = 1). When Limp Home mode is activated the TimerInrush is running independent of the state of the
channels. The bit ITCx and TimerInrush are reset at every state transition from Inrush to Operative or Inrush to
Fault. See Figure 8.
To limit the number of automatic retries each channel has its own retry counter. As soon the counter reaches the
maximum value (nretry), the device changes to Fault state. The value of this counter is frozen when the channel is
switched off for t < tdelay(Htrip). The behavior of this counter is shown in Table 6.
Table 6
nretry counter
nretry counter
TimerInrush not expired
TimerInrush expired
ON = 0
ON = 1
ON = 0
ON = 1
Inrush State
frozen
running
reset
n.a.
Operative / Fault State
reset
reset
reset
reset
Data Sheet
33
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Protection Functions
7.5
Undervoltage restarts
To increase the device robustness at low VS condition, the device provides VS monitoring functionality. In case
VS < VS(mon) the load current trip level is reduced to IL(Ltrip). In case IL > IL(Ltrip) the channel will restart until the
maximum number of retries (nretry(LV)) is reached. It has to be ensured that VS does not drop below VS(ext), otherwise
the undervoltage shutdown could be entered (see 5.3.3). If this occurs before current trip level is reached, the
protection mechanisms are reset and the channels are restarting with low current trip level IL(Ltrip). If this occurs
after over current detection (e.g. due to oscillations on battery) the protection mechanisms are reset and the
channels are restarting with high current trip level IL(Htrip). To mitigate oscillations on the battery a good filtering on
VS is recommended.
Inrush
IN /
OUTx
Fault
startup
t
VS
VS(nor)
V S(mon)
IL
IL(Htrip)
Current trip level reduced due to V S undervoltage
Latch off due to n retry (LV )
t
I L(Ltrip)
nretr y
0
1
2
ERR
3
4
32
31
*
*
* ERR-flag will be reset by standard
diagnosis readout during restart
Figure 19
Behavior of current trip level in VS undervoltage condition
7.6
Reverse Polarity Protection
t
t
VS_undervoltage.emf
To reduce power losses during reverse polarity ReversaveTM functionality is implemented for all internal channels.
They are turned-on to almost forward condition in reverse polarity condition, see parameter RDS(REV). In reverse
polarity mode, power dissipation is caused by the reverse ON-state resistance RDS(REV) of each channel as well as
each ESD diode of the logic pins. The reverse current through the channels has to be limited by the connected
loads. The current through the ground pin, sense pin IS, the logic power supply pin VDD, the SPI pins, input pins,
external driver pins and the limp home input pin has to be limited as well (please refer to the maximum ratings
listed on Page 10).
Note: No protection mechanism like temperature protection or current protection is active during reverse polarity.
7.7
Over Voltage Protection
In the case of supply voltages between VS(SC)max and VS(CL) the output transistors are still operational and follow
the input or the OUTL register. Parameters are not warranted and lifetime is reduced compared to normal mode.
In addition to the output clamp for inductive loads as described in Section 6.3, there is a clamp mechanism
available for over voltage protection of the internal circuits.
7.8
Loss of Ground
In case of complete loss of the device ground connections, but connected load ground, the SPOC - BTS5482SF
securely changes to or stays in OFF-state.
7.9
Loss of VS
In case of loss of VS connection in ON-state, all inductances of the loads have to be demagnetized through the
ground connection or through an additional path from VS to GND. For example, a suppressor diode is
recommended between VS and GND.
Data Sheet
34
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Protection Functions
7.10
Electrical Characteristics
Electrical Characteristics Protection Functions
Unless otherwise specified: VS = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C
typical values: VS = 13.5 V, VDD = 4.3 V, Tj = 25 °C
Pos. Parameter
Symbol
Limit Values
Unit Test Conditions
min.
typ.
max.
71
–
67
–
90
–
120
–
100
VDS < 7 V
Tj = -40 °C
1)
Tj = 25 °C
Tj = 150 °C
29
–
23
–
30
–
44
–
39
Tj = -40 °C
1)
Tj = 25 °C
Tj = 150 °C
–
8.5
–
12
–
11
HWCR.LEDn = 1
Tj = -40 °C
1)
Tj = 25 °C
Tj = 150 °C
10
14
ms
1)
160
250
ms
1)
Over Current Protection
IL(Htrip)
7.10.1 Load current trip level
A
channel 0, 1
channel 2, 3
HWCR.LEDn = 0
7
–
5.5
7.10.2 Operative State activation time
7.10.3 Inrush State re-activation time
7.10.4 Load current trip level after tdelay(Ltrip)
tdelay(Ltrip) 7
tdelay(Htrip) –
IL(Ltrip)
channel 0, 1
A
40
35
–
–
78
70
Tj = -40 °C
Tj = 150 °C
17
15.5
–
–
35
30
Tj = -40 °C
Tj = 150 °C
3.8
3.8
–
–
9
8
Tj = -40 °C
Tj = 150 °C
channel 2, 3
HWCR.LEDn = 0
HWCR.LEDn = 1
7.10.5 Load current trip level at high VDS
IL(Vtrip)
A
channel 0, 1
1)
40
35
–
–
78
70
Tj = -40 °C
Tj = 150 °C
17
15.5
–
–
35
30
Tj = -40 °C
Tj = 150 °C
3.8
3.8
–
–
9
8
Tj = -40 °C
Tj = 150 °C
channel 2, 3
HWCR.LEDn = 0
HWCR.LEDn = 1
7.10.6 Over current tripping at high VDS
activation level
VDS(Vtrip) 15
20
–
V
1)
7.10.7 VS monitoring threshold
VS(mon)
5.7
–
V
1)
Data Sheet
–
35
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Protection Functions
Electrical Characteristics Protection Functions (cont’d)
Unless otherwise specified: VS = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C
typical values: VS = 13.5 V, VDD = 4.3 V, Tj = 25 °C
Pos. Parameter
Symbol
Limit Values
Unit Test Conditions
min.
typ.
max.
7.10.8 Number of automatic retries at over
nretry(LV)
current or dynamic temperature sensor
shut down at low VDS
–
–
32
1)
VDS = 9 V
nretry(MV)
7.10.9 Number of automatic retries at over
current or dynamic temperature sensor
shut down at medium VDS
–
–
8
1)
VDS = 13 V
Tj(SC)
7.10.11 Thermal hysteresis of thermal shutdown ∆Tj
7.10.12 Dynamic temperature sensor restart
∆Tj(res)
150
180
210
°C
1)
–
15
–
K
1)
–
35
–
K
1)
mΩ
1)
Over Temperature Protection
7.10.10 Thermal shut down temperature
Reverse Battery
RDS(REV)
7.10.13 On-state resistance
channel 0, 1
–
–
4
6
–
–
–
–
15
21
–
–
channel 2, 3
VS = -13.5 V
IL = -7.5 A
Tj = 25 °C
Tj = 150 °C
IL = -2.6 A
Tj = 25 °C
Tj = 150 °C
Over Voltage
VS(CL)
7.10.14 Over voltage protection
V
VS to GND
40
60
71
channel 0, 1
32
–
54
40
–
55
32
–
54
40
–
55
channel 2, 3
IGND = 5 mA
Tj = 25 °C
IL = 20 mA
1)
Tj = 150 °C
IL = 6 A
Tj = 25 °C
IL = 20 mA
1)
Tj = 150 °C
IL = 2 A
1) Not subject to production test, specified by design.
Data Sheet
36
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Diagnosis
8
Diagnosis
For diagnosis purpose, the SPOC - BTS5482SF provides a current sense signal at pin IS and the diagnosis word
via SPI. There is a current sense multiplexer implemented that is controlled via SPI. The sense signal can also be
disabled by SPI command. A switch bypass monitor allows to detect a short circuit between the output pin and the
battery voltage.
In OFF-state a current source is able to be switched on for a selected channel with the DCR.CSOL bit. This allows
open load / short circuit detection to VS in OFF-state. The current value can be configured to a low or a high value
by programming the bit ICR.CSL. Please refer to parameter IL(OL) (8.5.16).
Note: All parameters and functions stated below are valid for the internal channels. The behavior of the current
sense of the two external channel is restricted to the behavior of the external drivers.
Please refer to Figure 20 for details on diagnosis function:
VS
IIS 0
latch
temperature
sensor
CSOL
IL(OL)
T
gate
control
OR
over current
protection
OUT3
OUT2
OUT1
OUT0
latch
load
current
sense
ERR0
channel 0
VS
DCR.MUX
VDS(SB )
DCR.
SBM
current sense multiplexer
IS
RIS
Diagnosis_STD.emf
Figure 20
Data Sheet
Block diagram: Diagnosis
37
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Diagnosis
For diagnosis feedback at different operation modes, please see following table.
Table 7
Operation Modes 1)
Operation Mode
Input Level Output
OUTL.OUTn Level VOUT
Current
Sense IIS
Error Flag
ERRn2)
SBM
DCR.SBM
Normal Operation (OFF)
L/0
GND
(OFF-state) GND
Z
0
1
Z
0
1
Short Circuit to GND
Thermal shut down
Z
Z
0
x
Short Circuit to VS
VS
Z
0
0
Open Load
Z
Z
0
03)
Inverse Current
> VS
Z
0
04)
Normal Operation (ON)
Short Circuit to GND
H/1
(ON-state)
Dynamic Temperature Sensor shut down
Over Current shut down
~ VS
IL / kILIS
0
0
~ GND
Z
1
1
Z
Z
1
Z
Z
x
1
5)
x
6)
x
Thermal shut down
Z
Z
1
Short Circuit to VS
VS
< IL / kILIS
0
0
Open Load
VS
Z
0
0
Inverse Current
> VS
Z
0
0
1)
2)
3)
4)
5)
6)
L = low level, H = high level, Z = high impedance, potential depends on leakage currents and external circuit x = undefined
The error flags are latched until they are transmitted in the standard diagnosis word via SPI
If the current sense multiplexer is set to Channel 0 to 3 and DCR.CSOL bit set
If the current sense multiplexer is set to Channel 0 to 3
The over current latch off flag is set latched and can be cleared by SPI command HWCR.CL
The over temperature flag is set latched and can be cleared by SPI command HWCR.CL
8.1
Diagnosis Word at SPI
The standard diagnosis at the SPI interface provides information about each channel. The error flags, an OR
combination of the over temperature flags and the over load monitoring signals are provided in the SPI standard
diagnosis bits ERRn.
The over load monitoring signals are latched in the error flags and cleared each time the standard diagnosis is
transmitted via SPI. In detail, they are cleared between the second and third raising edge of the SCLK signal.
The over temperature flags, which cause an overheated channel to latch off, are latched directly at the gate control
block. The over current flags, which cause a channel driving a too high current to switch off, are latched like the
over temperature flags. Those latches are cleared by SPI command HWCR.CL.
Note: The over temperature and over current information is latched twice. When transmitting a clear latch
command (HWCR.CL), the error flag is cleared during command transmission of the next SPI frame and
ready for latching after the third raising edge of the SCLK signal. As a result, the first standard diagnosis
information after a clear latch command will indicate a failure mode at the previously affected channels
although the thermal latches have been cleared already. In case of continuous over load, the error flags are
set again immediately because of the over load monitoring signal.
Data Sheet
38
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Diagnosis
8.2
Load Current Sense Diagnosis
There is a current sense signal available at pin IS which provides a current proportional to the load current of one
selected channel. The selection is done by a multiplexer which is configured via SPI.
Current Sense Signal
The current sense signal (ratio kILIS = IL / IS) is provided during on-state as long as no failure mode occurs. The
ratio kILIS can be adjusted to the load type (LED or bulb) via SPI register HWCR for channel 2 and 3. The accuracy
of the ratio kILIS depends on the load current. Usually a resistor RIS is connected to the current sense pin. It is
recommended to use resistors 1.5 kΩ < RIS < 5 kΩ. A typical value is 2.7 kΩ.
30000
kilis Tj = -40 °C
kilis typ Tj = 25 °C
kilis Tj = 25 °C, 150 °C
25000
kilis value
20000
15000
10000
5000
0
0
1
2
3
4
5
6
7
8
Load current IL [A]
Figure 21
Current Sense Ratio kILIS Channel 0, 1 1)
14000
kilis bulb Tj = 25 °C, 150 °C
kilis bulb typ Tj = 25 °C
kilis bulb Tj = -40 °C
12000
kilis value
10000
8000
6000
4000
2000
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Load current IL [A]
Figure 22
Current Sense Ratio kILIS Channel 2, 3 (bulb) 1)
1) The curves show the behavior based on characterization data. The marked points are guaranteed in this Data Sheet in
Section 8.5 (Position 8.5.1 and 8.5.2).
Data Sheet
39
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Diagnosis
1400
kilis LED Tj = 25 °C, 150 °C
kilis LED typ Tj = 25 °C
kilis LED Tj = -40 °C
1200
kilis value
1000
800
600
400
200
0
0
0.2
0.4
0.6
0.8
1
Load current IL [A]
Figure 23
Current Sense Ratio kILIS Channel 2, 3 (LED) 1)
In case of OFF-state, over current, dynamic temperature sensor latch as well as over temperature, the current
sense signal of the affected channel is switched off. To distinguish between a latched and non latched flag, the
SPI diagnosis word can be used. The over current shut down flag (n < nretry) is cleared every time the diagnosis is
transmitted, whereas the over temperature latch, dynamic temperature protection latch and over current latch is
cleared by a dedicated SPI command (HWCR.CL).
Details about timings between the current sense signal IIS and the output voltage VOUT and the load current IL can
be found in Figure 24.
OUTx
OFF
ON
OFF
t
VOUT
IL
tON
tsIS (ON)
t OFF
tsIS (LC)
tdIS (OFF )
t
t
IIS
t
SenseTiming.emf
Figure 24
Timing of Current Sense Signal
Current Sense Multiplexer
There is a current sense multiplexer implemented in the SPOC - BTS5482SF that routes the sense current of the
selected channel to the diagnosis pin IS. The channel is selected via SPI register DCR.MUX. The sense current
also can be disabled by SPI register DCR.MUX. For details on timing of the current sense multiplexer, please refer
to Figure 25.
The current sense diagnosis enable signal for the external smart power drivers also can be selected via the SPI
register DCR.MUX. For being compliant to PROFET+ diagnostic functions, it is possible to configure pin EDD0 as
DEN and EDD1 as DSEL. Therefore, the bit OUTH.PRO+ needs to be set.
Data Sheet
40
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Diagnosis
CS
DCR.MUX 110
000
010
110
ts IS (MUX )
IIS
tdIS (MUX)
t
ts IS(EN)
t
MuxTiming.emf
Figure 25
Timing of Current Sense Multiplexer
Current Sense Offset Trimming
To increase the current sense accuracy of SPOC - BTS5482SF, a circuitry to measure and trim the sense offset
current is implemented. This so called calibration mode is activated by the SPI command ICR.CAL = 1b. In
calibration mode, a current proportional to the positive offset of the operational amplifier is provided on the IS pin.
To increase the accuracy of the calibration this current is amplified when calibration mode is entered (see 8.5.4).
The offset of the operational amplifier can be trimmed by 15 steps which are selected by the bits KILIS.OSTn.
(see. Chapter 9.6 for detailed information). To exit the calibration mode ICR.CAL is set to 0b. During calibration
the state of the current sense multiplexer should not be changed, otherwise the measured current could be
affected. If DCR.MUX = 111 the device exits calibration mode and stand-by mode is entered. In general the
calibration mode does not have any effect on other SPI registers or functions of the device. In case of calibration
during operation switching transients on the supply line must be considered.
8.3
Switch Bypass Diagnosis
To detect short circuit to VS, there is a switch bypass monitor implemented for all internal channels. In case of short
circuit between the output pin OUT and VS in ON-state, the current will flow through the power transistor as well
as through the short circuit (bypass) with undefined ratio. As a result, the current sense signal will show lower
values than expected by the load current. In OFF-state, the output voltage will stay close to VS potential which
means a small VDS. The time for the output voltage to reach a steady state condition depends on the time constant
of the respective output pin which is affected by the resistance and capacitance introduced by external
components and the board layout.
The switch bypass monitor compares the voltage VDS across the power transistor of that channel, which is selected
by the current sense multiplexer (DCR.MUX) with threshold VDS(SB). The result of the comparison can be read in
SPI register DCR.SBM or in the standard diagnosis.
8.4
Open Load in OFF-State
For performing a dedicated open load in OFF-state detection a current source can be switched in parallel to the
DMOS according to the Figure 20. The current source current can be programmed in two steps by the bit
ICR.CSL.
The following procedure is recommended to use:
•
•
•
•
Select the dedicated channel with the multiplexer
Enable the open load current with the DCR.CSOL bit
Read the DCR.SBM or the standard diagnosis
Disable the open load current with the DCR.CSOL bit
Note: To distinguish between a short circuit to VS and an open load in OFF-state, a pull-down resistor at the output
would be needed to compensate the output leakage of the channel.
Data Sheet
41
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Diagnosis
8.5
Electrical Characteristics
Electrical Characteristics Diagnosis
Unless otherwise specified: VS = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C
typical values: VS = 13.5 V, VDD = 4.3 V, Tj = 25 °C
Pos. Parameter
Symbol
Limit Values
min.
typ.
Unit
Test Conditions
max.
Load Current Sense
8.5.1 Current sense ratio
kILIS
Tj = -40 °C
channel 0, 1:
1800
2200
4100
5030
5300
5600
0.456 A
0.600 A
1.3 A
2.6 A
4.0 A
7.5 A
6900
6700
6400
6400
6450
6450
29000
20000
10500
8200
7800
7300
channel 2, 3 (bulb):
HWCR.LEDn = 0
585
1000
1300
1500
1600
1600
0.115 A
0.300 A
0.600 A
1.3 A
2.6 A
4.0 A
2000
1830
1830
1830
1840
1840
13000
3630
2600
2100
2080
2080
channel 2, 3 (LED):
–
–
–
–
–
–
HWCR.LEDn = 1
170
300
350
400
400
0.050 A
0.150 A
0.300 A
0.600 A
1.0 A
8.5.2 Current sense ratio
–
–
–
–
–
–
400
440
450
460
500
1300
675
580
555
555
kILIS
–
–
–
–
–
Tj = 25 °C to 150 °C
channel 0, 1:
2700
3200
4500
5030
5300
5600
0.456 A
0.600 A
1.3 A
2.6 A
4.0 A
7.5 A
6000
6100
6350
6400
6450
6450
15000
10500
9100
8200
7800
7300
channel 2, 3 (bulb):
HWCR.LEDn = 0
600
1000
1300
1500
1600
1600
0,115
0.300 A
0.600 A
1.3 A
2.6 A
4.0 A
Data Sheet
–
–
–
–
–
–
42
1750
1790
1810
1830
1840
1840
7000
2600
2300
2100
2080
2080
–
–
–
–
–
–
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Diagnosis
Electrical Characteristics Diagnosis (cont’d)
Unless otherwise specified: VS = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C
typical values: VS = 13.5 V, VDD = 4.3 V, Tj = 25 °C
Pos. Parameter
Symbol
Limit Values
min.
typ.
Unit
max.
channel 2, 3 (LED):
HWCR.LEDn = 1
170
300
350
400
400
0.050 A
0.150 A
0.300 A
0.600 A
1.0 A
400
440
450
460
500
–
–
–
–
–
800
640
580
555
555
1)
8.5.3 Current sense drift of unaffected channel ∆kILIS(IC)
during inverse current of other channels
channel 0, 1
-20 % –
-20 % –
20 %
20 %
-20 % –
-20 % –
20 %
20 %
-20 % –
-20 % –
20 %
20 %
DCR.MUX ≠ 111
IL0, 1 = 7.5 A
IL1, 0 (IC) = 7.5 A
IL2, 3 (IC) = 2.6 A
HWCR.LEDn = 0
IL2, 3 = 2.6 A
IL0, 1 (IC) = 7.5 A
IL3, 2 (IC) = 2.6 A
HWCR.LEDn = 1
IL2, 3 = 0.6 A
IL0, 1 (IC) = 7.5 A
IL3, 2 (IC) = 2.6 A
channel 2, 3 (bulb)
channel 2, 3 (LED)
IIS(CAL)
8.5.4 Calibration step
8.5.5 Current sense voltage limitation
8.5.6 Maximum steady state current sense
output current
8.5.7 Current sense leakage / offset current
VIS(LIM)
IIS(MAX)
8.5.8 Current sense leakage, while diagnosis
disabled
µA
–
–
5
75
–
–
8
9.5
11
5.5
–
20
IIS(en)
channel 0, 1
channel 2, 3
Data Sheet
Test Conditions
IIS(dis)
43
–
–
–
–
70
70
–
–
1
1)
Tj = 25 °C
ICR.CAL = 0
ICR.CAL = 1
V
1)2)
mA
1)
µA
IL = 0 A
DCR.MUX ≠ 111
ICR.CAL = 0
KILIS.OSTn =
1000
µA
DCR.MUX = 110
ICR.CAL = 0
IIS = 3mA
VIS = 0 V
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Diagnosis
Electrical Characteristics Diagnosis (cont’d)
Unless otherwise specified: VS = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C
typical values: VS = 13.5 V, VDD = 4.3 V, Tj = 25 °C
Pos. Parameter
Symbol
Limit Values
min.
8.5.9 Current sense settling time after channel tsIS(ON)
activation
channel 0, 1
typ.
Unit
Test Conditions
µs
max.
–
–
150
VS = 13.5 V
RIS = 2.7 kΩ
RL = 2.2 Ω
–
–
150
RL = 6.8 Ω
100
HWCR.LEDn = 1
RL = 33 Ω
channel 2, 3
HWCR.LEDn = 0
–
8.5.10 Current sense desettling time after
channel deactivation
–
tdIS(OFF)
µs
–
–
8.5.11 Current sense settling time after change tsIS(LC)
of load current
channel 0, 1
–
–
µs
–
30
–
–
30
–
–
30
VS = 13.5 V
RIS = 2.7 kΩ
HWCR.LEDn = 0
HWCR.LEDn = 1
25
25
–
1)
channel 2, 3
1)
VS = 13.5 V
RIS = 2.7 kΩ
IL = 7.5 A to 4.0 A
HWCR.LEDn = 0
IL = 2.6 A to 1.3 A
HWCR.LEDn = 1
IL = 0.6 A to 0.3 A
8.5.12 Current sense settling time after current
sense activation
tsIS(EN)
–
–
25
µs
RIS = 2.7 kΩ
DCR.MUX:
110 -> 000
8.5.13 Current sense settling time after
multiplexer channel change
tsIS(MUX)
–
–
30
µs
RIS = 2.7 kΩ
RL0 = 2.2 Ω
RL2 = 33 Ω
DCR.MUX:
010 -> 000
8.5.14 Current sense deactivation time
tdIS(MUX)
–
–
25
µs
1)
VDS(SB)
1.5
–
4
V
–
IL(OL)
100
3.0
–
–
450
7.5
µA
mA
ICR.CSL = 0
ICR.CSL = 1
RIS = 2.7 kΩ
DCR.MUX:
000 -> 110
Switch Bypass Monitor
8.5.15 Switch bypass monitor threshold
Open load in off current source
8.5.16 Current source in OFF-state
1) Not subject to production test, specified by design.
2) Voltage clamp at current sense pin has to be considered as a protection feature.
Data Sheet
44
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Serial Peripheral Interface (SPI)
9
Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines: SO,
SI, SCLK and CS. Data is transferred by the lines SI and SO at the rate given by SCLK. The falling edge of CS
indicates the beginning of an access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on
line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter
ensures that data is taken only, when a multiple of 8 bit has been transferred. The interface provides daisy chain
capability.
SO
CS
SI
MSB
6
5
4
3
2
1
MSB
6
5
4
3
2
1
LSB
LSB
CS
SCLK
time
SPI.emf
Figure 26
Serial Peripheral Interface
9.1
SPI Signal Description
CS - Chip Select:
The system micro controller selects the SPOC - BTS5482SF by means of the CS pin. Whenever the pin is in low
state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are ignored and
SO is forced into a high impedance state.
CS High to Low transition:
•
•
The requested information is transferred into the shift register.
SO changes from high impedance state to high or low state depending on the logic OR combination between
the transmission error flag (TER) and the signal level at pin SI. As a result, even in daisy chain configuration,
a high signal indicates a faulty transmission. This information stays available to the first rising edge of SCLK.
TER
SI
OR
1
SO
0
SI
SPI
SO
S
CS
SCLK
S
TER.emf
Figure 27
Data Sheet
Combinatorial Logic for TER Flag
45
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Serial Peripheral Interface (SPI)
CS Low to High transition:
•
•
Command decoding is only done, when after the falling edge of CS exactly a multiple (1, 2, 3, …) of eight SCLK
signals have been detected. In case of faulty transmission, the transmission error flag (TER) is set and the
command is ignored.
Data from shift register is transferred into the addressed register.
SCLK - Serial Clock:
This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling
edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock.
It is essential that the SCLK pin is in low state whenever chip select CS makes any transition.
SI - Serial Input:
Serial input data bits are shift-in at this pin, the most significant bit first. SI information is read on the falling edge
of SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to Section 9.5 for
further information.
SO Serial Output:
Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CS pin
goes to low state. New data will appear at the SO pin following the rising edge of SCLK. Please refer to Section 9.5
for further information.
9.2
Daisy Chain Capability
The SPI of SPOC - BTS5482SF provides daisy chain capability. In this configuration several devices are activated
by the same CS signal MCS. The SI line of one device is connected with the SO line of another device (see
Figure 28), in order to build a chain. The ends of the chain are connected with the output and input of the master
device, MO and MI respectively. The master device provides the master clock MCLK which is connected to the
SCLK line of each device in the chain.
Figure 28
Data Sheet
SO
SPI
SI
SO
SPI
SCLK
SI
device 3
CS
SCLK
CS
MI
MCS
MCLK
SO
SPI
CS
SI
MO
device 2
SCLK
device 1
SPI_DaisyChain .emf
Daisy Chain Configuration
46
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Serial Peripheral Interface (SPI)
In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The
bit shifted out occurs at the SO pin. After eight SCLK cycles, the data transfer for one device has been finished.
In single chip configuration, the CS line must turn high to make the device accept the transferred data. In daisy
chain configuration, the data shifted out at device 1 has been shifted in to device 2. When using three devices in
daisy chain, three times eight bits have to be shifted through the devices. After that, the MCS line must turn high
(see Figure 29).
MI
MO
SO device 1
SO device 2
SO device 3
SI device 1
SI device 2
SI device 3
MCS
MCLK
time
SPI_DaisyChain2.emf
Figure 29
Data Transfer in Daisy Chain Configuration
9.3
Timing Diagrams
tCS(lead)
tCS(lag)
tCS(td)
tSCLK(P)
CS
0.7VDD
0.2VDD
tSCLK(H)
tSCLK(L)
0.7VDD
SCLK
tSI(su)
0.2VDD
tSI(h)
0.7VDD
SI
0.2VDD
tSO(en)
tSO(v)
tSO(dis)
0.7VDD
SO
0.2VDD
SPI Timing.emf
Figure 30
Data Sheet
Timing Diagram SPI Access
47
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Serial Peripheral Interface (SPI)
9.4
Electrical Characteristics
Electrical Characteristics Serial Peripheral Interface (SPI)
Unless otherwise specified: VS = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C
typical values: VS = 13.5 V, VDD = 4.3 V, Tj = 25 °C
Pos. Parameter
Symbol
Limit Values
min.
typ.
max.
0
–
0.2*
Unit
Test Conditions
V
VDD = 4.3 V
Input Characteristics (CS, SCLK, SI)
9.4.1 L level of pin
VDD
CS VCS(L)
SCLK VSCLK(L)
SI VSI(L)
–
VDD
V
VDD = 4.3 V
50
120
180
kΩ
1)
50
120
180
kΩ
1)
0
–
0.4
V
VDD - –
VDD
V
ISO = -0.5 mA
ISO = 0.5 mA
VDD = 4.3 V
VCS = VDD
0.4*
9.4.2 H level of pin
CS VCS(H)
SCLK VSCLK(H)
SI VSI(H)
RCS
9.4.3 Pull-up resistor at CS pin
9.4.4 Pull-down resistor at pin
VDD
SCLK RSCLK
SI RSI
Output Characteristics (SO)
9.4.5 L level output voltage
9.4.6 H level output voltage
VSO(L)
VSO(H)
0.4 V
ISO(OFF)
-10
–
10
µA
fSCLK
0
0
–
–
5
3
MHz
9.4.9 Serial clock period
tSCLK(P)
200
333
–
–
–
–
ns
9.4.10 Serial clock high time
tSCLK(H)
100
166
–
–
–
–
ns
9.4.11 Serial clock low time
tSCLK(L)
100
166
–
–
–
–
ns
9.4.12 Enable lead time (falling CS to rising
SCLK)
tCS(lead)
200
333
–
–
–
–
ns
200
333
–
–
–
–
ns
9.4.7 Output tristate leakage current
Timings
9.4.8 Serial clock frequency
9.4.13 Enable lag time (falling SCLK to rising tCS(lag)
CS)
tCS(td)
200
333
–
–
–
–
ns
9.4.15 Data setup time (required time SI to
falling SCLK)
tSI(su)
20
33
–
–
–
–
ns
9.4.16 Data hold time (falling SCLK to SI)
tSI(h)
20
33
–
–
–
–
ns
48
VDD = 4.3 V
VDD = 3.0 V
1)
VDD = 4.3 V
2)
VDD = 3.0 V
1)
VDD = 4.3 V
2)
VDD = 3.0 V
1)
VDD = 4.3 V
2)
VDD = 3.0 V
1)
VDD = 4.3 V
2)
VDD = 3.0 V
1)
VDD = 4.3 V
2)
VDD = 3.0 V
1)
VDD = 4.3 V
2)
VDD = 3.0 V
1)
VDD = 4.3 V
2)
VDD = 3.0 V
1)
VDD = 4.3 V
2)
VDD = 3.0 V
2)
9.4.14 Transfer delay time (rising CS to
falling CS)
Data Sheet
1)
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Serial Peripheral Interface (SPI)
Electrical Characteristics Serial Peripheral Interface (SPI) (cont’d)
Unless otherwise specified: VS = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C
typical values: VS = 13.5 V, VDD = 4.3 V, Tj = 25 °C
Pos. Parameter
Symbol
9.4.17 Output enable time (falling CS to SO
valid)
tSO(en)
9.4.18 Output disable time (rising CS to SO
tri-state)
tSO(dis)
Limit Values
min.
9.4.19 Output data valid time with capacitive tSO(v)
load
typ.
Unit
Test Conditions
ns
2)
max.
–
–
–
–
200
333
–
–
–
–
200
333
–
–
–
–
100
166
ns
ns
CL = 20 pF
VDD = 4.3 V
VDD = 3.0 V
2)
CL = 20 pF
VDD = 4.3 V
VDD = 3.0 V
2)
CL = 20 pF
VDD = 4.3 V
VDD = 3.0 V
1) Not subject to production test, specified by design. SPI functional test is performed at fSCLK = 5 MHz.
2) Not subject to production test, specified by design.
Data Sheet
49
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Serial Peripheral Interface (SPI)
9.5
SPI Protocol 8 Bit
CS1)
7
6
5
4
3
2
1
0
x
0
Write OUTL, OUTH and KILIS Register
SI
1
0
ADDR
DATA
Read OUTL, OUTH and KILIS Register
SI
0
0
ADDR
x
x
Write Configuration and Control Registers
SI
1
1
ADDR
DATA
Read Configuration and Control Registers
SI
0
1
ADDR
x
x
x
0
Read Standard Diagnosis
SI
0
x
x
x
x
x
x
1
SBM
x
ERR3
ERR2
ERR1
ERR0
OUT4
OUT3
OUT2
OUT1
OUT0
Standard Diagnosis
SO
TER
0
LHI
Second Frame of Read Command
SO
TER
1
0
SO
TER
1
1
OUT5
ADDR
DATA
1) The SO pin shows this information between CS hi -> lo and first SCLK lo -> hi transition.
Note: Reading a register needs two SPI frames. In the first frame the RD command is sent. In the second frame
the output at SPI signal SO will contain the requested information. A new command can be executed in the
second frame. The standard diagnosis can be accessed either by sending the standard diagnosis read
command or it is transmitted after each write command.
Field
Bits
Type
Description
W/R
7
w
0
1
RB
6
r
Register Bank
0
Read / write to OUTL, OUTH and KILIS register
1
Read / write to the other register
TER
CS
r
Transmission Error
0
Previous transmission was successful (modulo 8 clocks received)
1
Previous transmission failed or first transmission after reset
ADDR
6:5
rw
Address
Pointer to register for read and write command
DATA
4:0
rw
Data
Data written to or read from register selected by address ADDR
ERRn
n = 3 to 0
n
r
Diagnosis of Channel n 1)
0
No failure
1
Over temperature, over current, over load or short circuit for
channel 0 to 3
SBM
5
r
Switch Bypass Monitor 2)
0
VDS < VDS(SB)
1
VDS > VDS(SB)
Data Sheet
Read
Write
50
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Serial Peripheral Interface (SPI)
Field
Bits
Type
Description
OUTn
n = 5 to 0
n
r
Output Status for Channel n
0
Channel is switched off
1
Channel is switched on
LHI
6
r
Limp Home Enable 3)
0
H-input signal at LHI pin
1
L-input signal at LHI pin
1) No ERR-flags available for external drivers
2) Invalid in stand-by mode
3) Not latching information, read of LHI-status during falling CS
9.6
Register Overview
RB
Address
Name
Description
0
0
0
OUTL
Output Configuration Register Low
0
0
1
OUTH
Output Configuration Register High
0
1
0
KILIS
Current Sense Offset Calibration Register
0
1
1
SCCR
Short Circuit Configuration Register
1
0
1
ICR
Input and Current Source Configuration Register
1
1
0
HWCR
Hardware Configuration Register
1
1
1
DCR
Diagnosis Control Register
Bit
7
6
Name
W/R
RB
OUTL
W/R
0
0
0
OUT3
OUT2
OUT1
OUT0
80H
OUTH
W/R
0
0
1
PRO+
res.
OUT5
OUT4
90H
KILIS
W/R
0
1
0
OST3
OST2
OST1
OST0
A8H
SCCR
W/R
0
1
1
ITC3
ITC2
ITC1
ITC0
B0H
ICR
W/R
1
0
1
COL
INCG
CSL
CAL
D0H
R
1
1
0
LED3
LED2
STB
CL
E2H
W
1
1
0
LED3
LED2
RST
CL
-
R
1
1
1
SBM
MUX
F7H
W
1
1
1
CSOL
MUX
-
HWCR
DCR
5
4
3
2
ADDR
1
0
default 1)
DATA
1) The default values are set after reset.
Note: A readout of an unused register will return the standard diagnosis.
Data Sheet
51
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Serial Peripheral Interface (SPI)
Field
Bits
Type
Description
OUTL
n = 3 to 0
n
rw
Output Control Register for Channel 0 to 3
0
OFF
1
ON
OUTH
n = 3 to 0
n
rw
Output Control Register for Channel 4, 5 and PRO+ bit
0
OFF
1
ON
PRO+
0
rw
Configuration of EDD0 and EDD1 to be Compliant to PROFET+ Concept
0
Normal mode
1
EDD0=DEN, EDD1=DSEL
OSTn
n = 3 to 0
n
rw
IS Offset Trimming
0000
IIS(EN) - 8 x IIS(CAL)
0001
IIS(EN) - 7 x IIS(CAL)
0010
IIS(EN) - 6 x IIS(CAL)
0011
IIS(EN) - 5 x IIS(CAL)
0100
IIS(EN) - 4 x IIS(CAL)
0101
IIS(EN) - 3 x IIS(CAL)
0110
IIS(EN) - 2 x IIS(CAL)
0111
IIS(EN) - 1 x IIS(CAL)
1000
IIS(EN) without Offset calibration
1001
IIS(EN) + 1 x IIS(CAL)
1010
IIS(EN) + 2 x IIS(CAL)
1011
IIS(EN) + 3 x IIS(CAL)
1100
IIS(EN) + 4x IIS(CAL)
1101
IIS(EN) + 5 x IIS(CAL)
1110
IIS(EN) + 6 x IIS(CAL)
1111
IIS(EN) + 7 x IIS(CAL))
ITCn
n = 3 to 0
n
rw
Inrush Timer Control
0
Timer tdelay(Htrip) will run only in OFF state of respective channel
1
Timer tdelay(Htrip) will run in ON and OFF state of respective channel
CAL
0
rw
IS Offset Calibration
0
Calibration mode is deactivated
1
Calibration mode is activated
CSL
1
rw
Level for Current Source for Open Load Detection
0
Low level
1
High level
INCG
2
rw
Input Drive Configuration
0
Direct drive mode
1
Assigned drive mode
COL
3
rw
Input Combinatorial Logic Configuration
0
Input signal OR-combined with according OUTL register bit
1
Input signal AND-combined with according OUTL register bit
STB
1
r
Standby Mode
0
Device is awake
1
Device is in Standby mode
Data Sheet
52
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Serial Peripheral Interface (SPI)
Field
Bits
Type
Description
LEDn
n = 3 to 2
n
rw
Set LED Mode for Channel n
0
Channel n is in bulb mode
1
Channel n is in LED mode
CL
0
rw
Clear Latch
0
Thermal and over current latches are untouched
1
Command: Clear all thermal and over current latches
RST
1
w
Reset Command
0
Normal operation
1
Execute reset command
MUX
2:0
rw
Set Current Sense Multiplexer Configuration in OFF-state
000 IS pin is high impedance
001 IS pin is high impedance
010 IS pin is high impedance
011 IS pin is high impedance
100 OUTH.PRO+ = 0: Diagnosis enable of external driver 0 activated (EDD0
= 1)
101 OUTH.PRO+ = 0: Diagnosis enable of external driver 1 activated (EDD1
= 1)
100 OUTH.PRO+ = 1: EDD0 = 1, EDD1 = 0
101 OUTH.PRO+ = 1: EDD0 = 1, EDD1 = 1
110 IS pin is high impedance
111 Stand-by mode (IS pin is high impedance)
Set Multiplexer Configuration in ON-state
000 Current sense of channel 0 is routed to IS pin
001 Current sense of channel 1 is routed to IS pin
010 Current sense of channel 2 is routed to IS pin
011 Current sense of channel 3 is routed to IS pin
100 OUTH.PRO+ = 0: Diagnosis enable of external driver 0 activated (EDD0
= 1)
101 OUTH.PRO+ = 0: Diagnosis enable of external driver 1 activated (EDD1
= 1)
100 OUTH.PRO+ = 1: EDD0 = 1, EDD1 = 0
101 OUTH.PRO+ = 1: EDD0 = 1, EDD1 = 1
110 IS pin is high impedance
111 Stand-by mode (IS pin is high impedance))
SBM
3
r
Switch Bypass Monitor 1)
0
VDS < VDS(SB)
1
VDS > VDS(SB)
CSOL
3
w
Current Source Switch for Open Load Detection
0
OFF
1
ON
1) Invalid in stand-by mode
Data Sheet
53
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Application Description
10
Application Description
V bat
1
5V
100nF3
500Ω
100nF
WD-OUT
VDD
VCC
GPIO
8kΩ
IN1
GPIO
8kΩ
IN2
VS
IN3
OUT0
IS
OUT1
1kΩ
AD
65 W
OUT2
27 W
OUT3
2.7kΩ
1nF
10 W
GND
µC
10nF 3
e.g. XC2267
SPI
65 W
VDD
3.9kΩ
CS
3.9kΩ
SCLK
3.9kΩ
SO
3.9kΩ
SI
SPI
LHI
8kΩ
WD-OUT
100nF3
10kΩ
VS
IN1
VSS
PROFET OUT0
IN2
Ch1
external driver EDO0
control
EDD0
DEN
EDO1
DSEL
EDD1
GND
IS
PROFET OUT1
Ch2
GND
10Ω2
1
2
3
Figure 31
Data Sheet
For filtering and protection purposes
For increased ISO-pulse robustness
For improved electromagnetic compatibility (EMC)
Circuit _STD _EXT.emf
Application Circuit Example
54
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Package Outlines SPOC - BTS5482SF
2.65 MAX.
0.33 ±0.08
C
0.1
2)
0.17
M
0.7 ±0.2
C A-B D 36x
10.3 ±0.3
D
Bottom View
A
36
7.6 -0.2
8˚ MAX.
0.65
0.35 x 45˚
1)
0.23 +0.09
2.45 -0.2
Package Outlines SPOC - BTS5482SF
0.2 -0.1
11
19
19
36
Ejector Mark
1
18
18
B
1)
12.8 -0.2
1
Dimensions in mm
Index Marking
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion of 0.05 max. per side
GPS01089
Figure 32
PG-DSO-36-43 (Plastic Dual Small Outline Package)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
You can find all of our packages, sorts of packing and others in our Infineon Internet Page
“Products”: http://www.infineon.com/products.
Data Sheet
55
Rev. 1.0, 2013-06-05
SPOC - BTS5482SF
Revision History
12
Revision History
Revision
Date
Changes
1.0
2013-06-05
Data Sheet
Trademarks of Infineon Technologies AG
AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™,
CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™, EconoDUAL™,
EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™,
ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™,
POWERCODE™; PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™,
ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, TEMPFET™,
thinQ!™, TRENCHSTOP™, TriCore™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR
development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™,
FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG.
FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of
Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data
Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of
MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics
Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA
MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of
OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF
Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™
of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co.
TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™
of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas
Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes
Zetex Limited.
Last Trademarks Update 2011-11-11
Data Sheet
56
Rev. 1.0, 2013-06-05
Edition 2013-06-05
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2013 Infineon Technologies AG
All Rights Reserved.
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