AN4751, Schematic Guidelines for the MMPF0200 - Application Note

Freescale Semiconductor, Inc.
Application Note
Document Number: AN4751
Rev. 2.0, 6/2015
Schematic Guidelines for the MMPF0200
1
Introduction
This application note provides guidelines for schematic
entry using the MMPF0200. For an example Bill of
Materials, refer to the MMPF0200 Data Sheet.
Freescale analog ICs are manufactured using the
SMARTMOS process, a combinational BiCMOS
manufacturing flow that integrates precision analog, power
functions and dense CMOS logic together on a single
cost-effective die.
© Freescale Semiconductor, Inc., 2014-2015. All rights reserved.
Contents
1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Pin Connection Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Connection Guidelines
2
Pin Connection Guidelines
This section provides recommended pin connections in Table 1. These guidelines help ensure that the MMPF0200 functions
properly.
Table 1. MMPF0200 Pin Connection Guidelines
Pin
Pin Name
Pin Function
Recommended Connection
Recommended
connection when
not used
1
INTB
Open drain interrupt signal to Pull-up via 68 k- 100 k to VSNVS or other rail Leave floating
processor
at voltage less than or equal to VIN
2
SDWNB
Open drain signal to indicate Pull-up via 68 k- 100 k to VSNVS or other rail Leave floating
an imminent system
at voltage less than or equal to VIN
shutdown
3
RESETBMCU
Open drain reset output to
processor
Pull-up via 68 k- 100 k to VSNVS or other rail Leave floating
at voltage less than or equal to VIN
4
STANDBY
Standby input signal from
processor
Connect to PMIC_STBY_REQ signal from
processor
Connect to ground
5
ICTEST
Reserved Pin
Connect to ground
Connect to ground
6
SW1FB
Output voltage feedback for
SW1AB regulator
Connect to SW1AB output voltage rail near load. Leave floating
Leave floating if SW1 is used in SW1ABC Single
Phase mode
7
SW1AIN
Input to SW1A MOSFETs for Connect to VIN and bypass with 0.1 F + 4.7 F Connect to VIN
SW1AB regulator
to ground
8
SW1ALX
SW1A switching node
Connect to SW1AB inductor when used in
Leave floating
SW1AB Single Phase mode. Connect to
SW1ABC inductor when used in SW1ABC Single
Phase mode. Connect to SW1A inductor when
used in SW1AB Dual Phase mode
9
SW1BLX
SW1B switching node
Connect to SW1AB inductor when used in
Leave floating
SW1AB Single Phase mode. Connect to
SW1ABC inductor when used in SW1ABC Single
Phase mode. Connect to SW1B inductor when
used in SW1AB Dual Phase mode
10
SW1BIN
Input to SW1B MOSFETs for Connect to VIN and bypass with 0.1 F + 4.7 F Connect to VIN
SW1AB regulator
to ground
11
RSVD1
Reserved for pin to pin
compatibility. Internally
connected.
Leave floating
N/A
12
RSVD2
Reserved for pin to pin
compatibility. Internally
connected.
Connect to VIN
N/A
13
RSVD3
Reserved for pin to pin
compatibility. Internally
connected.
Leave floating
N/A
14
SW1VSSSNS
Ground reference for SW1
regulator
Connect to ground. Keep away from high current N/A
ground return paths.
15
GNDREF1
Ground reference for SW2
Connect to ground. Keep away from high current N/A
ground return paths.
16
VGEN1
VGEN1 regulator output
Bypass with 2.2 F to ground
Leave floating
AN4751 Application Note Rev. 2.0 6/2015
2
Freescale Semiconductor, Inc.
Pin Connection Guidelines
Table 1. MMPF0200 Pin Connection Guidelines (continued)
Pin
Pin Name
Pin Function
Recommended Connection
Recommended
connection when
not used
17
VIN1
VGEN1 and VGEN2 LDO
regulators’ input supply
Bypass with 1.0 F capacitor to ground
Connect to output of
a regulator with
voltage <3.4 V
18
VGEN2
VGEN2 regulator output
Bypass with 4.7 F to ground
Leave floating
19
RSVD4
Reserved for pin to pin
compatibility. Internally
connected
Leave floating
N/A
20
RSVD5
Reserved for pin to pin
compatibility. Internally
connected
Connect to VIN
N/A
21
RSVD6
Reserved for pin to pin
compatibility. Internally
connected
Leave floating
N/A
22
SW2LX
SW2 switching node
Connect to SW2 inductor
Leave floating
23
SW2IN
Input to SW2 regulator
24
SW2IN
Input to SW2 regulator
Connect to VIN and bypass with 0.1 F + 4.7 F Connect to VIN
to ground. Connect pins 23 and 24 together.
Connect to pin 23
25
SW2FB
Output voltage feedback for
SW2
Connect to SW2 output voltage rail near load
Leave floating
26
VGEN3
VGEN3 regulator output
Bypass with 2.2 F to ground
Leave floating
27
VIN2
VGEN3 and VGEN4 LDO
regulators’ input
Bypass with 1.0 F capacitor to ground
Connect to regulator
with output voltage
<3.6 V
28
VGEN4
VGEN4 regulator output
Bypass with 4.7 F to ground
Leave floating
29
VHALF
Half supply reference for
VREFDDR
Bypass with 0.1 F to ground
Leave floating
30
VINREFDDR
VREFDDR regulator input
Connect 0.1.0 F to VHALF pin. Ensure there is Leave floating
at least 1.0 F net capacitance from
VINREFDDR to ground
31
VREFDDR
VREFDDR regulator output
Bypass with 1.0 F to ground
32
SW3VSSSNS
Ground reference for SW3
regulator(s)
Connect to ground. Keep away from high current N/A
ground return paths.
33
SW3BFB
Output voltage feedback for
SW3B regulator
Leave floating when SW3 is used in SW3AB
Single Phase mode. Connect to SW3B output
voltage rail near load if SW3 is used in
independent mode
34
SW3BIN
Input to SW3B regulator
Connect to VIN and bypass with 0.1 F + 4.7 F Connect to VIN
to ground
35
SW3BLX
SW3B switching node
Connect to SW3AB inductor if SW3 is used in
Leave floating
Single Phase mode. Connect to SW3B inductor if
SW3 is used in independent mode.
36
SW3ALX
SW3A switching node
Connect to SW3AB inductor if SW3 is used in
Leave floating
Single Phase mode. Connect to SW3A inductor if
SW3 is used in independent mode.
37
SW3AIN
Input to SW3A regulator
Connect to VIN and bypass with 0.1 F + 4.7 F Connect to VIN
to ground
38
SW3AFB
Output voltage feedback for Connect to SW3A(B) output voltage rail near load Leave floating
SW3A or SW3AB regulators
Leave floating
Leave floating
AN4751 Application Note Rev. 2.0 6/2015
Freescale Semiconductor, Inc.
3
Pin Connection Guidelines
Table 1. MMPF0200 Pin Connection Guidelines (continued)
Pin
Pin Name
Pin Function
Recommended Connection
Recommended
connection when
not used
39
VGEN5
VGEN5 regulator output
Bypass with 2.2 F to ground
Leave floating
40
VIN3
VGEN5 and VGEN6 LDO
regulators' input
Bypass with 1.0 F capacitor to ground
Connect to VIN
41
VGEN6
VGEN6 regulator output
Bypass with 2.2 F to ground
Leave floating
42
LICELL
Coin cell supply input/output Bypass with 0.1 F capacitor. Connect to optional Bypass with 0.1 F
coin cell.
43
VSNVS
VSNVS regulator/switch
output
Bypass with 0.47 F to ground
44
SWBSTFB
SWBST regulator output
voltage feedback
Connect to SWBST output voltage rail near load Leave floating
45
SWBSTIN
Input to SWBST regulator
Connect to VIN and bypass with 0.1 F + 10 F
to ground
46
SWBSTLX
SWBST switch node
connection
Connect to SWBST inductor and Schottky diode Leave floating
47
VDDOTP
Supply to program OTP
fuses
Connect to VCOREDIG through a 100 kΩ
N/A
resistor if MMPF0200 is used in the default mode.
Connect to ground if MMPF0200 is used in the
fuse mode. If on-board programming is desired,
give provision to apply 8.0 V programming
voltage to the pin with bypass of 2x10 F
capacitors
48
GNDREF1
Ground reference for the
main band gap regulator.
Connect to ground. Keep away from high current N/A
ground return paths.
49
VCORE
Analog Core supply
Bypass with 1.0 F to ground
N/A
50
VIN
Main chip supply
Bypass with 1.0 F to ground
N/A
51
VCOREDIG
Digital Core supply
Bypass with 1.0 F to ground
N/A
52
VCOREREF
Main band gap reference
53
SDA
54
SCL
I
55
VDDIO
Supply for I2C bus
56
PWRON
Power On/off from processor Connect to PMIC_ON_REQ from processor. Pull N/A
up via 8 k- 100 k to VSNVS if required
EP
Expose pad. Functions as
ground return for buck and
boost regulators
-
2C
2C
I
Bypass with 0.47 F
to ground
Connect to VIN
Bypass with 0.22 F to ground
N/A
data line
Pull-up to VDDIO
Leave floating
clock line
Pull-up to VDDIO
Leave floating
Connect to 1.7 to 3.6 V supply. Bypass with
0.1 F to ground. Ensure that VDDIO is always
lesser than or equal to VIN.
Leave floating
Ground. Connect this pad to the inner and
external ground planes through multiple vias to
allow effective thermal dissipation.
N/A
AN4751 Application Note Rev. 2.0 6/2015
4
Freescale Semiconductor, Inc.
References
3
References
Following are URLs where you can obtain information on related Freescale products and application solutions:
Document Number
and Description
URL
MMPF0200
Data Sheet
http://www.freescale.com/files/analog/doc/data_sheet/MMPF0200.pdf
AN1902
QFN (Quad Flat
Pack No-Lead)
Application Note
http://www.freescale.com/files/analog/doc/app_note/AN1902.pdf
AN4622
MMPF0100 and
MMPF0200
Layout
Guidelines
http://www.freescale.com/files/analog/doc/app_note/AN4622.pdf
Freescale.com Support Pages
URL
MMPF0200
Product Summary Page
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MMPF0200
Power Management Home Page
http://www.freescale.com/PMIC
Analog Home Page
http://www.freescale.com/analog
AN4751 Application Note Rev. 2.0 6/2015
Freescale Semiconductor, Inc.
5
Revision History
4
Revision History
Revision
Date
Description
1.0
2/2014
• Initial release
2.0
6/2015
• AN4530 is replaced by AN1902
AN4751 Application Note Rev. 2.0 6/2015
6
Freescale Semiconductor, Inc.
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© 2015 Freescale Semiconductor, Inc.
Document Number: AN4751
Rev. 2.0
6/2015
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