AN3820, i.MX25 Power Management Using the MC34704

Freescale Semiconductor
Application Note
AN3820
Rev. 1.0, 3/2009
i.MX25 Power Management Using the
MC34704
1
Overview
This document presents an analysis of using the MC34704
power management IC to supply a system based on the
i.MX25. The focus was done on the i.MX25 itself, considering
its needs in terms of voltage, current, and the power-up
sequence. The DDR and Flash memory requirements were
also taken into account. However, the MC34704 voltage
capabilities are not limited to the scenarios presented within
this document.
© Freescale Semiconductor, Inc., 2009. All rights reserved.
Contents
1 Overview
2 i.MX25 Requirements
2.1 Voltage Requirements
2.2 Power-up Sequencing
3 MC34704 PMIC
4 MC34704 and i.MX25 Compatibility
4.1 Power Breakdown
4.2 Power Sequencing
4.3 i.MX25 System Power Block Diagram
5 Software Considerations
5.1 I2C Communication Protocol
5.2 Power-up Command Sequence
5.3 Dynamic Voltage Scaling (DVS)
6 MC34704 Power Supply Design
6.1 Components Selection and Consideration
6.2 i.MX25 Power Management Schematic
6.3 Layout Example
6.4 Layout Consideration
7 Bill of Material
8 References
i.MX25 Requirements
2
i.MX25 Requirements
2.1
Voltage Requirements
Table 1 summarizes the approximate voltage requirements on i.MX25:
Table 1. i.MX25 Voltage Requirements
Parameter
Min.
Typ.
Max.
Units
1.15
1.34
1.52
V
1.38
1.45
1.52
V
VDD_BAT
1.15
-
1.55
V
I/O supply voltage GPIO1 (NFC, CSI, SDIO)
NVDD_GPIO1
1.75
-
3.6
V
I/O supply voltage GPIO2 (CRM, LCDC, JTAG, MISC)
NVDD_GPIO2
3.0
3.3
3.6
V
I/O supply voltage DDR (Mobile DDR mode) (EMI1, EMI2)
NVDD_MDDR
1.75
-
1.95
V
I/O supply voltage DDR (DDR2 mode) (EMI1, EMI2)
NVDD_DDR2
1.75
-
1.9
V
I/O supply voltage DDR (SDRAM mode) (EMI1, EMI2)
NVDD_SDRAM
1.75
-
3.6
V
USBPHY1 supply (HS)
(USBPHY1_VDDA_BIAS, USBPHY1_UPLL_VDD. USBPHY1_VDDA)
VDD_USBPHY1
3.17
3.3
3.43
V
USBPHY2 supply (FS)
(USBPHY2_VDD)
VDD_USBPHY2
3.0
3.3
3.6
V
OSC24M supply (OSC24M_VDD)
VDD_OSC24M
3.0
3.3
3.6
V
PLL supply (MPLL_VDD, UPLL_VDD)
VDD_PLL
1.4
-
1.65
V
Supply of touch screen ADC (NVCC_ADC)
VDD_TSC
3.0
3.3
3.6
V
VREF
2.5
VDD_tsc
VDD_tsc
FUSEVDD
-
3.6
-
Core supply voltage (at 266 MHz)
Symbol
QVDD
Core supply voltage (at 400 MHz)
Coin Battery
External reference of touch screen ADC
Fusebox program supply voltage (FUSE_VDD)
V
The i.MX25 processor consists of four major sets for the power supply voltage: digital logic domains (VDDn), I/O
power supplies (NVDDx), analog power supplies, and the fuse voltage supply (FUSEVDD). These voltage domains
can be grouped together, depending on the operating mode and needs of the I.MX processor, and the specific
application.
2.2
Power-up Sequencing
The external voltage regulators and power-on devices must provide the application’s processor with a specific
sequence of power and resets to ensure proper operation.
The recommended power-up sequences is as follows:
1.
2.
3.
4.
Assert the power on reset signal (POR = Low)
Turn on the Digital logic domain and I/O power supplies (VDDn and NVCCx)
Turn on all Analog power supplies and FUSEVDD
Negate the POR signal (POR = High)
i.MX25 Power Management Using the MC34704 , Rev. 1.0
2
Freescale Semiconductor
i.MX25 Requirements
POR = Low
I/O supplies
Digital Logic
1.8 V
3.3 V
NVDD_DDR NVDD_GPIO2
NVDD_GPIO1
1.34 V-1.45 V
QVDD
Analog Power Supplies
1.5 V
3.3 V
VDD_USBPHY1 VDD_PLL
VDD_USBPHY2
VDD_OSC24M
VDD_TSC
FUSEVDD
3.3 V
POR = High
Figure 1. i.MX25 Recommended Power-up Sequencing
Some of the voltage domain may be powered-up out of the recommended sequence if necessary. However, it is
important to power QVDD before the FUSEVDD, to avoid an unintentional fuse blown. Figure 1 shows the
recommended power-up sequence and power terminal grouping to achieve successful a power-up.
Noticed that since the maximum operating voltage for the core voltage group is 1.52 V, caution must be taken in
order to have a very tight regulation, and avoid overstressing or blowing the microprocessor terminals.
i.MX25 Power Management Using the MC34704 , Rev. 1.0
Freescale Semiconductor
3
MC34704 PMIC
3
MC34704 PMIC
The MC34704 family features both a 5-channel (MC34704B) and an 8-channel (MC34704A) power management
IC (PMIC), housed in a 56 pin QFN package with pin-to-pin compatibility between both ICs. It is meant to address
power management needs for various components and loads, with a target overall efficiency of > 89% at typical
loads.
The MC34704 accepts an input voltage from 2.7 V to 5.5 V, from various sources:
• 1-cell Li-Ion/Polymer (2.7 V to 4.2 V)
• 5.0 V USB supply or AC wall adapter
The total voltage supply range the IC accommodates is 2.7 V to 5.5 V.
Taking advantage of its buck/boost blocks, the MC34704 is a highly flexible power management unit. Output
voltages can be ranged between 0.6 V to 3.6 V, even if low voltage is supplied by the battery.
Additionally, the Dynamic Voltage Scaling (DVS) feature allows programming the output voltages (±20% of the
nominal voltage), with the I2C bus on the fly. Hence, the dynamic power consumption of the i.MX can be dramatically
reduced.
Features:
•
•
•
•
•
•
•
•
•
•
8 DC/DC switching regulators with up to ±2% output voltage accuracy
Programable Switching Frequency from 250 KHz - 1.0 MHz and 750 KHz to 2.0 MHz
Effective Efficiency from 85% to 95% on REG1 - REG5 and 65% to 78% on REG6 - REG8
DVS (Dynamic voltage scaling) on all regulators.
I2C programmability
OV/UV detection for each regulator
Over-current limit detection and short-circuit protection.
Thermal limit detection (except REG7)
Internal compensation for REG1, REG3, REG6, and REG8
True cutoff on all of the boost and buck-boost regulators.
i.MX25 Power Management Using the MC34704 , Rev. 1.0
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Freescale Semiconductor
MC34704 and i.MX25 Compatibility
4
4.1
MC34704 and i.MX25 Compatibility
Power Breakdown
QVDD
1.45 V / ~140 mA
REG3
Buck
5.0 V supply
REG2
Buck.Boost
VDDn, NVDD_GPIO, FUSEVDD
3.3 V
Inverter
Boost
REG7
REG4
Buck.Boost
VDD_DDR2
1.8 V
REG8
Boost
REG5
Buck.Boost
Other I/O
3.3 V
REG6
Boost
I 2C
interface
Available only
on the MC34704A
REG1
Boost
Reset
Driver
Soft start, UVLO
Thermal protection
RST (POR)
SS
FREQ
Figure 2. MC34704 block diagram
Figure 2 shows the block diagram for the MC34704 and the simplified voltage distribution compatible with the
i.MX25 processor. Complementary LDO regulators may be needed in specific applications. A 1.5 V LDO is at least
required to supply the PLL voltage.
Figure 3 provides the detailed Power Map for a complete solution utilizing the MC34704A as the core PMIC,
complemented with various LDOs to provide some application oriented voltages.
i.MX25 Power Management Using the MC34704 , Rev. 1.0
Freescale Semiconductor
5
MC34704 and i.MX25 Compatibility
5.0 V_USB_OTG
SWITCH
REG1 - 5.0 V
REG2 - 3.3 V
REG3 - 1.45 V
VMAIN
CAN_5VDD
NVCC_CRM
NVCC_CSI
NVCC_SDIO
NVCC_NFC
NVCC_JTAG
NVCC_MISC
NVCC_ADC
VDD_I2C
VDD_EMI_DATA
VDD_EMI_ADDR
OSC24M_VDD
USBPHY1_VDD
USBPHY2_VDD
QVDD
REG4 - 1.8 V
DDR_VDDx
NVCC_EMI1
NVCC_EMI2
REG5 - 3.3 V
VDD_LCD_IO VDD_SD2_IO
VDD_ESAI_IO GPS_3V3
VDD_CSI_IO AUDIO CODEC
VDD_SIM_IO
MC34704
LDO - 1.5 V
MPLL_VDD
UPLL_VDD
WL_1V5ANA
Figure 3. i.MX25 Power Detailed Power Map
i.MX25 Power Management Using the MC34704 , Rev. 1.0
6
Freescale Semiconductor
MC34704 and i.MX25 Compatibility
4.2
Power Sequencing
RST=Low
REG3
VDDQ
REG2
VDDn, NVCCx, USBPHYx
REG4
1.5 V LDO
DDR_VDD, NVCC_EMIx
UPLL_VDD, MPLL_VDD
RST=High
REG1
5 V_I/OS
REG5
3.3 V I/OS
Figure 4. MC34704 power sequencing
The MC34704 provides standalone voltage on REG 2, 3, and 4, right after battery insertion or ON/OFF asserting.
The LDO providing the 1.5 V is supplied from the main voltage supply (DC_5.0 V or USB). However, the output
voltage is enabled with the REG2 output in order to assure proper sequencing. REG1 and REG5 are controlled via
I2C, and can be turned ON/OFF once the RST signal (POR) on the MC34704 is set high.
Note that even though this structure does not perfectly, follow the
power-up sequence, it has been proven to work correctly, and may
be counted as one of the recommended power-up sequences for the
i.MX25 processor.
REG2, 3, and 4 can only be powered off in two ways:
1. By a hardware power-off, holding down the ON/OFF terminal for a specific amount of time
(programmable).
2. By a soft power-off, by setting high the ALLOFF bit via I2C.
Note that these two processes will shut down the device completely,
including REG1, REG5, 1.5 V_LDO, and I2C communication. To
bring the device back up, generate a falling edge on the ON/OFF
terminal (commonly using a push button.)
i.MX25 Power Management Using the MC34704 , Rev. 1.0
Freescale Semiconductor
7
MC34704 and i.MX25 Compatibility
t = SS
t = SS
t = SS
REG1
REG5
REG2
REG4
1.5V LD O
REG3
RST
t = 10ms
Figure 5. System Power-up Waveform
Figure 5 shows the power sequence waveforms during a Power-up cycle.
Note that REG1 through REG5 on the MC34704 ramp-up in a
pre-defined soft start. The soft start is hardware configured and its
value is selectable among 0.5, 2.0, 8.0, and 32 ms. The 1.5 V LDO
waveform may reach its regulation point before or after REG4,
depending on the selected soft start.
4.3
i.MX25 System Power Block Diagram
I.MX25 Peripherals
5.0V_I/O
VMAIN
VOUT1
3.3V_I/O
VOUT5
VIN
PVIN2
PVIN3
PVIN4
PVIN5
VOUT3
VDDQ
VOUT2
VDDn
NVCCx
USBPHYx
VOUT4
NVCC_EMIx
PLL_VDD
I2C
AGND
RST
I2C
POR
i.MX25
MC34704
VOUT_LDO
xGND
DDR_VDD
1.5 V LDO
DDR2 MEM
Figure 6. i.MX25 Power Pins
i.MX25 Power Management Using the MC34704 , Rev. 1.0
8
Freescale Semiconductor
Software Considerations
5
Software Considerations
The MC34704 is programmed through a plain I2C protocol. The I.MX processor should include a firmware driver to
translate the controlling instructions into I2C commands, to allow register writing and flag reading for communication
acknowledgement. Such driver structure is not defined in this document. It discusses only the software portion that
concerns the MC34704, as well as the I2C commands needed to interact with the MC34704.
5.1
I2C Communication Protocol
The MC34704 is able to operate in two I2C modes:
•
•
Non-accurate mode: which uses a single repetition of register address and data to be read or written during
one cycle. This mode is used as the default by the MC34704.
Accurate mode: where each Address and Data word is sent twice to make sure the information written or
read is valid.
To simplify the I2C protocol, only non-accurate mode will be discussed in this document.
Figure 7 and Figure 8 show an example of a bits stream for an I2C writing and reading command respectively.
7 bit Physical Address +
(w) bit
ACK
Sub-Address
(MSB=0)
ACK
Data
ACK
1010100 + 0
0
0XXXXXXX
0
XXXXXXXX
0
ACK
Start Bit
ACK
ACK End Bit
SDA
1 0 1 0 1
0 0 0
0 0 0 0 0 0 1
0
0 0 0 0 1 1 1 1
SCL
Figure 7. Writing Sequence I2C Bit Stream.
7 bit Physical Add +
(w) bit
ACK
Sub-Address
(MSB=1)
ACK
RS
Physical Add
+ (r) bit
Data Read
ACK
1010100 + 0
0
1XXXXXXX
0
1
1010100+1
XXXXXXXX
0
Start Bit
ACK
ACK
ACK
SDA
1 0 1 0 1 0 0 0
0
0 0 0 0 0 1
0
RS
1 0 1 0 1 0 0
1 0 0 0 0
1 1 1 1
SCL
Figure 8. Reading Sequence I2C Bit Stream.
By default, the MC34704’s physical address is set to 0x54 in a 7-bit format. The extra bit to complete the 8-bit
indicates the reading or writing mode as shown in Figure 7 and Figure 8. After each byte read or sent, the MC34704
answers with an acknowledge bit, indicating the bite was transferred successfully.
i.MX25 Power Management Using the MC34704 , Rev. 1.0
Freescale Semiconductor
9
Software Considerations
Figure 9 shows the basic I2C register table, including both configuration and fault notification registers for each
regulator on the MC34704.
Figure 9. Basic I2C Register Table
5.2
Power-up Command Sequence
The Power on process is straight forward:
•
•
If there is a battery insertion, REG3, 2, and 4 will turn on in that order, enabling I2C communication protocol
as well as the i.MX processor power on sequence. The MC34704 will set the COLDF flag to acknowledge
that power on was a result of a battery insertion. During the power on process, the MPU should
acknowledge that power-up was a result of a battery insertion, and then send an ALLOFF I2C command to
disable the power supply and shut down until a desired hardware power on is present.
If the ON/OFF terminal detects a falling edge, then the MC34704 starts a power on cycle ramping up of
regulator 3, 2, and 4. The COLDF bit is not set high, and so when the i.MX processor reads this register, it
acknowledges it is an actual power up, and starts a full power on sequence. By now, the PMIC is providing
i.MX25 Power Management Using the MC34704 , Rev. 1.0
10
Freescale Semiconductor
Software Considerations
1.45 V, 1.8 V, 3.3 V, and 1.5 V, which is dispensed by the extra LDO, and the processor can administer the
following configuration commands:
— REG2, REG3, and REG4 OV/UV response
— REG1 and REG5 OV/UV response
— REG5 Soft start timing (if desired)
Now the processor can send a REG5 ON/OFF instruction via I2C, when the 3.3 V peripherals rail is required,
and also enable REG1 if the 5.0 V voltage rail is needed. Subsequently, all voltage rails can be dynamically
scaled (DVS) up or down using the 4 bits (4:1) from the REGxSET register.
The i.MX processor can send an I2C power-off command for REG1 or REG5 independently or a complete
shutdown by setting the ALLOFF bit on the GENERAL2 register when required.
•
•
5.3
Dynamic Voltage Scaling (DVS)
All regulators on the MC34704 allow voltage scaling, programmable through I2C, Table 2 defines the DVS capability
for each output as well as the I2C register corresponding to each.
Table 2. MC34704 DVS Definition
REGULATOR
SCALING WINDOW
SCALING STEP
I2C REGISTER
ADDRESS
REGISTER BITS
REG1
-10% to 10%
2.5%
VGSET1
0x04
[4:1]
REG2
-17.5% to 17.5%
2.5%
REG2SET1
0x06
[4:1]
REG3
-17.5% to 17.5%
2.5%
REG3SET1
0x08
[4:1]
REG4
-10% to 10%
1.0%
REG4SET1
0x0A
[4:1]
REG5
-17.5% to 17.5%
2.5%
REG5SET1
0x0C
[4:1]
For REG3, the MC34704 provides fine DVS adjustment on 0.5% steps, to achieve voltage scaling below the -17.5%
windows allowed with the default DVS. The following sequence should be followed to assure proper scaling without
activating OV/UV fault flags.
1.
2.
3.
4.
5.
Set the REG3SET1 register (ADD 0x08) to 0x10.
Mask the fault response by writing 0x80 to ADD 0x22.
Write a 0xAD to REG3DAC (ADD 0x49).
Decrease REG3DAC by one until reaching the desired value on REG3.
Clear the fault response masking by writing 0x00 to ADD 0x22.
i.MX25 Power Management Using the MC34704 , Rev. 1.0
Freescale Semiconductor
11
MC34704 Power Supply Design
6
6.1
6.1.1
MC34704 Power Supply Design
Components Selection and Consideration
Inductor Selection
VG serves as the internal supply for all gate drivers within the MC34704. L1 dimensions depend directly on the
inductance value and the saturation current ISAT. Chose an inductor with inductance value between 2.2 to 4.7 μH,
and an ISAT around 150 mA.
To select Inductors L2 - L5, choose inductance values between 3.0 to 4.7 μH, with an ISAT of approximately twice
the maximum current to be demanded from each regulator.
Note: make sure to use power inductors and not choke inductors for
these components. Shielded “Drum Core” inductors with low DCR
are recommended to improve the performance of the MC34704.
6.1.2
Capacitor and Resistor selection
Choose capacitors with at least twice the voltage rating as the maximum voltage that the capacitor will be exposed
to. For output capacitors, use capacitance values from 10 to 22 μF.
Resistors are straightforward to choose. The important thing to consider, while calculating the output voltage of each
regulator, is to take into consideration the resistor accuracy , especially on those voltage rails where the output
voltage is close to the maximum voltage rating of the I.MX terminal. A miscalculation of the resistor accuracy may
cause the output voltage to go slightly above the maximum allowed, overstressing or damaging the processor
terminal in the application. Use 1% or smaller tolerance resistors to have good control of output voltage values.
Note: for more details on external component calculation, please
refer to the MC34704 data sheet that can be found at
www.freescale.com.
i.MX25 Power Management Using the MC34704 , Rev. 1.0
12
Freescale Semiconductor
MC34704 Power Supply Design
6.2
i.MX25 Power Management Schematic
U12
VOUT8
VOUT1/NC0
23
VG
22
0 OHM
REG8
30mA
Boost
SW8
2
D5
MBR120VLSFT1G
2
20
REG1/VG
500mA
Boost
SW1
21
1
C176
47UF
2
1
1
1
19
REG1_5V
for LCD backlight
R286
C167
47UF
BKLT_5V_60MA_A
VIN
2
3.0UH L21
BT8
17
FB8
53
PVIN5
PVIN2
46
54
BT5D
BT2D
45
52
SW5D
SW2D
47
VOUT2
48
24
VIN
C170
10.0uF
C173
68PF
49
BT2U
42
FB2
44
R265
2.7K
1%
C155
1uF
55
BT5U
FB5
R322
33.0K
C172
68PF
R333
33.0K
1%
C130
10PF
C164
10PF
1%
GND
R334
68K
1%
5
SW2U
C138
1uF
1
R310
15K
1%
SW5U
RS-
50
L19
4.7UH
1
R309
68K
1%
REG2
500mA
Buck-Boost
0.02 OHM
RC0805
C171
22UF
GND
REG5
500mA
Buck-Boost
2
R253
2.7K
CPU_3.3V
R291
1
L16
4.7UH
4
VOUT5
1
C165
22UF
for Digital and
Analog 3.3V to CPU
REG2_3V3
RS+
51
R318
for IO and Peripherial
on CPU board
C124
1uF
2
for IO and Peripherial on Per board
REG5_3V3
U25
MAX4372FEUK+
VCC
C186
1uF
OUT
BT1
VMAIN
3
C175
10.0uF
0 OHM
C180
1uF
18
2
VIN
C166
10.0uF
C163
1uF
R319
15K
1%
GND
C177
1000PF
C181
1000PF
56
VIN
COMP5
3
PVIN4
2
BT4D
C125
10.0uF
COMP2
43
PVIN3
11
BT3
10
CURRENT_MEAS_CPU3V3
VIN
C135
10.0uF
C182
0.01uF
C132
0.01uF
12
L20
4.7UH
for MX25 Core
CORE_1.45V
REG3_1V45
VOUT3
R262
13
R312
34.0K
1%
C156
150PF
5
FB3
14
RS+
FB4
RS-
BT4U
8
1%
C134
22UF
R320
12.7K
C117
5PF
OUT
VMAIN
C184
1uF
R276
62.0K
1%
7
0.02 OHM
RC0805
R313
18K
1%
SW4U
4
6
REG3
550mA
Buck
U28
MAX4372FEUK+
VCC
REG4
300mA
Buck-Boost
GND
RS-
VCC
OUT
GND
SW3
C185
0.01uF
C161
120PF
3
2
1
VOUT4
1
5
R331
680 OHM
1%
RS+
U31
MAX4372FEUK+
SW4D
5
L22
4.7UH
R325
68K
1%
4
GND
4
VMAIN
3
C151
22UF
2
RC0805
1
0.02 OHM1%
1
REG4_1V8
R264
2
for DDR2
DDR_1.8V
AGND
2
AGND
AGND
9
COMP4
C160
1uF
CURRENT_MEAS_CORE
VIN
AGND
CURRENT_MEAS_DDR
R304
10K
GND
32
VOUT7/PGND2
ONOFF
41
1
0 OHM
GND
2
R328
ON_OFF
REG2_3V3
R305
1.0K
1%
DRV7/NC3
RST
27
C133
0.1UF
CC0201
1.5V
1
VIN
3
EN
REG2_3V3
C150
1uF
10K
GND
R314
2
VOUT
5
ADJ
4
GND
R335
4.99K
1%
1.5V
VDDI
39
output,2.5V
GND
R315
10K
C153
2.2UF
D6
GREEN
DNP
1
REG7
60mA
IVTER
U23
VIN
POR_B
2
31
R323
10K
GND
GND
RT9179
GND
R336
18K
1%
Vout=(1+4.99K/18K)x1.175=1.5V
GND
C187
0.01uF
30
FB7/AGND1
29
VREF7/NC2
28
COMP7/NC1
36
FREQ
16
phase control,default 2MHz
SS
15
soft start timng
AGND
37
SCL
25
SDA
26
R327
10K
DNP
C144
1uF
R330
10K
DNP
VOUT6/PGND5
AGND
35
34
33
SW6/PGND4
REG6
60mA
Boost
1
0 OHM
1
0 OHM
LION
40
VIN
VIN
38
VIN
PGND
57
BT6/NC4
FB6/AGND3
2
R306
2
R307
I2C1_CLOCK <8,9,12>
I2C1_DATA <8,9,12>
VMAIN
0 OHM
R332
C183
1uF
MC34704
AGND
Figure 10. MC34704 + 1.5 V LDO Schematic
i.MX25 Power Management Using the MC34704 , Rev. 1.0
Freescale Semiconductor
13
MC34704 Power Supply Design
6.3
Layout Example
The following layout is an implementation of the MC34704 interacting with the i.MX25 in the PDK developed by
Freescale. The layout stacking is defined based upon the i.MX requirements of a 10 layer PCB. Layer 2 and 8
correspond to GND planes, while layers 5 and 6 are power planes. For simplification, these layers will not be
presented, since they do not provide significant information about the power management design. The remaining
layers are dedicated to signal and voltage rail routing, and are shown in Figure 11 through Figure 17.
This layout design has been cropped to show components placement and routing, relating to the power supply
design with the MC34704 (U10). However, some extra components may be shown as part of the complete system
design using the i.MX25 chip.
6.3.1
Top Layer
Figure 11. MC34704 Top Layer PCB Layout Implementation.
i.MX25 Power Management Using the MC34704 , Rev. 1.0
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MC34704 Power Supply Design
6.3.2
Internal Layer 1 (Signal)
Figure 12. MC34704 Implementation Internal Layer 1
i.MX25 Power Management Using the MC34704 , Rev. 1.0
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15
MC34704 Power Supply Design
6.3.3
Internal Layer 2 (Signal)
Figure 13. MC34704 Implementation Internal Layer 2
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MC34704 Power Supply Design
6.3.4
Internal Layer 3 (GND + Signals)
Figure 14. MC34704 Implementation Internal Layer 3
i.MX25 Power Management Using the MC34704 , Rev. 1.0
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17
MC34704 Power Supply Design
6.3.5
Internal Layer 4 (Signal)
Figure 15. MC34704 Implementation Internal Layer 4
i.MX25 Power Management Using the MC34704 , Rev. 1.0
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MC34704 Power Supply Design
6.3.6
Bottom Layer
Figure 16. MC34704 Implementation Bottom Layer
i.MX25 Power Management Using the MC34704 , Rev. 1.0
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19
MC34704 Power Supply Design
6.3.7
All layers combination
Figure 17. MC34708 All Layers Displayed
6.4
•
•
•
•
•
•
•
Layout Consideration
Create a ground plane layer and tie it to ground signals with vias.
Place test vias as close to the IC as possible, to ensure a good measurement values.
PVIN, VIN, and VOUT signals have to be tracked with a wide and straight copper area.
Never trace the feedback signal in parallel to the SW signal.
Ensure the SW inductor is placed as close to its pads as possible.
The SW track must be as thin and short as possible.
Make sure the I/O connectors are capable of managing the load current.
i.MX25 Power Management Using the MC34704 , Rev. 1.0
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Bill of Material
7
Bill of Material
Table 3. Simplified Bill of Material
Reference
Description(1)
Quantity
Part
C14
1
0.1 μF
CAP CER 0.1 μF 6.3 V 10% X5R 0201
C29, C96, C97, C100
4
0.01 μF
CAP CER 0.01 μF 25 V 10% X7R 0402
C74, C75
2
47 μF
CAP CER 47 μF 16 V 10% X5R 1210
C76, C80, C81, C85, C86,
C107, C108, C146
8
1.0 μF
CAP CER 1.0 μF 25 V 10% X7R 0603
C77, C78, C79, C94, C95
5
10.0 μF
CAP CER 10 μF 16 V 10% X7R 0805
C82, C83, C98, C99
4
22 μF
CAP CER 22 μF 6.3 V 10% X5R 0805
C84, C87
2
68 PF
CAP CER 68 PF 50 V 5% C0G 0603
C90, C91
2
10 PF
CAP CER 10 PF 50 V 1% C0G 0603
C92, C93
2
1000 PF
CAP CER 1000 PF 25 V 5% C0G CC0603
C101
1
120 PF
CAP CER 120 PF 50 V 5% C0G 0603
C102
1
5.0 PF
CAP CER 5.0 PF 50 V 0.25 PF C0G 0805
C104
1
150 PF
CAP CER 150 PF 50 V 5% C0G 0603
C142
1
2.2 μF
CAP CER 2.2 μF 6.3 V 20% X5R 0402
D2
1
MBR120VLSFT1G
D3
1
GREEN
LED GREEN GAP ON GAP SM 0603
L11
1
3.0 μH
IND PWR 3.0 [email protected] KHZ 3.0 A 30% SMT
L12, L13, L14, L15
4
4.7 μH
IND PWR 4.7 [email protected] MHZ 1.2 A 20% SMT
R234, R268, R271, R272,
R273, R274
6
10 K
RES MF 10 K 1/16 W 5% 0402
R247, R248
2
2.7 K
RES MF 2.70 K 1/10 W 1% 0603
R249, R251, R261
3
68 K
RES MF 68 K 1/10 W 1% 0603
R250
1
1.0 K
RES MF 1.0 K 1/16 W 1% 0402
R254, R257
2
15 K
RES MF 15.0 K 1/10 W 1% 0603
R255, R256
2
33.0 K
R259
1
680 OHM
R266
1
34.0 K
RES MF 34.0 K 1/10 W 1% 0603
R267
1
62.0 K
RES MF 62.0 K 1/10 W 1% 0603
R285
1
4.99 K
RES MF 4.99 K 1/10 W 1% 0603
DIODE SCH RECT 1.0 A 20 V SMT
RES MF 33 K 1/10 W 1% 0603
RES MF 680 OHM 1/10 W 1% 0603
i.MX25 Power Management Using the MC34704 , Rev. 1.0
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21
Bill of Material
Table 3. Simplified Bill of Material
Reference
Description(1)
Quantity
Part
R287, R298
2
18 K
RES MF 18.0 K 1/10 W 1% 0603
R302
1
12.7 K
RES MF 12.7 K 1/10 W 1% 0603
U10
1
MC34704
IC LIN DCDC PWR SWT 2.0 MHZ 2.7-5.5 V QFN56
U18
1
RT9179(1)
IC VREG LDO ADJ 1.175-4.5 V 300 MA 3-5.5 V
SOT-23-5
Notes:
1. Freescale does not assume liability, endorse, or warrant components from external manufacturers referenced in
drawings or tables. While Freescale offers component recommendations, it is the customer’s responsibility to validate
their application.
i.MX25 Power Management Using the MC34704 , Rev. 1.0
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Freescale Semiconductor
References
8
References
1. MC34704 data sheet MC34704
2. i.MX25 data sheet
3. i.MX25 PDK
i.MX25 Power Management Using the MC34704 , Rev. 1.0
Freescale Semiconductor
23
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