74HCT595

74HCT595
8-BIT SHIFT REGISTER WITH 8-BIT OUTPUT REGISTER
Description
Pin Assignments
The 74HCT595 is an high speed CMOS device that is designed to
be pin compatable with 74LS low power Schottky types.
An eight bit shift register accpets data from the serial input (DS)
on each positive transition of the shift register clock (STCP).
When asserted low the reset function (MR) sets all shift register
Preliminary
values to zero and is indepent of all clocks.
Data from the input serial shift register is placed in the output
register with a rising pulse on the storages resister clock (SHCP).
With the output enable (OEሻ asserted low the 3-state outputs Q0Q7 become active and present th
All registers capture data on rising edge and change output on the
falling edge. If both clocks are connected together the input shift
register is always one clock cycle ahead of the output register.
Features
Applications
•
Supply Voltage Range from 4.5V to 5.5V
•
General Purpose Logic
•
Sinks or sources 8mA at VCC = 4.5V
•
Serial to Parallel Data conversion
•
CMOS low power consumption
•
Capture and hold data for extended periods of time.
•
Schmitt Trigger Action at All Inputs
•
Allow simple serial bit streams from a microcontroller to
•
Inputs accept up to 6.0V
•
ESD Protection Tested per JESD 22
control as many peripheral lines as needed.
•
Exceeds 200-V Machine Model (A115-A)
o
Computer peripherals
Exceeds 2000-V Human Body Model (A114-A)
o
Appliances
Exceeds 1000-V Charged Device Model (C101C)
o
Industrial control
•
Latch-Up Exceeds 250mA per JESD 78, Class II
•
Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
•
Halogen and Antimony Free. “Green” Device (Note 3)
Notes:
Wide array of products such as:
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free,
"Green" and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl)
and <1000 ppm antimony compounds.
Click for Ordering Information
74HCT595
Document number: DS35493 Rev. 3 - 2
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74HCT595
Preliminary
Pin Descriptions
Functional Diagram
Pin Number
Pin Name
Description
1
Q1
Parallel Data Output 1
2
Q2
Parallel Data Output 2
3
Q3
Parallel Data Output 3
4
Q4
Parallel Data Output 4
5
Q5
Parallel Data Output 5
6
Q6
Parallel Data Output 6
7
Q7
8
GND
Parallel Data Output 7
Ground
9
Q7S
Serial Data Output
10
MR
Master Reset Input
11
SHCP
12
STCP
13
OE
Output Enable Input
14
DS
Serial Data Input
15
Q0
Parallel Data Output 0
16
Vcc
Supply Voltage
Shift Register Clock Input
Storage Register Clock Input
Logic Diagram
STAGE 0
DS
D
STAGES 1 TO 6
Q
D
STAGE 7
Q
D
Q
FF0
CP
Q7S
FF7
CP
R
R
SHCP
MR
D
Q
D
LATCH
Q
LATCH
CP
CP
STCP
OE
Q0
74HCT595
Document number: DS35493 Rev. 3 - 2
Q1 Q2 Q3
Q4 Q5 Q6
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Q7
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74HCT595
Functional Description and Timing Diagram
Preliminary
Control
Input
Output
Function
SHCP
STCP
OE
MR
DS
Q7S
Qn
X
X
L
L

L
NC
X
↑
L
L

L
L
Empty shift register transferred to storage register
X
X
H
L

L
Z
Shift register remains clear; All Q ouputs in Z state
↑
X
L
H

Q6S
NC
X
↑
L
H

NC
QnS
↑
↑
L
H

Q6S
QnS
Low-level asserted on MR clears shift register
Storage register is unchanged
HIGH is shifted into first stage of Shift Register Contents of each
register shifted to next register
The content of Q6S has been shifted to Q7S and now appears on
device pin Q7S
Contents of shift register copied to storage register
With output now in active state, the storage resister contents
appear on Q outputs
Contents of shift register copied to output register then shift register
shifted.
H=HIGH voltage state
L=LOW voltage state
↑=LOW to HIGH transition
X= don’t care – high or low (not floating)
NC= No change
Z= high-impedance state
74HCT595
Document number: DS35493 Rev. 3 - 2
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74HCT595
Absolute Maximum Ratings (Note 4) (@TA = +25°C°C, unless otherwise specified.)
Symbol
ESD HBM
ESD CDM
ESD MM
VCC
Preliminary
VI
Description
Rating
Unit
Human Body Model ESD Protection
2
kV
Charged Device Model ESD Protection
1
kV
200
V
Supply Voltage Range
-0.5 to +7.0
V
Input Voltage Range
-0.5 to +7.0
V
Machine Model ESD Protection
Vo
Voltage applied to output in high or low state
-0.3 to VCC +0.5
V
IIK
Input Clamp Current
VI < -0.5V
-20
mA
IIK
Input Clamp Current
VI > Vcc +0.5V
20
mA
IOK
Output Clamp Current
VO < -0.5V
-20
mA
IOK
Output Clamp Current
VO > VCC + 0.5V
20
mA
IO
Continuous output current
ICC
Continuous current through VCC or GND
IGND
Q7 standard output
+/- 25
mA
Qn bus driver outputs
+/- 35
mA
70
mA
Continuous current through VCC or GND
-70
mA
Operating Junction Temperature
-40 to +150
°C
TSTG
Storage Temperature
-65 to +150
°C
PTOT
Total Power Dissipation
500
mW
TJ
Note:
4. Stresses beyond the absolute maximum may result in immediate failure or reduced reliability. These are stress values, and device
operation should be within recommend values.
Recommended Operating Conditions (Note 5)
Symbol
Conditions
Min
Max
Supply Voltage

4.5
5.5
V
VI
Input Voltage

0
5.5
V
VO
Output Voltage
VCC
Parameter
(@TA = +25°C°C, unless otherwise specified.)
Unit
Active Mode
0
VCC
V
t/V
Input transition rise or fall rate
VCC = 4.5V to 5.5V

100
ns/V
TA
Operating free-air temperature

-40
125
°C
Note:
5. Unused inputs should be held at Vcc or Ground.
74HCT595
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74HCT595
Electrical Characteristics (@TA = +25°C°C, unless otherwise specified.)
Preliminary
Symbol
Parameter
Test Conditions
VCC
TA = +25°C°C
TA = -40°C°C to
+85°C°C
TA = -40°C°C to
+125°C°C
Min
Typ
Max
Min
Max
Min
Max
Unit
VIH
High-Level
Input Voltage

4.5V to
5.5V
2.0


2.0

2.0

V
VIL
Low-Level
Input Voltage

4.5V to
5.5V


0.8

0.8

0.8
V
IOH = -20μA
High-Level
Output Voltage All outputs
4.5V
4.4
4.5

4.4

4.4

Q7S output
IOH = -4mA
4.5V
3.84
4.32

4.32

3.7

Qn Bus
Outputs
IOH = -6.0mA
3.7
4.32

4.32

3.7

VOH
VOL
II
IOZ
ICC
IOL = 20μA
Low-Level
Output Voltage All outputs
4.5V

0
0.1

0.1

0.1
Q7S output
IOL = 4mA
4.5V

0.15
0.33

0.33

0.4
Qn Bus
Outputs
IOL = 6.0mA
4.5V

.016
0.33

0.33

0.4
5.5V


±0.1

±1

±1
μA
5.5V


±5

±5

± 10
μA
5.5V


8.0

80

160
μA
4.5V to
5.5V

100
450

450

490
μA
5.5V

4
10

10

10
pF
Input Current
OFF-state
output current
Supply Current
VI =GND to
5.5V
Qn internal high or
low.
Ci
VI = GND or VCC
IO=0
VI = Vcc -2.1V
Supply Current
IO=0
per Input
Input
Capacitance
V
Vo=Vcc or Gnd
Additional
∆ICC
4.5V
V
Vi = VCC or GND
Operating Characteristics (@TA = +25°C°C, unless otherwise specified.)
Parameter
Cpd
Power dissipation
capacitance
74HCT595
Document number: DS35493 Rev. 3 - 2
Test Conditions
f = 1 MHz all outputs switching-no load
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VCC = 5V
TYP
42
Unit
pF
July 2013
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74HCT595
Switching Characteristics
Symbol /
Parameter
fMAX
Maximum
Frequency
Pins
Test
Conditions
VCC
Figure 1
SHCP or
STCP
-40°C°C to
+85°C°C
TA = +25°C°C
-40°C°C to
+125°C°C
Min
Typ.
Max
Min
Max
Min
Max
4.5V to 5.5V
30
52

24

20

Figure 1
4.5V to 5.5V
16
6

20

24

Unit
MHz
Preliminary
SHCP
HIGH or
LOW
tW
STCP
Pulse Width
HIGH or
LOW
Figure 1
4.5V to 5.5V
16
5

20

24

MR LOW
Figure 1
4.5V to 5.5V
20
8

25

30

DS to SHCP
Figure 1
4.5V to 5.5V
16
5

20

24

ns
SHCP to
STCP
Figure 1
4.5V to 5.5V
16
8

20

24

ns
DS to SHCP
Figure 1
4.5V to 5.5V
3
-2

3

3

ns
MR to SHCP
Figure 1
4.5V to 5.5V
10
-7

13

15

ns
SHCP to
Q7S
Figure 1
4.5V to 5.5V

25
42

53

63
ns
4.5V to 5.5V

24
40

50

60
ns
4.5V to 5.5V

23
40

50

60
ns
4.5V to 5.5V

21
35

44

53
ns
4.5V to 5.5V

18
30

38

45
ns
ns
tSU
Set-up Time
tH
Hold Time
tREC
Recovery Time
CL=50pF
tPD
Propagation
Delay
STCP to Qn
MR to Q7S
tEN
Enable Time
tDIS
Disable Time
OE to Qn
OE to Qn
Figure 1
CL=50pF
Figure 1
CL=50pF
Figure 1
CL=50pF
Figure 1
CL=50pF
74HCT595
Document number: DS35493 Rev. 3 - 2
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74HCT595
Preliminary
Parameter Measurement Information
4.5V to 5.5V
Vload
Open
tPLZ/tPZL
VCC
tPHZ/tPZH
GND
VM
Inputs
VCC
TEST
tPLH/tPHL
CL
VI
tr/tf
Input
Output
3.0V
3ns
1.5V
VCC/2
15pF, 50pF
1/f MAX
tW
Vl
Input
VM
VM
0V
MR
trec
Voltage Waveform
Pulse Duration and Recovery Time
Voltage Waveform
Set-up and Hold Times
Voltage Waveform
Propagation Delay Times
Inverting and Non Inverting Outputs
Voltage Waveform
Enable and Disable Times
Notes: A . Includes test lead and test apparatus capacitance.
B. Output Waveform 1 depends on the internal QN node being low and behaves in this manner based on OE pin.
Output Waveform 2 depends on the internal QN node being high and behaves in this manner based on OE pin.
C. All pulses are supplied at pulse repetition rate ≤ 10 MHz
D. Inputs are measured separately one transition per measurement
E. tPLH and tPHL are the same as tPD
Figure 1. Load Circuit and Voltage Waveforms
74HCT595
Document number: DS35493 Rev. 3 - 2
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74HCT595
Preliminary
Ordering Information
Device
Package Code
7” Tape and Reel(Note 6)
Packaging
Quantity
Part Number Suffix
74HCT595S16-13
S16
SO-16
2500/Tape & Reel
-13
74HCT595T16-13
T16
TSSOP-16
2500/Tape & Reel
-13
Notes:
6. . The taping orientation is located on our website at http://www.diodes.com/datasheets/ap02007.pdf
Marking Information
(1) SO-16, TSSOP-16
74HCT595
Document number: DS35493 Rev. 3 - 2
Part Number
Package
74HCT595S16
SO-16
74HCT595T16
TSSOP-16
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74HCT595
Package Outline Dimensions (All Dimensions in mm)
Please see AP02002 at http://www.diodes.com/datasheets/ap02002.pdf for latest version.
(1)
Package Type: SO-16
H
E
Gauge Plane
L
Preliminary
SO-16
Dim
Min
Max
A
1.40
1.75
A1
0.10
0.25
A2
1.30
1.50
B
0.33
0.51
C
0.19
0.25
D
9.80
10.00
E
3.80
4.00
e
1.27 Typ
H
5.80
6.20
L
0.38
1.27
Θ
0
8
All Dimensions in mm

Detail ‘A’
D
A
A2
e
B
(2)
A1
C
Detail ‘A’
Package Type: TSSOP-16
TSSOP-16
E/2
SEE DETAIL 'A'
E1
E
Y
Dim
Min
Max
A
-
1.08
-
A1
0.05
0.15
-
A2
0.80
0.93
-
b
0.19
0.30
-
c
0.09
0.20
-
D
4.90
5.10
-
E
E1
X
6.40 BSC
4.30
e
PIN 1
L
0.45
A2
R1
D
R
C
L2
GAUGE
PLANE
A
L
SEATING PLANE
A1
74HCT595
Document number: DS35493 Rev. 3 - 2
L1
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
-
0.75
-
1.00 REF
L2

Ø0.760Depth0.050±0.02
4.50
0.65 BSC
L1
x)
b
e
Typ
0.25 BSC
R
0.09
-
-
R1
0.09
-
-
X
-
-
1.350
Y
-
-
1.050
Θ
0°
8°
-
Θ1
5°
15°
-
Θ2
0°
-
-
All Dimensions in mm
July 2013
© Diodes Incorporated
74HCT595
Suggested Pad Layout
Please see AP02001 at http://www.diodes.com/datasheets/ap02001.pdf for the latest version.
Package Type: SO-16
X1
Preliminary
Y1
Y
Pin 1
C
X
Dimensions
C
X
X1
Y
Y1
Value (in mm)
1.270
0.670
9.560
1.450
6.400
Package Type: TSSOP-16
X1
Dimensions
C
X
X1
Y
Y1
Y1
Y (16x)
Value (in mm)
0.650
0.350
4.900
1.400
6.800
1
X (16x)
74HCT595
Document number: DS35493 Rev. 3 - 2
C
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74HCT595
IMPORTANT NOTICE
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INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
(AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION).
Preliminary
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without further notice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the
application or use of this document or any product described herein; neither does Diodes Incorporated convey any license under its patent or
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final and determinative format released by Diodes Incorporated.
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Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without the
express written approval of the Chief Executive Officer of Diodes Incorporated. As used herein:
A. Life support devices or systems are devices or systems which:
1. are intended to implant into the body, or
2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the
labeling can be reasonably expected to result in significant injury to the user.
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the
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Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or systems,
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its representatives against any damages arising out of the use of Diodes Incorporated products in such safety-critical, life support devices or
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74HCT595
Document number: DS35493 Rev. 3 - 2
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