Freescale Semiconductor Application Note AN4604 Rev. 2.0, 5/2013 Interfacing the MC34709 with the i.MX53 Microprocessor 1 Purpose The present document shows the reader how to supply and interface the i.MX53 with the Freescale MC34709 PMIC, as well as showing an example of the system implementation at schematic level. 2 Introduction The MC34709 is a multi-channel power management IC prepared to supply power to various members of the i.MX family, including the i.MX53 processor. It provides all require voltage domains as well as configurable power-up sequence to fulfill the processor requirements. Freescale analog ICs are manufactured using the SMARTMOS process, a combinational BiCMOS manufacturing flow that integrates precision analog, power functions and dense CMOS logic together on a single cost-effective die. © Freescale Semiconductor, Inc., 2013. All rights reserved. Contents 1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 i.MX53 Microprocessor Overview . . . . . . . . 2 4 MC34709 Overview . . . . . . . . . . . . . . . . . . . . 9 5 Interfacing the i.MX53 with the MC34709. . 13 6 Application Example . . . . . . . . . . . . . . . . . . 18 7 Migrating from MC34708 to MC34709 . . . . 22 8 References . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9 Revision History . . . . . . . . . . . . . . . . . . . . . 30 i.MX53 Microprocessor Overview 3 i.MX53 Microprocessor Overview The i.MX53 multimedia applications processors constitute Freescale Semiconductor's latest addition to a growing family of multimedia-focused products offering high performance processing optimized for lowest power consumption. The i.MX53 processors features Freescale's advanced implementation of the ARM Cortex-A8™ core, which operates at speeds as high as 1.0 GHz, and interfaces with DDR2-800, LVDDR2-800 or DDR3-800 DRAM memories. This device is suitable for applications such as the following: • • • • • • • Automotive navigation and entertainment (see automotive datasheet, IMX53AEC) High-end Mobile Internet Devices (MID), High-end PDAs Netbooks (web tablets) Nettops (internet desktop devices) High-end portable media players (PMP) with HD video capability Portable navigation devices (PND) Gaming consoles The flexibility of the i.MX53 architecture allows it to be used in a wide variety of applications. As the heart of the application chipset, the i.MX53 processor provides all the interfaces for connecting peripherals, such as WLAN, BluetoothTM, GPS, camera sensors and dual displays. i.MX53 power requirements are summarized in the following table. Table 1. i.MX53 Power Requirements Voltage Domain Name i.MX535/i.MX538 i.MX537 V mA V mA V mA fARM ≤ 167 MHz 0.90 - - - - - fARM ≤ 400 MHz 0.95 - - - 0.95 - fARM ≤ 800 MHz 1.10 - 1.10 1450 1.10 1450 fARM ≤ 1000 MHz 1.25 1700 - - - - fARM ≤ 1200 MHz 1.35 2200 - - - - Stop Mode 0.85 - 0.85 - 0.85 - Peripherals Supply 1.30 800 1.30 800 1.30 800 Stop Mode 0.95 - 0.95 - 0.95 - VDDA VDDAL1 Memory Arrays 1.30 100 1.30 100 1.30 100 Stop Mode 0.95 - 0.95 - 0.95 - VDD_DIG_PLL PLL Digital Supply 1.30 10 1.30 10 1.30 10 VDD_ANA_PLL PLL Analog Supply 1.80 10 1.80 10 1.80 10 NVCC_CKIH FUSE Supply and UHVIO Bias. 1.80 Note (1) 1.80 Note (1) 1.80 Note (1) NVCC_LCD GPIO digital power supplies 1.80 or 2.775 Note (1) VDDGP VCC NVCC_JTAG Description i.MX534/i.MX536 1.875 or 2.775 Note (1) 1.80 or 2.775 Note (1) Note (1) Note (1) Note (1) AN4604 Application Note Rev. 2.0 5/2013 2 Freescale Semiconductor i.MX53 Microprocessor Overview Table 1. i.MX53 Power Requirements Voltage Domain Name i.MX535/i.MX538 Description i.MX534/i.MX536 i.MX537 V mA V mA V mA NVCC_LVDS LVDS Supply 2.50 Note (1) 2.50 Note (1) 2.50 Note (1) NVCC_LVDS_BG LVDS Band Gap Supply 2.50 Note (1) 2.50 Note (1) 2.50 Note (1) NVCC_EMI_DRAM DDR2 1.80 800 1.80 800 1.80 800 LPDDR2 1.20 250 1.20 250 1.20 250 LV-DDR2 1.55 - 1.55 - 1.55 - DDR3 1.50 650 1.50 650 1.50 650 120 3.0 - 3.3 120 3.0 - 3.3 120 VDD_FUSE Fusebox Supply 3.0-3.3 NVCC_NANDF UHVIO Supplies • UHVIO_L • UHVIO_H • UHVIO_UH 1.875 2.775 3.30 NVCC_SD1 NVCC_SD2 Note (1) Note (1) 1.80 2.775 3.30 Note (1) 1.80 2.775 3.30 NVCC_PATA NVCC_KEYPAD NVCC_GPIO NVCC_FEC NVCC_EIM_MAIN NVCC_EIM_SEC NVCC_CSI TVDAC_DHVDD TVE Digital and TVDAC_AHVDDRGB Analog Supply 2.75 200 GPIO (TVE not in use) 1.875 or 2.775 SRTC Core NVCC_RESET LVIO USB_H1_VDDA25 USB_PHY Analog Supply. 2.50 50 2.50 NVCC_XTAL Oscillator Amplifier Supply 2.50 25 USB_H1_VDDA33 USB PHY I/O Analog Supply 3.30 20 USB_OTG_VDDA33 200 1.80 or 2.775 NVCC_SRTC_POW USB_OTG_VDDA25 1.30 2.75 <1 1.30 2.75 200 1.80 or 2.775 <1 1.30 <1 1.80 or 2.775 Note (1) 50 2.50 50 2.50 25 2.50 25 3.30 20 3.30 20 1.875 or 2.775 Note (1) 1.80 or 2.775 Note (1) AN4604 Application Note Rev. 2.0 5/2013 Freescale Semiconductor 3 i.MX53 Microprocessor Overview Table 1. i.MX53 Power Requirements Voltage Domain Name i.MX535/i.MX538 Description i.MX534/i.MX536 i.MX537 V mA V mA V mA VDD_REG Supply for Linear Regulators. 2.50 325 2.50 325 2.50 325 VP SATA PHY Core 1.30 20 1.30 20 1.30 20 VPH SATA PHY I/O 2.50 60 2.50 60 2.50 60 Notes 1.Refer to the IMX53x data sheets for I/O maximum power calculation. AN4604 Application Note Rev. 2.0 5/2013 4 Freescale Semiconductor i.MX53 Microprocessor Overview 3.1 i.MX53 Power-up/down Sequence The system design must comply with the power-up and power-down sequence guidelines as described in this section to guarantee reliable operation of the device. Any deviation from these sequences may result in the following situations: • • • Excessive current during power-up phase Prevention of the device from booting Irreversible damage to the i.MX53 processor (worst-case scenario) VDDA VDDAL1 VDDGP NVCC_SRTC_POW VCC VDD_REG VDD_DIG_PLL(1) VDD_ANA_PLL(1) NVCC_EMI_DRAM NVCC_CKIH VP VPH Supplies below or equal to 2.8V nom./ 3.1V max (2) Supplies above 2.8V nom/3.1V max(2) 1. When VDD_DIG_PLL and VDD_ANA_PLL are power on externally it is recommended to activate the VDD_REG before or at the same time with VDD_DIG_PLL and VDD_ANA_PLL to reduce current leakage during the power-up. 2. This group should not exceed NVCC_CKIH until it reaches at least 90% Figure 1. i.MX53 Power-up Sequence AN4604 Application Note Rev. 2.0 5/2013 Freescale Semiconductor 5 i.MX53 Microprocessor Overview The following observations should be considered: The consequent steps in power-up sequence should not start before the previous step supplies have been stabilized within 90 to 110% of their nominal voltage, unless stated otherwise. • • • • • • • • NVCC_SRTC_POW should remain powered ON continuously, to maintain internal real-time clock status. Otherwise, it has to be powered ON preceding VCC. The VCC should be powered ON after NVCC_SRTC_POW. NVCC_CKIH should be powered ON after VCC is stable and before other supplies are powered ON. Supplies below or equal to 2.8 V nom/3.1 V max. should not precede NVCC_CKIH. They can start powering ON during NVCC_CKIH ramp-up, before it is stabilized. Within this group, the supplies can be powered-up in any order. Supplies above 2.8 V nom/3.1 V max. should be powered ON only after NVCC_CKIH is stable. In case VDD_DIG_PLL and VDD_ANA_PLL are powered ON from internal voltage regulator (default case for i.MX53 revision 2.0), there are no restrictions on VDD_REG, as it is used as their internal regulators power source. If VDD_DIG_PLL and VDD_ANA_PLL are powered on externally, to reduce current leakage during the power-up, it is recommended to activate the VDD_REG before or at the same time with VDD_DIG_PLL and VDD_ANA_PLL. If this sequencing is not possible, make sure that the 2.5 V VDD_REG supply output impedance is higher than 1.0 k when it is inactive (or tie 1.0 K? current limiting resistor between the supply source and VDD_REG). VDD_REG supply is required to be powered ON to enable DDR operation. It must be powered on after VCC and before NVCC_EMI_DRAM. The sequence should be: VCC --> VDD_REG --> NVCC_EMI_DRAM • • • • • • VDDA can be powered ON anytime before POR_B, regardless of any other power signal. VDDGP can be powered ON anytime before POR_B, regardless of any other power signal. VP and VPH can be powered together, or anytime after, the VCC. VP and VPH should come before POR. If not using SATA, interface and the embedded thermal sensor, the VP and VPH should be grounded. It is not recommended to turn off the VPH while the VP is active. When internal clock source is used for SATA temperature monitor the USB_PHY supplies and PLL need to be active because they are providing the clock. TVDAC_DHVDD and TVDAC_AHVDDRGB should be powered from the same regulator. This is due to ESD diode protection circuit, that may cause current leakage if one of the supplies is powered ON before the other. If not using TVE module on a product, the TVDAC_DHVDD and TVDAC_AHVDDRGB can remain floating. If only the GPIO pads in TVDAC_AHVDDRGB domain are in use, the supplies can be set to GPIO pad voltage range (1.65 V to 3.1 V). NOTE: The POR_B input must be immediately asserted at power-up and remain asserted until after the last power rail is at its working voltage. AN4604 Application Note Rev. 2.0 5/2013 6 Freescale Semiconductor i.MX53 Microprocessor Overview Figure 2 shows the recommended power-up sequence diagram considering the fix. NVCC_SRTC_POW (may remain ON) 90% VCC 90% 't > 0 NVCC_CKIH 90% 't > 0 I/O Supplies below or equal to 2.8 V nom./3.1 V max. (in any order, after NVCC_CKIH ramp up start, if needed) 90% 't > 0 I/O Supplies above 2.8 V nom./3.1 V max (in any order, if needed) 90% 't > 0 VDD_REG 't > 0 90% 't > 0 NVCC_EMI_DRAM 90% 't > 0 VP, VPH (in any order) 90% VDDA,VDDAL1,VDDGP (in any order) 90% 't > 0 't > 0 POR_B Figure 2. i.MX53 Power-up Timing diagram Power-down sequence should follow one of the following two options: Option 1: Switch all supplies down simultaneously with further free discharge. A deviation of few microseconds of actual power-down of the different power rails is acceptable. Option 2: Switch down supplies, in any order, keeping the following rules: • • • NVCC_CKIH must be powered down at the same time or after the UHVIO IO cell supplies (for full supply list, refer to Table 9, Ultra High voltage I/O (UHVIO) supplies). A deviation of few microseconds of actual power-down of the different power rails is acceptable. VDD_REG must be powered down at the same time or after NVCC_EMI_DRAM supply. A deviation of few microseconds of actual power-down of the different power rails is acceptable. If all of the following conditions are met: — VDD_REG is powered down to 0V (Not Hi-Z) — VDD_DIG_PLL and VDD_ANA_PLL are provided externally, — VDD_REG is powered down before VDD_DIG_PLL and VDD_ANA_PLL AN4604 Application Note Rev. 2.0 5/2013 Freescale Semiconductor 7 i.MX53 Microprocessor Overview Then the following rule should be kept: VDD_REG output impedance must be higher than 1.0 k, when inactive (or tie 1.0 K current limiting resistor between the supply source and VDD_REG). 3.2 i.MX53 Internal LDOs The i.MX53 integrates two internal LDOs to supply each of the PLL voltage domains. These LDOs are supplied from the VDD_REG pin and deliver 1.3V for the VDD_DIG_PLL and 1.8 V for the VDD_ANA_PLL. The 1.3 V regulator outputs its voltage on the VDD_DIG_PLL pin. VDDA, VDDAL1, and VP can be supplied externally from this pin, care must be taken to place a ferrite in order to avoid noise coupling between voltage domains. The analog supply LDO can be software configured through the PLL1P8_VREG[4:0] bits for an output voltage from 1.5 to 2.275 V in 25 mV steps, being the default 1.8 V, and has an output current capability up to 125 mA. The digital supply LDO can be configured by means of the PLL1P2_VREG[4:0] bits from 0.8 to 1.575 V in 25m V steps. Its default voltage is 1.2 V and it is able to supply up to 125 mA. This LDO must be programmed to 1.3 V after boot up. The LDO default state is controlled through eFuses on i.MX53. By default, the internal LDOs is used. • • LDO_DIS[0]: Controls Analog PLL supply. LDO_DIS[1]: Controls Digital PLL supply. If any of these bits is 0, the respective PLL supply is provided by internal LDO source, if it is set to 1, the fuse is blown and the PLL supply is provided by the external pad, which is not recommended due to possible noise injections or other issues. i.MX53 VDD_REG 1.8V 2.5V VDD_ANA_PLL NVCC_RESET 1.3V VDD_DIG_PLL VDDA VDDAL1 VP Figure 3. Internal PLL supply. AN4604 Application Note Rev. 2.0 5/2013 8 Freescale Semiconductor MC34709 Overview 4 MC34709 Overview The MC34709 is a power management IC that includes the necessary sources to supply the i.MX53. Its main features are: • • • • • • • • • • • 10 bit ADC for monitoring. Four-wire resistive touchscreen interface Five Buck regulators for direct supply of the processor core and memory One Boost regulator for USB OTG support Eight LDO regulators with internal and external pass devices for thermal budget optimization Power control logic with processor interface and event detection Real time clock and crystal oscillator circuitry with coin cell backup Support for external secure real time clock on a companion system processor IC Single SPI/I2C bus for control & register access Four general purpose low voltage I/Os with interrupt capability Two PWM outputs 4.1 MC34709 Voltage supplies Table 2. MC34709 Voltage Supplies Summary Supply Purpose (typical application) Output Voltage (in V) Load Capability (in mA) SW1 Buck regulator for processor VDDGP domain 0.650 - 1.4375 2000 SW2 Buck regulator for processor VCC domain 1000 SW3 Buck regulator for processor VDD domain and 0.650 - 1.425 peripherals 500 SW4A Buck regulator for DDR memory and peripherals 1.200 – 1.975: 2.5/3.15/3.3 500 SW4B Buck regulator for DDR memory and peripherals 1.200 – 1.975: 2.5/3.15/3.3 500 SW5 Buck regulator for I/O domain 1.200 – 1.975 1000 SWBST Boost regulator for USB OTG 5.00/5.05/5.10/5.15 380 VSRTC Secure Real Time Clock supply 1.2 0.05 VPLL Quiet Analog supply 1.2/1.25/1.5/1.8 50 VREFDDR DDR Ref supply 0.6-0.9V 10 VDAC TV DAC supply, external PNP 2.5/2.6/2.7/2.775 250 VUSB2 VUSB/peripherals supply, internal PMOS 2.5/2.6/2.75/3.0 65 VUSB/peripherals external PNP 2.5/2.6/2.75/3.0 350 VGEN1 General peripherals supply #1 1.2/1.25/1.3/1.35/1.4/1.45/1.5/1.55 250 VGEN2 General peripherals supply #2, internal PMOS 2.5/2.7/2.8/2.9/3.0/3.1/3.15/3.3 50 General peripherals supply #2, external PNP 2.5/2.7/2.8/2.9/3.0/3.1/3.15/3.3 250 USB Transceiver supply 3.3 100 VUSB 0.650 - 1.4375 AN4604 Application Note Rev. 2.0 5/2013 Freescale Semiconductor 9 MC34709 Overview 4.2 MC34709 Power-up Sequence The MC34709 has five PUMS signals that enable to program the power-up sequence as well as the default output voltage for specific rails, making the part suitable to supply DDR2, DDR3, LPDDR2, LVDDR3 memories with the correct power-up sequence for many processors of the i.MX family. The following table shows the power-up sequence and all possible voltage combinations to supply the i.MX53 in all possible modes. Table 3. Configurable Power-up Sequence for MC34709 i.MX53 Sequence LPM DDR2 DDR3 LVDDR3 LPDDR2 0101 0110 0111 1000 1001 PUMS5=0 VUSB2 VGEN2 Ext PNP Ext PNP Ext PNP Ext PNP Ext PNP PUMS5=1 VUSB2 VGEN2 Internal PMOS Internal PMOS Internal PMOS Internal PMOS Internal PMOS PUMS[4:1] VSRTC Always on 1.2 1.3 1.3 1.3 1.3 SW2 (2) (VCC) 1 1.225 1.3 1.3 1.3 1.3 VPLL 2 1.8 1.8 1.8 1.8 1.8 VGEN2 3 2.5 2.5 2.5 2.5 2.5 SW1A (VDDGP) 4 1.1 1.1 1.1 1.1 1.1 SW1B (VDDGP) 4 1.1 1.1 1.1 1.1 1.1 SW4A (2) (DDR/SYS) 5 1.5 1.8 1.5 1.35 1.2 SW4B (2) (DDR/SYS) 5 1.5 1.8 1.5 1.35 1.2 VREFDDR 5 On On On On On SW5 (2) (I/O) 6 1.8 1.8 1.8 1.8 1.8 VUSB Note (3) 3.3 3.3 3.3 3.3 3.3 VUSB2 7 2.5 2.5 2.5 2.5 2.5 VDAC 8 2.775 2.775 2.775 2.775 2.775 AN4604 Application Note Rev. 2.0 5/2013 10 Freescale Semiconductor MC34709 Overview Table 3. Configurable Power-up Sequence for MC34709 (continued) i.MX53 PUMS[4:1] Sequence LPM DDR2 DDR3 LVDDR3 LPDDR2 0101 0110 0111 1000 1001 Not used on system SW3(2) (VDDA) 1.2 1.3 1.2 1.2 1.2 VGEN1 1.2 1.3 1.3 1.3 1.3 SWBST Off Off Off Off Off Notes 2.The SWx node are activated in APS mode when enabled by the start-up sequencer. 3.VUSB is turned on by enabling the SWBST block (auto or PFM) and the VUSBEN bit though I2C/SPI. If SWBST is not used, leave the SWBSTIN connected to BP, SWBSTFB connected to ground and SWBSTLX unconnected. Make sure VUSBIN has a valid 5.0 V before enabling VUSB. AN4604 Application Note Rev. 2.0 5/2013 Freescale Semiconductor 11 MC34709 Overview VSRTC* Power on event SW2 VPLL VGEN2 SW1A/B SW4A/B VREFDDR SW5 VUSB2 VDAC VUSB** 2ms 2ms 4ms 2ms 4ms 2ms 2ms * VSRTC is turned on right after Main supply is powered up. ** VUSB is turned of via I2C/SPI as required. Figure 4. MC3709 Power-up Sequence for i.MX53 processors. AN4604 Application Note Rev. 2.0 5/2013 12 Freescale Semiconductor Interfacing the i.MX53 with the MC34709 5 Interfacing the i.MX53 with the MC34709 Table 4 shows all the i.MX voltage rails, their power requirements and their associated MC34709 regulator. Most of the supply domains have flexible voltage and could be adjusted or supplied with a different regulator depending on each application needs Table 4. i,MX53 Voltage Domain Supplies with the MC34709 I.MX53 MC34709 Nominal Voltage Units Associated Regulator fARM ≤ 167 MHz 0.90 V SW1A/B 1.1 2000 mA 5 fARM ≤ 400 MHz 0.95 V fARM ≤ 800 MHz 1.10 V fARM ≤ 1000 MHz 1.25 V fARM ≤ 1200 MHz 1.35 V Stop Mode 0.85 V Peripheral supply Voltage 1.30 V SW2 1.3 1000 mA 1 Stop Mode 0.95 V Memory array voltage 1.30 V i.MX Internal - - - - Stop Mode 0.95 V VDD_DIG_PLL 1.30 V i.MX Internal - - - - VDD_ANA_PLL 1.80 V i.MX Internal - - - - NVCC_CKIH 1.80 V VPLL 1.8 50 mA 2 NVCC_LCD 1.875 or 2.775 V VDAC 2.775 250 mA 10 NVCC_JTAG 1.875 or 2.775 V SW5 1.8 1000 mA 8 NVCC_LVDS 2.5 V VGEN2 2.5 250 mA 3 DDR2 1.8 V SW4A/B 1.8 1000 mA 6 PVDDR2 1.2 V 1.2 LV-DDR2 1.55 V 1.55 LV-DDR2 1.5 V 1.5 DDR3 1.5 V 1.5 3.15 V 1000 mA VDDGP VCC VDDA VDDAL1 0111 Current Units DDR3 PUS NVCC_LVDS_BG NVCC_EMI_DRAM VDD_FUSE EXT DC-DC 3.2 AN4604 Application Note Rev. 2.0 5/2013 Freescale Semiconductor 13 Interfacing the i.MX53 with the MC34709 Table 4. i,MX53 Voltage Domain Supplies with the MC34709 (continued) I.MX53 MC34709 Nominal Voltage NVCC_NANDF NVCC_SD1 NVCC_SD2 (UHVIO) supplies UHVIO_L UHVIO_H UHVIO_UH 1.875 2.775 3.3 Units V Associated Regulator 0111 Current Units DDR3 PUS SW5 1.8 1000 mA 8 VUSB 3.3 100 mA Note (4) SW5 1.8 1000 mA 8 VDAC 2.775 250 mA 10 NVCC_PATA NVCC_KEYPAD NVCC_GPIO NVCC_FEC NVCC_EIM_MAIN NVCC_EIM_SEC NVCC_CSI TVDAC_DHVDD TVDAC_AHVDDRGB 2.775 V 1.875 or 2.775 V 1.3 V VSRTC 1.3 0.05 mA ON 1.875 or 2.775 V SW5 1.8 1000 mA 8 USB_H1_VDDA25 2.5 V VUSB2 2.5 250 mA 9 USB_OTG_VDDA25 2.5 V NVCC_XTAL 2.5 V USB_H1_VDDA33 3.3 V VUSB 3.3 100 mA Note (4) USB_OTG_VDDA33 3.3 V VDD_REG 2.5 V VGEN2 2.5 250 mA 3 VP 1.3 V i.MX Internal - - - - VPH 2.5 V VGEN2 2.5 250 mA 3 NVCC_SRTC_POW NVCC_RESET Notes 4.Turn on via I2C/SPI AN4604 Application Note Rev. 2.0 5/2013 14 Freescale Semiconductor Interfacing the i.MX53 with the MC34709 5.1 Interfacing Block Diagram The following block diagrams show all the power connections needed for the interface, as well as how the communication signals must be connected between the i.MX53 and MC34709. MC34709 i.MX53 SW1A/B VDDGP SW2 VCC SW4A/B NVCC_EIM_DRAM USB_H1_VDDA33 VUSB USB_OTG_VDDA33 NVCC_RESET NVCC_JTAG SW5 NVCC_NANDF 5.0V NVCC_CKIH NVCC_CSI VPLL Buck Regulator or Battery BP VDD_ANA_PLL NVCC_RESET VDD_DIG_PLL FB VDDA VDDAL1 VP VDD_REG VGEN2 NVCC_LVDS NVCC_LVDS_BG VPH NVCC_XTAL USB_H1_VDDA25 USB_OTG_VDDA25 VUSB2 TVDAC_DHVDD TVDAC_AHVDDRGB VDAC NVCC_LCD NVCC_SRTC_POW VSRTC NVCC_SD1 NVCC_SD2 NVCC_KEYPAD NVCC_EIM_MAIN NVCC_EIM_SEC NVCC_PATA NVCC_GPIO NVCC_FEC Peripherals External DC/DC regulator 3.2V CODEC HDMI ETHERNET 3G PCIe RS-232 Figure 5. i.MX53 Power Interface with MC34709 Block Diagram AN4604 Application Note Rev. 2.0 5/2013 Freescale Semiconductor 15 Interfacing the i.MX53 with the MC34709 SWx MC34709 i.MX53 POR_B RESETBMCU RESET_IN_B RESETB PMIC_STBY_REQ STANDBY POWERON1 PMIC_ON_REQ SWx WDI GPIOX_X INT GPIOX_X SWx UID USB_OTG_ID CLK KEY_COL3 KEY_ROW3 MISO/SDA CLK32MCU CLK PUMS1 PUMS2 VDC PUMS3 PUMS4 PUMS5 Figure 6. i.MX53 Control Interface with MC34709 Block Diagram AN4604 Application Note Rev. 2.0 5/2013 16 Freescale Semiconductor Interfacing the i.MX53 with the MC34709 5.2 Interface Power-up Sequence The resulting power-up sequence of the interface is shown in the following figure NVCC_SRTC_POW VSRTC VCC SW2 NVCC_CKIH VPLL VGEN2 VPH VDD_REG NVCC_LVDS NVCC_LVDS_BG VDD_ANA_PLL VDD_DIG_PLL VDDA VDDAL1 VP NVCC_RESET VDDGP NVCC_EMI_DRAM NVCC_SD1 NVCC_SD2 NVCC_PATA NVCC_KEYPAD NVCC_GPIO NVCC_FEC NVCC_EIM_MAIN NVCC_EIM_SEC NVCC_LCD NVCC_JTAG NVCC_NANDF NVCC_CSI NVCC_RESET USB_H1_VDDA25 USB_OTG_VDDA25 NVCC_XTAL TVDAC_DHVDD TVADC_AHVDDRGB USB_H1_VDDA33 USB_OTG_VDDA33 SW1A SW1B SW4A SW4B VREFDDR 3.2 V DC-DC Converter SW5 VUSB2 VDAC VUSB* * VUSB is turned on via I2C/SPI Figure 7. Power-up Sequence Flow Chart AN4604 Application Note Rev. 2.0 5/2013 Freescale Semiconductor 17 Application Example 6 Application Example The following schematic is simplified application example for interfacing the MC34709 with an i.MX53 processor. note that this schematic only includes the block related to the power section as well as power management controlling signals. i.MX53 - POWER A1 A2 A11 A13 A18 A22 A23 B1 B11 B13 B18 B23 C12 C20 C21 D19 E19 F19 F20 F21 F22 G7 G19 H8 H10 H12 J9 J11 J13 J15 J17 J20 K8 K10 K12 K14 K16 K21 L7 L9 L11 L13 L15 M8 M10 M12 M14 M16 N9 N11 N13 N15 P7 P8 P10 P12 P14 P16 P21 R9 R11 R13 R15 R17 R20 T8 T10 AA11 T14 T16 U15 U19 V15 V18 V19 V20 V21 V22 W19 Y14 Y15 Y19 AA15 AA20 AA21 AB1 AB18 AB23 AC1 AC2 AC18 AC22 AC23 AB22 AB2 GND1 GND5 GND2 GND3 GND4 GND6 GND7 GND22 GND23 GND24 GND25 GND26 GND27 GND28 GND29 GND30 GND31 GND32 GND33 GND34 GND35 GND37 GND36 GND40 GND38 GND39 GND46 GND41 GND42 GND43 GND44 GND45 GND52 GND47 GND48 GND49 GND50 GND51 GND56 GND57 GND53 GND54 GND55 GND62 GND58 GND59 GND60 GND61 GND66 GND63 GND64 GND65 GND72 GND73 GND67 GND68 GND69 GND70 GND71 GND79 GND74 GND75 GND76 GND77 GND78 GND83 GND80 GND8 GND81 GND82 GND84 GND85 GND86 GND87 GND88 GND89 GND90 GND91 GND92 GND93 GND94 GND95 GND9 GND10 GND11 GND12 GND13 GND16 GND17 GND19 GND18 GND20 GND21 GND15 GND14 VDDGP3 VDDGP1 VDDGP2 VDDGP5 VDDGP6 VDDGP4 VDDGP9 VDDGP7 VDDGP8 VDDGP11 VDDGP12 VDDGP10 VDDGP15 VDDGP13 VDDGP14 SVDDGP VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC11 VCC8 VCC9 VCC10 VCC16 VCC12 VCC13 VCC14 VCC15 VCC20 VCC17 VCC18 VCC19 VCC25 VCC21 VCC22 VCC23 VCC24 VCC30 VCC31 VCC26 VCC27 VCC28 VCC29 VCC33 VCC32 SVCC VDDA1 VDDA3 VDDA2 VDDA4 VDDAL1 VDD_REG C9 C10 C11 C12 C13 C14 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF C18 C19 C20 0.22UF 0.22UF 47UF GND C17 C16 0.22UF 0.22UF VDDGP To SW1A/B @1.1V 2A max VCC_1V3 To SW2 @1.3V 1A max. C15 22UF GND H13 J14 J16 K13 K15 L14 L16 M9 M11 M13 M15 N8 N10 N12 N14 N16 P9 P11 P13 P15 R8 R10 R12 R14 R16 T7 T9 T11 T13 T15 T17 U8 U18 B22 Place on TOP TP1 SVDDGP C21 C22 C23 C24 C25 C26 C27 C28 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 10UF GND C29 C30 C31 C32 C33 C34 C35 C36 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 47UF To VGEN1 @1.3V 250mA max VDDA_1V3 GND C37 C38 C39 C40 C41 0.22UF 0.22UF 0.22UF 10UF 22UF GND To VGEN1 @1.3V 250mA max VDDAL_1V3 Place on TOP TP2 C42 C43 0.22UF 0.22UF SVCC G12 M7 M17 U12 IMX_VDDA_1V2 GND VDD_REG_2V5 F9 C44 G18 0.1UF 22UF DDR_1.5V NVCC_EMI_DRAM1 NVCC_EMI_DRAM2 NVCC_EMI_DRAM3 NVCC_EMI_DRAM4 NVCC_EMI_DRAM5 NVCC_NANDF NVCC_EIM_MAIN2 NVCC_EIM_MAIN1 NVCC_EIM_SEC NVCC_RESET NVCC_SD1 NVCC_SD2 NVCC_PATA NVCC_LCD1 NVCC_LCD2 NVCC_CSI NVCC_FEC NVCC_GPIO NVCC_JTAG NVCC_KEYPAD VDD_FUSE NVCC_CKIH VDD_ANA_PLL VDD_DIG_PLL NVCC_XTAL FASTR_ANA FASTR_DIG H18 K17 N17 P17 T18 T12 To VGEN2 @2.5V 250mA max. C45 GND NVCC_SRTC_POW GND G8 G10 G11 H7 H9 H11 J8 J10 J12 K7 K9 K11 L8 L10 L12 B2 To SW4 @1.5V 1A max. GND C46 C47 C48 C49 C50 C51 0.1UF 0.1UF 0.01UF 0.01UF 0.01UF 22UF 1.8V GND U9 U10 U7 3.3V 3.3V 3.3V H16 H15 H14 N7 J6 J7 R7 F11 F8 G9 F7 1.8V 3.3V 3.3V 3.3V 2.775V 2.775V 1.8V 3.3V 3.3V 1.8V 3.3V VDD_FUSE DCDC_3V2 To DCDC_3V2 @3.2V 2A max. C54 C55 C56 C57 C58 C59 C60 C61 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF GND 2V775_VDAC G15 G17 1.8V G16 H17 1.8V ANA_PLL_1.8V DIG_PLL_INT V12 2.5V IMX_NVCC_XTAL V11 1.2V C62 C63 0.1UF 0.1UF To VDAC @2.775V 250mA max. To SW5 @1.8V 1.0A max. GND E18 E17 FASTR_SIG FASTR_SIG 1V8_SW5 C64 C65 C70 C71 0.22UF 22UF 0.1UF 22UF PCIMX535DVV1C GND GND GND C67 C68 C52 C53 0.1UF 0.1UF 0.1UF 0.1UF GND GND 1V8_VPLL NVCC_XTAL_2V5 L2 1 C66 2 120OHM 0.1UF C69 0.1UF To VPLL @1.8V 50mA max. GND GND NVCC_SRTC C72 0.1UF GND Figure 8. i.MX53 Voltage Domain Distribution AN4604 Application Note Rev. 2.0 5/2013 18 Freescale Semiconductor Application Example U27C VCC_BP VCC_BP F15 SWBSTIN G14 SW1IN1 SW1IN2 SWBSTFB SW1 0.650-1.4375V 2000mA Buck VCC_BP GND P7 SW5IN C204 C203 0.1UF 4.7uF R8 1V8_SW5 1UH (PUS_8) 2 SW5LX SW1BLX SW1FB SW5 1.200-1.85V 1000mA Buck SW5LX GND 1 C201 0.1UF 1V1_SW1(PUS_5) SW1ALX H15 C200 4.7uF SWBST 5.00, 5.05, 5.10, 5.15V 380mA Boost SWBSTLX P11 P10 R9 SW1LX BRL3225 2 L29 1 GND C207 C208 22UF 22UF 2V775_VDAC R11 R34 200K TP63 P13 GND SW1PWGD SW1CFG K10 VCOREDIG L12 VCOREDIG for Parallel Single Phase Mode VCORE for Parallel Dual Phase Mode L16 C202 VCC_BP 22UF SW2IN1 M8 VCC_BP P5 GND R6 SW4ALX GND 1UH 2 SW4B 1.200-1.85, 2.5, 3.15V 500mA Buck SW4BLX L14 1 C210 0.1UF 4.7uF C199 0.1UF 1V5_SW4 (PUS_6) C209 SW4BIN C198 4.7uF B11 SW5FB SW2 0.650-1.4375V 1000mA Buck GND 1V3_SW2 1UH SW2LX1 A10 1 SW2LX (PUS_1) 2 L17 TP64 C205 DCDC_3V2 C230 P2 VCC_BP SW4BFB 22UF SW2PWGD P4 GND SW2FB SW4AIN C188 SW3IN1 C187 0.1UF 4.7uF SW4A 1.200-1.85, 2.5, 3.15V 500mA Buck GND R3 SW4ALX 22UF R26 200K A13 VCC_BP GND E14 SW3 0.650-1.4375V 500mA Buck SW4ALX SW3LX1 N2 VCOREDIG A12 D15 SW4AFB M6 SW4CFG SW3FB MC34709 B13 GND VCOREDIG for Parallel Single Phase Mode PC34709VK U27B VCC_BP 1V5_SW4 J14 DDR_VREF K15 LDOVDD 0.1UF C226 0.1UF C227 J15 Support source for VUSB2,VDAC and VGEN2 VREFDDR VREFDDR C228 1uF N15 VINREFDDR MC34709 0.6-0.9V 10mA LDO VHALF VCC_BP GND VUSB2 2.5, 2.6, 2.75, 3.0V 4 VCC_BP Q8 3 NSS12100XV6T1G P14 VUSB2DRV 6 5 2 1 R14 VUSB2 65mA INT. 350mA EXT. PNP L15 C218 2.2UF 1V8_VPLL (PUS_2) 50mA LDO VPLL K14 GND 1V8_SW5 VCC_BP H14 VINGEN1 GND 1V3_VGEN1 H12 (PUS_8) VGEN1 1.2, 1.25, 1.3, 1.35, 1.4, 1.45, 1.5, 1.55V VDAC LDO 2.5, 2.6, 2.7, 2.775V 4 C222 2.2UF VUSB2DRV VINPLL VDACDRV VDAC VGEN1 250mA INT N14 VDACDRV D1 D2 C206 2.2UF VINUSB VUSB 100mA INT. VGEN2 LDO 2.5, 2.7, 2.8, 2.9, 3.0, 3.1, 3.15, 3.3V, (PUS_10) 50mA INT. 250mA EXT. PNP VCC_BP 4 VUSB LDO 3.3V GND 2V775_VDAC C224 2.2UF VGEN2DRV VGEN2 L14 VGEN2DRV GND Q16 NSS12100XV6T1G 3 2V5_VGEN2 (PUS_3) M15 1 2 5 6 5V_MAIN 3V3_VUSB GND 250mA C231 2.2UF (PUS_9) Q17 NSS12100XV6T1G 3 P15 C221 2.2UF 1 2 5 6 2V5_VUSB2 (PUS_9) VPLL LDO 1.2, 1.25, 1.5, 1.8V C220 2.2UF GND VCC_BP VCC_BP VCC_BP GND PC34709VK GND For BUSB2 For VDAC C229 0.1UF C223 0.1UF GND For VGEN2 C225 0.1UF GND Figure 9. MC34709 Power Supplies Schematic AN4604 Application Note Rev. 2.0 5/2013 Freescale Semiconductor 19 Application Example RESET RESET_IN_B 14 SW3 2 1.8V 1 TL1015AF160QG DNP 1V8_SW5 DCDC_3V2 GND C132 14 R36 0 DNP POR_B 0.1UF U2C GND R221 4.7K i.MX53 - CONTROL PINS C131 R222 4.7K 1.8V 1V8_SW5 BOOT_MODE0 BOOT_MODE1 C18 B20 TEST_MODE D17 GND RESET_IN POR BOOT_MODE0 BOOT_MODE1 NVCC_RESET A21 C19 GND NVCC_JTAG 0.1UF R37 4.7K TEST_MODE NVCC_SRTC PMIC_ON_REQ CKIH1 CKIH2 TP3 TP12 B21 D18 TP4 R42 49.9 DNP CKIH1 CKIH2 NVCC_CKIH TVDAC_1 14 PMIC_STBY_REQ PMIC_ON_REQ NVCC_GPIO W15 W14 PMIC_STBY_REQ R43 49.9 DNP GND "LCD" A AC10 AB10 SH36 D13 BLUE ECKIL CKIL NVCC_SRTC D9 A8 B8 A7 E9 C9 JTAG_TCK 16 JTAG_TMS 16 JTAG_TDI 16 JTAG_TDO 16 JTAG_nTRST 16 GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8 GPIO_9 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 NVCC_GPIO GPIO_16 GPIO_17 GPIO_18 NVCC_KEYPAD GPIO_19 NVCC_XTAL EXTAL XTAL C8 B7 C7 A6 D8 A5 B6 A4 B5 E8 DCDC_3V2 GPIO_0(CLK0) 9,13 DISP0_CONTRAST 11,13 I2C3_SDA R41 10K GND I2C3_SCL 11 SATA_CLK_GPEN 10 SYSTEM_DOWN (GPIO_5) 6,14 11 PCLOCK WDT_OUTPUT W16 V17 W17 AA18 W18 DCDC_3V2 R168 10K C6 A3 D7 B4 AB11 AC11 13 WDT_OUTPUT 14 SPDIF_TX 13 MX53_EXTAL MX53_XTAL R45 10M DNP PCIMX535DVV1C C Y1 0 LCD_LED R38 0 DNP JTAG_MOD R40 4.7K TP5 14 JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRST JTAG_MOD 14 1 4 GND ECKIL 2 3 24MHz GND R176 1.0K C133 C134 18pF A GND 18pF GND Figure 10. i.MX53 Control Signals AN4604 Application Note Rev. 2.0 5/2013 20 Freescale Semiconductor Application Example 2V5_VUSB2 U27A R396 10.0K R397 10.0K VCC_BP 13 13 H6 PORT_ID0 ADIN9 BP J5 PORT_ID1 ADIN10 J6 General Purpose ADCs ADIN11 NC_1 USB/Audio NC_2 2.2UF GND K6 C271 TOUCH_X0 K5 13 TOUCH_X1 L4 13 TOUCH_Y0 L6 13 TOUCH_Y1 L3 13 TSREF NC_3 TSX1/ADIN12 TSX2/ADIN13 GPIOVDD GPIOLV0 A4 SPIVCC GPIOLV1 B2 I2C1_SCL I2C1_SDA CS B1 SPI/I2C Interface CLK A2 GPIOLV2 GPIOLV3 MOSI CLK32K Control Logic CLK32KMCU GND CLK32KVCC VCOREDIG VSRTC L1 0 1.5V VCOREDIG J1 2.775V VCORE J2 1.2V PWM1 16 1.8V logic level A7 C8 1V8_SW5 C7 B7 B9 E10 E3 G3 Output, 0~1V2_RTC ECKIL F3 6 3V3_VUSB H2 1V3_RTC C262 VDDLP 0.1UF Reference Generation VCOREDIG VCORE K1 REFCORE A8 MISO B3 DNP VCORE R149 B15 TSY2/ADIN15 1V8_SW5 13,16 A14 TSY1/ADIN14 PWM2 13,16 R1 Touch Screen Interface PWM1 VCOREDIG N1 GND VCOREREF Output, 0~SPIVCC DCDC_3V2 C266 C267 C268 C270 VDDLP 0.1UF 1uF 1uF 100pF R226 100K A 1 MBR0520LT1G U30 VOUT CE 5 2 C275 0.1UF NCP4682 TAB_GND GND D22 C VIN 3 GND A C LICELL 4 D23 MBR0520LT1G WDI C259 0.1UF C274 0.1UF 3.3V GPIO9 (NVCC_GPIO) Coincell M2 Battery Backup SDWN RESET C D24 A BP GND RESETBMCU MBR0520LT1G INT GND STANDBY GLBRST PWRON1 PWRON2 G1 XTAL2 E1 PUMS1 Crystal Oscillator PUMS2 XTAL1 PUMS3 QZ2 1 PUMS4 2 PUMS5 32.768KHZ ICTEST C258 C257 15pF 15pF K3 WDT_OUTPUT D6 SYSTEM_DOWN (GPIO_5) RESETB B5 D5 RESETBMCU B4 PMIC_INT P1 STANDBY PMIC_STBY_REQ A5 GLBRST A6 PWNON1 E5 PWRON2 G6 1 PUMS1 G5 1 PUMS2 F6 1 F5 0 PUMS4 E6 0 PUMS5 VCOREDIG PUMS3 Power Up Mode (DDR3) A9 GND MC34709 VCOREDIG DNP R151 SH37 0 R150 DNP 0 PC34709VK GND 0 GND PMIC_ICTEST POWER ON/OFF 13 RESET SW7 2 1 GLBRST PWRON1/2 - Pullup to VCOREDIG (1.5V) TL1015AF160QG 1V3_RTC 5 1 VCC 4 GND GND PMIC_ON_REQ 2 PWRON2 1V8_SW5 U7 R229 68K 1.3V GPIO (NVCC_SRTC_POW) R227 68K 3 RESETBMCU NC7SP125P5X POR_B GND RESET_IN_B SW6 C272 PWNON1 2 1 TL1015AF160QG RESETB D21 BAT54A-7-F 1 GND 0.1UF 3 16 GND 2 JTAG_nSRST Power Up Sequence: 0) VSRTC 1) SW2 2) VPLL 3) VGEN2 4) SW3 5) SW1A/B 6) SW4A/B 7) VGEN1, SW5 8) VUSB2, VUSB 9) VDAC GND GND SW1VSSSNS GNDSW2 GNDSW1B1 GNDSW4B GNDSW4A GNDSW1A1 GNDSW5 GNDSWBST GNDSW3 D14 R13 B10 P12 P6 P3 P9 P8 F14 GNDREG1 GNDREG2 GNDREF1 GNDREF2 M14 J12 N9 B12 GNDSPI GNDCORE GNDREF GNDUSB GNDGPIO GNDRTC GNDCTRL GNDADC A3 H1 M1 C1 C9 F1 B6 SUBSLDO SUBSGND SUBSPWR SUBSPWR3 SUBSPWR2 SUBSPWR1_8 SUBSPWR1_7 SUBSPWR1_6 SUBSPWR1_5 SUBSPWR1_4 SUBSPWR1_3 SUBSPWR1_2 SUBSPWR1_1 H5 K8 K12 F10 H10 J8 K9 G10 E11 J9 H9 H8 G9 G8 F9 F8 E8 SUBSREF SUBSANA1 SUBSANA2 U27D PC34709VK Figure 11. MC34709 System/Control signals If an external battery charger is required, it is recommended to use a charger with power path management which isolates the battery from the system node while charging. The main system voltage from the charger is connected directly to the BP node while the external charging voltage and the battery are connected on the charger’s end. AN4604 Application Note Rev. 2.0 5/2013 Freescale Semiconductor 21 Migrating from MC34708 to MC34709 7 Migrating from MC34708 to MC34709 For customers migrating from the MC34708 platform to the MC34709 a very low design effort is required due to the high compatibility system between the to devices. Table 5 shows the main difference between both power management devices. Table 5. MC34708 and MC34709 difference Features MC34708 MC34709 Power control logic with processor interface and event detection Yes Yes Single SPI/I2C bus for control & register access Yes Yes Real time clock and crystal oscillator circuitry with coin cell backup Yes Yes Support for external secure real time clock on a companion system processor IC Yes Yes Four-wire resistive touchscreen interface Yes Yes Seven External ADC inputs. Yes Yes Dedicated ADC channel for battery voltage sensing Yes No Dedicated ADC channel for battery current sensing Yes No Dedicated ADC channel for BP voltage Yes No Dedicated ADC channel for die temperature Yes Yes Dedicated ADC channel for VBUS voltage. (USB device detection) Yes No Dedicated ADC channel for coin cell voltage Yes Yes Five Buck regulator Yes Yes One Boost regulator Yes Yes Eight LDO Regulators with internal and external pass devices. Yes Yes USB/UART/Audio switching for mini-micro USB connector Yes No Four general purpose low voltage I/Os with interrupt capability Yes Yes Two PWM outputs Yes Yes Two General purpose LED drivers Yes No Control Logic 10-bit ADC Power Supplies(5) Auxiliary Circuits AN4604 Application Note Rev. 2.0 5/2013 22 Freescale Semiconductor Migrating from MC34708 to MC34709 Table 5. MC34708 and MC34709 difference (continued) Features MC34708 MC34709 206 MAPBGA - 8.0 x 8.0 mm - 0.5 mm pitch Yes No 206 MAPBGA - 13 x 13 mm - 0.8 mm pitch Yes No 130 MAPBGA - 8.0 x 8.0 mm - 0.5 mm Pitch No Yes Package Notes: 5.All Power supplies have the same voltage and current rating on both devices. Firmware portability is straightforward, since register maps are bit to bit compatible. However, the MC34709 uses a reduced set of registers which eliminate all registers/bits related to the functionality not supported on the MC34709, therefore care must be taken that RESERVED registers/bits are not addressed on the firmware when porting the application to the MC34709. AN4604 Application Note Rev. 2.0 5/2013 Freescale Semiconductor 23 Migrating from MC34708 to MC34709 7.1 MC34709 layout example The following is a layout example of the MC34709 implemented on a four layer board with all components on the top layer and using standard 8.0 mil vias. 2 16 BH2 VSWBST_SENSE1 J122 J125 BH1 12 2 15 11 1 D20 C A 6 8 1 C A D23 R141 C A R142 C75 D18 C A R140 C76 D19 C A R143 C74 D24 C A D22 C A D21 D25 C A 1 5 J124 2 8 1 R138 C77 R160 C72 R156 R157 R139 C73 R161 R162 R164 R163 R165 1 1 J68 J120 J3 8 1 J2 1 R32 1 R136 C71 R31 R34 SWBSTLX1 C34 C26 C14 + D3 A + + C 6 R121 C62 2 1 5 C60 1 R130 R57 1 C50 C38 C39 Y1 R64 1 C33 1 J64 C53 TSREF1 J37 J69 C45 C7 6 R55 5 C8 2 R126 1 R59 1 1 2 C57 R52 1 C41 R58 R127 J58 CLKVCC1 19 20 SW3LX1 L10 D9 R48 R47 GNDSW4A1 D10 1C66 C6 1 U1 GNDSW3 A BC D16 R124 J21 DE C59 C28 FG R65 1 C3 1 HJ C32 KL C30 C49 C40 Q3 M C31 C23 C46 VGEN2 VHALF1 PN C22 Q4 C44 C21 C20 D11R VREFDDR1 VDAC1 C58 D13 D7 C37 R49 C15 L7 R53 C27 C13 D12 1 D8 C9 TSY2 LDOVDD1 L8 L9 J52 J56 VUSB2 1 Q6 C16 B 1 1 1 1 1 1 B SW4ALX1 C Q5 C19 GNDSWBST1 GNDSW4B1 1 C25 2 2 SW4BLX1 R125 R60 R128 VPLL1 Q2 J32 J43 1 J47 1 BAT1 1 1 Q1 1 J78 J79 J77 1 R41 1 J81 R44 SW1ALX1 SW1BLX1 1 R43 1 C R40 L2 L3 1 R38 R42 R35 J76 R37 A J40 J65 ADIN11 R66 R67 R152 R153 PWRON2 1 J25 ADIN9 GNDSWBST2 SW3FB2 L5 C11 1 2 SW2LX1 R56 R129 GNDSW2 VUSB1 6 J123 J118 SW2FB1 J30 1 ADIN10 R46 1 PWRON1 1 J31 GNDSW1B1 VSRTC1 1 1 INT1 SW4 5 REFCORE1 BP_SENSE1 R16 L4 R15 R122 R51 C61 R14 C64 3 U5 J74 1 STANDBY1 PWM1 GLBRST1 J29 1 1 2 PWM2 4 J67 J62 1 SW3 SW2 R150 5 C80 2 TP_XTAL2 VDDLP1 R151 C84 1 A VCORE1 J60 1 C79 R145 R144 C78 C68 C86 1 1 R33 WDI1 2 C85 L12 Q7 C D4 TP_XTAL1 C67 5 J121 A VCOREDIG1 1 36 37 R131 48 4 3 R135 R137 S2 S4 Q8 C81 13 12 U6 1 Y2 2 1 A D5 BH5 L11 S1 C C90 D17 1 S3 1 C 4 U4 5 RESETBMCU1 24 25 C91 C89 C87 R132 C88 A R133 C69 + C94 C95 5 TP1 F1 C92 U7 3 4 U2 5 R147 R146 R148 R149 C93 R155 R154 4 C82 R158 R159 R134 C70 4 U3 5 C83 BH6 SW1FB1 GNDSW5 TSY1 GNDSW1A1 SW5LX1 C29 R45 2 1 R36 KIT34709VKEVBE R39 2012 FREESCALE TSX2 TSX1 J80 S/N 1 1 1 J72 J117 1 9 16 700-XXXXX REV X J73 J71 J70 1 20 19 J66 SW1 SCH-XXXXX REV X 1 8 1 BH4 STANDOFFS REQUIRED BH3 Figure 12. KIT34709VKEVBE FAB Drawing AN4604 Application Note Rev. 2.0 5/2013 24 Freescale Semiconductor Migrating from MC34708 to MC34709 Figure 13. KIT34709VKEVBE Top Layer AN4604 Application Note Rev. 2.0 5/2013 Freescale Semiconductor 25 Migrating from MC34708 to MC34709 Figure 14. KIT34709VKEVBE Layer 2 AN4604 Application Note Rev. 2.0 5/2013 26 Freescale Semiconductor Migrating from MC34708 to MC34709 Figure 15. KIT34709VKEVBE Layer 3 AN4604 Application Note Rev. 2.0 5/2013 Freescale Semiconductor 27 Migrating from MC34708 to MC34709 A VER 83372-071 Figure 16. KIT34709VKEVBE Bottom Layer AN4604 Application Note Rev. 2.0 5/2013 28 Freescale Semiconductor References 8 References Document Description URL MC34709 Data sheet http://www.freescale.com/files/analog/doc/data_sheet/MC34709.pdf IMX53AEC Data sheet http://www.freescale.com/files/32bit/doc/data_sheet/IMX53AEC.pdf IMX53IEC Data sheet http://www.freescale.com/files/32bit/doc/data_sheet/IMX53IEC.pdf IMX53CEC Data sheet http://www.freescale.com/files/32bit/doc/data_sheet/IMX53CEC.pdf IMX53UG User’s Guide http://www.freescale.com/files/32bit/doc/user_guide/MX53UG.pdf Freescale.com Support Pages URL i.MX53 Product Summary Page http://www.freescale.com/webapp/sps/site/taxonomy.jsp?code=IMX53_FAMILY Analog Home Page http://www.freescale.com/analog Automotive Home Page http://www.freescale.com/automotive AN4604 Application Note Rev. 2.0 5/2013 Freescale Semiconductor 29 Revision History 9 Revision History Revision Date Description of Changes 1.0 1/2013 • Initial release 2.0 4/2013 • Annotate tables 3 and 4 • Update figures 4 and 7 AN4604 Application Note Rev. 2.0 5/2013 30 Freescale Semiconductor How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale products. 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