AN4603, Power Management Design Guidelines for the i.MX50x Family of Microprocessors - Application Note

Freescale Semiconductor
Application Note
Document Number: AN4603
Rev. 1.0, 12/2012
Power Management Design Guidelines for
the i.MX50x Family of Microprocessors
1
Purpose
The present document is intended to teach the reader how to
supply the power management to the i.MX50x family of
processors using either the Freescale MC13892 or the
MC34709 as the main power management device.
2
Introduction
The i.MX50x family of microprocessors requires complex
power management distribution along with specific
sequencing for proper power up. To supply integrated power
management to the i.MX50 processors, Freescale provides
two highly integrated PMICs solutions for different specific
scenarios. The MC13892, provide a highly integrated solution
which provides most of the required voltage rails as well as
integrated battery charger, 10 bits ADC and backlight LED
drivers. Likewise, the MC34709 is a reduced solution
providing as well the majority of the required power rails for
applications with less system requirements.
© Freescale Semiconductor, Inc., 2012. All rights reserved.

Contents
1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 i.MX50 Microprocessor Overview . . . . . . . . 2
4 i.MX50 Power Management Design with
MC13892 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5 i.MX50 Power Management Design with the
MC34709 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6 References . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7 Revision History . . . . . . . . . . . . . . . . . . . . . 44
i.MX50 Microprocessor Overview
3
i.MX50 Microprocessor Overview
The i.MX50 Applications Processors (i.MX50) is part of a growing family of multimedia-focused products, offering
high performance processing optimized for lowest power consumption.
The i.MX50 is optimized for portable multimedia applications and it features Freescale's advanced implementation
of the ARM Cortex-A8™ core, which operates at speed as high as 800 MHz. The i.MX50 provides a powerful display
architecture, including a 2D Graphics Processing Unit (GPU) and Pixel Processing Pipeline (ePXP). In addition,
i.MX508 includes a complete integration of the electrophoretic display function. The i.MX50 supports DDR2,
LPDDR2, and LPDDR1 DRAM at clock rate up to 266 MHz to enable a range of performance and power trade-offs.
The flexibility of the i.MX50 architecture allows it to be used in a variety of applications. As the heart of the application
chipset, the i.MX50 provides a rich set of interfaces for connecting peripherals, such as WLAN, Bluetooth™, GPS,
and displays.
i.MX50 power requirements are summarized in Table 1.
Table 1. i.MX50 Power requirements
Voltage Domain
Name
Current
Description
TYP
Units
Max
Units
400< fARM ≤ 800 MHz
1.05
V
1250
mA
167< fARM ≤ 400 MHz
0.95
V
24< fARM ≤ 167 MHz
0.9
V
Stop Mode
0.85
V
LPM
0.95
V
400
mA
RPM
1.05
V
HPM
1.225
V
Run Mode
1.2
V
250
mA
Stop Mode
0.95
V
Run Mode
1.2
V
Stop Mode
0.95
V
VDD3P0
Bandgap and 480 MHz PLL
supply
3.0
V
10
mA
VDD2P5
Efuse, 24 MHz oscillator, 32 kHz
oscillator mux supply
2.5
V
150
mA
VDD1P2
PLL digital supplies
1.8
V
10
mA
VDD1P8
PLL analog supplies
1.8
V
10
mA
NVCC_JTAG
GPIO digital power supplies
1.875 or 2.775
V
NVCC_EMI_DRAM
DDR2/LPDDR1
1.8
V
350
mA
LPDDR2
1.2
V
VDDGP
VCC
VDDA
VDDAL1
2
Voltage
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
i.MX50 Microprocessor Overview
Table 1. i.MX50 Power requirements
Voltage Domain
Name
Voltage
Current
Description
TYP
Units
Max
Units
VREF
DRAM Reference Voltage Input
1/2
NVCC_E
MI_DRAM
V
0.004
mA
VDDO25
EMI Pad Predriver supply
2.5
V
10
mA
NVCC_NANDF
NVCC_SD1
NVCC_SD2
NVCC_KEYPAD
NVCC_EIM
NVCC_EPDC
NVCC_LCD
NVCC_MISC
NVCC_SPI
NVCC_SSI
NVCC_UART
High voltage I/O (HVIO)
supplies
HVIO_L=1.875
HVIO_H=3.0
V
NVCC_SRTC
SRTC core and I/O supply
(LVIO)
1.2
V
NVCC_RESET
LVIO
1.875 or 2.775
V
USB_H1_VDDA25
USB_OTG_VDDA25
USB_PHY analog supply
2.5
V
50
mA
USB_DDA33
USB_OTG_VDA33
USB PHY I/O analog supply
3.3
V
16
mA
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
3
i.MX50 Power Management Design with MC13892
3.1
i.MX50 Power-up/down Sequence
NVCC_SRTC
VCC
VDDA
VDDAL1
VDDGP
VDD3P0
VDD2P5
VDDO2P5
NVCC_EMI_DRAM
VDD1P8 VDD1P2
VREF
NVCC_EIM
NVCC_EPDC
NVCC_JTAG
NVCC_KEYPAD
NVCC_LCD
NVCC_MISC
NVCC_NANDF
NVCC_RESET
NVCC_SD1
NVCC_SD2
NVCC_SSI
NVCC_UART
USB_OTG_VDDA25
USB_H1_VDDA25
USB_OTG_VDDA33
USB_H1_VDDA33
Figure 1. i.MX50 Power up Sequence
•
•
3.2
NOTE
The POR_B input must be immediately asserted at power-up and remain
asserted until after the last power rail is at its working voltage.
No power-up sequence dependencies exist between the supplies shown
shaded in gray.
Power-Down Sequence
The power-down sequence is recommended to be the opposite of the power-up sequence. In other words, the same
power supply constraints exist while powering off as while powering on.
4
i.MX50 Power Management Design with MC13892
The MC13892 is a power management IC that includes the necessary sources to supply the i.MX50. Its main
features are:
•
•
•
•
•
•
4
Battery charger system for wall charging and USB charging
10-bit ADC for monitoring battery and other inputs, plus a coulomb counter support module
Four adjustable output buck regulators for direct supply of the processor core and memory
12 adjustable output LDOs with internal and external pass devices
Boost regulator for supplying RGB LEDs
Serial backlight drivers for displays and keypad, plus RGB LED drivers
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
i.MX50 Power Management Design with MC13892
•
•
•
•
Power control logic with processor interface and event detection
Real time clock and crystal oscillator circuitry, with coin cell backup and support for external secure real time
clock on a companion system processor IC
Touch screen interface
SPI/I2C bus interface for control and register access
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
5
i.MX50 Power Management Design with MC13892
4.1
MC13892 Voltage supplies
Table 2. MC13892 Voltage Supplies Summary
Supply
Load Capability
(in mA)
SW1
Buck regulators for processor core(s)
0.600-1.375
1050
SW2
Buck regulators for processor SOG, etc.
0.600-1.375; 1.100-1.850
800
SW3
Buck regulators for internal processor memory and 0.600-1.375; 1.100-1.850
peripherals
800
SW4
Buck regulators for external memory and
peripherals
SWBST
Boost regulator for USB OTG, Tri-color LED drivers 5.0
300
VIOHI
IO and Peripheral supply, eFuse support
2.775
100
VPLL
Quiet Analog supply (PLL, GPS)
1.2/1.25/1.5/1.8
50
VDIG
Low voltage digital (DPLL, GPS)
1.05/1.25/1.65/1.8
50
VSD
SD Card, external PNP
1.8/2.0/2.6/2.7/2.8/2.9/3.0/
3.15
250
VUSB2
External USB PHY supply
2.4/2.6/2.7/2.775
50
VVIDEO
TV DAC supply, external PNP
2.5/2.6/2.7/2.775
350
VAUDIO
Audio supply
2.3/2.5/2.775/3.0
150
VCAM
Camera supply, internal PMOS
2.5/2.6/2.75/3.0
65
Camera supply, external PNP
2.5/2.6/2.75/3.0
250
VGEN1
General peripherals supply #1, external PNP
1.2/1.5/2.775/3.15
200
VGEN2
General peripherals supply #2, external PNP
1.2/1.5/1.6/1.8/2.7/2.8/3.0/
3.15
350
VGEN3
General peripherals supply #3, internal PMOS
1.8/2.9
50
General peripherals supply #3, external PNP
1.8/2.9
250
USB Transceiver supply
3.3
100
VUSB
4.2
Output Voltage
(in V)
Typical Application
0.600-1.375; 1.100-1.850
800
MC13892 Power-up Sequence
The Power Up mode Select pins (PUMS1 and 2) are used to configure the startup characteristics of the regulators.
Supply enabling and output level options are selected by hardwiring the PUMSx pins for the desired configuration.
Tying the PUMSx pins to ground corresponds to 00, open to 01, VCOREDIG to 10, and VCORE to 11.
The recommended power up strategy for end products is to bring up as little of the system as possible at booting,
essentially sequestering just the bare essentials, to allow processor startup and software to run. With such a
strategy, the startup transients are controlled at lower levels, and the rest of the system power tree can be brought
up by software. This allows optimization of supply ordering where specific sequences may be required, as well as
supply default values. Software code can load up all of the required programmable options to avoid sneak paths,
under/over-voltage issues, startup surges, etc., without any change in hardware. For this reason, the Power Gate
drivers are limited to activation by software rather than the sequencer, allowing the core(s) to startup before any
peripheral loading is introduced.
6
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
i.MX50 Power Management Design with MC13892
The power up defaults Table 3 shows the initial setup for the voltage level of the switching and LDO regulators,
and whether they get enabled.
Table 3. Power Up Defaults Table
PUMS1
GND
Open
VCOREDIG
VCORE
GND
Open
PUMS2
Open
Open
Open
Open
GND
GND
SW1 (1)
0.775
1.050
1.050
0.775
1.200
1.200
SW2 (1)
1.025
1.225
1.225
1.025
1.350
1.450
(1)
1.200
1.200
1.200
1.200
1.800
1.800
SW4 (1)
1.800
1.800
1.800
1.800
1.800
1.800
SWBST
Off
Off
Off
Off
5.000
5.000
VUSB
3.300 (2)
3.300 (2)
3.300 (2)
3.300 (2)
3.300 (4)
3.300 (4)
VUSB2
2.600
2.600
2.600
2.600
2.600
2.600
VPLL
1.800
1.800
1.800
1.800
1.500
1.500
VDIG
1.250
1.250
1.250
1.250
1.250
1.250
VIOHI
2.775
2.775
2.775
2.775
2.775
2.775
VGEN2
3.150
Off
3.150
Off
3.150
3.150
VSD
Off
Off
Off
Off
3.150
3.150
SW3
Not initialized during power-up
VCAM
Off
Off
Off
Off
Off
Off
VGEN1
Off
Off
Off
Off
Off
Off
VGEN3
Off
Off
Off
Off
Off
Off
VVIDEO
Off
Off
Off
Off
Off
Off
VAUDIO
Off
Off
Off
Off
Off
Off
Notes
1. The SWx regulators are activated in PWM pulse skipping mode, but allowed when enabled by the startup sequencer.
2. USB supply VUSB, is only enabled if 5.0 V is present on UVBUS.
3. The following supplies are not included in the matrix since they are not intended for activation by the startup sequencer: VCAM, VGEN1,
VGEN3, VVIDEO, and VAUDIO
4. SWBST = 5.0 V powers up and does VUSB regardless of 5.0 V present on UVBUS. By default VUSB will be supplied by SWBST.
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
7
i.MX50 Power Management Design with MC13892
The power up sequence is shown in Table 4. VCOREDIG, VSRTC, and VCORE are brought up in the pre-sequencer
startup. Once VCOREDIG is activated (i.e., at the first-time power application), it will be continuously powered as
long as a valid coin cell is present.
Table 4. Power Up Sequence
Tap x 2ms
PUMS2 = Open
PUMS2 = GND
0
SW2
SW2
1
SW4
VGEN2
2
VIOHI
SW4
3
VGEN2
VIOHI, VSD
4
SW1
SWBST, VUSB (7)
5
SW3
SW1
6
VPLL
VPLL
7
VDIG
SW3
8
-
VDIG
9
VUSB (6), VUSB2
VUSB2
Notes
5. The following supplies are not included in the matrix since they are not intended for activation by the startup
sequencer: VCAM, VGEN1, VGEN3, VVIDEO, and VAUDIO. SWBST is not included on the PUMS2 = Open column.
6. USB supply VUSB, is only enabled if 5.0 V is present on UVBUS.
7. SWBST = 5.0 V powers up and so does VUSB regardless of 5.0 V present on UVBUS. By default VUSB will be
supplied by SWBST.
8
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
i.MX50 Power Management Design with MC13892
Power on event
SW2
SW4
VIOHI
VGEN2
SW1
SW3
VPLL
VDIG
VUSB
VUSB2
2ms 2ms 2ms 2ms 2ms
2ms 2ms
4ms
Figure 2. MC13892 Power up Sequence for i.MX50 processors.
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
9
i.MX50 Power Management Design with MC13892
4.3
Interfacing the i.MX50 with the MC13892.
Table 5, shows all the i.MX50 voltage rails, their power requirements and their associated MC13892 regulator. Most
of the supply domains have flexible voltage and could be adjusted or supplied with a different regulator depending
on each application needs
Table 5. i,MX50 voltage domain supplies with the MC13892
I.MX50
Power Rail of i.MX50
Power Domain
MC13892
TYP
Associated
Regulator
Voltage
Current
PUM[4:0]=1110
(mA)
PUS
NVCCSRTC
32 kHz osc. power (when
chip off)
1.2
VSRTC
1.2
0.05
-
VCC
LP Transistor power
1.2
SW2
1.2
800
0
VDDA
Peripheral Memory + L2
Cache power
1.2
SW3
1.2
800
5
VDDAL1
L1 Cache power
1.2
SW3
1.2
800
5
VDDGP
Core and G Transistor
power
1
SW1
1
1050
4
VDDO2P5
Predriver for EMI pads
2.5
External LDO
2.5
250
-
VDD2P5
Power to 24 MHz osc,
efuse, xtalok,
32 kHz osc. power mux
2.5
External LDO
2.5
250
-
NVCC_EMI_DRAM
Power to EMI pins
1.2
External Buck
1.2
-
-
VREF
DRAM Reference
0.9
Voltage divider 0.5
x
NVCC_EMI_DRA
M
1.2 * 0.5
250
-
NVCC EIM
NVCC JTAG
NVCC SPI
NVCC SD
NVCC NANDF
NVCC SSI
NVCC MISC
NVCC KEYPAD
3.0 V I/Os
VGEN2
3.0
350
3
ALL 3.3V IO NVCC
NVCC EPDC
NVCC LCD
NVCC UART
3.0 V I/Os
External Buck
3.15
5000
-
VSD
3.15
250
-
VGEN2
3.0
350
3
3.15
3.15
3.15
NVCC_SD2
VDD3P0
10
3
3
3
3
3
3.15
VDD2P5 LDO input +
power to Bandgap,
DCDC predriver,
tempsensor, 480 MHz PLL
3
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
i.MX50 Power Management Design with MC13892
Table 5. i,MX50 voltage domain supplies with the MC13892
I.MX50
Power Rail of i.MX50
Power Domain
MC13892
TYP
Associated
Regulator
Voltage
Current
PUM[4:0]=1110
(mA)
PUS
USB_OTG_VDDA33
Power to USB Host
3.3
VUSB
3.3
100
9
USB_H1_VDDA33
Power to USB OTG
3.3
VUSB
3.3
100
9
All 1.8 IO NVCC
VDD DCDCI
VDD DCDCO
1.8 V I/Os
SW4
1.8
800
1
NVCC_RESET (LVIO)
Power to
POR_B,RESET_IN_B,
TESTMODE, &
BOOTMODE[0:1]
VPLL
1.8
50
6
USB_OTG_VDDA25
Power to USB Host
2.5
VUSB2
2.5
50
9
USB_H1VDDA25
Power to USB OTG
2.5
VUSB2
2.5
50
9
VDD1P8
Power to all PLLs
1.8
VPLL
1.8
50
6
VDD1P2
Power to all PLL digital, 32
kHz osc.
(when chip on), much of
analog, digital
1.2
VDIG
1.2
50
7
1.8
Not used
1.875 or
2.775
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
11
i.MX50 Power Management Design with MC13892
4.3.1
Interfacing Block Diagram
The following block diagrams show all the power connections needed for the interface, as well as how the
communication signals must be connected between the i.MX50 and MC13892.
MC13892
5.0V
i.MX50
SW1
VDDGP
SW2
VCC
SW4B
4.2V
regulator
VIN
1.2V
Buck
NVCC_EIM_DRAM
VUSB
USB_VDDA33
VUSB2
USB_VDDA25
VDIG
VDD1P2
VPLL
VDD1P8
NVCC_RESET
VSW3
VGEN2
VDDA
VDDAL1
VDD3P0
NVCC_MISC
NVCC_SPI
NVCC_SD1
NVCC_NANDF
NVCC_KEYPAD
NVCC_SSI
NVCC_JTAG
2.5V
LDO
VDD2P5
2.5V
LDO
VDDO25
NVCC_UART
NVCC_LCD
NVCC_EPDC
Peripherals
3.15V
Buck
regulator
3.15V
CODEC
HDMI
ETHERNET
3G PCIe
RS-232
Figure 3. i.MX50 Power Interface with MC13892 Block Diagram
12
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
i.MX50 Power Management Design with MC13892
SWx
MC13892
i.MX50
POR_B
RESETBMCU
RESET_IN_B
RESETB
PMIC_STBY_REQ
STANDBY
POWERON1
PMIC_ON_REQ
SWx
WDOG
WDI
GPIOX_X
INT
SWx
UID
USB_OTG_ID
CKL
CSPI_SCLK
CSPI_MISO/MOSI
MISO/SDA
CLK32MCU
PUMS1
PUMS2
CLK
VCOREDIG
NC
Figure 4. i.MX50 Control Interface with MC34709 Block Diagram
4.3.1.1
3.15 V Buck Regulator
For system stability, it is recommended that you use an extra 3.15 V DCDC power supply to support large current
requirements (for example a 3G module or Wi-Fi card). The MC34709 has limited 3.15 V output ability.
4.3.1.2
1.2 V Buck Regulator
A 1.2V Buck regulator is required to provide voltage to the 1.2V LPDDR2 module and the NVCC_EMI_DRAM
domain in the i.MX50 processor. Regulator SW4 will supply the input of this regulator at 1.8V and will also be used
as the 1.8V supply on the LPDDR2 Module as well.
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
13
i.MX50 Power Management Design with MC13892
4.3.1.3
2.5 V LDO Regulators
Due to the Power-up sequence dependency, two 2.5V LDO regulators are required to power up the VDD2P5 and
VDDO25 domains in the i.MX processor. The first one is enabled by the SW2 voltage rail, while the second LDO is
enabled with the VGEN2 voltage rail. See Figure 3.
4.3.2
Interface Power-up Sequence
The resulting power-up sequence of the interface is shown in the following figure
NVCCSRTC
VSRTC
VCC
VDD2P5
SW2
2.5V
LDO
regulator
SW4
1.8 NVCC I/O rails
VDD DCDCI
VDD DCDCO
NVCC_EMI
_DRAM
N/A
1.2V
DC-DC
regulator
VIOHI
VDD3P0
NVCC EIM
NVCC JTAG
NVCC SPI
NVCC SD
NVCC NANDF
NVCC SSI
NVCC MISC
NVCC KEYPAD
VDDO25
VGEN2
2.5V
LDO
regulator
VDDGP
3.3V NVCC
I/O
NVCC_EPDC
NVCC_LCD
NVCC UART
VDDA
VDDAL1
SW1
3.15V
Buck
regulator
SW3
VPLL
VDD1P8
NVCC_RESET (LVIO)
VDIG
VDD1P2
USB_OTG_VDDA33
USB_H1_VDDA33
USB_OTG_VDDA25
USB_H1VDDA25
SD2
VUSB
VUSB2
VSD* Enabled via
SPI
Figure 5. Power up Sequence Flow Chart
14
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
i.MX50 Power Management Design with MC13892
4.4
Application Example with the MC13892
The following schematic is simplified application example for interfacing the MC13892 with an i.MX50 processor.
note that this schematic only includes the block related to the power section as well as power management
controlling signals.
JP3
HDR 1X2
DNP
U12E
PCIMX508DJV1A
AD3
VDD3P0
i.MX50 - POWER
VDD2P5
SH8
DNP
GND
VDD2P5
AD4
VDD1P8
AD7
C74
VDD2P5
0.1UF
1V8_ANA_PLL
GND
C89
C75
0.1UF
VDD1P8
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
22UF
1V2_DIG GND
VDD1P2
C81
C82
22UF
0.1UF
AD6
VDDGP_1
VDDGP_2
VDDGP_3
VDDGP_4
VDDGP_5
VDDGP_6
VDDGP_7
VDDGP_8
VDDGP_9
VDDGP_10
VDDGP_11
VDDGP_12
VDDGP_13
VDDGP_14
VDDGP_15
VDD1P2
G8
G9
G10
H8
H9
H10
H11
J8
K7
K8
K10
K11
L8
L10
L11
1
2
1V_SW1
VDD3P0
C66
0.1UF
C67
C68
C69
C85
C70
C86
C87
C71
C88
C72
C73
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.01UF
0.01UF
10UF
22UF
SH7
0
GND
JP2
HDR 1X2
DNP
VCC
1V2_SW2
H14
H15
H16
H17
J17
K14
K15
K17
L15
1
2
3V_VGEN2
SH4
DNP
VDDGP
C76
C90
C77
C91
C78
C92
C79
C80
C93
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.01UF
0.01UF
10UF
22UF
SH5
0
GND
1V2_SW3
GND
VDDA_1
VDDA_2
1V8_SW4
SH6
DNP
VDD_DCDCI
Y6
C84
P17 VDDA
R17
C83
0.1UF
VDD_DCDCI
VDDAL_1
VDDAL_2
GND
P15 VDDA_L
C95
R15
DNP
C97
68uFDNP
2
2.2UH
C98
DNP
0.1UF
0.1UF
GND
0.1UF
TP11
SH9
0
C94
Y5
W5
SH10
0
C96
0.1UF
L8 1 VDD_DCDCO
0.1UF
VDD_DCDCO
VDDO2P5
GND
GND_DCDC
VDDO25
N23
SH11
0
C99
GND
GND
JP4
HDR 1X2
DNP
0.1UF
3V_VGEN2
SH12
DNP
NVCC_KEYPAD
N8
NVCC_KEYPAD
NVCC_EMI_DRAM_1
NVCC_EMI_DRAM_2
NVCC_EMI_DRAM_3
NVCC_EMI_DRAM_4
NVCC_EMI_DRAM_5
NVCC_EMI_DRAM_6
NVCC_EMI_DRAM7
NVCC_EMI_DRAM8
NVCC_EMI_DRAM9
NVCC_EMI_DRAM10
NVCC_EMI_DRAM11
NVCC_EMI_DRAM12
NVCC_EMI_DRAM13
NVCC_EMI_DRAM14
NVCC_EMI_DRAM15
NVCC_EMI_DRAM16
C100
0.1UF
GND
3V_VGEN2
SH14
DNP
NVCC_MISC
P8
NVCC_MISC
C113
0.1UF
GND
DCDC_3V15
SH15
DNP
NVCC_UART
T8
NVCC_UART
NVCC_EIM1
NVCC_EIM2
NVCC_EIM3
C117
0.1UF
A21
B21
D21
D23
D24
K21
K23
K24
R21
R23
R24
AA21
AA23
AA24
AC21
AD21
1V2_DDR
C101
C102
C103
C104
C105
C106
C107
C108
C109
C110
C111
C112
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.01UF
0.01UF
10UF
10UF
C114
C115
C116
C118
C119
C120
0.1UF
0.1UF
0.1UF
0.01UF
0.01UF
10UF
C121
C122
C123
C124
C125
C126
0.1UF
0.1UF
0.1UF
0.1UF
0.01UF
10UF
1
2
GND
SH13
0
GND
NVCC_EIM
3V_VGEN2
L7
M7
M8
SH16
DNP
GND
3V_VGEN2
SH17
DNP
GND
NVCC_SSI
R8
NVCC_SSI
NVCC_EPDC1
NVCC_EPDC2
NVCC_EPDC3
NVCC_EPDC4
NVCC_EPDC5
C127
0.1UF
GND
DCDC_3V15
M10
N10
P10
R10
U10
NVCC_EPDC
DCDC_3V15
SH18
DNP
GND
NVCC_LCD U11
SH19
DNP
NVCC_LCD
3V3_USB
C128
0.1UF
USB_OTG_VDDA33
USB_H1_VDDA33
AD11
AC11
SH20
DNP
C129
C130
0.1UF
0.1UF
GND
3V_VGEN2
SH21
DNP
NVCC_NANDF
C131
0.1UF
V10
V9
C132
0.1UF
NVCC_NANDF2
NVCC_NANDF1
GND
USB_OTG_VDDA25_1
USB_H1_VDDA25_1
3V15_VSD
SH23
DNP
NVCC_SD2
U8
SH22
DNP
C133
C134
0.1UF
0.1UF
NVCC_SD2
C135
0.1UF
3V_VGEN2
SH25
DNP
2V5_VUSB2
AC9
AD9
GND
NVCC_SRTC
GND
AA1 NVCC_SRTC
1V2_RTC
SH24
DNP
C136
0.1UF
GND
NVCC_SD1
T7
NVCC_SD1
C137
0.1UF
GND
NVCC_JTAG
U9
3V_VGEN2
SH27
DNP
3V_VGEN2
R56 DNP
NVCC_JTAG
GND
C138
0.1UF
NVCC_SPI
R7
NVCC_SPI
3V_VGEN2
0
C143
1V8_SW4
22UF
C144
0.01UF
SH26
DNP
GND
C145
0.1UF
GND
1V8_ANA_PLL
NVCC_RESET
V8
NVCC_RESET
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
GND3P0
GND1P8
GND2P5
GND_KEL
GND1P2
SH28
DNP
C146
0.1UF
GND
A1
A18
A24
B18
G20
G21
G23
H12
H13
K12
K13
L12
L13
L14
L17
M11
M14
M15
M17
M18
M20
M21
N11
N14
N15
N17
P11
P12
P13
P14
R11
R12
R13
R14
T17
T18
U12
U13
U14
U15
U16
U17
U18
V17
V18
V20
V21
V23
AA9
AA11
AC18
AD1
AD18
AD24
AC3
AC7
AC4
AA2
AA7
AC6
NGND_SRTC
GND
ICAP Classification:
Drawing Title:
GND
Figure 6. i.MX50 Voltage Domains
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
FCP: ___
FIUO: X
i MX50 Reference Des
15
i.MX50 Power Management Design with MC13892
VCC_BP
0.02
5V_APL
A2
B2
B1
C2
C2
C1
C1
C2
CHRGISNS
B1
B2
A2
R1
C1
Q1
FDZ193P
10UF 2.2uF
5V Selection
Q2
FDZ193P
B1
B2
A2
SH83
0
DNP
Q3
FDZ193P
GND
A1
5V_MAIN
USB_5V
BATTFET
CHRGCTRL
1V8_SW4
0
SH85
0
DNP
CHRGCTRL1
5V_APL
BATTISNS
D1
2
LI-ION_BATTERY
10K
R4
Note: use 10uF for Coulomb Counting of a battery.
DNP if not required.
C22
10UF K8
R14
2.775V
R15
4.7K
K2
L2
M2
J2
H2
H4
100K
DNP
2.2UF VCORE
C25
A9
GND
1.5V
C27
2.2UF VCOREDIG
B9
1.2V
C28
0.1UF REFCORE
D7
B8
GND
B7
E4
B5
E5
A7
D5
F5
B6
A6
NC
LEDMD
LEDAD
LEDKP
GNDSWLED
B11
A11
C12
E9
D8
E8
CHRGLED
CHRGSE1B
GNDCHRG
CHRGRAW
CHRGCTRL1
LEDR
LEDG
LEDB
GNDLED
SW4IN
SW4OUT
SW4FB
GNDSW4
SPIVCC
CS
CLK
MOSI
MISO
GNDSPI
SWBST
350mA
Boost
SPI/I2C
interface
VVIDEODRV
VVIDEO
VVIDEO
350mA
VCORE
VUSB2
50mA
VCOREDIG Reference
Generation
REFCORE
GNDCORE
GND
VVIOHI
100mA
5V_APL
TP4
R17
R18 DNP
0
E6
E1
R19
F2
G2
0
3V3_USB
D1
(PUS_9)
C37
VINUSB
VUSB
100mA
D9
R20
1V2_RTC
C44
2
6
C43
0.1UF
A
B
15pF
4
R26
GND
3
K5
J4
M4
C21
VCC_BP
10UF
SWBST
1
C23
VCC_BP
10uF
3
GND
Q6
VVIDEODRV
VCC_BP
C24
A3
A1
A2
B1
2.2UF
GND
C26
2.2UF
C31
2.2UF
(PUS_9)
GND
N7
N8
UNUSED
N10
N9
2V5_VUSB2
NOTE: (PUS_X) means the Power Up
Sequence index number during turn on.
3V_VAUDIO
VCC_BP
NSS12100XV6T1G
2V775_VVIDEO
2V775_VIOIH
(PUS_2)
C32
UNUSED
2.2UF GND
C1
E2
1V8_ANA_PLL
GND (PUS_6)
VCC_BP
C33
2.2UF
C34
2.2UF GND
M9
M8
M6
K6
VCC_BP
Q7
NSS12100XV6T1G
DNP
1V2_DIG
(PUS_7)
3
VCAMDRV
GND
C35
2.2UF
C36
2.2UF
UNUSED
C2
D2
VCC_BP
3V_VCAM
Q8
NSS12100XV6T1G
3
VCC_BP
VSDDRV
M10
N11
VGEN1DRV
N4
M3
VGEN2DRV
N3
M1
N1
N2
VGEN3DRV
C38
3V15_VSD
3
Q9
NSS12100XV6T1G
DNP
VCC_BP
UNUSED
2.2UF
3V_VGEN1 Q10
NSS12100XV6
3
3V_VG
(PUS_3)
C40
2.2UF
VINGEN3DRV
VGEN3_1
VGEN3_2
VGEN3_3
GPO1
GPO2
GPO3
GPO4
DVS2
DVS1
GNDREG3
GNDREG2
GNDREG1
GND
VGEN3
50mA
B2
F10
F9
G12
CLK32K
CLK32KMCU
VSRTC
RESETB
STANDBYSEC
STANDBY
INT
WDI
RESETBMCU
SW4
VCC_BP
Q11
NSS12100UW3
DNP
C41
2.2UF
1
UNUSED
GND
1V8_VGEN3
TP59
GND
GPO1
APL_GPIO2
5
1V2_RTC
15pF
VCOREDIG R23 DNP
R24
ECKIL
R27
R25
R28 DNP
0
5
VCOREDIG R29
R30 DNP
0
0
4,9
RESET_IN_B 4,9,15
POR_B
4,9
3V_VGEN2
0
0
0
U6
NLSV1T34
1V8_SW4
(PUS_1)
GND
TP8
R22
0
C45
GND
(active high)
GND VCORE
NC
Y1
1GND
32.768KHz
GND
VCCB
GND
VCCA
1
C42
0.1UF
1V2_SW3
SW3
10M
2
GND
F12
H12
0
DNP
1V8_SW4
J5
E12
G10
F11
XTAL2
GNDRTC
GNDCTRL
MODE
PUMS1
PWRON1
PWRON2
PWRON3
N6
F6
F7
F8
G6
G7
G8
H6
H7
H8
XTAL1
GNDSUB1
GNDSUB2
GNDSUB3
GNDSUB4
GNDSUB5
GNDSUB6
GNDSUB7
GNDSUB8
GNDSUB9
-
GND
R21
VGEN1DRV
VGEN1
VGEN2DRV
VGEN2
Coin cell.
SW2
GND
VGEN2
350mA
GND
BT1
2994TR
N5
M5
H9
A8
G9
D13
E10
J8
2
1
+
3
VGEN1
200mA
LICELL
0.1UF
1V2_SW2
(PUS_0)
(PUS_5)
GND
VSDDRV
VSD
VSD
250mA
GND
C39
VINDIG
VDIG
VCAMDRV
VCAM
VUSB
GND
MBR120LSFT1G
VCAM
250mA
2.2UF
SW1
10UF
VCC_BP
VINPLL
VPLL
VDIG
50mA
VBUSEN
1V_SW1
+/- 1%
C17
2
2.2uH
is for optional
D2
2
A4
B4
D4
A5
K12
L13
3.3uH
VCC_BP
VINIOHI
VIOHI
VPLL
50mA
UID
UVBUS
0
TP5
VINUSB2
VUSB2_1
VUSB2_2
VUSB2_3
VINAUDIO
VAUDIO
VAUDIO
150mA
GND
SWBST
SWBSTIN
SWBSTOUT
SWBSTFB
GNDSWBST
GND
GND
L6
1
CFP
TO-2.0A
GND
(PUS_4)
VCC_BP
CFM
GND
VCC_BP
1.5UH
G13
1L2
2
F13
H10
R10
0
E13
VCC_BP
H13
1L3
2
J13
2.2UH
C18
10UF
J10
R11
0
GND
K13
VCC_BP
H1
1L4
2
G1
2.2UH
C19
10UF
F4
F1
VCC_BP
GND
J1
1L5
2
K1
2.2UH
G4
L1
BATTISNSCC
3V_VGEN2
4,8
CSPI_SS0
1,15 CSPI_SCLK
1,15 CSPI_MOSI
1,15 CSPI_MISO
SW4
800mA
Buck
GND
Put 4.7UF capacitors at pins G13, H13, H1 and J1.
4
K7
SW3IN
SW3OUT
SW3FB
GNDSW3
E7
K4
M7
1
2
5
6
B12
BATTISNS
SW3
800mA
Buck
GND
4
GND
ADTRIG
SW2IN
SW2OUT
SW2FB
GNDSW2
4.7uF
1
2
5
6
E11
2.2UF
SW2
800mA
Buck
C13
4.7uF
4
C20
Touch
Screen
interface
SW1IN
SW1OUT
SW1FB
GNDSW1
C12
4.7uF
1
2
5
6
Sensitive analog lines.
X1-X2 and Y1-Y2
make differential pairs.
TSX1
TSX2
TSY1
TSY2
TSREF_1
TSREF_2
TSREF_3
PWGTDRV1
PWGTDRV2
SW1
1050mA
Buck
C11
4.7uF
4
4,15 TOUCH_X0
4,15 TOUCH_X1
4,15 TOUCH_Y0
4,15 TOUCH_Y1
ADIN5
ADIN6
ADIN7
Tri-Color
LED Drive
PUMS2
C10
1
2
5
6
J9
J12
M12
L12
M13
N12
N13
Backlight
LED Drive
Charger
Interface
and Control
GNDADC
GND
4
TP3
GND
GND
MC13892
1
2
5
6
Touch Screen
Connector
K9
GND K10
M11
0
BATT_NTC
8
VCC_BP
2
4,5
CHGR_DET_B_TO_PMIC
3
R9
10K
J6
R320
DNP
A12
A13
B13
CHRGISNS
Battery
Interface &
Protection
GND
BATT_NTC
SH30
0
DNP
B3
D6
H5
G5
J7
10K
CHRGCTRL2_1
CHRGCTRL2_2
CHRGCTRL2_3
B10
D12
BP
BPSNS
BATT
GND
GPO1
R8
DNP
R6
C7
10UF
U2
GND
GND
C9
10UF 10UF
C13
C8
C6
0.1UF
1
LED_ORANGE
D10
R7
47K
DNP
0.02
BATTISNS
DNP
A10
R3
BATTFET
5V_APL
4,9 PMIC_STBY_REQ
1.2V LPDDR2
0
R313
C1
C2
PCB MOD:
Cut Trace
4,5
SH88
A1
5V_APL
A1
VCC_BP
PWRON2
4.7K
0
C46
1uF
1V2_RTC
5
GND
WDOG_B
4,8
PWR_INT(GP4_18) 4,8
PWRON3
4,15
PWRON1
Open-drain
4,9
U5
1
VCC
PMIC_ON_REQ
4,9
2
4
required
GND
3
NC7SP125P5X
GND
GND
GND
Figure 7. MC13892 Schematic
16
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
i.MX50 Power Management Design with MC13892
VSOURCE
SH1
0
C47
+ C48
+ C49
+ C50
C51
VDDI
100UF
100UF
100UF
4.7uF
0.1UF
22
23
PVIN1 PVIN2 PVIN3 VIN1
NC1
NC2
18
VIN2
U7
5
8
R31
9.31K
GND
19
20
Vout = 0.7 * [ R(sw-inv) / R(inv-gnd) + 1 ]
C53
Vout = 3.14V for R39=17.4K, R44=4.99K
0.1UF
21
BOOT
DDR2/DDR3 Power
7
Note: Freq=1Mhz, Tsoftstart=3.2ms
C54
R34
5.1K
3
R33
10.0K 0.1UF
R37
GND
3V_VGEN2
SH71
DNP
2
0
VDDI
R41
10K
24
R42
DNP 4.99K
6
VREFIN
11
VOUT
0.7V
ILIM
FREQ
DCDC_3V15
2
SH2
0
1.0UH
R35
4.12K
9
COMP
L7
1
15
16
17
SW1
SW2
SW3
R38
15K
C55
10
INV
VDDI
R39
17.4K
20PF
C56
560PF
4
PG
C57
470pF
SD
C58
+
100UF
C59
100UF
+ C60
+
100UF
PGND1 PGND2 PGND3GND1 GND2
C61
12
13
14
1
R44
4.99K
25 MC34713EP
0.1UF
GND
Figure 8. 3.15V Buck Regulator
SH84
DNP
U1
LTC3409EDD
3
SH85
0
DNP
SH86
7
4
2
MODE
RUN
SW
VIN2
GND
VFB
SYNC
5
1V2_DDR
L1
1
6
2.2UH
2
1
R2
127.0K
C4
20PF
8
9
C3
10uF
VIN1
E_PAD
1V8_SW4
SH87
DNP
C5
10uF
R5
133.0K
Vout = 0.613 * [ R(Vout-Vfb) / R(Vfb-Gnd) + 1 ]
Vout = 1.2V for R(Vout-Vfb) = 127K & R(Vfb-Gnd)=133K
GND
Figure 9. 1.2V Buck Regulator
VDDO2P5 LDO
VSOURCE
VDDO2P5
U3
1
VIN
4
C16
C15
100 PF
2.2uF
5
VOUT
C14
BYP
3
4.7uF
ON/OFF
2
GND
GND
LP2992
GND
Q4
IRLML6401
VSOURCE
2
3
R307
100K
1
R306
100K
GND
3
1V2_SW2
1
10K
Q5
MMBT3904
2
R13
GND
VDD2P5 LDO
3V_VGEN2
VDD2P5
U4
1
10K
R16
4
C30
100 PF
3
2
VIN
BYP
VOUT
5
C29
22UF
ON/OFF
GND
GND
LP2992
GND
Figure 10. 2.5V LDO Regulators
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
17
i.MX50 Power Management Design with MC13892
U12C
PCIMX508DJV1A
RESET_IN_B
POR_B
AB1
AB2
BOOT_MODE0
BOOT_MODE1
AC2
TEST_MODE
10K
1V8_SW4
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRSTB
JTAG_MOD
CKIH
W2
W1
GND
4,6 PMIC_STBY_REQ
4,6 PMIC_ON_REQ
PMIC_STBY_REQ
PMIC_ON_REQ
Y1
Y2
QZ1
1
NVCC_JTAG
BOOT_MODE0
BOOT_MODE1
R73
AC1
AD2
CKIL
ECKIL
NVCC_RTC
4,6,15 RESET_IN_B
4,6
POR_B
NVCC_RESET
i.MX50 - CONTROL PINS
EXTAL
XTAL
W4
Y4
AA4
U7
AA5
V7
AA6
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST_B
SH33
R85
10K
DNP
JTAG_MOD
DNP
R86
1K
AC5
AD5
GND
2
R74
1.0M
1V8_ANA_PLL
Y3
32.768KHZ
DNP
C148
18PF
DNP
C149
18PF
DNP
GND
SH31
SH0603
DNP
4
1
3
2
GND
3
OUT
VCC
EN/DIS
GND
GND
4,6
OSC.
Y2
C152
15PF
C153
15PF
24MHZ
ECKIL
DGND
4
1
10K
R76
2
C154
0.1UF
22.5792MHZ
DNP
GND
GND
Figure 11. i.MX50 Control Signals
4.5
MC13892 PCB Layout Example
The following example shows the PMIC layout section for a reference design of the i.MX50 using the MC13892
power management. It is design in 10 layers with 4 inner planes (GND and PWR) form layer 4 to layer 7. For
simplicity, only top, bottom and Inner signal layers are shown in figures x to y.
1
4
JP5
TP15
SH79
C233
TP18
R16
1U6 U4
TP59
TP17
TP20
SH31
J20
TP23
TP21
5 C30
1
+
L3
S
1
C22 TP3
C154
1
Y3
S
S
TP
SH
1
R66
Y1
R21
R76
C44
C45
R67
R62
TP8
1
C38
C31
C21 JP3
SH13
R93
R92
R20
C411
C2 10 1
1
C A L2
1
1 C40
JP4
18
U2
1
C49
4
1
1
L5
1
C7 R1
C1
C48
TP4
TP5
C47 L4
R315
C37
R316
R31910
2
D2
1
L6
L9
C
1
Figure 12. Top Fabrication Drawing
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
i.MX50 Power Management Design with MC13892
03
6C
02C
19Q
7Q
1TB
1
5U
5
6Q
023R
1
93C
71R 01R
11R
1
21C
1
1
02J
72R 2
82R
52R
92R
62R
71C
34C
81C
22R
24C
5PJ 1
5
1
51 71
51PT
4PJ1
1
1
02HS
57C 7HS
62HS
36R
8HS
4HS 53C
43C
7R
23C
01Q
11Q
1
3PJ
611C
411C
911C
1C 811C
81R
91R
51R
2HS
421C
121C
921C
031C
431C
331C
1C
831C
6
H
S
01C
8C
48C 9
841C
8Q
02
01
38HS
1
03R 64C
92C
2
91C
01
1HS
02
2
04
Figure 13. Bottom Fabrication Drawing
2
2
1
10
10 1
1
1
1
C A
1
1
1
1
1
5
4
1
1
1
1
1
+
1
4
1
Figure 14. Top Layer
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
19
i.MX50 Power Management Design with MC13892
Figure 15. Inner Layer 2 (Signal)
Figure 16. Inner Layer 3 (Signal)
20
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
i.MX50 Power Management Design with MC13892
Figure 17. Inner Layer 8 (Signal)
Figure 18. Inner Layer 9 (Signal)
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
21
i.MX50 Power Management Design with MC13892
02
01
2
04
2
03
02
01
1
1
1
1
5
1
2
1
1
1
1
1
1
51 71
1
1
Figure 19. Bottom Layer
22
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
i.MX50 Power Management Design with the MC34709
5
i.MX50 Power Management Design with the MC34709
The MC34709 is a power management IC that includes the necessary sources to supply the i.MX50. Its main
features are:
•
•
•
•
•
•
•
•
•
•
•
Ten-bit ADC for monitoring.
Four-wire resistive touchscreen interface
Five buck converters for direct supply of the processor core and memory
One boost converter for USB OTG support
Eight LDO Regulators with internal and external pass devices for thermal budget optimization
Power control logic with processor interface and event detection
Real time clock and crystal oscillator circuitry with coin cell backup
Support for external secure real time clock on a companion system processor IC
Single SPI/I2C bus for control & register access
Four general purpose low voltage I/Os with interrupt capability
Two PWM outputs
5.1
MC34709 Voltage supplies
Table 6. MC34709 Voltage Supplies Summary
Supply
Typical Application
Output Voltage
(in V)
Load Capability
(in mA)
SW1
Buck regulator for processor VDDGP domain
0.650 - 1.4375
2000
SW2
Buck regulator for processor VCC domain
0.650 - 1.4375
1000
SW3
Buck regulator for processor VDD domain and peripherals
0.650 - 1.425
500
SW4A
Buck regulator for DDR memory and peripherals
1.200 – 1.975: 2.5/3.15/3.3
500
SW4B
Buck regulator for DDR memory and peripherals
1.200 – 1.975: 2.5/3.15/3.3
500
SW5
Buck regulator for I/O domain
1.200 – 1.975
1000
SWBST
Boost regulator for USB OTG
5.00/5.05/5.10/5.15
380
VSRTC
Secure Real Time Clock supply
1.2
0.05
1.2/1.25/1.5/1.8
50
0.6-0.9V
10
VPLL
VREFDDR
Quiet Analog supply
DDR Ref supply
VDAC
TV DAC supply, external PNP
2.5/2.6/2.7/2.775
250
VUSB2
VUSB/peripherals supply, internal PMOS
2.5/2.6/2.75/3.0
65
VUSB/peripherals external PNP
2.5/2.6/2.75/3.0
350
VGEN1
General peripherals supply #1
1.2/1.25/1.3/1.35/
1.4/1.45/1.5/1.55
250
VGEN2
General peripherals supply #2, internal PMOS
2.5/2.7/2.8/2.9/3.0/
3.1/3.15/3.3
50
General peripherals supply #2, external PNP
2.5/2.7/2.8/2.9/3.0/
3.1/3.15/3.3
250
3.3
100
VUSB
USB Transceiver supply
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
23
i.MX50 Power Management Design with the MC34709
5.2
MC34709 Power-up Sequence
The MC34709 has 5 PUMS signals that enable to program the power up sequence as well as the default output
voltage for specific rails, making the part suitable to supply DDR2, DDR3, LPDDR2, LVDDR3 memories with the
correct power up sequence for many processors of the i.MX family. The following table shows the power up
sequence and all possible voltage combinations to supply the i.MX50 in all possible modes.
Table 7. Power-up Defaults
i.MX50
mDDR
LPDDR2
LPDDR2
mDDR
LPDDR2
mDDR
PUMS[4:1]
1010
1011
1100
1101
1110
1111
PUMS5=0
VUSB2/VGEN2
Ext PNP
Ext PNP
Ext PNP
Ext PNP
Ext PNP
Ext PNP
PUMS5=1
VUSB2/VGEN2
Internal
PMOS
Internal
PMOS
Internal
PMOS
Internal
PMOS
Internal
PMOS
Internal
PMOS
SW1A
(VDDGP)
1.1
1.1
1.1
1.1
1.1
1.1
SW1B
(VDDGP)
1.1
1.1
1.1
1.1
1.1
1.1
SW2(8)
(VCC)
1.2
1.2
1.2
1.2
1.2
1.2
SW3(8)
(VDDA)
1.2
1.2
1.2
1.2
1.2
1.2
SW4A(8)
(DDR/SYS)
1.8
1.2
3.15
3.15
3.15
3.15
SW4B(8)
(DDR/SYS)
1.8
1.2
1.2
1.8
1.2
1.8
SW5(8)
(I/O)
1.8
1.8
1.8
1.8
1.8
1.8
VUSB(9)
3.3
3.3
3.3
3.3
3.3
3.3
VUSB2
2.5
2.5
2.5
2.5
2.5
2.5
VSRTC
1.2
1.2
1.2
1.2
1.2
1.2
VPLL
1.8
1.8
1.8
1.8
1.8
1.8
VREFDDR
On
On
On
On
On
On
VDAC
2.5
2.5
2.5
2.5
2.5
2.5
VGEN1
1.2
1.2
1.2
1.2
1.2
1.2
VGEN2
3.1
3.1
3.1
3.1
2.5
2.5
Off
Off
Off
Not used on System
SWBST
Off
Off
Off
Notes
8. The SWx node are activated in APS mode when enabled by the start-up sequencer.
9. VUSB is supplied by SWBST.
24
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
i.MX50 Power Management Design with the MC34709
Table 8. Power-up Sequence i.MX50
Tap x
2.0 ms
PUMS [4:1] = [0100, 1011, 1100, 1101, 1110, 1111]
0
SW2
1
SW3
2
SW1A/B
3
VDAC
4
SW4A/B, VREFDDR
5
SW5
6
VGEN2, VUSB2
7
VPLL
8
VGEN1
9
VUSB
VCOREDIG, VSRTC, and VCORE, are brought up in the pre-sequencer start-up. See Figure 2
ow
Turn On Event
WDI Pulled Low
Sequencer time slots
System Core Active
Turn On Verification
Power Up Sequencer
UV Masking
RESETB
INT
WDI
8 ms
1 - Off
8 ms
20 ms
2 - Cold Start
12 ms
128 ms
3 - Watchdog
4 - On
Power up of the system upon a Turn On Event followed by a transition to the On state if WDI is pulled high
3- Watchdog
1 - Off
... or transition to Off state if WDI remains low
Turn on Event is based on PWRON being pulled low
= Indeterminate State
Figure 20. Complete MC34709 Power-up Sequence
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
25
i.MX50 Power Management Design with the MC34709
Power on event
SW2
SW3
SW1A/B
VDAC
SW4A/B
VREFDDR
SW5
VGEN2
VUSB2
VPLL
VGEN1
VUSB
2ms 2ms 2ms 2ms 2ms
2ms 2ms
2ms
2ms
Figure 21. MC3709 Power up Sequence for i.MX50 processors.
26
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
i.MX50 Power Management Design with the MC34709
5.3
Interfacing the i.MX50 with the MC34709
Table 9, shows all the i.MX voltage rails, their power requirements and their associated MC34709 regulator. Most of
the supply domains have flexible voltage and could be adjusted or supplied with a different regulator depending on
each application needs
Table 9. i.MX50 voltage domain supplies with the MC34709
I.MX50
Power Rail of
i.MX50
Power Domain
MC34709
MIN
TYP
MAX
Associated PUM[4:0] Curren
PUS
Regulator
=1110
t (mA)
NVCCSRTC
32 kHz osc. power
(when chip off)
1.2
VSRTC
1.2
VCC
LP Transistor
power
1.2
SW2
1.2
1000
0
VDDA
Peripheral
Memory + L2
Cache power
1.2
SW3
1.2
500
1
VDDAL1
L1 Cache power
1.2
SW3
1.2
500
1
VDDGP
Core and G
Transistor power
1
1
1600
2
VDDO2P5
Predriver for EMI
pads
2.5
VDAC
2.5
50
3
NVCC_EMI_DRAM
Power to EMI pins
1.2
SW4B
1.2
500
4
VREF
DRAM Reference
0.9
ALL 3.3V IO NVCC
3.0 V I/Os
-
VDD3P0
VDD2P5 LDO
input + power to
Bandgap,
DCDC predriver,
tempsensor, 480
MHz PLL
3
SW4A
3.15
500
4
USB_OTG_VDDA33
Power to USB
Host
3.3
VUSB
3.3
100
9
USB_H1_VDDA33
Power to USB
OTG
3.3
VUSB
3.3
100
9
All 1.8 IO NVCC
1.8 V I/Os
SW5
1.8
1000
5
NVCC_RESET (LVIO) Power to
POR_B,RESET_I
N_B,
TESTMODE, &
BOOTMODE[0:1]
SW1A/B
-
1.875 or
2.775
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
27
i.MX50 Power Management Design with the MC34709
Table 9. i.MX50 voltage domain supplies with the MC34709
I.MX50
Power Rail of
i.MX50
Power Domain
MC34709
MIN
TYP
MAX
Associated PUM[4:0] Curren
PUS
Regulator
=1110
t (mA)
VDD2P5
Power to 24 MHz
osc, efuse, xtalok,
32 kHz osc. power
mux
2.5
VGEN2
2.5
250
6
USB_OTG_VDDA25
Power to USB
Host
2.5
VGEN2
2.5
250
6
USB_H1VDDA25
Power to USB
OTG
2.5
VGEN2
2.5
250
6
VDD1P8
Power to all PLLs
1.8
VPLL
1.8
50
7
VDD1P2
Power to all PLL
digital, 32 kHz osc.
(when chip on),
much of analog,
digital
1.2
VGEN1
1.2
250
8
28
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
i.MX50 Power Management Design with the MC34709
5.3.1
Interfacing Block Diagram
The following block diagrams show all the power connections needed for the interface, as well as how the
communication signals must be connected between the i.MX50 and MC34709.
MC34709
i.MX50
SW1A/B
SW2
SW4
5.0V
VUSB
4.2V
regulator
VIN
SW5
VPLL
VGEN2
VDDGP
VCC
NVCC_EIM_DRAM
USB_VDDA33
POP_LPDDR2_18V
NVCC_RESET
NVCC_JTAG
VDD1P8
NVCC_KEYPAD
(OPT)
VSW3
VDDA
VDDAL1
VUSB2
VDD2P5
VDAC
VDDO25
VSW4A
VDD3P0
NVCC_MISC
NVCC_SPI
NVCC_SD1
NVCC_SD2
POP_NAND_VCC
NVCC_NANDF
NVCC_KEYPAD
NVCC_SSI
NVCC_UART
NVCC_LCD
NVCC_EPDC
VGEN1
External
DC/DC
regulator
VDD1P2
Peripherals
3.15 V
CODEC
HDMI
ETHERNET
3G PCIe
RS-232
Figure 22. i.MX50 Power Interface with MC34709 Block Diagram
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
29
i.MX50 Power Management Design with the MC34709
SWx
MC34709
i.MX50
POR_B
RESETBMCU
RESET_IN_B
RESETB
PMIC_STBY_REQ
STANDBY
POWERON1
PMIC_ON_REQ
SWx
WDOG
WDI
GPIOX_X
INT
SWx
UID
USB_OTG_ID
CKL
CSPI_SCLK
CSPI_MISO/MOSI
MISO/SDA
CLK32MCU
CLK
PUMS1
PUMS2
PUMS3
VDC
PUMS4
PUMS5
Figure 23. i.MX50 Control Interface with MC34709 Block Diagram
5.3.1.1
3.15 V DC-DC power supply
For system stability, it is recommended that you use an extra 3.15 V DCDC power supply to support large current
requirements (for example a 3G module or Wi-fi card). The MC34709 has limited 3.15 V output ability to supply al
peripherals, however, in cases where Ethernet, 3G, or Wi-fi are not required, this buck converter may be eliminated
from the power three.
30
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
i.MX50 Power Management Design with the MC34709
5.3.2
Interface Power-up Sequence
The resulting power-up sequence of the interface is shown in the following figure
VCC
SW2
VDDA
VDDA1
SW3
VDDGP
SW1A/B
VDAC
VDDO2P5
Peripherals
CODEC
HDMI
ETHERNET
3G PCIe
RS-232
VDD3P0
NVCC_MISC
NVCC_SPI
NVCC_SD1
NVCC_SD2
POP_NAND_VCC
NVCC_NANDP
NVCC_KEYPAD
NVCC_SSI
NVCC_UART
NVCC_LCD
NVCC_EPDC
SW4A
SW4B
VREFDDR
3.15V
DC-DC
regulator
POP_LPDDR2_18V
NVCC_RESET
SW5
NVCC_JTAG
VDD2P5
VGEN2
USB_VDDA25
VUSB2
VDD1P8
VPLL
VDD1P2
HDMI (perpheral)
VGEN1
USB_VDDA33
VUSB
Figure 24. Power up Sequence Flow Chart
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
31
i.MX50 Power Management Design with the MC34709
5.4
Application Example with the MC34709
The following schematic is simplified application example for interfacing the MC34709 with an i.MX50 processor.
note that this schematic only includes the block related to the power section as well as power management
controlling signals.
JP2
HDR 1X2
DNP
U6E
5_VGEN2
DCDC_3V15
3V15_SW4A_CPU
VDD3P0 U5
C63
VDD3P0
i.MX50 - POWER
VDDGP_1
VDDGP_2
VDDGP_3
VDDGP_4
VDDGP_5
VDDGP_6
VDDGP_7
VDDGP_8
VDDGP_9
VDDGP_10
VDDGP_11
VDDGP_12
VDDGP_13
VDDGP_14
VDDGP_15
0.1UF
DNP 0
R499
VUSB2_2V5 2V5_VGEN2
GND
0
VDD2P5 V5
R92
C68
R479
0
VDD2P5
DNP
0.1UF
1V8_VPLL
GND
0
VDD1P8 V6
R93
C84
C69
0.1UF
VDD1P8
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
22UF
1V2_VGEN1
GND
0
VDD1P2 U6
R95
C90
C91
22UF
0.1UF
VDD1P2
GND
VDDA_1
VDDA_2
1V8_SW5
0
R7
VDD_DCDCI
R463
C76
Not used (tied off to 1.8V)
VDD_DCDCI
VDDAL_1
VDDAL_2
G6
H6
J6
K6
L6
G7
H7
J7
K7
G8
H8
G9
H9
G10
H10
VDDGP
K10
L10
M10
K11
L11
M11
J12
K12
L12
VCC
C64
C65
C66
C77
C78
C79
C80
C67
C81
C82
C83
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.01UF
0.01UF
10UF
22UF
R91
0.001
GND
JP1
HDR 1X2
DNP
1V2_SW2
1
2
R462
C70
C85
C71
C86
C87
C88
C72
C73
C89
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.01UF
0.01UF
10UF
22UF
R94
GND
K9
J11
JP3
HDR 1X2
DNP
VDDA
C74
J9
J10
0.1UF
0.001
1V2_SW3
1
2
R412
0
1
2
1V_SW1
DNP 0
C92
C93
C75
0.1UF
0.1UF
0.1UF
R96
0.001
GND
0.1UF
2V5_VDAC
GND
L10
1 VDD_DCDCO
DNP
2
C96
DNP
0.1UF
C95
68uFDNP
VDDO25
T6
2.2UH
R6
L17
VDDO2P5
R370
0
C94
VDD_DCDCO
0.1UF
GND_DCDC
GND
GND
JP4
HDR 1X2
DNP
GND
2V5_VGEN2
3V15_SW4A_CPU
0
R466
0
H5
DNP
NVCC_KEYPAD
NVCC_EMI_DRAM_1
NVCC_EMI_DRAM_2
NVCC_EMI_DRAM_3
NVCC_EMI_DRAM_4
NVCC_EMI_DRAM_5
NVCC_EMI_DRAM_6
NVCC_EMI_DRAM7
NVCC_EMI_DRAM8
NVCC_EMI_DRAM9
NVCC_EMI_DRAM10
NVCC_EMI_DRAM11
NVCC_EMI_DRAM12
NVCC_EMI_DRAM13
NVCC_EMI_DRAM14
NVCC_EMI_DRAM15
C97
0.1UF
GND
3V15_SW4A_CPU
J5
NVCC_MISC
C110
0.1UF
GND
3V15_SW4A_CPU
L5
K14
N14
J15
K15
L15
N15
P15
H16
J16
K16
L16
M16
N16
P16
R16
NVCC_EMI_DRAM
C98
C99
C100
C101
C102
C103
C104
C105
C106
C107
C108
1
2
1V2_SW4
R465
C109
R97
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
C111
C112
C113
C115
C116
C117
0.1UF
0.1UF
0.1UF
0.01UF
0.01UF
10UF
C118
C119
C120
C121
C122
C123
0.1UF
0.1UF
0.1UF
0.1UF
0.01UF
10UF
R98
0
R99
0 DNP
0.22UF
0.22UF
0.01UF
0.01UF
10UF
0.001
10UF
GND
NVCC_EIM
3V15_SW4A_CPU
NVCC_UART
NVCC_EIM1
NVCC_EIM2
NVCC_EIM3
C114
0.1UF
F6
F7
F8
SH8
DNP
GND
3V15_SW4A_CPU
GND
K5
NVCC_SSI
NVCC_EPDC1
NVCC_EPDC2
NVCC_EPDC3
NVCC_EPDC4
C124
0.1UF
F9
F10
F11
F12
NVCC_EPDC
3V15_SW4A_CPU
SH10
DNP
3V15_SW4A_CPU
GND
3V15_SW4A
R368
3V15_SW4A_CPU
GND
P10
0.001
3V15_SW4A_CPU
3V3_USB
NVCC_LCD
C126
0.1UF
USB_OTG_VDDA33
USB_H1_VDDA33
Y11
W11
USB_3V3
C128
0.1UF
P11
P12
C130
0.1UF
C131
0.1UF
NVCC_NANDF2
NVCC_NANDF1
W9
Y9
GND
3V15_SW4A_CPU
P5
0.1UF
VUSB2_2V5
USB_2V5
C132
C133
0.1UF
0.1UF
R100
0
NVCC_SD2
C134
0.1UF
3V15_SW4A_CPU
0.01UF
PLace close to MX50
GND
USB_OTG_VDDA25_1
USB_H1_VDDA25_1
C127
GND
GND
3V15_SW4A_CPU
SH12
DNP
C125
22UF
C129
NVCC_SRTC
R5
GND
NVCC_SRTC
1V2_RTC
SH14
DNP
C135
0.1UF
GND
N5
NVCC_SD1
C136
0.1UF
GND
NVCC_JTAG
P9
3V15_SW4A_CPU
NVCC_JTAG
GND
C137
0.1UF
3V15_SW4A_CPU
M5
R101
0
R459
0
DNP
1V8_SW5
NVCC_SPI
C138
0.1UF
GND
1V8_SW5
NVCC_RESET
P6
NVCC_RESET
R460
0
R461
0
3V15_SW4A_CPU
DNP
NC1
NC2
NC3
NC4
GND
A1
Y1
A20
Y20
T7
T5
W5
M6
N6
L7
M7
N7
P7
J8
K8
L8
M8
N8
P8
L9
M9
N9
N10
R10
G11
H11
N11
R11
G12
H12
M12
N12
R12
G13
H13
J13
K13
L13
M13
N13
P13
R13
G14
H14
J14
L14
M14
P14
R14
H15
M15
R15
MCIMX508
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
C139
0.1UF
GND_KEL
GND
GND
ICAP Classification:
Drawing Title:
FCP: ___
FIUO: X
PU
i.MX50 Reference Desig
Figure 25. i.MX50 Voltage Domain Distribution
32
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
i.MX50 Power Management Design with the MC34709
U3C
VCC_BP
VCC_BP
C28
10UF
F15
2
C21
SWBSTIN
0.1UF
21
SWBSTLX
D6
MBR120LSFT1G
C252
0.01UF
BRL3225
SWBSTFB
P7
C20
4.7uF
SW5IN
C27
0.1UF
R8
GND
BRL3225
2
0.02 R367
L8
1
SW5LX
SW5LX
2
L3
R11
SW1BLX
C31
22UF
22UF
(PUS_3)
K10
SW1PWGD
TP63
L12
SW1CFG
GND
R35
0
R36
0
VCOREDIG
DNP
VCOREDIG for Parallel Single Phase Mode
VCORE for Parallel Dual Phase Mode
GND
C45
22uF
B11
SW2IN1
M8
C30
P13
SW1FB
SW5
1.200-1.85V
1000mA Buck
1V8_SW5
(PUS_6)
1
SW1
0.650-1.4375V
2000mA Buck
GND
VCC_BP
1V_SW1
R9
SW1ALX
H15
C22
0.1UF
GND
1
C46
22UF
G14
C15
4.7uF
SWBST
5.00, 5.05, 5.10, 5.15V
380mA Boost
SWBST
GND
P11
P10
SW1IN1
SW1IN2
L9
2.2UH
VCC_BP
SW5FB
C16
GND
P5
VCC_BP
C19
4.7uF
1V2_SW4B
for EMI_DRAM_PAD
R6
GND
BRL3225
2
C39
L7
1
SW2
0.650-1.4375V
1000mA Buck
SW4B
1.200-1.85, 2.5, 3.15V
500mA Buck
1V2_SW4B
(PUS_5)
C23
0.1UF
4.7uF
SW4BIN
C26
0.1UF
SW4BLX
SW4BLX
GND
L4
SW2LX 1
A10
SW2LX1
1V2_SW2
BRL3225
2
C33
(PUS_1)
22UF
P2
SW4BFB
C18
4.7uF
3V15_SW4A
(PUS_5)
2
0.02
1
L6
BRL3225
SW4A
1.200-1.85, 2.5, 3.15V
500mA Buck
R3
SW4ALX
C38
N2
22UF
M6
VCOREDIG
DNP 0
DNP 0
0
GND
E14
SW3IN1
GND
R369
TP64
GND
SW4AIN
C25
0.1UF
22UF
A13
SW2PWGD
P4
VCC_BP
A12
SW2FB
GND
VCC_BP
C17
SW3
0.650-1.4375V
500mA Buck
1V2_SW3
GND
D15
SW3LX1
1
L5
SW3LX
SW4AFB
SW4CFG
R56
R57
R58
C24
0.1UF
4.7uF
SW4ALX
B13
SW3FB
MC34709
2
BRL3225
(PUS_2)
C35
10UF
VCORE
GND
GND
VCORE for Parallel Dual Phase Mode
VCOREDIG for Parallel Single Phase Mode
GND for separate independent output mode
PC34709VK
U3B
VCC_BP
1V2_SW4B
J14
VREFDDR
0
K15
R378
LDOVDD
VREFDDR
VREFDDR
C49
C47
0.1UF
1uF
0.1UF
C48
J15
N15 R363
Support source for VUSB2,VDAC and VGEN2
0
VINREFDDR
MC34709
0.6-0.9V
10mA LDO
VHALF
VCC_BP
GND
VUSB2
2.5, 2.6, 2.75, 3.0V
4
VCC_BP
Q8
3
NSS12100XV6T1G
P14
VUSB2DRV
R14
C51
2.2UF
VUSB2
VPLL
K14
H14
R373
0
VGEN1 has an internal PMOS pass FET and is powered from the SW5
for an efficiency advantage
and reduced power dissipation in the pass devices.
1V8_VPLL
GND
R366
VINGEN1
H12
R365
VGEN1
1.2, 1.25, 1.3, 1.35,
1.4, 1.45, 1.5, 1.55V
VDAC LDO
2.5, 2.6,
2.7, 2.775V
4
0
VDACDRV
VDAC
VGEN1
buck
250mA INT
N14 VDACDRV
VUSB LDO
3.3V
GND
R65
0
D1
R375
0
D2
C52
2.2UF
VINUSB
VUSB
100mA INT.
1.8V for PLL Analog
VGEN2 LDO
2.5, 2.7, 2.8, 2.9,
3.0, 3.1, 3.15, 3.3V,
50mA INT.
250mA EXT. PNP
0
C50
2.2UF
Q9
NSS12100XV6T1G
3
GND
2V5_VDAC
P15
R364
250mA
0
2.5V for VDDO2P5 (EMI PADS)
(PUS_4)
C53
2.2UF
C57
2.2UF
SWBST
3V3_USB
C158
2.2UF
(PUS_8)
50mA LDO
VCC_BP
1.2V for PLL Digtal 1V2_VGEN1
(PUS_10)
65mA INT.
350mA EXT. PNP
1V8_SW5
GND
(PUS_9)
VUSB2DRV
1
2
5
6
R401
L15
VCC_BP
4
0
VINPLL
VGEN2DRV
VGEN2
L14
VGEN2DRV
GND
Q10
NSS12100XV6T1G
3
2V5_VGEN2
Power for Keypad
(PUS_7)
M15
R362
1
2
5
6
VUSB2_2V5
6
5
2
1
(PUS_10)
VPLL LDO
1.2, 1.25,
1.5, 1.8V
0
C59
2.2UF
GND
GND
VCC_BP
VCC_BP
PC34709VK
For VDAC (Q9)
For VGEN2(Q10)
C55
0.1UF
GND
C58
0.1UF
GND
Figure 26. MC34709 Power Supplies Schematic
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
33
i.MX50 Power Management Design with the MC34709
3.15V/2A Regulator
VSOURCE
R1
5
PVDD
J84
1
2
R78
0
3V15_SW4A
R8
3
1
2
2.2uH
VDD
1
8
C3
22UF
FB
SHDN/RT
COMP
2
R474
13K
R2
294K
R1
6
0 DNP
R475
332K
LX
HDR 1X2
DCDC_3V15_EN
DCDC_3V15
L13
U30
0
PGND
PAD
GND
7
4
9
C2
22UF
R3
100K
R2
GND
C290
1000PF
GND
GND
Vout = 3.15V for R1=294K, R2=100K
Vout = 0.8v* (R(out-fb) / R(fb-gnd) + 1)
GND
Figure 27. 3.15V DC-DC Regulator
Battery Regulator & Terminals
3-pin connector J2 allows the use of aftermarket Li-ION batteries. Recommended battery
capacity is 800 - 1500 mAh.
BATT
J1
+
2
1
J2
J3
3
2
1
-
THERMCON_1X3
B2B-PH-K-S
DNP
Silkscreen Labels:
3
2
1
HDR_1X3
GND
+
-
VCC_BP
THERMISTOR
BATT_NTC
(pg6)
C4
47uF
3
2
1
HDR_1X3
J4
GND
5V_MAIN
SH1
DNP
C7
10UF
U2
2
1
3
6
IN
EN
REG_4V2
OUT
NR/FB
GND
GND_TAB
4
5
R1
C6
20PF C5
10UF
TPS78601
R2
GND
R4
42.2K
R7
17.4K
Vout = 1.2246 * [ R(out-fb) / R(fb-gnd) + 1 ]
Vout = 4.19V for R1=42.2K, R2=17.4K
Figure 28. Main BP Supply (Battery or 4.2V)
34
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
i.MX50 Power Management Design with the MC34709
U3A
VCC_BP
J5
J6
ADIN9
BP
ADIN10
General
Purpose ADCs
ADIN11
NC_1
USB/Audio
NC_2
Sensitive analog lines.
X1-X2 and Y1-Y2
make differential pairs.
C32
K6
2.2UF
K5
GND
(pg17)
TOUCH_X0
(pg17)
TOUCH_X1
L4
(pg17)
TOUCH_Y0
L6
(pg17)
TOUCH_Y1
L3
TSREF
NC_3
TSX1/ADIN12
N1
R28
R1
A14
0
C14
10UF
MBR120LSFT1G
C
LICELL A
D15
CE
4
VIN
A
C
C291
D16
0.1UF
MBR120LSFT1G
BP
Touch Screen
Interface
TSX2/ADIN13
U10
NCP4682
3
GND
B15
D14
GND
TAB_GND
H6
ADIN9
VOUT
1
A
C
VDDLP
MBR120LSFT1G
C292
0.1UF
2
5
1
TP1
DNP
0
0
0
TSY1/ADIN14
TSY2/ADIN15
VSRTC WORKAROUND
3V15_SW4A
R46
0
C159
PWM1
C161
PWM2
PWM1
A8
(pg10)
A7
0.1UF 1uF
GPIOVDD
1.75V~3.6V
SPI: Hold low when cold start
I2C: Hold high when cold start.
(pg9)
GND
A4
R49
CSPI_SS0
(pg12,9)
CSPI_SCLK
(pg12,9)
CSPI_MISO
(pg12,9)
CSPI_MOSI
B2
0
R48
0
B1
R51
0
A2
R52
0
B3
GPIOLV0
SPIVCC
GPIOLV1
CS
SPI/I2C
Interface
CLK
GPIOLV2
GPIOLV3
R54
CLK32K
CLK32KMCU
4.7K
CLK32KVCC
VSRTC
L1
0 DNP
1.5V
VCOREDIG
J1
2.775V
VCORE
J2
1.2V
K1
REFCORE
R72
0
R77
0
GPIOLV4
R82
0
C41
C42
C44
0.1UF 1uF
1uF
0.01UF
DNP
1
TP6
DNP
1
TP7
B9
E10
E3
G3
F3
Output, 0~1V2_RTC
ECKIL
R76
0
(pg10)
3V15_SW4A
H2
R73
0
1V2_RTC
3V15_SW4A
C249
VDDLP
0.1UF
Reference
Generation
VCOREDIG
VCORE
R454
GND
3V15_SW4A
VCOREREF
3V15_SW4A
C40
1.8V logic level
1V8_SW5
GPIOLV1
B7
Output, 0~SPIVCC
MOSI
GND
VCORE R34
C7
MISO
Control Logic
VCOREDIG
C8
10K
U20
5
1V8_SW5
Input, 0~3.6V
1
VCC
R86
0
WDOG_B
(pg9)
SYSTEM_DOWN(GP4_17)
(pg9)
2
R80
100K
4
R79
10K
GND
+
2
1
M2
-
3
Coin cell.
Coincell
LICELL
WDI
Battery Backup
C56
0.1UF
BT1
2994TR
SDWN
RESET
RESETBMCU
GND
INT
STANDBY
GND
GLBRST
PWRON1
PWRON2
G1
E1
QZ1
1
XTAL2
PUMS1
Crystal
Oscillator
PUMS2
XTAL1
PUMS3
2
PUMS4
32.768KHZ
C61
15pF
C62
PUMS5
15pF
ICTEST
3
GND
NC7SP125P5X
GND
K3
D6
R89
0
open drain output
B5
R88
0
(active low)
D5
R87
0
R85
0
Output, 0~SPIVCC
R84
0
(active high)
R83
0
B4
P1
A5
A6
RESETB
RESETBMCU
STANDBY
PMIC_INT(GP4_18)
(pg9)
Input, 0~3.6V, high level (1.0~3.6V)
GLBRST
Input, 0~VCOREDIG(1.5V)
PWNON1
E5
PWRON2
G6
PUMS1
G5
PUMS2
F6
PUMS3
F5
PUMS4
E6
PUMS5
10K
R90
DNP
VCOREDIG
GND
R74
0
A9
High: ICTEST mode
Low: normal mode
MC34709
R75
0
DNP
GND
PC34709VK
Power Up Mode
GND
1V8_SW5
VCOREDIG
VCOREDIG
1V2_RTC
R45
6
R32
0
DNP
GND
PUMS5
PUMS4
PUMS3
PUMS2
PUMS1
3
C37
0.1UF
R66
10K
1
4
GND
2
GLBRST
GLBRST
SPST PB
(pg17)
C54
VCCB
R31
0
1
R30
0
(active high)
0.1UF
GND
(pg10,6)
2
PMIC_STBY_REQ
A
B
4
R50
0
STANDBY
1V8_SW5
GND
1.2V level input
R37
0
R38
0
DNP
R39
0
DNP
R40
0
DNP
GND
R53
10K
R41
0
NC
5
U4
NLSV1T34
3
0
1
1
1
0
R27
0
VCCA
R29
0
DNP
RESET
0
SW2
C36
0.1UF
STANDBY
GLBRST
R67
0
RESETBMCU
R70
0
DNP
R68
68K
R69
68K
GND
POR_B
GND
(pg10,6)
GND
R55
PMIC_STBY_REQ
0
DNP
RESETB
R71
0
D13
BAT54A-7-F
1
(pg10)
JTAG_RESET_B
R397
0
(pg10)
RESET_IN_B
(pg10)
C60
3
0.1UF
2
GND
GND
GND
SW1VSSSNS
GNDSW2
GNDSW3
D14
R13
B10
GNDSW1B1
GNDSW4B
GNDSW4A
GNDSW1A1
P6
P3
P9
P12
GNDSWBST
GNDSW5
P8
F14
GNDREG1
GNDREG2
GNDREF1
GNDREF2
M14
J12
N9
B12
GNDSPI
GNDCORE
GNDREF
GNDUSB
GNDGPIO
GNDRTC
GNDCTRL
GNDADC
A3
H1
M1
C1
C9
F1
B6
SUBSLDO
SUBSGND
SUBSPWR
SUBSPWR3
SUBSPWR2
SUBSPWR1_8
SUBSPWR1_7
SUBSPWR1_6
SUBSPWR1_5
SUBSPWR1_4
SUBSPWR1_3
SUBSPWR1_2
SUBSPWR1_1
H5
K8
K12
F10
H10
J8
K9
G10
E11
J9
H9
H8
G9
G8
F9
F8
E8
SUBSREF
SUBSANA1
SUBSANA2
U3D
PC34709VK
Figure 29. MC34709 System/Control Signals
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
35
i.MX50 Power Management Design with the MC34709
U6C
U4
10K
(pg6)
(pg6)
TEST_MODE
1V8_SW5
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRSTB
JTAG_MOD
CKIH
Y2
Y3
GND
PMIC_STBY_REQ
PMIC_ON_REQ
Y4
W4
QZ2
1
BOOT_MODE0
BOOT_MODE1
NVCC_JTAG
V3
U3
BOOT_MODE0
BOOT_MODE1
R128
RESET_IN_B
POR_B
PMIC_STBY_REQ
PMIC_ON_REQ
CKIL
ECKIL
NVCC_RTC
(pg10)
(pg10)
W3
Y5
RESET_IN_B
(pg6)
POR_B
NVCC_RESET
i.MX50 - CONTROL PINS
(pg6)
EXTAL
XTAL
R8
R9
U8
T9
U7
T8
V4
JTAG_TCK
(pg10)
JTAG_TMS
(pg10)
JTAG_TDI
(pg10)
JTAG_TDO
(pg10)
JTAG_TRST_B
(pg10)
SH21
R119
10K
DNP
JTAG_MOD
DNP
R129
1K
W6
Y6
GND
2
R130
1.0M
1V8_VPLL
MCIMX508
32.768KHZ
DNP
C140
18PF
DNP
C141
18PF
DNP
Y2
SH22
GND
4
1
Y1
OSC.
3
2
GND
3
OUT
VCC
EN/DIS
GND
DNP
GND
(pg6)
ECKIL
C144
15pF
C143
15pF
24MHZ
DGND
4
1
2
10K
R134
C142
0.1UF
22.5792MHZ
DNP
GND
GND
Figure 30. i.MX50 Control Signals
If an external battery charger is required, it is recommended to use a charger with power path management which
isolates the battery from the system node while charging. The main system voltage from the charger will be
connected directly to the BP node while the external charging voltage and the battery are connected on the charger’s
end.
36
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
i.MX50 Power Management Design with the MC34709
5.5
MC34709 layout example
The following is a layout example of the MC34709 implemented on a four layer board with all component on the top
layer and using standard 8 mils vias.
2
16
BH2
VSWBST_SENSE1
J122
J125
BH1
12
2
15
11
1
D20
C A
6
8
1
C A
D23
R141
C A
R142 C75
D18
C A
R140 C76
D19
C A
R143 C74
D24
C A
D22
C A
D21
D25
C A
1
5
J124
2
8
1
R138 C77
R160
C72
R156
R157
R139 C73
R161
R162
R164
R163
R165
1
1
J68
J120
J3
8
1
J2
1
R32
1
R31
R34
C34
+
D3
A
+
+
C
6
SWBSTLX1
C26
C14
5
R121 C62
2 1
C60
1
C50 C38
C39
Y1 R64
1
R65
C53
TSREF1
J37
J69
C45
C7
6
R55
5
C8
2
R126
1
R59
1
1
2
C57
R52
1
C41
R58
R127
J58
CLKVCC1
19
20
SW3LX1
R130
R57
1
ADIN11
GNDSWBST2
SW3FB2
L5
C11
C33
1
J64
ADIN9
L10
D9 R48 R47
GNDSW4A1
D10
1C66
C6
1 U1
GNDSW3
A
BC
D16
R124
J21
DE
C59
C28
FG
1
C3
1
HJ
C32
KL
C30
C49
C40 Q3
M
C31
C23 C46
VGEN2 VHALF1
PN
C22
Q4
C44
C21 C20 D11R
VREFDDR1
VDAC1
C58 D13 D7 C37
R49
C15
L7
R53
C27
C13
D12
1
D8 LDOVDD1
C9
TSY2
L8
L9
J52
J56
VUSB2
1 Q6
C16 B
1
1
1
1
1
1
B
SW4ALX1
C
Q5
C19
GNDSWBST1
GNDSW4B1
1
C25
2
2
R125
SW4BLX1
R60
R128
VPLL1
Q2
J32
J43
1
J47
1
BAT1
1
1
Q1
1
J78
J79
J77
1 R41
1
J81
R44
SW1ALX1
SW1BLX1
1
R43
1
C
R40
L2
L3
1 R38
R42
R35
J76
R37
A
J40
J118
R66 R67
R152
R153
PWRON2
1
J65
SW2LX1
PWRON1
R56
R129
J30
1
R46
PWM1
1
ADIN10
SW2FB1
R16
L4
R15
R122
R51
C61
R14
C64
C80
1
J31
GNDSW1B1
VSRTC1
GNDSW2 VUSB1
J25
REFCORE1
BP_SENSE1
1
2
J74
1
2
1 1
INT1
SW4
6
1
STANDBY1
PWM2
GLBRST1
J29
3
J67
J62
1
SW3
SW2
4
U5
J123
TP_XTAL2
VDDLP1
R151
C84
R150
5
1
5
A
VCORE1
J60
1
C79
R145
R144
C78
C68
C86
2
1
R33
WDI1
2
C85
1
Q7
C
D4
TP_XTAL1
C67
1
A
VCOREDIG1
1
36
37 R131 48
4
3
L11
5
J121
L12
Q8
BH5
R135
R137
S2
S4
A
D5
C81 13
12
U6
1 Y2 2
1
C
C90
D17
S1
R136
C71
TP1
1
S3
1
C
4 U4 5
RESETBMCU1
24
25
C91
C89 C87
R132 C88
A
R133
C69
+
C94
C95
5
F1
C92
U7 3
4 U2 5
R147
R146
R148
R149
C93
R155
R154
4
C82
R158 R159
R134
C70
4 U3 5
C83
BH6
SW1FB1
GNDSW5
TSY1
GNDSW1A1
SW5LX1
C29
R45
2
1
R36
KIT34709VKEVBE
R39
2012 FREESCALE
TSX2
TSX1
J80
S/N
1
1
1
J72
J117
1
9
16
700-XXXXX REV X
1
J73
J71
J70
20
19
J66
SW1
SCH-XXXXX REV X
1
8
1
BH4
STANDOFFS REQUIRED
BH3
Figure 31. KIT34709VKEVBE FAB Drawing
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
37
i.MX50 Power Management Design with the MC34709
Figure 32. KIT34709VKEVBE Top Layer
38
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
i.MX50 Power Management Design with the MC34709
Figure 33. KIT34709VKEVBE Layer 2
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
39
i.MX50 Power Management Design with the MC34709
Figure 34. KIT34709VKEVBE Layer 3
40
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
i.MX50 Power Management Design with the MC34709
A VER 83372-071
Figure 35. KIT34709VKEVBE Bottom Layer
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
41
i.MX50 Power Management Design with the MC34709
5.6
Migrating from MC34708 to MC34709
For customers migrating from the MC34708 platform to the MC34709 a very low design effort is required due to the
high compatibility system between the to devices. Table 10 shows the main difference between both power
management devices.
Table 10. MC34708 and MC34709 difference
Features
MC34708
MC34709
• Power control logic with processor interface and event detection
Yes
Yes
• Single SPI/I2C bus for control & register access
Yes
Yes
• Real time clock and crystal oscillator circuitry with coin cell backup
Yes
Yes
• Support for external secure real time clock on a companion system
processor IC
Yes
Yes
• 4 wire resistive touchscreen interface
Yes
Yes
• 7 External ADC inputs.
Yes
Yes
• Dedicated ADC channel for Battery voltage sensing
Yes
No
• Dedicated ADC channel for battery current sensing
Yes
No
• Dedicated ADC channel for BP voltage
Yes
No
• Dedicated ADC channel for Die temperature
Yes
Yes
• Dedicated ADC channel for VBUS voltage. (USB device detection)
Yes
No
• Dedicated ADC channel for coin cell voltage
Yes
Yes
• 5 Buck regulator
Yes
Yes
• 1 Boost regulator
Yes
Yes
• 8 LDO Regulators with internal and external pass devices.
Yes
Yes
• USB/UART/Audio switching for mini-micro USB connector
Yes
No
• Four general purpose low voltage I/Os with interrupt capability
Yes
Yes
• Two PWM outputs
Yes
Yes
• Two General purpose LED drivers
Yes
No
• 206 MAPBGA - 8.0 x 8.0 mm - 0.5 mm pitch
Yes
No
• 206 MAPBGA - 13 x 13 mm - 0.8 mm pitch
Yes
No
• 130 MAPBGA - 8.0 x 8.0 mm - 0.5 mm Pitch
No
Yes
Control Logic
10 bit ADC
Power Supplies(10)
Auxiliary Circuits
Package
Notes:
10. All Power supplies have the same voltage and current rating on both devices.
42
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
References
Firmware portability is straights forward, since register maps are bit to bit compatible. However, the MC34709 uses
a reduced set of register which eliminate all registers/bits related to the functionality not supported on the MC34709,
therefore care must be taken that RESERVED registers/bits are not addressed on the firmware when porting the
application to the MC34709.
6
References
Document
Number
MC34709
MC13892
IMX50SDG
IMX50RM
IMX50CEC
Description
Data Sheet
Data Sheet
Development Guide
Reference Manual
Data Sheet
Description / URL
http://cache.freescale.com/files/analog/doc/data_sheet/MC34709.pdf?fsrch=1&sr=2
http://cache.freescale.com/files/analog/doc/data_sheet/MC13892.pdf?fsrch=1&sr=1
http://cache.freescale.com/files/32bit/doc/user_guide/IMX50SDG.pdf?fsrch=1&sr=1
http://cache.freescale.com/files/32bit/doc/ref_manual/IMX50RM.pdf?fsrch=1&sr=10
http://cache.freescale.com/files/32bit/doc/data_sheet/IMX50CEC.pdf
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
43
Revision History
7
44
Revision History
Revision
Date
1.0
12/2012
Description of Changes
• Initial release
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
Revision History
Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0
Freescale Semiconductor
45
How to Reach Us:
Information in this document is provided solely to enable system and software
Home Page:
freescale.com
implementers to use Freescale products. There are no express or implied copyright
Web Support:
freescale.com/support
information in this document.
licenses granted hereunder to design or fabricate any integrated circuits on the
Freescale reserves the right to make changes without further notice to any products
herein. Freescale makes no warranty, representation, or guarantee regarding the
suitability of its products for any particular purpose, nor does Freescale assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters that may be provided in Freescale data sheets and/or
specifications can and do vary in different applications, and actual performance may
vary over time. All operating parameters, including “typicals,” must be validated for
each customer application by customer’s technical experts. Freescale does not convey
any license under its patent rights nor the rights of others. Freescale sells products
pursuant to standard terms and conditions of sale, which can be found at the following
address: http://www.reg.net/v2/webservices/Freescale/Docs/TermsandConditions.htm
Freescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire, C-Ware,
Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, Qorivva, StarCore, and
Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.
Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, MagniV, MXC, Platform in a
Package, Processor expert, QorIQ Qonverge, QUICC Engine, Ready Play,
SMARTMOS, TurboLink, Vybrid, and Xtrinsic are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their
respective owners.
© 2012 Freescale Semiconductor, Inc.
Document Number: AN4603
Rev. 1.0
12/2012
Similar pages