74LV132A

74LV132A
QUADRUPLE 2-INPUT NAND GATES WITH SCHMITT TRIGGER INPUTS
Description
Pin Assignments
Preliminary
The 74LV132A provides provides four independent 2-input NAND
gates with standard push-pull outputs. Each input is a Schmitt Trigger
device with a significant amount of hysteresis suiting the device for
noisy environments. The device is designed for operation with a
power supply range of 2.0V to 5.5V.
The inputs are tolerant to 5.5V allowing this device to be used in a
mixed voltage environment. The device is fully specified for partial
power down applications using IOFF. The IOFF circuitry disables the
output preventing damaging current backflow when the device is
powered down.
The gates perform the Boolean function:
Y  A B
or
Y  AB
Features
Applications














Wide Supply Voltage Range from 2.0V to 5.5V
Sinks or sources 12mA at VCC = 4.5V
CMOS low power consumption
IOFF Supports Partial -Power Down Operation
Inputs or Outputs accept up to 5.5V
Inputs can be driven by 3.3V or 5V allowing for voltage
translation applications.
Schmitt Trigger Action at All Inputs
ESD Protection Tested per JESD 22

Exceeds 200-V Machine Model (A115)

Exceeds 2000-V Human Body Model (A114)

Exceeds 1000-V Charged Device Model (C101)
Latch-Up Exceeds 100mA per JESD 78, Class I
Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
Halogen and Antimony Free. “Green” Device (Note 3)
Notes:
General Purpose Logic
Power Down Signal Isolation
Wide array of products such as:

PCs, networking, notebooks, ultrabooks, netbooks

Computer peripherals, hard drives, CD/DVD ROM

TV, DVD, DVR, set top box
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free,
"Green" and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl)
and <1000ppm antimony compounds.
Click for Ordering Information
74LV132A
Document number: DS35706 Rev. 1 - 2
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74LV132A
Pin Descriptions
Logic Diagram
Pin Name
1
1A
Data Input
2
1B
Data Input
3
1Y
Data Output
4
2A
Data Input
5
2B
Data Input
Preliminary
Pin Number
Description
6
2Y
7
GND
Data Output
8
3Y
Data Output
9
3A
Data Input
10
3B
Data Input
1
1A
2
1B
4
2A
5
2B
9
3A
10
3B
1Y
3
2Y
6
3Y
8
Ground
11
4Y
Data Output
12
4A
Data Input
12
4A
13
4B
Data Input
14
Vcc
Supply Voltage
13
4B
4Y 11
Function Table
Inputs
Output
A
B
Y
H
H
L
L
X
H
X
L
H
Absolute Maximum Ratings (Note 4)
Rating
Unit
ESD HBM
Symbol
Human Body Model ESD Protection
2
kV
ESD CDM
Charged Device Model ESD Protection
1
kV
ESD MM
200
V
Supply Voltage Range
-0.5 to 7.0
V
VI
Input Voltage Range note 4
-0.5 to 7.0
V
IIK
Input Clamp Current
-20
mA
IOK
Output Clamp Current
-50
mA
IO
Continuous Output Current - 0.5V < VO VCC + 0.5V
+/- 25
mA
ICC
Continuous Current Through Vcc
50
mA
IGND
Continuous Current Through GND
-50
mA
Operating Junction Temperature
-40 to +150
°C
TSTG
Storage Temperature
-65 to +150
°C
PTOT
Total Power Dissipation
500
mW
VCC
TJ
Note:
Description
Machine Model ESD Protection
VI < 0V
VO < -0V
4. Stresses beyond the absolute maximum may result in immediate failure or reduced reliability. These are stress values and device
operation should be within recommend values.
74LV132A
Document number: DS35706 Rev. 1 - 2
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74LV132A
Recommended Operating Conditions (Note 5)
Symbol
VCC
VI
VO
Parameter
Supply Voltage
Input Voltage
Output Voltage
High-Level Output Current
Preliminary
IOH
Low-Level Output Current
IOL
Min
2.0
0
0
2.0V
–
VCC
-50
2.3V to 2.7V
–
-2
μA
3.0V to 3.6V
–
-6
mA
4.5V to 5.5V
–
-12
mA
2.0V
–
50
μA
2.3V to 2.7V
–
2
mA
3.0V to 3.6V
–
6
mA
4.5V to 5.5V
–
12
mA
–
-40
+125
°C
Operating Free-Air
Temperature
TA
Note:
Conditions
–
–
–
Max
5.5
5.5
Unit
V
V
V
mA
5. Unused inputs should be held at Vcc or Ground.
Electrical Characteristics
Symbol
VT+
VT-
VH
VOH
Parameter
Positive Going
Threshold
Negative Going
Threshold
Hysteresis
(VT+ - VT-)
High-Level
Output Voltage
Test Conditions
VCC
TA = -40 to +85°C
TA = -40 to +125°C
Min
Max
Min
Max
–
2.5 V
1
1.75
1
1.75
–
3.3 V
1.31
2.31
1.31
2.31
–
5.0 V
1.95
3.5
1.95
3.5
–
2.5 V
0.75
1.5
0.75
1.5
–
3.3 V
0.99
2.07
0.99
2.07
–
5.0 V
1.5
3.05
1.5
3.05
–
2.5 V
0.25
1
0.25
1
–
3.3 V
0.33
1.32
0.33
1.32
–
5.0 V
0.5
2
0.5
2
IOH = -50μA
2.0V to 5.5V
VCC-0.1
–
VCC-0.1
–
IOH = -2mA
2.3V
2.0
–
2.0
–
IOH = -6mA
3.0V
2.48
–
2.48
–
IOH = -12mA
4.5V
3.8
–
3.8
–
Unit
V
–
V
V
IOL = 50μA
2.0V to 5.5V
–
0.1
–
0.1
IOL = 2mA
2.3V
–
0.4
–
0.4
IOL = 6mA
3.0V
–
0.44
–
0.44
IOL = 12mA
4.5V
–
0.55
–
0.55
0V
–
5
–
5
μA
VOL
Low-Level
Output Voltage
IOFF
Power Down
VI or VO = 0 to 5.5V
Leakage Current
II
Input Current
VI =GND or 5.5V
0 to 5.5V
–
±1
–
±1
μA
Supply Current
VI = GND or VCC
IO=0
5.5V
–
20
–
20
μA
ICC
74LV132A
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October 2013
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74LV132A
Switching Characteristics
Symbol
Preliminary
tPD
Parameter
Propagation
Delay AN to YN
VCC
Figure 1
CL=15pF
2.5V ± 0.2V
3.3V ± 0.3V
5.0V ± 0.5V
Figure 1
CL=50 pF
-40 to +85°C
-40 to +125°C
15.4
Min
1
1
1
1
1
Max
18.5
14
9
23
17.5
Min
1
1
1
1
1
Max
18.5
14
9
23
17.5
9.7
1
11
1
11
TA = +25°C
Test
Conditions
2.5V ± 0.2V
3.3V ± 0.3V
Min
–
–
–
–
–
Typ.
7.9
5.6
3.9
10.8
7.6
Max
16.5
11.9
7.7
20.2
5.0V ± 0.5V
–
5.3
Unit
ns
ns
Operating Characteristics
TA = +25°C
Test
Conditions
Parameter
Cpd
Power Dissipation
Capacitance per Gate
F= 10 MHz
CL=50pF
VCC
TYP
3.3V
7.5
5.0V
11.2
Unit
pF
Noise Characteristics
VCC =3V, CL=50pF, TA = +25°C
Symbol
Parameter
Min
Typ.
Max
Unit
VOL(p)
Quiet output, maximum dynamic VOL
–
0.2
0.8
VOL(V)
Quiet output, minimum dynamic VOL
–
-0.1
-0.8
V
V
VOH(V)
Quiet output, minimum dynamic VOH
–
3.1
–
–
–
V
–
0.99
V
VIH(D)
High Level dynamic input voltage
VIL(D)
Low Level dynamic input voltage
2.31
–
V
Package Characteristics
Symbol
Ci
Parameter
Input Capacitance
74LV132A
Document number: DS35706 Rev. 1 - 2
Test Conditions
Vi = VCC – or GND
Vcc
Min
Typ.
Max
Unit
2.0 to 5.5V
–
3.3
10
pF
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74LV132A
Preliminary
Parameter Measurement Information
Inputs
Vcc
VI
2.0V to 5.5V
VCC
tr / tf
<3ns
VM
CL
VCC / 2
15pF or 50pF
Voltage Waveform
Pulse Duration
Voltage Waveform
Propagation Delay Times
Inverting and Non Inverting Outputs
Notes: A. Includes test lead and test apparatus capacitance.
B. All pulses are supplied at pulse repetition rate ≤ 10MHz
C. Inputs are measured separately one transition per measurement
D. tPLH and tPHL are the same as tPD
Figure 1. Load Circuit and Voltage Waveforms
74LV132A
Document number: DS35706 Rev. 1 - 2
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74LV132A
Preliminary
Ordering Information
13” Tape and Reel
Package Code
Packaging
(Note 6)
Quantity
Part Number Suffix
74LV132AS14-13
S14
SO-14
2500/Tape & Reel
-13
74LV132AT14-13
T14
TSSOP-14
2500/Tape & Reel
-13
Device
Note:
6. The taping orientation and tape details can be found at http://www.diodes.com/datasheets/ap02007.pdf
Marking Information
(1) SO14, TSSOP14
74LV132A
Document number: DS35706 Rev. 1 - 2
Part Number
Package
74LV132AS14
74LV132AT14
SO-14
TSSOP-14
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74LV132A
Package Outline Dimensions (All Dimensions in mm)
Package Type: SO-14
E
H
Gauge Plane

Detail “A”
D
7°
(4
x)
A2
A
e
B
A1
Detail “A”
0.25
Package Type: TSSOP-14
Pin# 1 Indent
B
L
F1
Gauge Plane
Seating Plane
a2
Preliminary
L
SO-14
Dim
Min
Max
A
1.47
1.73
A1
0.10
0.25
A2
1.45 Typ
B
0.33
0.51
D
8.53
8.74
E
3.80
3.99
e
1.27 Typ
H
5.80
6.20
L
0.38
1.27
0
8

All Dimensions in mm
F
Detail ‘A’
G
K
A
a1
D
C
TSSOP-14
Dim
Min
Max
a1
7° (4X)
a2
8°
0
A
4.9
5.10
B
4.30
4.50
C
1.2

D
0.8
1.05
F
1.00 Typ
F1
0.45
0.75
G
0.65 Typ
K
0.19
0.30
L
6.40 Typ
All Dimensions in mm
Detail ‘A’
74LV132A
Document number: DS35706 Rev. 1 - 2
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74LV132A
Suggested Pad Layout
Package Type: SO-14
X
Dimensions Value (in mm)
X
0.60
Y
1.50
C1
5.4
C2
1.27
Preliminary
C1
C2
Y
Package Type: TSSOP-14
X
C1
C2
Dimensions Value (in mm)
X
0.45
Y
1.45
C1
5.9
C2
0.65
Y
74LV132A
Document number: DS35706 Rev. 1 - 2
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74LV132A
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INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION).
Preliminary
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without further notice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the
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the
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