AN5076, MC34VR500 Layout Guidelines - Application Note

Freescale Semiconductor
Application Note
Document Number: AN5076
Rev. 2.0, 6/2015
MC34VR500 Layout Guidelines
1
Introduction
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
This document describes good practices for layout of the 34VR500
device on printed circuit boards.
2 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Recommended Layer Stack . . . . . . . . . . . . . . . . . . . 2
2
Packaging
4 Component Placement Hints . . . . . . . . . . . . . . . . . . 2
The 34VR500 is a SMARTMOS device intended for use in commercial,
industrial and automotive applications. The 34VR500 is available in a
Wettable-Flank QFN package. The package is 56-pin and has an 8.0 mm
x 8.0 mm outline. Refer to Table 1 for the package drawing information.
Refer to Application Note AN1902 for guidelines on the handling and
assembly of Freescale QFN packages during PCB assembly, guidelines
for PCB design and rework, and package performance information (such
as Moisture Sensitivity Level (MSL) rating, board level reliability,
mechanical, and thermal resistance data).
Package dimensions are provided in package drawings. To find the most
current package outline drawing, go to www.freescale.com and perform a
keyword search for the drawing's document number.
Table 1. Package Drawing Information
Product
Family
Package
Suffix
Package Outline
Drawing Number
MC34VR500
56 QFN-EP WF 8.0 mm x
8.0 mm - 0.5 mm pitch
ES
98ASA00589D
© Freescale Semiconductor, Inc., 2015. All rights reserved.
5 General Routing Guidelines. . . . . . . . . . . . . . . . . . . 2
6 I2C Communication Signals. . . . . . . . . . . . . . . . . . . 2
7 Switching Power Supply Traces . . . . . . . . . . . . . . . 3
8 Effective Grounding . . . . . . . . . . . . . . . . . . . . . . . . . 5
9 Exposed Pad Connection. . . . . . . . . . . . . . . . . . . . . 5
10 Feedback Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 6
11 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
12 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended Layer Stack
3
Recommended Layer Stack
Table 2 shows the recommended layer stack-up for the signals to receive good shielding.
Table 2. Layer Stack-up Recommendation
Layer
Stack-up
Layer 1 (Top)
Signal
Layer 2 (Inner 1)
Ground
Layer 3 (Inner 2)
Power
Layer 4 (Bottom)
Signal/Ground
Note: A more detailed layer design may be required to route the QorlQ processor. If the 34VR500 is being interfaced with a QorlQ
processor, just four of the layers are needed to route it. An example of a design with a QorlQ processor is on the LS1021A IOT Gateway
Board.
4
Component Placement Hints
Place these components as close as possible to the IC in order of priority:
•
Input and decoupling capacitors of the buck regulators (SW1, SW2, SW3, and SW4)
•
VIN, VBG, VCC, and VDIG capacitors
•
REFOUT and LDOs capacitors
•
Switching regulator inductors and output capacitors
5
General Routing Guidelines
•
•
•
•
•
•
6
Shield feedback paths of the regulators from noise planes and traces, and connect them as close as possible to the load
It is recommended to add a high frequency filter input capacitor, to filter out any noise at the buck regulators inputs. This capacitor
should be in the range of 100 nF and should be placed right next to or under the 34VR500, closest to the IC pins (between the
input pin and the exposed pad, for example)
The exposed pad (EP) on the 34VR500 is the high current ground return for the buck regulators. Use vias under the EP to drop
in directly onto the ground plane(s), ensuring sufficient copper for the ground return
SGND1 (pin 14), SGND2 (pin 15), SGND3 (pin 32), and SGND4 (pin 48) are signal ground pins. Connect these pins to the
ground plane using separate vias not through the EP, to prevent coupling from return currents of the switching regulators passing
through the EP
The PVINx and LXx nodes are high dI/dt nodes and act as antennas. They are also high current paths. Hence their traces must
be kept short and wide
Avoid coupling traces between important signal/low noise supplies (like VBG) and switching nodes
I2C Communication Signals
To avoid contamination of these signals by nearby high power or high frequency signals, it is a good practice to shield them with ground
planes placed on adjacent layers. Make sure the ground plane is uniform throughout the whole signal trace length.
AN5076 Application Note Rev. 2.0 6/2015
2
Freescale Semiconductor
Switching Power Supply Traces
Figure 1. Recommended Shielding for Critical Signals
7
Switching Power Supply Traces
In the buck configuration, length of the 'critical traces' must be kept minimal. 'Critical traces' refer to current paths which have high dI/dt.
Refer to Section 7.1 for details.
7.1
Buck Regulator
Figure 2 shows current paths in a buck converter in the 'on' and 'off' periods of the switching cycle. Critical traces refer to traces which
conduct either only during the 'on' or only during the 'off' periods, as highlighted in red.
Control FET On
Synchronous FET On
PVINx
LXx
Critical Traces
EP
Figure 2. Buck Converter Critical Traces
In the buck regulators of the 34VR500, the top and bottom MOSFETs are integrated within the package. Hence, placement of the input
capacitors close to the PVINx pin and the exposed pad (EP) is critical. Figure 4 and Figure 5 show an example layout for the buck
regulators.
AN5076 Application Note Rev. 2.0 6/2015
Freescale Semiconductor
3
Switching Power Supply Traces
Figure 3. SW1 Schematic - Reference for Figures 4 and 5
LX1_3 LX1_2 LX1_1 L1
Figure 4. SW1 Layout - Top Layer Components
AN5076 Application Note Rev. 2.0 6/2015
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Freescale Semiconductor
Effective Grounding
C59 C64 C55 C56 C21
C22 C23 C25 C12 C24 C11 C19 Figure 5. SW1 Layout - Bottom Layer Components
8
Effective Grounding
•
•
•
9
The practice of 'star grounding' must be followed for best performance of the 34VR500
The exposed pad (EP) is the ground return for all the switching regulators and should be connected to the ground plane through
at least 16 thermal vias
SGND1 (pin 14), SGND2 (pin 15), SGND3 (pin 32), and SGND4 (pin 48) are signal ground pins. Connect these pins to the ground
plane using separate vias not through EP, to prevent coupling from return currents of the switching regulators which pass through
the EP
Exposed Pad Connection
The exposed pad (EP) is the ground return for all the switching regulators and should be connected to the ground plane(s) through vias.
A minimum of 16 vias is recommended under the EP. The EP also acts as a heat sink for the 34VR500, hence the vias should not have
thermal relief. They must be solid thermal vias as shown in Figure 6.
Thermal Relief Via – Not Recommended
Solid Thermal Via – Recommended
Figure 6. Types of Via
AN5076 Application Note Rev. 2.0 6/2015
Freescale Semiconductor
5
Feedback Signals
'Wicking' of solder through the bore in the vias increases their thermal resistance. Follow techniques such as tenting or via encroaching
to prevent solder wicking. Using a bore diameter of 0.3 mm or less helps minimize wicking due to the surface tension of the liquid solder.
Apply the solder paste to approximately 50% to 75% of the area of the exposed pad. Rather than applying the solder paste in one large
section, apply it in multiple smaller sections. This can be accomplished by using an array of openings in the solder stencil. Sectioning
helps in even spreading of the solder, as well as in minimizing out-gassing, which can create voids and bridges under the exposed pad.
Figure 7 shows an example of how the exposed pad can be laid out.
Figure 7. Exposed Pad Via Array
10 Feedback Signals
The control loop regulates output voltage at the point where the feedback trace meets the output rail. It is recommended to connect the
feedback trace to the output voltage rail near the load for best load regulation. It must be ensured that this trace does not couple noise
from other traces/layers.
Figure 8 shows an example of layout for a feedback signal connected to a DDR memory.
DDR
34VR500 Figure 8. Feedback Signal
AN5076 Application Note Rev. 2.0 6/2015
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Freescale Semiconductor
References
11 References
Document Number and Description
URL
MC34VR500
Data Sheet
http://www.freescale.com/files/analog/doc/data_sheet/MC34VR500.pdf
AN1902
QFN Application Note
http://www.freescale.com/files/analog/doc/app_note/AN1902.pdf
AN5064
Schematic Guidelines
for the MC34VR500
http://www.freescale.com/files/analog/doc/app_note/AN5064.pdf
Freescale.com Support Pages
URL
MC34VR500 Product Summary Page
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MC34VR500
Power Management Home Page
http://www.freescale.com/webapp/sps/site/homepage.jsp?code=POWERMGTHOME
Analog Home Page
http://www.freescale.com/analog
AN5076 Application Note Rev. 2.0 6/2015
Freescale Semiconductor
7
Revision History
12 Revision History
Revision
Date
Description of Changes
1.0
1/2015
Initial release
2.0
6/2015
AN4530 is replaced by AN1902
AN5076 Application Note Rev. 2.0 6/2015
8
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© 2015 Freescale Semiconductor, Inc.
Document Number: AN5076
Rev. 2.0
6/2015
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