Application Notes

Freescale Semiconductor
Application Note
AN3279
Rev. 3.0, 2/2009
MC34670 Usage and Configuration
By: Jan Krellner
1
Purpose
This document shows how to configure the IC to
comply to the IEEE 802.3af standard and how to
set-up the DC/DC converter part of the IC.
2
Scope
The MC34670 combines a Power Interface Port for
IEEE 802.3af Powered Devices (PD) and a high
performance current mode switching regulator. It
allows Freescale to build PDs with a minimum of
external components by means of integrating the
required IEEE 802.3af functions, and all functions
necessary to build a high efficiency DC/DC
converter.
3
Power-over-Ethernet and
MC34670 Overview
Figure 1 shows a simple 1-port PoE system,
comprising a PSE Hub or Switch (PSE — Power
Sourcing Equipment) and an Ethernet appliance or
© Freescale Semiconductor, Inc., 2006. All rights reserved.
Contents
1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Power-over-Ethernet and
MC34670 Overview . . . . . . . . . . . . . . . . . . . . . 1
3.1 Block Diagram of the MC34670. . . . . . . . . . 3
3.2 Typical Application Schematics . . . . . . . . . 4
4 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Signature Detection and UVLO
Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 Classification . . . . . . . . . . . . . . . . . . . . . . . . 8
4.3 Inrush Current . . . . . . . . . . . . . . . . . . . . . . 10
4.4 Flyback Configuration . . . . . . . . . . . . . . . . 10
4.5 Transient Voltage Suppression . . . . . . . . 33
5 References. . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Power-over-Ethernet and MC34670 Overview
PD (PD — Powered Device). The PoE technology allows transmitting of power along with data
over existing Cat5/Cat5e/Cat6 cables in a safe and reliable manner.
It can be used to power e.g. IP Phones, WLAN Access Points, network cameras, and various
other network terminals that are in the allowed power range of 13 W, as measured at the PD side.
Power-over-Ethernet is also known as Power over LAN. It is based on the IEEE 802.3af
Standard.
RJ-45
PSE Hub or Switch
Ethernet Appliance (PD)
TX
RX
PHY
PHY
RX
Host
Processor
TX
Switch
48-V Power
Supply
Host
Controller
PSE Power
Controller
Cat 5 cable
-48V
PD Power
Controller
GND
-48V
Switch
DC/DC
Figure 1. Simple Power-over-Ethernet System
There are many key benefits of PoE. Only one set of wires is necessary to bring power and data
to the appliance, and this simplifies installation and saves space. There is no need to pay for an
expensive electrician, or delay the installation to meet the electrician's schedule — thus it saves
time and money. Furthermore, the appliance can be easily moved to wherever you can lay a LAN
cable.
Since there are no mains voltages present anywhere, it is safe. Using an uninterruptable power
supply (UPS) can guarantee power to the appliance even during main power failure.
The user can use SNMP (Simple Network Management Protocol) network management
infrastructure to monitor and control the appliance, as well as the data transfer to and from the
appliance. So, the appliances can be managed, shut down or reset remotely in a centralized
matter.
The PD interface of the MC34670 has been designed to comply with the requirements of the
IEEE standard 802.3af.
MC34670 Usage and Configuration, Rev. 3.0
2
Freescale Semiconductor
Power-over-Ethernet and MC34670 Overview
3.1
Block Diagram of the MC34670
Figure 2 shows the block diagram of the MC34670. It can be divided into two sections: on the
left hand side one can find all circuitry that belongs to the PD part of the IC, whereas on the right
hand side all PWM controller functions are located.
FREQ
High Voltage
Regulator
VPWR
VDD
2.5V
8V
Internal
Supply
0.8R
5.7V
R
POR
RCLA
S R
OSC
R
GATE
Q
EN
3.5V
Under Voltage Lock Out OV OR UVLO
Over voltage Detection
OV OR UVLO
5 A
SS
0.3V
Control Logic
5kΩ
S
R
4.5V
PWM
COMPARATOR
Q
0.6 – 2.6V
Blank
CS
0.4V
1.4V
0.6V
Current
limitation
ILIM
3
Gate
Drive
COMP
Slope comp
UVLO
FB
250mV
Rsense
Temp.
Sensor
1.2V
Reg Detect
VOUT
VIN
RESET
Figure 2. MC34670 Block Diagram
On the PD side, the MC34670 fully supports the IEEE802.3af standard and provides complete
signature detection and power classification functions. It controls inrush current limiting and
incorporates an adjustable undervoltage lockout. The MC34670 includes thermal protection
circuitry to protect the device in case of high power dissipation.
The MC34670 also offers an input overvoltage detection to protect the external switching
MOSFET by disabling the gate driver in case of input line overvoltage.
The MC34670 switching regulator provides excellent line and load regulation. It drives an
external power MOSFET with a sense resistor. The switching frequency is adjustable between
100 kHz and 400 kHz. The output voltage feedback information can be accomplished by an
optocoupler, if isolation is required.
An internal logic control block manages the sequencing of signature detection, classification and
proper turn-on and turn-off of the DC/DC converter.
MC34670 Usage and Configuration, Rev. 3.0
Freescale Semiconductor
3
Power-over-Ethernet and MC34670 Overview
3.2
Typical Application Schematics
The MC34670 supports various configurations and settings. On the PD side, it complies with the
IEEE 802.3af standard in terms of signature detection, classification, UVLO and inrush current
requirements, but also supports legacy standards with different UVLO and inrush current needs.
On the PWM controller side it supports isolated or non-isolated Flyback or Forward topologies,
where the switching frequency is adjustable by the IC.
In non-isolated applications, the RESET open-drain output can assert a reset signal whenever
the output voltage VOUT is out of regulation.
Figure 3 shows an application schematic of an isolated Flyback converter using an auxiliary
winding to provide the supply voltage for the gate driver of the external switching MOSFET M1.
T1
NAUX
+VPORT
VOUT = [email protected]
3
NP
34670
RX
NS
VPWR
6
RESET
1
RCLA
VDD
TX
2
R1
CIN
RCLASS
UVLO
R2
4
5
GATE
CDD
0.1 F
CPORT
RV
CS
ILIM
VIN
M1
RCS
SS
FREQ COMP
FB VOUT
-VPORT
CSS
7
8
Figure 3. Isolated Flyback Converter w/ Bias Winding
In cases where the external MOSFET gate drive pulls more than 5 mA of current, an auxiliary
winding is needed to reduce the power dissipation in the internal high voltage LDO. It is
recommended to add a 0.1 μF ceramic capacitor in parallel with the existing load capacitor. This
reduces noise at the VDD pin caused by the auxiliary winding.
The schematic in Figure 3 shows how to configure the default inrush current and UVLO settings.
Pins ILIM and UVLO are connected to VIN and ensure correct settings for IEEE 802.3af
compliance.
For applications which require a lower inrush current limit, a resistor RILIM is added between pins
ILIM and VIN.
To use a switching frequency other than the 250 kHz default frequency the FREQ pin has to be
connected via a resistor RFREQ to VIN, as shown in Figure 4. To use the default switching
frequency, the FREQ pin can be left open or directly connected to VIN as shown in Figure 3.
MC34670 Usage and Configuration, Rev. 3.0
4
Freescale Semiconductor
Power-over-Ethernet and MC34670 Overview
+VPORT
VOUT = [email protected]
T1
3 RX
+
NP
34670
RX
D1
VPWR
6 RX
RESET
+
1 TX
RCLA
VPORT
TX
NS
VDD
2 TX
R1
CIN
UVLO
R2
4
M1
GATE
RCLASS
VIN
RV
CPORT
CS
ILIM
5
CDD
RCS
SS
FREQ COMP
FB VOUT
SPARE+
-VPORT
7
CSS
SPARE-
8
Figure 4. Isolated Flyback Converter w/o Bias Winding
The MC34670 also supports Forward converter topology as depicted in Figure 5. The advantage
of the Forward converter is better efficiency. However it adds a second diode and an inductor on
the secondary side of the converter. If an auxiliary winding is required to supply the gate driver,
the Forward transformer needs a total of 4 windings. This increases the overall cost of the PD
slightly. Furthermore, a Forward converter is usually more difficult to configure and design,
compared to a Flyback converter.
The configuration in Figure 5 also shows the appropriate setup to adjust the UVLO trip point by
adding resistors R1 and R2 between VPWR, UVLO, and VIN.
T1
+VPORT
NR
3
NP
34670
RX
NS
VPWR
6
RESET
1
RCLA
VDD
TX
2
R1
CIN
RCLASS
UVLO
R2
4
GATE
M1
CDD
CPORT
RV
CS
ILIM
RCS
Rv1
5
VIN
SS
FREQ COMP
FB VOUT
Rv2
-VPORT
CSS
7
8
Figure 5. Isolated Forward Converter w/o Bias Winding
MC34670 Usage and Configuration, Rev. 3.0
Freescale Semiconductor
5
Power-over-Ethernet and MC34670 Overview
Figure 6 shows an isolated Flyback Converter that utilizes primary control. Primary control offers
a cheap power supply solution, since it doesn’t use an optocoupler nor a shunt regulator on the
secondary side. However, the line and load regulation of a primary controlled Flyback regulator
is less favorable to an optocoupler/shunt regulated one.
T1
CAUX
NAUX
+VPORT
VOUT = [email protected]
3
NP
34670
RX
NS
VPWR
6
RESET
1
RCLA
VDD
TX
2
R1
CIN
RCLASS
UVLO
R2
4
GATE
5
CDD
CPORT
CS
ILIM
VIN
M1
RCS
SS
FREQ COMP
-VPORT
CSS
FB VOUT
C2
R2
7
C1
8
Figure 6. Isolated Flyback Converter with Primary Control
Figure 7 shows a non-isolated Flyback converter. It uses the default configuration for UVLO and
inrush current limit. In non-isolated applications, the RESET pin can be used to directly drive a
microcontroller RESET pin.
+VPORT
T1
3
NP
34670
RX
VOUT = [email protected]
NS
D1
CO
VPWR
6
RSIG
RESET
1
RCLA
Rpullup
VDD
TX
2
RCLASS
CIN
UVLO
5
VIN
CDD
CPORT
to C RESET pin
CS
ILIM
4
RCS
SS
FREQ COMP
-VPORT
CSS
FB VOUT
C2
R1
R2
7
8
M1
GATE
Rb
C1
Figure 7. Non-Isolated Flyback Converter
MC34670 Usage and Configuration, Rev. 3.0
6
Freescale Semiconductor
Configuration
4
Configuration
This chapter gives detailed explanations how to setup the MC34670. Chapters 4.1 to 4.3 cover
the PD part of the IC, like the inrush current limit and UVLO setup. Chapter 4.4 describes the
configuration of the DC/DC converter. This application note covers only the Flyback topology.
4.1
Signature Detection and UVLO Adjustment
The MC34670 has default UVLO settings that are in line with the IEEE 802.3af Standard. The
standard defines a maximum PD supply turn-on voltage of 42 V and a minimum power supply
turn-off voltage of 30 V, respectively. The maximum turn-on voltage of the device is 40 V and the
minimum turn-off voltage is 30 V, respectively.
Nevertheless, the user can adjust the UVLO voltage by an external resistor divider as sketched
in Figure 8.
Since the UVLO resistor divider replaces the signature resistor, the total resistance of R1 and R2
must equal 25 kΩ.
+VPORT
VPWR
RCLA
R1
UVLO
R2
ILIM
VIN
-VPORT
Figure 8. UVLO Adjustment by External Resistor Divider
To calculate the values for R1 and R2 the following equations should be used:
R sig = R 1 + R 2 = 25kΩ
V UVLO ( REF )
R 2 = ---------------------------- – R SIG
V UVLO ( ON )
where VUVLO(ON) is the desired turn-on voltage threshold and VUVLO(REF) the UVLO reference voltage.
R 1 = R SIG – R 2
MC34670 Usage and Configuration, Rev. 3.0
Freescale Semiconductor
7
Configuration
The typical turn-off voltage VUVLO(OFF) is 85% of the turn-on voltage VUVLO(ON):
V UVLO ( OFF ) = V UVLO ( ON ) ⋅ 0.85
As previously mentioned, the default UVLO settings can be achieved by connecting the UVLO
pin to VIN (Figure 9).
+VPORT
VPWR
RCLA
RSIG
25kΩ
UVLO
ILIM
VIN
-VPORT
Figure 9. Default UVLO Settings
4.2
Classification
The IEEE 802.3af Standard provides the possibility that a PD may optionally be classified by the
PSE (Power Sourcing Equipment). The intent of classification is to provide a method for more
efficient power allocation through the PSE. Knowing the power consumption of all connected
PD’s gives the PSE the ability to budget it’s power resources to always stay within the limits of
the power supply.
The PD classification allows the PSE to identify four different power classes depending on the
required power that the PD will draw during normal operation. The classes and the
corresponding maximum power that will be drawn by the PD is shown in Table 1.
Table 1. PD Classes
Class
Usage
Maximum Power [W]
0
Default
0.44 - 12.95
1
Optional
0.44 - 3.84
2
Optional
3.84 - 6.49
3
Optional
6.49 - 12.95
4
Reserved
MC34670 Usage and Configuration, Rev. 3.0
8
Freescale Semiconductor
Configuration
During classification, the PSE applies a voltage in the range of 15.5 V to 20.5 V to the PD. When
the voltage is applied, the PSE measures the current and determines the class. Table 2 shows
the relationship between class and current.
Table 2. PD Class vs. Classification Current
Classification Current [mA]
Class
0
1
2
3
4
Min
Max
0
9
17
26
36
4
12
20
30
44
To generate a constant current during classification, the MC34670 provides the appropriate
circuitry. An internal LDO generates a constant voltage at pin RCLA and the external resistor
Rclass sets the current depending on the PD class (see Figure 10) following the simple relation:
V RCLA
I CLASS = -----------------R CLASS
+VPort
MC34670
VREF
VPWR
+
-
EN
RSIG
RCLA
ICLASS
VIN
RCLASS
-VPort
Figure 10. Classification Circuitry
Table 3 shows the value for RCLASS that correspond to a PD class.
Table 3. PD Class vs. Classification Resistor Rclass
Classification
Current [mA]
Rclass [Ω]
0
2.0
4.42k
1
2
3
4
10.5
18.5
28.0
40.0
475
261
169
113
Class
MC34670 Usage and Configuration, Rev. 3.0
Freescale Semiconductor
9
Configuration
4.3
Inrush Current
The MC34670 has been also designed to interface with legacy PoE-PSEs, which do not meet
the inrush current requirements of the IEEE 802.3af Standard. By setting the initial inrush current
limit to a low level, a PD using the MC34670 minimizes the current drawn from the PSE during
start-up. The maximum inrush current level can be set by connecting a resistor from pin ILIM to
VIN as illustrated in Figure 11.
+VPORT
VPWR
RCLASS
RCLA
RSIG
25kΩ
UVLO
RILIM
ILIM
VIN
-VPORT
Figure 11. Inrush Current Limitation by External Resistor RILIM
Table 4 shows the selectable current limits and the corresponding value for the resistor that has
to be connected between pins ILIM and VIN.
Table 4. Inrush Current Limit vs. RILIM
Inrush Current Limit [mA]
RILIM Value [kΩ]
180
12.1
110
42.2
65
191
After powering up, the MC34670 switches to the high level current limit, thereby allowing the PD
to consume up to 12.95 watts if a 802.3af PSE is present.
4.4
4.4.1
Flyback Configuration
Flyback Basics
Flyback converters are widely used for output powers from about 150 W down to under 5 W.
They do not require a secondary output inductor (as a Forward converter does), which leads to
power supply cost savings and reduced board space. Usually Flyback converters are easy to
MC34670 Usage and Configuration, Rev. 3.0
10
Freescale Semiconductor
Configuration
design and very robust. They are attractive for multi-output supplies, since line and load
regulation is far better than for the Forward topology.
Flyback topologies store energy during the on time of the power transistor in the power
transformer and deliver energy to the load when the power transistor turns off. This is a
fundamentally different way compared to pure transformer based converters, like the Forward
converter.
4.4.1.1
Topology
A typical Flyback converter is sketched in Figure 12.
ip
T1
is
D1
V
1:n
C
vp
Np
Ns
R
rC
Vg
R1
R2
Q1
DC voltage controlled
variable-width pulse
generator
VREF
Figure 12. General Flyback Topology
The circuitry in Figure 12 has only one output, but multi-output supplies are very common. A
negative feedback loop that includes the resistor divider R1 and R2, the voltage reference
comparator and a PWM controller regulates the output voltage against line and load changes. A
fraction of the output voltage is compared to a reference VREF and the error voltage controls the
on and off time of Q1.
It is important to connect the transformer T1 as indicated in Figure 12 with the dot end (or no-dot
end) of the primary side to the positive terminal of Vg and the dot end (or no-dot end) of the
secondary side to the common secondary ground.
4.4.1.2
Discontinuous Conduction Mode (DCM)
In discontinuous conduction mode the Flyback converter works as follows. During Q1 on time,
the current in the primary winding ramps up linearly at a rate:
MC34670 Usage and Configuration, Rev. 3.0
Freescale Semiconductor
11
Configuration
di p
V
= -----gdt
L
At the end of the on time of Q1 the primary current has ramped up to:
Vg
I p = ------ ⋅ T on
L
When Q1 turns off, the primary current transfers to the secondary side of T1:
I
I s = ---pn
where n is the winding ratio between the secondary and primary side:
The current ramps down linearly at a rate:
N
n = ------s
Np
di s
V
= ----Ls
dt
In discontinuous conduction mode the current ramps down to zero before the start of a new cycle,
and all the energy stored in the primary has been delivered to the secondary and thus to the load.
The current Ip at the end of Ton represents the stored Energy in Joules:
2
L ⋅ ( Ip )
E = -----------------2
Consequently, the power drawn from the supply Vg in a time T is:
2
L ⋅ ( Ip )
P = -----------------2T
2
But,
V g ⋅ T on
( V g ⋅ T on )
I p = ------------------, so P in = -------------------------- [W] . If we let P in = P out
2TL
L
and assuming 100 % efficiency, we get
the following relation between output voltage and input voltage:
2
2
( V g ⋅ T on )
V
--------------------------- = -----2TL
R
V
R
D
After some algebra we find for the conversion ratio: M ( D, K ) = ----- = T on ----------- = -------- , whereas
Vg
2L
K = -------RT
2TL
K
and T on = DT .
To ensure that the core doesn’t saturate and the circuit remains in the discontinuous mode, the
volt-second products A1 and A2 (see Figure 13) must be equal.
MC34670 Usage and Configuration, Rev. 3.0
12
Freescale Semiconductor
Configuration
Ip
Ton
Is
Tr
Tdt
A2
Vdc
A1
Figure 13. Waveforms in DCM
It is therefore advisable to add a dead time Tdt to give extra time and margin before starting a new
cycle. On-time plus reset time should not exceed 80% of one full cycle, or: T on + T r = 0.8T.
4.4.1.3
Continuous Conduction Mode (CCM)
By changing the transformer’s magnetizing inductance and output load, the Flyback converter
changes operating mode. For a given magnetizing inductance the converter works in
discontinuous conduction mode for a certain load, but changes to continuous conduction mode
with increasing load. Generally, a Flyback converter should be designed to work optimally in
either continuous or discontinuous mode.
The difference in the waveforms can be immediately seen in Figure 14. Compared to Figure 13
the primary and secondary currents ip and is have a step at its front end. As for the discontinuous
mode Flyback, the volt-second product across the primary when Q1 is on must be equal that
across it when Q1 is off:
V⋅T
off
V ⋅T
= ------------------g on
n
N
whereas n = -------s . Rearranged, the term for V leads to:
N
p
T
V = V
on
⋅ 1--- ⋅ ---------g n T
off
Thus, the conversion ratio is given by:
whereas
D
D
V
M ( D ) = ------- = n ⋅ ------------- = n -----1–D
D′
V
g
T
T
on
off
D = ---------- , D′ = 1 – D = ----------- .
T
T
MC34670 Usage and Configuration, Rev. 3.0
Freescale Semiconductor
13
Configuration
Ip
ip
Ton
Is
is
Toff
A1
Vg
A2
V + nVg
vp
Figure 14. Waveforms in CCM
4.4.1.4
Conversion Ratio CCM vs. DCM
As previous calculations showed, the conversion ratios for CCM and DCM are very different. For
CCM the conversion ratio depends on the transformer secondary to primary ratio and the duty
cycle. For DCM the conversion ratio depends on K, the duty cycle, and T = 1/f. Figure 15 shows
the curves for CCM and DCM conversion ratio.
(a)
(b)
Figure 15. Conversion Ratio (a) CCM, (b) DCM
MC34670 Usage and Configuration, Rev. 3.0
14
Freescale Semiconductor
Configuration
4.4.1.5
4.4.1.5.1
Flyback Converter Transfer Function and Bode Plot
Continuous Conduction Mode
DCM and CCM have significantly different dynamic behaviors. Figure 16 shows the transfer
function of a Flyback converter in CCM. The transfer function has a right-half-plane zero (RHP)
that is difficult to stabilize and may lead to oscillations of the converter under certain
circumstances. RHP zeros are a characteristic of several converters, including Flybacks in CCM,
caused by mutually responding in the wrong direction when a load change occurs. Figure 16
shows typical open loop gain and phase characteristics of a Flyback converter in CCM.
Figure 16. Open Loop Flyback in CCM
The open loop control-to-output transfer function of a Flyback converter in CCM under current
mode control is defined as:
s ⎞
s⎞ ⎛
⎛
1 + ------ ⋅ 1 – ------------⎝
ω zrhp⎠
ω z⎠ ⎝
f ( s ) = K ⋅ ------------------------------------------------------s
1 + -----ωp
with a dominant pole at:
1+D
ω p = -------------RC
and the RHP zero at:
2
2
R(1 – D)
ω zrhp = ------------------------- , L = L p ⋅ n
DL
MC34670 Usage and Configuration, Rev. 3.0
Freescale Semiconductor
15
Configuration
The ESR zero is located at:
1
ω z = --------rC C
K can be calculated as:
R ⋅ (1 – D)
K = ---------------------------------------------------n ⋅ R CS ⋅ A v ⋅ ( 1 + D )
where RCS is the current sense resistor and AV the gain factor of the CS voltage amplifier. AV is 3
for the MC34670.
4.4.1.5.2
Discontinuous Conduction Mode
Figure 17 shows phase and gain plots of a Flyback converter working in DCM under current
mode control.
Figure 17. Open Loop Flyback in DCM
For DCM operation, the control-to-output transfer function of the Flyback converter using current
mode control is given by: •
S
1 + --------
ωz
f ( s ) = K • ------------------S
1 + --------
ωp
MC34670 Usage and Configuration, Rev. 3.0
16
Freescale Semiconductor
Configuration
As for the Flyback in CCM the ESR zero is located at:
1
ω z = --------rc C
A dominant pole exists at:
2
ω p = --------RC
Contrary to the flyback converter in CCM, there is no RHP zero. The DC gain does not change
as the input voltage varies.
4.4.2
MC34670 Flyback Configuration
The configuration of the device is explained by means of a specific example, but alternatives are
shown where applicable. For most applications, the device is configured as isolated Flyback
converter with the following specification:
• Input voltage VI: 36-57 V
• Output voltage VO: 5 V
• Output current IO: 0.4 - 2 A
• Maximum output ripple Vr: 50 mV
• Converter operates in CCM
Other than the above mentioned specification items, a few design assumptions can be made
prior to the design process. Since the output voltage is set to 5 [email protected] A, an appropriate
transformer can be selected off-the-shelf from different suppliers, e.g. the DA 2362-AL from
Coilcraft. This specific transformer is designed for CCM at 250 kHz switching frequency and has
a bias winding supplying 12 [email protected] mA output.
The input capacitor CIN (see Figure 3) is given by the IEEE 802.3af standard and must not
exceed 0.12 μF, we choose 0.1 μF/100 V. The decoupling capacitor CPORT should be in a range
of 22 μF to 47 μF (100 V rated) with low ESR. Place them near the transformer T1.
4.4.2.1
Calculating RCS
To calculate the current sense resistor it is necessary to know the maximum primary peak current
Ipeak of the transformer drawn at minimum input voltage. This value can usually be found from
the datasheet of the transformer. If not, use the following equations:
1 V
I dc = n ⋅ ----- ⋅ ------o
D' R o
V PORT ⋅ D ⋅ T s
Δi m = ----------------------------------2L
I peak = I dc + Δi m
The equations calculate the magnetizing DC current Idc and the current ripple Δim. Both the
datasheet and the calculations gives the same maximum peak current: Ipeak = 1 A.
MC34670 Usage and Configuration, Rev. 3.0
Freescale Semiconductor
17
Configuration
The MC34670 device offers two voltage trip levels, a high limit at 600 mV without blanking and
a low limit at 400 mV with 50 ns (typical) blanking time. In case of an overcurrent condition, where
the high limit trip point is reached, the GATE output is immediately pulled low and the current
cycle is terminated.
The current sense resistor can then be calculated as follows:
V cs
400mV
R cs = ----------= ------------------- = 400mΩ
1A
I peak
We choose the next smaller standard value, which is 330 mΩ. This gives a maximum peak
current of 1.2 A which is acceptable and tolerable by the transformer. A higher value of the
current sense resistor would lead to a higher voltage drop across the resistor and thus reaching
the low voltage trip level of the current comparator, which leads to premature termination of the
switch cycle at high load and low line condition.
4.4.2.2
Calculating Co
The output capacitor(s) see high stresses in Flyback converters. It is important to select
capacitors which can sustain high current ripple and have low ESR. We’re actually looking for
the minimum output capacitor Co and maximum ESR to be below the maximum specified ripple
voltage Vr. Assuming Vr = VC/2 + VrC/2:
0.37
D
C o = I o ⋅ ---------------- = 2A ⋅ ----------------------------------------- = 120μF
250kHz ⋅ 25mV
VC
f s ⋅ ------2
The maximum duty cycle D can be found easily:
The maximum ESR value is:
1
1
D = ---------------------------------- = ---------------------------------------- = 0.37
36V
⋅
0.25
V PORT ⋅ n
------------------------------ + 1
-----------------------+1
5V + 0.36V
Vo + Vd
1 – 0.37
1–D
ESR = V rC ⋅ ------------- = 25mV ⋅ --------------------- = 8mΩ
2A
Io
4.4.2.3
Snubber Design
Despite the many advantages of the Flyback converter, it has the disadvantage of (large)
transient voltage spikes at the drain of the power switch and also at the secondary rectifier diode.
These spikes are caused by mainly the leakage inductance of the transformer and must be
suppressed to avoid destruction of semiconductors and to reduce noise. The leakage inductance
rings with stray capacitances (PCB layout) and produces the characteristic waveforms.
Snubbers are designed to control and to minimize the effects of the leakage inductance.
Figure 18 shows the waveforms at the drain of the switching MOSFET M1 (a) and at the anode
of the secondary rectifier (b).
MC34670 Usage and Configuration, Rev. 3.0
18
Freescale Semiconductor
Configuration
snubbed waveform
un-snubbed waveform
un-snubbed waveform
(a)
snubbed waveform
(b)
Figure 18. Primary and Secondary Snubbed and Un-Snubbed Waveforms
Figure 19 shows the RC snubber for the primary and secondary side. The resistor Rsn damps
the LC resonance and the series capacitor Csn prevents the voltages from being applied across
the resistor.
RESET
Csn
T1
VDD
GATE
Rsn
VO
Csn
M1
Rsn
NP
NS
CS
RCS
COMP
FB VOUT
Figure 19. Snubber Circuits for Primary and Secondary Side
There is a simple step-by-step approach to determine the correct values for the snubber
elements. This includes as a first step the measurement of the ringing frequency on both the
primary and the secondary sides. See Figure 20, for where to measure the waveforms.
MC34670 Usage and Configuration, Rev. 3.0
Freescale Semiconductor
19
Configuration
RESET
T1
VDD
GATE
NP
M1
VO
NS
CS
RCS
COMP
FB VOUT
Figure 20. Measurement of Waveforms
Once the ringing frequency is know, the remaining steps can be performed as follows:
Z = 2πf r L l
R = Z
1
C = --------------2πf r R
where Ll is the leakage inductance of the transformer. The leakage inductance for the
transformer can be obtained from the datasheet of the transformer.
Assuming the ringing frequencies have been measured as fr(primary) = 17 MHz and
fr(secondary) = 37 MHz we can complete the calculations.
Primary side:
Z = R sn ( primary ) = 2π ⋅ 17MHz ⋅ 1.9μH = 203Ω
1
C sn ( primary ) = --------------------------------------------------- = 46pF
2π ⋅ 17MHz ⋅ 203Ω
Secondary side:
Z = R sn ( sec ondary ) = 2π ⋅ 37MHz ⋅ 43nH = 10Ω
1
C sn ( sec ondary ) = ----------------------------------------------- = 430pF
2π ⋅ 37MHz ⋅ 10Ω
4.4.2.4
Converter Transfer Function and Bode Plot
With the information given in chapter 4.4.1 Flyback Basics we can easily estimate the transfer
function of our Flyback example and draw a Bode plot. In a later step we calculate the
compensation loop elements.
MC34670 Usage and Configuration, Rev. 3.0
20
Freescale Semiconductor
Configuration
NOTE
It is essential for every power supply design to measure the open
loop gain of the converter and re-measure the system after closing
the loop. Never trust only the theoretical calculations and
simulations. Real world systems behave differently, due to parasitics
and nonlinearities of the circuitry or simply due to simplifications we
made during the calculations.
The open loop control-to-output transfer function for the Flyback example is:
s
s⎞ ⎛
⎛ 1 + ----- ⋅ 1 – -------------⎞
⎝
ω zrhp⎠
ω z⎠ ⎝
f p ( s ) = K ⋅ ------------------------------------------------------s
1 + -----ωp
For high load and low input line we get the dominant pole at:
1+D
1 + 0.37
f p = ---------------- = ----------------------------------------------- = 727Hz
2πRC
2π ⋅ 2.5Ω ⋅ 120μF
and the RHP zero at:
2
2
R(1 – D)
2.5Ω ( 1 – 0.37 )
f zrhp = ------------------------- = -------------------------------------------- = 54kHz
2πDL
2π ⋅ 0.37 ⋅ 7.9μH
The ESR zero is located at:
1
1
f z = ---------------- = ----------------------------------------------- = 166kHz
2πr c C
2π ⋅ 8mΩ ⋅ 120μF
K can be calculated as follows and represents the DC gain:
R ⋅ (1 – D)
2.5Ω ⋅ ( 1 – 0.37 )
K = ---------------------------------------------------- = ----------------------------------------------------------------------- = 4.6 = 13dB
n ⋅ R CS ⋅ A v ⋅ ( 1 + D )
0.25 ⋅ 0.33Ω ⋅ 3 ⋅ ( 1 + 0.37 )
Figure 21 shows the transfer function of our example Flyback converter. One can see the poles
and zeros and the DC gain as calculated.
MC34670 Usage and Configuration, Rev. 3.0
Freescale Semiconductor
21
Configuration
20
10
DC gain
fp
Gain (dB)
0
fzrhp fz
-10
-20
-30
-40
-50
10
100
1000
10000
Frequency (Hz)
100000
1000000
100000
1000000
0
-50
Phase (deg)
-100
-150
-200
-250
-300
10
100
1000
10000
Frequency (Hz)
Figure 21. Transfer Function of Flyback Example
4.4.2.5
Flyback Converter Current-Mode Compensation
The compensation network of choice for current mode control is a Type-II amplifier which gives
two poles and one zero, see 4.4.2.6 Type II Amplifier for details. A simple drawing of the
working principle of the Type-II amplifier and the compensation of the Flyback power stage is
shown in Figure 22. There are different approaches where to set the poles and zeros:
a) The first pole is placed at origin for DC regulation. The second pole should be placed just after
the RHP or ESR zero, or at half the switching frequency, whichever is lower in frequency. The
first zero should be placed at about 1/5 of the desired crossover, see Figure 22.
b) Poles and zeros are placed using the K-Factor approach, explained in 4.4.2.8 Feedback
Design Using the K-Factor Approach.
MC34670 Usage and Configuration, Rev. 3.0
22
Freescale Semiconductor
Configuration
fp
Flyback
Power Stage
fs/2
frhp
fesr
Type II
Amplifier
Loop
Gain
0 dB
Figure 22. Flyback Compensation with Type-II Amplifier
4.4.2.5.1
Loop Gain Crossover Frequency
In general, the selection on the loop gain crossover frequency depends on:
• Power supply topology
• Switching frequency fs
• Voltage mode or current mode control
• Output capacitor C
• Power stage components (variations)
Higher crossover frequency can reduce output overshoot but can also increase noise.
4.4.2.5.2
RHP Zero Crossover Limit
As we have seen in the previous chapters, the RHP zero crossover is constrained by the Flyback
power stage dynamics:
2
R ⋅ (1 – D)
f c = ----------------------------2π ⋅ D ⋅ L s
The crossover frequency should not exceed 1/3 the RHP zero.
2
R ⋅ (1 – D)
f c ≤ ----------------------------6π ⋅ D ⋅ L s
4.4.2.5.3
Switching Frequency Crossover Limit
Switching power supplies are sampled data systems. The Nyquist frequency fs/2 is the absolute
limit for fc. However, a more reasonable limit is:
MC34670 Usage and Configuration, Rev. 3.0
Freescale Semiconductor
23
Configuration
fs
f c ≤ --5
Noise becomes an issue if you come closer to the theoretical limit.
4.4.2.5.4
Capacitor ESR Crossover Limit
If the main performance objective of the switch mode power supply is driven by step load
requirements, there is no benefit in raising the crossover frequency above the output capacitor
ESR frequency:
1
f c ≤ -----------------------2π ⋅ C ⋅ r c
4.4.2.5.5
Choosing the Right Crossover Frequency
With the formulas given in chapters 4.4.2.5.2 to 4.4.2.5.4 we are able to choose the right
crossover frequency by picking the one with the lowest frequency:
2
2.5Ω ⋅ ( 1 – 0.37 )
f c ( rhp ) ≤ ---------------------------------------------- = 18kHz
6π ⋅ 0.37 ⋅ 7.9μH
250kHz
f c ( fs ) ≤ --------------------- = 50kHz
5
1
f c ( esr ) ≤ ----------------------------------------------- = 166kHz
2π ⋅ 120μF ⋅ 8mΩ
which results in a crossover frequency of 18 kHz, constrained by the RHP zero.
4.4.2.6
Type II Amplifier
The Type-II amplifier schematic and Bode plot is shown in Figure 23. Rb doesn’t play any role in
the transfer function and has no effect on amplifier gain, but is needed to adjust the output
steady-state voltage.
UGF (unity gain frequency) denotes the pole at the origin. The Type-II amplifier gives a maximum
90 degree phase boost. In practice, fz and fp are placed symmetrically around the desired loop
crossover frequency and gives the maximum phase boost at crossover. The gain at crossover is
roughly the ratio of R2 to R1.
It is recommended to connect R2 rather than C1 to the summing node of the error amplifier.
MC34670 Usage and Configuration, Rev. 3.0
24
Freescale Semiconductor
Configuration
C2
R2
C1
R1
Rb
Gain
dB
Vref
Phase
deg
-1
fz
fp
-1
UGF
-180
Boost
-270
Figure 23. Type-II Amplifier Schematic and Bode Plot
Below is the transfer function of the Type-II amplifier:
1 + sR 2 C 1
T ( s ) = --------------------------------------------------------------------------------C1 C2 ⎞
sR 1 ( C 1 + C 2 ) ⎛ 1 + sR 2 ------------------⎝
C 1 + C 2⎠
1
UGF = ------------------------------------------2π ⋅ R 1 ( C 1 + C 2 )
1
f z = --------------------2πR 2 C 1
1
f p = --------------------------------------C1C2
2π ⋅ R 2 ------------------C1 + C2
MC34670 Usage and Configuration, Rev. 3.0
Freescale Semiconductor
25
Configuration
4.4.2.7
Optocoupler and Shunt Regulator as Feedback
For isolated applications it is necessary to use an optocoupler to close the feedback loop and to
cross the isolation barrier between primary and secondary side. The optocoupler is used in
conjunction with a TL431.
5V
Vo
R4 = 5k
CTR ⋅ R 1 1 + sR 1 C 1
T ( s ) = -----------------------4- ⋅ --- ⋅ -------------------------R 5 R 1 C 1 s 1 + sR 4 C 3
R5
Ve
CTR ⋅ R 4
UGF = -------------------------------2 π ⋅ R5R1C1
C3
CTR
C1
TL431
R1
1
f z = --------------------2 π R1 C1
Rb
1
f p = --------------------2 π R4C3
Figure 24. Schematic of Optocoupler with Shunt Regulator Forming Type-II Amplifier
The circuitry shown in Figure 24 is still a Type-II amplifier. The mid-band gain (between fz and fp
in Figure 23) depends on the current transfer ratio of the optocoupler (CTR) and R4 and R5. R4
is already determined by the 5 kΩ pull-up resistor of the MC34670.
The high frequency pole of the optocoupler feedback circuitry in mainly determined by the
characteristic of the optocoupler and it’s bias point. The more current flowing in the device, the
higher the bandwidth. The rolloff of the gain is usually around 8 kHz to 10 kHz.
Figure 25 shows the gain and phase for the optocoupler feedback circuitry for the values given
below:
R1 = Rb = 5 kΩ
R5 = 2 kΩ
C1 = 100 nF
C3 = 3.9 nF
CTR = 100%
MC34670 Usage and Configuration, Rev. 3.0
26
Freescale Semiconductor
Configuration
60.00
dB(ve/vin)
45.00
fz = 318Hz
30.00
fp = 8.2kHz
(dB)
15.00
0.000
UGF = 3.2 kHz
-15.00
-30.00
-45.00
-60.00
10.00
100.0
1.000k
Frequency (Hz)
10.00k
150.0
100.0k
PHASE(ve/vin)
140.0
130.0
120.0
(Deg)
110.0
100.0
90.00
80.00
70.00
60.00
50.00
10.00
100.0
1.000k
Frequency (Hz)
10.00k
100.0k
Figure 25. Compensation Gain using TL431
4.4.2.8
Feedback Design Using the K-Factor Approach
For designing the feedback loop, we are using the K-Factor approach to synthesize an amplifier
to design a stable feedback loop. For that reason a few preliminary steps are required to proceed:
• Calculate or measure the power stage
• Choose the crossover frequency
• Choose your desired phase margin e.g. 90°/60°/30°
• Determine the required compensator gain at cross-over
• Calculate the required phase boost: Boost = M – P – 90
— M: Modulator phase shift
— P: Desired phase margin
As outlined in chapter 4.4.2.4 Converter Transfer Function and Bode Plot it is good practice
to measure the power stage open loop gain and phase. The calculated poles and zeros should
be in line with the measurement results.
MC34670 Usage and Configuration, Rev. 3.0
Freescale Semiconductor
27
Configuration
We proceed with the proper choice of the crossover frequency as described in chapter 4.4.2.5.5
Choosing the Right Crossover Frequency. After that, we choose our desired phase margin.
60 degrees is a good compromise between high stability (90 degrees) and fast transient
response (30 degrees). Systems with 30 degrees or less phase margin tend to ring and offer less
tolerance against component variations.
For our example:
fc = 18kHz
M = 60
P = -107 degrees
We can now determine the required compensator gain at cross-over and calculate the required
phase boost.
Boost = M – P – 90 = 60 – (-107) – 90 = 77 degrees
4.4.2.8.1
Calculating Components for Type-II Amplifier
Below are the calculations to get the components for the Type-II amplifier:
•
77
Boost
K = tan ⎛ ----------------⎞ + 45 = tan ⎛ ------⎞ + 45 = 8.8
⎝ 2⎠
⎝ 2 ⎠
•
Set R2 to 10 kΩ
•
K
8.8
C 1 = -------------------------- = ------------------------------------------------- = 7.8nF
2 π ⋅ fc ⋅ R2
2 π ⋅ 18kHz ⋅ 10k Ω
•
C1
7.8nF
C 2 = --------------= ------------------- = 102pF
2
2
K –1
8.8 – 1
•
1
1
R 1 = -------------------------------------------- = ------------------------------------------------------------------------ = 2k Ω
2 π ⋅ fc ⋅ G ⋅ K ⋅ C2
2 π ⋅ 18kHz ⋅ 5 ⋅ 8.8 ⋅ 102pF
The poles and zeros of the compensator can be determined as follows:
1
1
UGF = ------------------------------------------------ = ------------------------------------------------------------------------ = 10kHz
2 π ⋅ R1 ⋅ ( C1 + C2 )
2 π ⋅ 2k Ω ⋅ ( 7.8nF + 120pF )
1
1
f z = ----------------------------- = ----------------------------------------------- = 2kHz
2 π ⋅ R2 ⋅ C1
2 π ⋅ 10k Ω ⋅ 7.8nF
1
1
f p = ------------------------------------------- = ----------------------------------------------------------------------- = 158kHz
C1 ⋅ C2
7.8nF ⋅ 102pF
2 π ⋅ 10k Ω ⋅ ---------------------------------------2 π ⋅ R 2 ⋅ -------------------7.8nF + 102pF
C1 + C2
MC34670 Usage and Configuration, Rev. 3.0
28
Freescale Semiconductor
Configuration
The resulting transfer function for the compensator is shown in Figure 26.
70
60
Gain (dB)
50
40
30
fz
20
10
fp
UGF
0
Phase (deg)
10
100
1000
10000
Frequency (Hz)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
100000
1000000
Boost
10
100
1000
10000
Frequency (Hz)
100000
1000000
Figure 26. Transfer Function of the Type-II Compensator
The process of determining the components for the optocoupler feedback circuitry is similar to
the previously shown process. However, as discussed in chapter 4.4.2.7 Optocoupler and
Shunt Regulator as Feedback the second pole cannot be placed at a higher frequency than the
rolloff frequency of the optocoupler. Typically, and depending on the bias current of the
optocoupler, the rolloff frequency is around 8 kHz to 10 kHz.
4.4.2.8.2
Bode Plot — Power Stage, Compensator, and Loop
After calculation of the components for the Type-II amplifier it is good practice to plot the closed
loop transfer function in worst case conditions, e.g. at high input line and light load and at low
input line and full load.
To guarantee stability over the entire input voltage and output load range, the compensator
should be designed at low input line and full load. Furthermore, the design has to be done in such
a way, that mode transitions from CCM to DCM and vice versa don’t lead to unstable behavior.
MC34670 Usage and Configuration, Rev. 3.0
Freescale Semiconductor
29
Configuration
NOTE
If the Flyback converter works in CCM and DCM, design the
feedback loop for CCM. This guarantees stability in CCM and DCM.
The Bode plot in Figure 27 shows the Flyback converter at high input line and light load. The
dominant pole and RHP zero have moved compared to the locations with low input line and full
load and the converter works now in DCM. But as mentioned previously, the converter is still
stable in DCM
Gain (dB)
100
80
Power stage
60
Compensator
40
Loop
20
0
-20
-40
-60
10
100
1000
10000
Frequency (Hz)
100000
1000000
100000
1000000
0
Phase (deg)
-50
-100
-150
-200
-250
10
100
1000
10000
Frequency (Hz)
Figure 27. Flyback Converter at High Input Line and Light Load
As for the Flyback in CCM the ESR zero is located at the same location and doesn’t change
therefore. The DC gain increased to 22 dB and the dominant pole moves to approximately
200 Hz.
Figure 28 shows again the converter Bode plots at full load and low input line, as already shown
in chapter 4.4.2.4.
MC34670 Usage and Configuration, Rev. 3.0
30
Freescale Semiconductor
Configuration
80
Power stage
60
Compensator
Gain (dB)
40
Loop
20
0
-20
-40
-60
10
100
1000
10000
Frequency (Hz)
100000
1000000
0
-50
Phase (deg)
-100
-150
-200
-250
-300
-350
-400
10
100
1000
10000
Frequency (Hz)
100000
1000000
Figure 28. Flyback Converter at Low Input Line and High Load
4.4.3
VDD High Voltage Supply
The internal high voltage supply regulates from the input voltage across VPWR and VIN down to
the VDD voltage. During start-up the high voltage regulator provides the necessary voltage for the
internal gate driver to commence switching. If the external MOSFET gate drive pulls less than
3 mA to 4 mA (average) after start-up and during normal operating conditions, an auxiliary
transformer winding that usually provides the bias voltage for the chip and the gate driver is not
required.
Use the following equation to calculate the average current:
1
I avg = --- ⋅ C eff ⋅ VDD Reg ⋅ f s
2
where
VPWR + VDD Reg
- ⋅ C rss
C eff = C iss + ---------------------------------------------VDD Reg
Ciss and Crss can be found in the datasheet of the external switching MOSFET and fs is the
switching frequency. VPWR is the input voltage of the MC34670 and VDDReg the high voltage
regulator output voltage.
MC34670 Usage and Configuration, Rev. 3.0
Freescale Semiconductor
31
Configuration
In cases where the external MOSFET gate drive pulls more than 5 mA, an auxiliary winding is
needed to reduce the power dissipation in the internal high voltage LDO. Alternatively, the
switching frequency can be reduced or a MOSFET with lower Ceff is used.
A load capacitor on pin VDD is needed to ensure proper behavior and stability of the high voltage
supply. The supply has been designed to allow capacitors with a wide spread of ESRs. Use a
electrolytic capacitor with 10 μF to 20 μF for best performance at lowest cost.
It is recommended to add a 0.1 μF ceramic capacitor in parallel with the existing load capacitor
if the auxiliary winding is used. This reduces noise at the VDD pin caused by the auxiliary winding
when switching on and off.
4.4.4
Efficiency
Figure 29 shows efficiency plots for different PoE transformers with or without use of the bias
winding. It can be seen, that the efficiency is slightly better with bias winding.
MC34670 Efficiency Plot: Vo = 5V, w/o bias winding, Coilcraft
DA2142-AL
90.00
85.00
80.00
%
75.00
70.00
65.00
60.00
57V
55.00
48V
36V
50.00
0.40
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
I O [A]
MC34670 Efficiency Plot: Vo = 5V, w/ bias winding, Coilcraft
DA2362-AL
90.00
85.00
80.00
%
75.00
70.00
65.00
60.00
57V
48V
55.00
36V
50.00
0.40
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
IO [A]
Figure 29. Efficiency Plots for 13 W Transformers
MC34670 Usage and Configuration, Rev. 3.0
32
Freescale Semiconductor
Configuration
4.5
Transient Voltage Suppression
The application can see over 80 V transients at the RJ45 connector, due to possible long cables
(up to 100 m) and Ethernet data transformers. Transients in excess of kV’s are not uncommon.
To prevent these transients from exceeding the device’s maximum voltage rating of 80 V, one can
place a transient voltage surge suppressor (TVS) between VPORT+ and VPORT- in parallel with CIN.
+VPORT
3
RX
6
1
E.g. SMAJ58A
TX
2
CIN
4
5
-VPORT
7
8
Figure 30. Transient Voltage Suppression
The TVS should be selected so it doesn’t trigger below 57 V (maximum PD input voltage), but
must trigger before reaching 80 V (absolute maximum rating of the MC34670). A good choice is
the SMAJ58A or SMAJ60A.
MC34670 Usage and Configuration, Rev. 3.0
Freescale Semiconductor
33
References
5
References
Abraham I. Pressman, Switching Power Supply Design, Second Edition, McGraw-Hill, 1998.
Ron Lenk, Practical Design of Power Supplies, IEEE Press, 2005.
Robert W. Erickson, Dragan Maksimovic, Fundamentals of Power Electronics, Second Edition,
Kluwer, 2001.
Dr. Ray Ridley, Power Supply Design Workshop 2005, Ridley Engineering, Inc., 2005.
MC34670 Usage and Configuration, Rev. 3.0
34
Freescale Semiconductor
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AN3279
Rev. 3.0
2/2009
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