Data Sheet

Freescale Semiconductor
Document Number: MPC885EC
Rev. 7, 07/2010
Technical Data
MPC885/MPC880 PowerQUICC
Hardware Specifications
This hardware specification contains detailed information on
power considerations, DC/AC electrical characteristics, and
AC timing specifications for the MPC885/MPC880. The
MPC885 is the superset device of the MPC885/MPC880
family. The CPU on the MPC885/MPC880 is a 32-bit core
built on Power Architecture™ technology that incorporates
memory management units (MMUs) and instruction and
data caches. For functional characteristics of the
MPC885/MPC880, refer to the MPC885 PowerQUICC
Family Reference Manual.
To locate published errata or updates for this document, refer
to the MPC875/MPC870 product summary page on our
website listed on the back cover of this document or, contact
your local Freescale sales office.
© 2010 Freescale Semiconductor, Inc. All rights reserved.
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Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 9
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . 10
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Thermal Calculation and Measurement . . . . . . . . . . 12
Power Supply and Power Sequencing . . . . . . . . . . . 15
Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 16
IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 44
CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 46
UTOPIA AC Electrical Specifications . . . . . . . . . . . 69
USB Electrical Characteristics . . . . . . . . . . . . . . . . . 71
FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 71
Mechanical Data and Ordering Information . . . . . . . 75
Document Revision History . . . . . . . . . . . . . . . . . . . 85
Overview
1
Overview
The MPC885/MPC880 is a versatile single-chip integrated microprocessor and peripheral combination
that can be used in a variety of controller applications and communications and networking systems. The
MPC885/MPC880 provides enhanced ATM functionality, an additional fast Ethernet controller, a USB,
and an encryption block.
Table 1 shows the functionality supported by MPC885/MPC880.
Table 1. MPC885 Family
Cache (Kbytes)
Ethernet
Part
SCC
SMC
USB
ATM Support
Security
Engine
I Cache
D Cache
10BaseT
10/100
MPC885
8
8
Up to 3
2
3
2
1
Serial ATM and
UTOPIA interface
Yes
MPC880
8
8
Up to 2
2
2
2
1
Serial ATM and
UTOPIA interface
No
2
Features
The MPC885/MPC880 is comprised of three modules that each use the 32-bit internal bus: a MPC8xx
core, a system integration unit (SIU), and a communications processor module (CPM).
The following list summarizes the key MPC885/MPC880 features:
• Embedded MPC8xx core up to 133 MHz
• Maximum frequency operation of the external bus is 80 MHz (in 1:1 mode)
— The 133-MHz core frequency supports 2:1 mode only.
— The 66-/80-MHz core frequencies support both the 1:1 and 2:1 modes.
• Single-issue, 32-bit core (compatible with the Power Architecture definition) with thirty-two
32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch and without conditional
execution.
— 8-Kbyte data cache and 8-Kbyte instruction cache (see Table 1)
– Instruction cache is two-way, set-associative with 256 sets in 2 blocks
– Data cache is two-way, set-associative with 256 sets
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
cache blocks.
– Caches are physically addressed, implement a least recently used (LRU) replacement
algorithm, and are lockable on a cache block basis.
— MMUs with 32-entry TLB, fully associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address
spaces and 16 protection groups
— Advanced on-chip emulation debug mode
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
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Features
•
•
•
•
•
•
•
Provides enhanced ATM functionality found on the MPC862 and MPC866 families and includes
the following:
— Improved operation, administration and maintenance (OAM) support
— OAM performance monitoring (PM) support
— Multiple APC priority levels available to support a range of traffic pace requirements
— Port-to-port switching capability without the need for RAM-based microcode
— Simultaneous MII (100BaseT) and UTOPIA (half- or full -duplex) capability
— Optional statistical cell counters per PHY
— UTOPIA L2-compliant interface with added FIFO buffering to reduce the total cell
transmission time and multi-PHY support. (The earlier UTOPIA L1 specification is also
supported.)
— Parameter RAM for both SPI and I2C can be relocated without RAM-based microcode
— Supports full-duplex UTOPIA master (ATM side) and slave (PHY side) operations using a split
bus
— AAL2/VBR functionality is ROM-resident
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
Thirty-two address lines
Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS to support a DRAM bank
— Up to 30 wait states programmable per memory bank
— Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory
devices
— DRAM controller programmable to support most size and speed memory interfaces
— Four CAS lines, four WE lines, and one OE line
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbytes–256 Mbytes)
— Selectable write protection
— On-chip bus arbitration logic
General-purpose timers
— Four 16-bit timers or two 32-bit timers
— Gate mode can enable/disable counting.
— Interrupt can be masked on reference match and event capture
Two fast Ethernet controllers (FEC)—Two 10/100 Mbps Ethernet/IEEE Std. 802.3™ CDMA/CS
that interface through MII and/or RMII interfaces
System integration unit (SIU)
— Bus monitor
— Software watchdog
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
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Features
•
•
•
— Periodic interrupt timer (PIT)
— Clock synthesizer
— Decrementer and time base
— Reset controller
— IEEE Std 1149.1™ test access port (JTAG)
Security engine is optimized to handle all the algorithms associated with IPsec, SSL/TLS, SRTP,
IEEE Std 802.11i™, and iSCSI processing. Available on the MPC885, the security engine contains
a crypto-channel, a controller, and a set of crypto hardware accelerators (CHAs). The CHAs are:
— Data encryption standard execution unit (DEU)
– DES, 3DES
– Two key (K1, K2, K1) or three key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
— Advanced encryption standard unit (AESU)
– Implements the Rijndael symmetric key cipher
– ECB, CBC, and counter modes
– 128-, 192-, and 256- bit key lengths
— Message digest execution unit (MDEU)
– SHA with 160- or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
— Crypto-channel supporting multi-command descriptor chains
— Integrated controller managing internal resources and bus mastering
— Buffer size of 256 bytes for the DEU, AESU, and MDEU, with flow control for large data sizes
Interrupts
— Six external interrupt request (IRQ) lines
— 12 port pins with interrupt capability
— 23 internal interrupt sources
— Programmable priority between SCCs
— Programmable highest priority request
Communications processor module (CPM)
— RISC controller
— Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT
MODE, and RESTART TRANSMIT)
— Supports continuous mode transmission and reception on all serial channels
— 8-Kbytes of dual-port RAM
— Several serial DMA (SDMA) channels to support the CPM
— Three parallel I/O registers with open-drain capability
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
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Freescale Semiconductor
Features
•
•
•
•
•
On-chip 16 × 16 multiply accumulate controller (MAC)
— One operation per clock (two-clock latency, one-clock blockage)
— MAC operates concurrently with other instructions
— FIR loop—Four clocks per four multiplies
Four baud rate generators
— Independent (can be connected to any SCC or SMC)
— Allow changes during operation
— Autobaud support option
Up to three serial communication controllers (SCCs) supporting the following protocols:
— Serial ATM capability on SCCs
— Optional UTOPIA port on SCC4
— Ethernet/IEEE Std 802.3™ optional on the SCC(s) supporting full 10-Mbps operation
— HDLC/SDLC
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support point-to-point protocol (PPP)
— AppleTalk
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Binary synchronous communication (BISYNC)
— Totally transparent (bit streams)
— Totally transparent (frame based with optional cyclic redundancy check (CRC))
Up to two serial management channels (SMCs) supporting the following protocols:
— UART (low-speed operation)
— Transparent
— General circuit interface (GCI) controller
— Provide management for BRI devices as GCI controller in time-division multiplexed (TDM)
channels
Universal serial bus (USB)—Supports operation as a USB function endpoint, a USB host
controller, or both for testing purposes (loop-back diagnostics)
— USB 2.0 full-/low-speed compatible
— The USB function mode has the following features:
– Four independent endpoints support control, bulk, interrupt, and isochronous data transfers.
– CRC16 generation and checking
– CRC5 checking
– NRZI encoding/decoding with bit stuffing
– 12- or 1.5-Mbps data rate
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
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Features
•
•
•
•
•
•
•
– Flexible data buffers with multiple buffers per frame
– Automatic retransmission upon transmit error
— The USB host controller has the following features:
– Supports control, bulk, interrupt, and isochronous data transfers
– CRC16 generation and checking
– NRZI encoding/decoding with bit stuffing
– Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and
data rate configuration). Note that low-speed operation requires an external hub.
– Flexible data buffers with multiple buffers per frame
– Supports local loop back mode for diagnostics (12 Mbps only)
Serial peripheral interface (SPI)
— Supports master and slave modes
— Supports multiple-master operation on the same bus
Inter-integrated circuit (I2C) port
— Supports master and slave modes
— Supports a multiple-master environment
Time-slot assigner (TSA)
— Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined
— 1- or 8-bit resolution
— Allows independent transmit and receive routing, frame synchronization, and clocking
— Allows dynamic changes
— Can be internally connected to four serial channels (two SCCs and two SMCs)
Parallel interface port (PIP)
— Centronics interface support
— Supports fast connection between compatible ports on MPC885/MPC880 and other MPC8xx
devices
PCMCIA interface
— Master (socket) interface, release 2.1-compliant
— Supports two independent PCMCIA sockets
— 8 memory or I/O windows supported
Debug interface
— Eight comparators: four operate on instruction address, two operate on data address, and two
operate on data
— Supports conditions: = ≠ < >
— Each watchpoint can generate a break point internally.
Normal high and normal low power modes to conserve power
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
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Features
•
•
1.8-V core and 3.3-V I/O operation
The MPC885/MPC880 comes in a 357-pin ball grid array (PBGA) package
The MPC885 block diagram is shown in Figure 1.
8-Kbyte
Instruction
Instruction Cache
Bus
System Interface Unit (SIU)
Instruction MMU
32-Entry ITLB
Embedded
MPC8xx
Processor
Core
Memory Controller
Unified
Bus
Internal
External
Bus Interface Bus Interface
Unit
Unit
8-Kbyte
Data Cache
System Functions
Data MMU
Load/Store
Bus
32-Entry DTLB
PCMCIA-ATA Interface
Slave/Master IF
Security Engine
Fast Ethernet
Controller
Controller
AESU
DEU
MDEU
Channel
DMAs
DMAs
DMAs
FIFOs
4
Timers
Parallel I/O
10/100
BaseT
Media Access
Control
4 Baud Rate
Generators
MIII/RMII
Parallel Interface
Port
USB
Timers
SCC2
Interrupt
8-Kbyte
Controllers Dual-Port RAM
32-Bit RISC Controller
and Program
ROM
SCC3
SCC4/
UTOPIA SMC1
Virtual IDMA
and
Serial DMAs
SMC2
SPI
I2C
Time-Slot Assigner
Serial Interface
Figure 1. MPC885 Block Diagram
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
7
Features
The MPC880 block diagram is shown in Figure 2.
Instruction
8-Kbyte
Bus
Instruction Cache
System Interface Unit (SIU)
Instruction MMU
32-Entry ITLB
Embedded
MPC8xx
Processor
Core
Unified
Bus
8-Kbyte
Data Cache
Memory Controller
External
Internal
Bus Interface Bus Interface
Unit
Unit
System Functions
Data MMU
Load/Store
Bus
32-Entry DTLB
PCMCIA-ATA Interface
Slave/Master IF
Fast Ethernet
Controller
DMAs
DMAs
FIFOs
Parallel I/O
10/100
BaseT
Media Access
Control
4 Baud Rate
Generators
MIII/RMII
Parallel Interface
Port
USB
4
Timers
Interrupt
8-Kbyte
Controllers Dual-Port RAM
32-Bit RISC Controller
and Program
ROM
Virtual IDMA
and
Serial DMAs
Timers
SCC4/
SCC3 UTOPIA SMC1
SMC2
SPI
I 2C
Time-Slot Assigner
Serial Interface
Figure 2. MPC880 Block Diagram
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
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Maximum Tolerated Ratings
3
Maximum Tolerated Ratings
This section provides the maximum tolerated voltage and temperature ranges for the MPC885/MPC880.
Table 2 displays the maximum tolerated ratings, and Table 3 displays the operating temperatures.
Table 2. Maximum Tolerated Ratings
Rating
Symbol
Value
Unit
VDDH
–0.3 to 4.0
V
VDDL
–0.3 to 2.0
V
VDDSYN
–0.3 to 2.0
V
Difference between VDDL and VDDSYN
<100
mV
Input voltage2
Vin
GND – 0.3 to VDDH
V
Storage temperature range
Tstg
–55 to +150
°C
Supply voltage1
1
2
The power supply of the device must start its ramp from 0.0 V.
Functional operating conditions are provided with the DC electrical specifications in Table 6. Absolute maximum ratings are
stress ratings only; functional operation at the maxima is not guaranteed. Stress beyond those listed may affect device
reliability or cause permanent damage to the device. See Section 8, “Power Supply and Power Sequencing.”
Caution: All inputs that tolerate 5 V cannot be more than 2.5 V greater than V DDH. This restriction applies to power up and
normal operation (that is, if the MPC885/MPC880 is unpowered, a voltage greater than 2.5 V must not be applied to its inputs).
Figure 3 shows the undershoot and overshoot voltages at the interfaces of the MPC885/MPC880.
VDDH/VDDL + 20%
VDDH/VDDL + 5%
VIH
VDDH/VDDL
GND
GND – 0.3 V
VIL
GND – 0.7 V
Not to Exceed 10%
of tinterface1
Note:
1. tinterface refers to the clock period associated with the bus clock interface.
Figure 3. Undershoot/Overshoot Voltage for VDDH and VDDL
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
9
Thermal Characteristics
Table 3. Operating Temperatures
Rating
Temperature1 (standard)
Temperature (extended)
1
Symbol
Value
Unit
TA(min)
0
°C
TJ(max)
95
°C
TA(min)
–40
°C
TJ(max)
100
°C
Minimum temperatures are guaranteed as ambient temperature, TA. Maximum
temperatures are guaranteed as junction temperature, TJ.
This device contains circuitry protecting against damage due to high-static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for example, either GND or VDD).
4
Thermal Characteristics
Table 4 shows the thermal characteristics for the MPC885/MPC880.
Table 4. MPC885/MPC880 Thermal Resistance Data
Rating
Environment
Junction-to-ambient1
Natural convection
Airflow (200 ft/min)
Junction-to-board4
Junction-to-case 5
Junction-to-package
1
2
3
4
5
6
top6
Symbol
Value
Unit
Single-layer board (1s)
RθJA2
37
°C/W
Four-layer board (2s2p)
RθJMA3
25
Single-layer board (1s)
RθJMA3
30
Four-layer board (2s2p)
RθJMA3
22
—
—
RθJB
17
—
—
RθJC
10
Natural convection
—
Ψ JT
2
Airflow (200 ft/min)
—
Ψ JT
2
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance.
Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method
(MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. For exposed pad packages
where the pad would be expected to be soldered, junction-to-case thermal resistance is a simulated value from the junction to
the exposed pad without contact resistance.
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2.
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
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Power Dissipation
5
Power Dissipation
Table 5 provides information on power dissipation. The modes are 1:1, where CPU and bus speeds are
equal, and 2:1, where CPU frequency is twice bus speed.
Table 5. Power Dissipation (PD)
Die Revision
Bus Mode
CPU
Frequency
Typical1
Maximum2
Unit
0
1:1
66 MHz
310
390
mW
80 MHz
350
430
mW
133 MHz
430
495
mW
2:1
1
2
Typical power dissipation at VDDL = VDDSYN = 1.8 V, and VDDH is at 3.3 V.
Maximum power dissipation at VDDL = VDDSYN = 1.9 V, and VDDH is at 3.5 V.
NOTE
The values in Table 5 represent VDDL-based power dissipation and do not
include I/O power dissipation over VDDH. I/O power dissipation varies
widely by application due to buffer current, depending on external circuitry.
The VDDSYN power dissipation is negligible.
6
DC Characteristics
Table 6 provides the DC electrical characteristics for the MPC885/MPC880.
Table 6. DC Electrical Specifications
Characteristic
Symbol
Min
Max
Unit
VDDL (core)
1.7
1.9
V
VDDH (I/O)
3.135
3.465
V
VDDSYN1
1.7
1.9
V
Difference
between VDDL
and VDDSYN
—
100
mV
Input high voltage (all inputs except EXTAL and EXTCLK)2
VIH
2.0
3.465
V
Input low voltage3
VIL
GND
0.8
V
VIHC
0.7*(VDDH)
VDDH
V
Input leakage current, Vin = 5.5 V (except TMS, TRST, DSCK and DSDI
pins) for 5-V tolerant pins 2
Iin
—
100
µA
Input leakage current, Vin = VDDH (except TMS, TRST, DSCK, and DSDI)
IIn
—
10
µA
Input leakage current, Vin = 0 V (except TMS, TRST, DSCK and DSDI
pins)
IIn
—
10
µA
Input capacitance4
Cin
—
20
pF
Operating voltage
EXTAL, EXTCLK input high voltage
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
11
Thermal Calculation and Measurement
Table 6. DC Electrical Specifications (continued)
Characteristic
Symbol
Min
Max
Unit
Output high voltage, IOH = –2.0 mA, except XTAL and open-drain pins
VOH
2.4
—
V
Output low voltage
IOL = 2.0 mA (CLKOUT)
IOL = 3.2 mA5
IOL = 5.3 mA6
IOL = 7.0 mA (TXD1/PA14, TXD2/PA12)
IOL = 8.9 mA (TS, TA, TEA, BI, BB, HRESET, SRESET)
VOL
—
0.5
V
1
2
3
4
5
6
The difference between VDDL and VDDSYN cannot be more than 100 mV.
The signals PA[0:15], PB[14:31], PC[4:15], PD[3:15], PE(14:31), TDI, TDO, TCK, TRST, TMS, MII1_TXEN, MII_MDIO are 5-V
tolerant. The minimum voltage is still 2.0 V.
VIL(max) for the I2C interface is 0.8 V rather than the 1.5 V as specified in the I2C standard.
Input capacitance is periodically sampled.
A(0:31), TSIZ0/REG, TSIZ1, D(0:31), IRQ(2:4), IRQ6, RD/WR, BURST, IP_B(3:7), PA(0:11), PA13, PA15, PB(14:31),
PC(4:15), PD(3:15), PE(14:31), MII1_CRS, MII_MDIO, MII1_TXEN, and MII1_COL.
BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:7), WE(0:3), BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1,
GPL_A(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, UPWAITB/GPL_B4, GPL_A5, ALE_A, CE1_A, CE2_A, OP(0:3), and
BADDR(28:30).
7
Thermal Calculation and Measurement
For the following discussions, PD= (VDDL × IDDL) + PI/O, where PI/O is the power dissipation of the I/O
drivers.
NOTE
The VDDSYN power dissipation is negligible.
7.1
Estimation with Junction-to-Ambient Thermal Resistance
An estimation of the chip junction temperature, TJ, in °C can be obtained from the following equation:
TJ = TA + (RθJA × PD)
where:
TA = ambient temperature (ºC)
RθJA = package junction-to-ambient thermal resistance (ºC/W)
PD = power dissipation in package
The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy
estimation of thermal performance. However, the answer is only an estimate; test cases have demonstrated
that errors of a factor of two (in the quantity TJ – TA) are possible.
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
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Freescale Semiconductor
Thermal Calculation and Measurement
7.2
Estimation with Junction-to-Case Thermal Resistance
Historically, thermal resistance has frequently been expressed as the sum of a junction-to-case thermal
resistance and a case-to-ambient thermal resistance:
RθJA = RθJC + RθCA
where:
RθJA = junction-to-ambient thermal resistance (ºC/W)
RθJC = junction-to-case thermal resistance (ºC/W)
RθCA = case-to-ambient thermal resistance (ºC/W)
RθJC is device-related and cannot be influenced by the user. The user adjusts the thermal environment to
affect the case-to-ambient thermal resistance, RθCA. For instance, the user can change the airflow around
the device, add a heat sink, change the mounting arrangement on the printed-circuit board, or change the
thermal dissipation on the printed-circuit board surrounding the device. This thermal model is most useful
for ceramic packages with heat sinks where some 90% of the heat flows through the case and the heat sink
to the ambient environment. For most packages, a better model is required.
7.3
Estimation with Junction-to-Board Thermal Resistance
A simple package thermal model that has demonstrated reasonable accuracy (about 20%) is a two-resistor
model consisting of a junction-to-board and a junction-to-case thermal resistance. The junction-to-case
covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the
top of the package. The junction-to-board thermal resistance describes the thermal performance when most
of the heat is conducted to the printed-circuit board. It has been observed that the thermal performance of
most plastic packages and especially PBGA packages is strongly dependent on the board temperature; see
Figure 4.
Figure 4. Effect of Board Temperature Rise on Thermal Behavior
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
13
Thermal Calculation and Measurement
If the board temperature is known, an estimate of the junction temperature in the environment can be made
using the following equation:
TJ = TB + (RθJB × PD)
where:
RθJB = junction-to-board thermal resistance (ºC/W)
TB = board temperature (ºC)
PD = power dissipation in package
If the board temperature is known and the heat loss from the package case to the air can be ignored,
acceptable predictions of junction temperature can be made. For this method to work, the board and board
mounting must be similar to the test board used to determine the junction-to-board thermal resistance,
namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground
plane.
7.4
Estimation Using Simulation
When the board temperature is not known, a thermal simulation of the application is needed. The simple
two resistor model can be used with the thermal simulation of the application [2], or a more accurate and
complex model of the package can be used in the thermal simulation.
7.5
Experimental Determination
To determine the junction temperature of the device in the application after prototypes are available, the
thermal characterization parameter (ΨJT) can be used to determine the junction temperature with a
measurement of the temperature at the top center of the package case using the following equation:
TJ = TT + (ΨJT × PD)
where:
ΨJT = thermal characterization parameter
TT = thermocouple temperature on top of package
PD = power dissipation in package
The thermal characterization parameter is measured per the JESD51-2 specification published by JEDEC
using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple
should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is
placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The
thermocouple wire is placed flat against the package case to avoid measurement errors caused by the
cooling effects of the thermocouple wire.
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
14
Freescale Semiconductor
Power Supply and Power Sequencing
7.6
References
Semiconductor Equipment and Materials International(415) 964-5111
805 East Middlefield Rd
Mountain View, CA 94043
MIL-SPEC and EIA/JESD (JEDEC) specifications800-854-7179 or
(Available from Global Engineering Documents)303-397-7956
JEDEC Specifications
http://www.jedec.org
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an
Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.
2. 2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal
Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego,
1999, pp. 212–220.
8
Power Supply and Power Sequencing
This section provides design considerations for the MPC885/MPC880 power supply. The
MPC885/MPC880 has a core voltage (VDDL) and PLL voltage (VDDSYN), which both operate at a lower
voltage than the I/O voltage VDDH. The I/O section of the MPC885/MPC880 is supplied with 3.3 V across
VDDH and VSS (GND).
The signals PA[0:15], PB[14:31], PC[4:15], PD[3:15], TDI, TDO, TCK, TRST_B, TMS, MII_TXEN, and
MII_MDIO are 5 V tolerant. All inputs cannot be more than 2.5 V greater than VDDH. In addition, 5-V
tolerant pins cannot exceed 5.5 V and remaining input pins cannot exceed 3.465 V. This restriction applies
to power up/down and normal operation.
One consequence of multiple power supplies is that when power is initially applied the voltage rails ramp
up at different rates. The rates depend on the nature of the power supply, the type of load on each power
supply, and the manner in which different voltages are derived. The following restrictions apply:
• VDDL must not exceed VDDH during power up and power down.
• VDDL must not exceed 1.9 V, and VDDH must not exceed 3.465 V.
These cautions are necessary for the long-term reliability of the part. If they are violated, the electrostatic
discharge (ESD) protection diodes are forward-biased, and excessive current can flow through these
diodes. If the system power supply design does not control the voltage sequencing, the circuit shown
Figure 5 can be added to meet these requirements. The MUR420 Schottky diodes control the maximum
potential difference between the external bus and core power supplies on power up, and the 1N5820 diodes
regulate the maximum potential difference on power down.
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
15
Layout Practices
VDDH
VDDL
MUR420
1N5820
Figure 5. Example Voltage Sequencing Circuit
9
Layout Practices
Each VDD pin on the MPC885/MPC880 should be provided with a low-impedance path to the board’s
supply. Each GND pin should likewise be provided with a low-impedance path to ground. The power
supply pins drive distinct groups of logic on chip. The VDD power supply should be bypassed to ground
using at least four 0.1 µF by-pass capacitors located as close as possible to the four sides of the package.
Each board designed should be characterized and additional appropriate decoupling capacitors should be
used if required. The capacitor leads and associated printed-circuit traces connecting to chip VDD and
GND should be kept to less than half an inch per capacitor lead. At a minimum, a four-layer board
employing two inner layers as VDD and GND planes should be used.
All output pins on the MPC885/MPC880 have fast rise and fall times. Printed-circuit (PC) trace
interconnection length should be minimized in order to minimize undershoot and reflections caused by
these fast output switching times. This recommendation particularly applies to the address and data buses.
Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all
device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and
bypassing becomes especially critical in systems with higher capacitive loads because these loads create
higher transient currents in the VDD and GND circuits. Pull up all unused inputs or signals that will be
inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. For
more information, please refer to the MPC885 PowerQUICC™ Family Reference Manual, Section 14.4.3,
“Clock Synthesizer Power (VDDSYN, VSSSYN, VSSSYN1).”
10 Bus Signal Timing
The maximum bus speed supported by the MPC885/MPC880 is 80 MHz. Higher-speed parts must be
operated in half-speed bus mode (for example, an MPC885/MPC880 used at 133 MHz must be configured
for a 66 MHz bus). Table 7 shows the frequency ranges for standard part frequencies in 1:1 bus mode, and
Table 8 shows the frequency ranges for standard part frequencies in 2:1 bus mode.
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
16
Freescale Semiconductor
Bus Signal Timing
Table 7. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode)
66 MHz
80 MHz
Part Frequency
Min
Max
Min
Max
Core frequency
40
66.67
40
80
Bus frequency
40
66.67
40
80
Table 8. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode)
66 MHz
80 MHz
133 MHz
Part Frequency
Min
Max
Min
Max
Min
Max
Core frequency
40
66.67
40
80
40
133
Bus frequency
20
33.33
20
40
20
66
Table 9 provides the timings for the MPC885/MPC880 at 33-, 40-, 66-, and 80-MHz bus operation.
The timing for the MPC885/MPC880 bus shown assumes a 50-pF load for maximum delays and a 0-pF
load for minimum delays. CLKOUT assumes a 100-pF load for maximum delays and a 50-pF load for
minimum delays.
Table 9. Bus Operation Timings
33 MHz
Num
40 MHz
66 MHz
80 MHz
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
B1
Bus period (CLKOUT), see Table 7
—
—
—
—
—
—
—
—
ns
B1a
EXTCLK to CLKOUT phase skew - If CLKOUT is
an integer multiple of EXTCLK, then the rising
edge of EXTCLK is aligned with the rising edge of
CLKOUT. For a non-integer multiple of EXTCLK,
this synchronization is lost, and the rising edges of
EXTCLK and CLKOUT have a continuously
varying phase skew.
–2
+2
–2
+2
–2
+2
–2
+2
ns
B1b
CLKOUT frequency jitter peak-to-peak
—
1
—
1
—
1
—
1
ns
B1c
Frequency jitter on EXTCLK
—
0.50
—
0.50
—
0.50
—
0.50
%
B1d
CLKOUT phase jitter peak-to-peak for
OSCLK ≥ 15 MHz
—
4
—
4
—
4
—
4
ns
CLKOUT phase jitter peak-to-peak for
OSCLK < 15 MHz
—
5
—
5
—
5
—
5
ns
B2
CLKOUT pulse width low (MIN = 0.4 × B1,
MAX = 0.6 × B1)
12.1
18.2
10.0
15.0
6.1
9.1
5.0
7.5
ns
B3
CLKOUT pulse width high (MIN = 0.4 × B1,
MAX = 0.6 × B1)
12.1
18.2
10.0
15.0
6.1
9.1
5.0
7.5
ns
B4
CLKOUT rise time
—
4.00
—
4.00
—
4.00
—
4.00
ns
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
17
Bus Signal Timing
Table 9. Bus Operation Timings (continued)
33 MHz
Num
40 MHz
66 MHz
80 MHz
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
—
4.00
—
4.00
—
4.00
—
4.00
ns
B5
CLKOUT fall time
B7
CLKOUT to A(0:31), BADDR(28:30), RD/WR,
BURST, D(0:31) output hold (MIN = 0.25 × B1)
7.60
—
6.30
—
3.80
—
3.13
—
ns
B7a
CLKOUT to TSIZ(0:1), REG, RSV, BDIP, PTR
output hold (MIN = 0.25 × B1)
7.60
—
6.30
—
3.80
—
3.13
—
ns
B7b
CLKOUT to BR, BG, FRZ, VFLS(0:1), VF(0:2)
IWP(0:2), LWP(0:1), STS output hold
(MIN = 0.25 × B1)
7.60
—
6.30
—
3.80
—
3.13
—
ns
B8
CLKOUT to A(0:31), BADDR(28:30) RD/WR,
BURST, D(0:31) valid (MAX = 0.25 × B1 + 6.3)
—
13.80
—
12.50
—
10.00
—
9.43
ns
B8a
CLKOUT to TSIZ(0:1), REG, RSV, AT(0:3) BDIP,
PTR valid (MAX = 0.25 × B1 + 6.3)
—
13.80
—
12.50
—
10.00
—
9.43
ns
B8b
CLKOUT to BR, BG, VFLS(0:1), VF(0:2),
IWP(0:2), FRZ, LWP(0:1), STS valid 4
(MAX = 0.25 × B1 + 6.3)
—
13.80
—
12.50
—
10.00
—
9.43
ns
B9
CLKOUT to A(0:31), BADDR(28:30), RD/WR,
BURST, D(0:31), TSIZ(0:1), REG, RSV, AT(0:3),
PTR High-Z (MAX = 0.25 × B1 + 6.3)
7.60 13.80
6.30 12.50
3.80 10.00
3.13
9.43
ns
B11
CLKOUT to TS, BB assertion
(MAX = 0.25 × B1 + 6.0)
7.60 13.60
6.30 12.30
3.80
9.80
3.13
9.13
ns
B11a
CLKOUT to TA, BI assertion (when driven by the
memory controller or PCMCIA interface)
(MAX = 0.00 × B1 + 9.301)
2.50
2.50
9.30
2.50
9.30
2.50
9.30
ns
B12
CLKOUT to TS, BB negation
(MAX = 0.25 × B1 + 4.8)
7.60 12.30
6.30 11.00
3.80
8.50
3.13
7.92
ns
B12a
CLKOUT to TA, BI negation (when driven by the
memory controller or PCMCIA interface)
(MAX = 0.00 × B1 + 9.00)
2.50
2.50
2.50
9.00
2.5
9.00
ns
B13
CLKOUT to TS, BB High-Z (MIN = 0.25 × B1)
7.60 21.60
6.30 20.30
3.80 14.00
3.13 12.93
ns
B13a
CLKOUT to TA, BI High-Z (when driven by the
memory controller or PCMCIA interface)
(MIN = 0.00 × B1 + 2.5)
2.50 15.00
2.50 15.00
2.50 15.00
2.5
15.00
ns
B14
CLKOUT to TEA assertion
(MAX = 0.00 × B1 + 9.00)
2.50
2.50
2.50
2.50
9.00
ns
B15
CLKOUT to TEA High-Z (MIN = 0.00 × B1 + 2.50) 2.50 15.00
2.50 15.00
2.50 15.00
2.50 15.00
ns
B16
TA, BI valid to CLKOUT (setup time)
(MIN = 0.00 × B1 + 6.00)
6.00
—
6.00
—
6.00
—
6
—
ns
B16a
TEA, KR, RETRY, CR valid to CLKOUT (setup
time) (MIN = 0.00 × B1 + 4.5)
4.50
—
4.50
—
4.50
—
4.50
—
ns
9.30
9.00
9.00
9.00
9.00
9.00
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
18
Freescale Semiconductor
Bus Signal Timing
Table 9. Bus Operation Timings (continued)
33 MHz
Num
40 MHz
66 MHz
80 MHz
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
B16b
BB, BG, BR, valid to CLKOUT (setup time)2
(4MIN = 0.00 × B1 + 0.00)
4.00
—
4.00
—
4.00
—
4.00
—
ns
B17
CLKOUT to TA, TEA, BI, BB, BG, BR valid (hold
time) (MIN = 0.00 × B1 + 1.003)
1.00
—
1.00
—
2.00
—
2.00
—
ns
B17a
CLKOUT to KR, RETRY, CR valid (hold time)
(MIN = 0.00 × B1 + 2.00)
2.00
—
2.00
—
2.00
—
2.00
—
ns
B18
D(0:31) valid to CLKOUT rising edge (setup time)4
(MIN = 0.00 × B1 + 6.00)
6.00
—
6.00
—
6.00
—
6.00
—
ns
B19
CLKOUT rising edge to D(0:31) valid (hold time)4
(MIN = 0.00 × B1 + 1.005)
1.00
—
1.00
—
2.00
—
2.00
—
ns
B20
D(0:31) valid to CLKOUT falling edge (setup
time)6 (MIN = 0.00 × B1 + 4.00)
4.00
—
4.00
—
4.00
—
4.00
—
ns
B21
CLKOUT falling edge to D(0:31) valid (hold time)6
(MIN = 0.00 × B1 + 2.00)
2.00
—
2.00
—
2.00
—
2.00
—
ns
B22
CLKOUT rising edge to CS asserted GPCM
ACS = 00 (MAX = 0.25 × B1 + 6.3)
7.60 13.80
3.13
9.43
ns
B22a
CLKOUT falling edge to CS asserted GPCM
ACS = 10, TRLX = [0 or 1]
(MAX = 0.00 × B1 + 8.00)
—
8.00
ns
B22b
CLKOUT falling edge to CS asserted GPCM
ACS = 11, TRLX = [0 or 1], EBDF = 0
(MAX = 0.25 × B1 + 6.3)
7.60 13.80
6.30 12.50
3.80 10.00
3.13
9.43
ns
B22c
CLKOUT falling edge to CS asserted GPCM
ACS = 11, TRLX = [0 or 1], EBDF = 1
(MAX = 0.375 × B1 + 6.6)
10.90 18.00 10.90 16.00
5.20 12.30
4.69 10.93
ns
B23
CLKOUT rising edge to CS negated GPCM read
access, GPCM write access ACS = 00 and CSNT
= 0 (MAX = 0.00 × B1 + 8.00)
2.00
8.00
2.00
8.00
2.00
8.00
2.00
8.00
ns
B24
A(0:31) and BADDR(28:30) to CS asserted
GPCM ACS = 10, TRLX = 0
(MIN = 0.25 × B1 – 2.00)
5.60
—
4.30
—
1.80
—
1.13
—
ns
B24a
A(0:31) and BADDR(28:30) to CS asserted
GPCM ACS = 11 TRLX = 0
(MIN = 0.50 × B1 – 2.00)
13.20
—
10.50
—
5.60
—
4.25
—
ns
B25
CLKOUT rising edge to OE, WE(0:3) asserted
(MAX = 0.00 × B1 + 9.00)
—
9.00
—
9.00
—
9.00
—
9.00
ns
B26
CLKOUT rising edge to OE negated
(MAX = 0.00 × B1 + 9.00)
2.00
9.00
2.00
9.00
2.00
9.00
2.00
9.00
ns
B27
A(0:31) and BADDR(28:30) to CS asserted
GPCM ACS = 10, TRLX = 1
(MIN = 1.25 × B1 – 2.00)
35.90
—
29.30
—
16.90
—
13.60
—
ns
—
8.00
6.30 12.50
—
8.00
3.80 10.00
—
8.00
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
19
Bus Signal Timing
Table 9. Bus Operation Timings (continued)
33 MHz
Num
40 MHz
66 MHz
80 MHz
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
43.50
—
35.50
—
20.70
—
16.75
—
ns
—
9.00
—
9.00
—
9.00
—
9.00
ns
3.13
9.93
ns
—
9.93
ns
4.69 11.29
ns
B27a
A(0:31) and BADDR(28:30) to CS asserted
GPCM ACS = 11, TRLX = 1
(MIN = 1.50 × B1 – 2.00)
B28
CLKOUT rising edge to WE(0:3) negated GPCM
write access CSNT = 0 (MAX = 0.00 × B1 + 9.00)
B28a
CLKOUT falling edge to WE(0:3) negated GPCM
write access TRLX = 0, CSNT = 1, EBDF = 0
(MAX = 0.25 × B1 + 6.80)
B28b
CLKOUT falling edge to CS negated GPCM write
access TRLX = 0, CSNT = 1 ACS = 10 or
ACS = 11, EBDF = 0 (MAX = 0.25 × B1 + 6.80)
B28c
CLKOUT falling edge to WE(0:3) negated GPCM 10.90 18.00 10.90 18.00
write access TRLX = 0, CSNT = 1 write access
TRLX = 0, CSNT = 1, EBDF = 1
(MAX = 0.375 × B1 + 6.6)
B28d
CLKOUT falling edge to CS negated GPCM write
access TRLX = 0, CSNT = 1, ACS = 10, or
ACS = 11, EBDF = 1 (MAX = 0.375 × B1 + 6.6)
—
18.00
—
18.00
—
12.30
—
11.30
ns
B29
WE(0:3) negated to D(0:31) High-Z GPCM write
access, CSNT = 0, EBDF = 0
(MIN = 0.25 × B1 – 2.00)
5.60
—
4.30
—
1.80
—
1.13
—
ns
B29a
WE(0:3) negated to D(0:31) High-Z GPCM write
access, TRLX = 0, CSNT = 1, EBDF = 0
(MIN = 0.50 × B1 – 2.00)
13.20
—
10.50
—
5.60
—
4.25
—
ns
B29b
CS negated to D(0:31) High-Z GPCM write
access, ACS = 00, TRLX = 0 & CSNT = 0
(MIN = 0.25 × B1 – 2.00)
5.60
—
4.30
—
1.80
—
1.13
—
ns
B29c
CS negated to D(0:31) High-Z GPCM write
access, TRLX = 0, CSNT = 1, ACS = 10, or
ACS = 11 EBDF = 0 (MIN = 0.50 × B1 – 2.00)
13.20
—
10.50
—
5.60
—
4.25
—
ns
B29d
WE(0:3) negated to D(0:31) High-Z GPCM write
access, TRLX = 1, CSNT = 1, EBDF = 0
(MIN = 1.50 × B1 – 2.00)
43.50
—
35.50
—
20.70
—
16.75
—
ns
B29e
CS negated to D(0:31) High-Z GPCM write
access, TRLX = 1, CSNT = 1, ACS = 10, or
ACS = 11 EBDF = 0 (MIN = 1.50 × B1 – 2.00)
43.50
—
35.50
—
20.70
—
16.75
—
ns
B29f
WE(0:3) negated to D(0:31) High-Z GPCM write
access, TRLX = 0, CSNT = 1, EBDF = 1
(MIN = 0.375 × B1 – 6.30)7
5.00
—
3.00
—
0.00
—
0.00
—
ns
B29g
CS negated to D(0:31) High-Z GPCM write
access, TRLX = 0, CSNT = 1 ACS = 10 or
ACS = 11, EBDF = 1 (MIN = 0.375 × B1 – 6.30)7
5.00
—
3.00
—
0.00
—
0.00
—
ns
7.60 14.30
—
14.30
6.30 13.00
—
13.00
3.80 10.50
—
10.50
5.20 12.30
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
20
Freescale Semiconductor
Bus Signal Timing
Table 9. Bus Operation Timings (continued)
33 MHz
Num
40 MHz
66 MHz
80 MHz
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
B29h
WE(0:3) negated to D(0:31) High-Z GPCM write
access, TRLX = 1, CSNT = 1, EBDF = 1
(MIN = 0.375 × B1 – 3.30)
38.40
—
31.10
—
17.50
—
13.85
—
ns
B29i
CS negated to D(0:31) High-Z GPCM write
access, TRLX = 1, CSNT = 1, ACS = 10 or
ACS = 11, EBDF = 1 (MIN = 0.375 × B1 – 3.30)
38.40
—
31.10
—
17.50
—
13.85
—
ns
B30
CS, WE(0:3) negated to A(0:31), BADDR(28:30)
Invalid GPCM read/write access8
(MIN = 0.25 × B1 – 2.00)
5.60
—
4.30
—
1.80
—
1.13
—
ns
B30a
13.20
WE(0:3) negated to A(0:31), BADDR(28:30)
Invalid GPCM, write access, TRLX = 0, CSNT = 1,
CS negated to A(0:31) invalid GPCM write access
TRLX = 0, CSNT =1 ACS = 10, or ACS == 11,
EBDF = 0 (MIN = 0.50 × B1 – 2.00)
—
10.50
—
5.60
—
4.25
—
ns
B30b
43.50
WE(0:3) negated to A(0:31) invalid GPCM
BADDR(28:30) invalid GPCM write access,
TRLX = 1, CSNT = 1. CS negated to A(0:31)
invalid GPCM write access TRLX = 1, CSNT = 1,
ACS = 10, or ACS == 11 EBDF = 0
(MIN = 1.50 × B1 – 2.00)
—
35.50
—
20.70
—
16.75
—
ns
B30c
WE(0:3) negated to A(0:31), BADDR(28:30)
invalid GPCM write access, TRLX = 0, CSNT = 1.
CS negated to A(0:31) invalid GPCM write
access, TRLX = 0, CSNT = 1 ACS = 10,
ACS == 11, EBDF = 1 (MIN = 0.375 × B1 – 3.00)
8.40
—
6.40
—
2.70
—
1.70
—
ns
B30d
38.67
WE(0:3) negated to A(0:31), BADDR(28:30)
invalid GPCM write access TRLX = 1, CSNT =1,
CS negated to A(0:31) invalid GPCM write access
TRLX = 1, CSNT = 1, ACS = 10 or 11, EBDF = 1
—
31.38
—
17.83
—
14.19
—
ns
B31
CLKOUT falling edge to CS valid, as requested by
control bit CST4 in the corresponding word in the
UPM (MAX = 0.00 × B1 + 6.00)
1.50
6.00
1.50
6.00
1.50
6.00
1.50
6.00
ns
B31a
CLKOUT falling edge to CS valid, as requested by
control bit CST1 in the corresponding word in the
UPM (MAX = 0.25 × B1 + 6.80)
7.60 14.30
6.30 13.00
3.80 10.50
3.13 10.00
ns
B31b
CLKOUT rising edge to CS valid, as requested by
control bit CST2 in the corresponding word in the
UPM (MAX = 0.00 × B1 + 8.00)
1.50
1.50
1.50
8.00
1.50
8.00
ns
B31c
CLKOUT rising edge to CS valid, as requested by
control bit CST3 in the corresponding word in the
UPM (MAX = 0.25 × B1 + 6.30)
7.60 13.80
6.30 12.50
3.80 10.00
3.13
9.40
ns
B31d
CLKOUT falling edge to CS valid, as requested by 13.30 18.00 11.30 16.00
control bit CST1 in the corresponding word in the
UPM EBDF = 1 (MAX = 0.375 × B1 + 6.6)
7.60 12.30
4.69 11.30
ns
8.00
8.00
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
21
Bus Signal Timing
Table 9. Bus Operation Timings (continued)
33 MHz
Num
40 MHz
66 MHz
80 MHz
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
6.00
1.50
6.00
1.50
6.00
1.50
6.00
ns
B32
CLKOUT falling edge to BS valid, as requested by
control bit BST4 in the corresponding word in the
UPM (MAX = 0.00 × B1 + 6.00)
1.50
B32a
CLKOUT falling edge to BS valid, as requested by
control bit BST1 in the corresponding word in the
UPM, EBDF = 0 (MAX = 0.25 × B1 + 6.80)
7.60 14.30
6.30 13.00
3.80 10.50
3.13 10.00
ns
B32b
CLKOUT rising edge to BS valid, as requested by
control bit BST2 in the corresponding word in the
UPM (MAX = 0.00 × B1 + 8.00)
1.50
1.50
1.50
1.50
8.00
ns
B32c
CLKOUT rising edge to BS valid, as requested by
control bit BST3 in the corresponding word in the
UPM (MAX = 0.25 × B1 + 6.80)
7.60 14.30
6.30 13.00
3.80 10.50
3.13 10.00
ns
B32d
CLKOUT falling edge to BS valid, as requested by 13.30 18.00 11.30 16.00
control bit BST1 in the corresponding word in the
UPM, EBDF = 1 (MAX = 0.375 × B1 + 6.60)
7.60 12.30
4.49 11.30
ns
B33
CLKOUT falling edge to GPL valid, as requested
by control bit GxT4 in the corresponding word in
the UPM (MAX = 0.00 × B1 + 6.00)
1.50
1.50
1.50
6.00
ns
B33a
CLKOUT rising edge to GPL valid, as requested
by control bit GxT3 in the corresponding word in
the UPM (MAX = 0.25 × B1 + 6.80)
7.60 14.30
6.30 13.00
3.80 10.50
3.13 10.00
ns
B34
A(0:31), BADDR(28:30), and D(0:31) to CS valid,
as requested by control bit CST4 in the
corresponding word in the UPM
(MIN = 0.25 × B1 – 2.00)
5.60
—
4.30
—
1.80
—
1.13
—
ns
B34a
A(0:31), BADDR(28:30), and D(0:31) to CS valid, 13.20
as requested by control bit CST1 in the
corresponding word in the UPM
(MIN = 0.50 × B1 – 2.00)
—
10.50
—
5.60
—
4.25
—
ns
B34b
A(0:31), BADDR(28:30), and D(0:31) to CS valid, 20.70
as requested by CST2 in the corresponding word
in UPM (MIN = 0.75 × B1 – 2.00)
—
16.70
—
9.40
—
6.80
—
ns
B35
A(0:31), BADDR(28:30) to CS valid, as requested
by control bit BST4 in the corresponding word in
the UPM (MIN = 0.25 × B1 – 2.00)
5.60
—
4.30
—
1.80
—
1.13
—
ns
B35a
A(0:31), BADDR(28:30), and D(0:31) to BS valid, 13.20
as requested by BST1 in the corresponding word
in the UPM (MIN = 0.50 × B1 – 2.00)
—
10.50
—
5.60
—
4.25
—
ns
B35b
A(0:31), BADDR(28:30), and D(0:31) to BS valid, 20.70
as requested by control bit BST2 in the
corresponding word in the UPM
(MIN = 0.75 × B1 – 2.00)
—
16.70
—
9.40
—
7.40
—
ns
8.00
6.00
1.50
8.00
6.00
8.00
6.00
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
22
Freescale Semiconductor
Bus Signal Timing
Table 9. Bus Operation Timings (continued)
33 MHz
Num
40 MHz
66 MHz
80 MHz
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
B36
A(0:31), BADDR(28:30), and D(0:31) to GPL
valid, as requested by control bit GxT4 in the
corresponding word in the UPM
(MIN = 0.25 × B1 – 2.00)
5.60
—
4.30
—
1.80
—
1.13
—
ns
B37
UPWAIT valid to CLKOUT falling edge9
(MIN = 0.00 × B1 + 6.00)
6.00
—
6.00
—
6.00
—
6.00
—
ns
B38
CLKOUT falling edge to UPWAIT valid 9
(MIN = 0.00 × B1 + 1.00)
1.00
—
1.00
—
1.00
—
1.00
—
ns
B39
AS valid to CLKOUT rising edge10
(MIN = 0.00 × B1 + 7.00)
7.00
—
7.00
—
7.00
—
7.00
—
ns
B40
A(0:31), TSIZ(0:1), RD/WR, BURST, valid to
CLKOUT rising edge (MIN = 0.00 × B1 + 7.00)
7.00
—
7.00
—
7.00
—
7.00
—
ns
B41
TS valid to CLKOUT rising edge (setup time)
(MIN = 0.00 × B1 + 7.00)
7.00
—
7.00
—
7.00
—
7.00
—
ns
B42
CLKOUT rising edge to TS valid (hold time)
(MIN = 0.00 × B1 + 2.00)
2.00
—
2.00
—
2.00
—
2.00
—
ns
B43
AS negation to memory controller signals
negation (MAX = TBD)
—
TBD
—
TBD
—
TBD
—
TBD
ns
1
For part speeds above 50 MHz, use 9.80 ns for B11a.
The timing required for BR input is relevant when the MPC885/MPC880 is selected to work with the internal bus arbiter. The
timing for BG input is relevant when the MPC885/MPC880 is selected to work with the external bus arbiter.
3 For part speeds above 50 MHz, use 2 ns for B17.
4 The D(0:31) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input signal is asserted.
5 For part speeds above 50 MHz, use 2 ns for B19.
6 The D(0:31) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only for read accesses
controlled by chip-selects under control of the user-programmable machine (UPM) in the memory controller, for data beats
where DLT3 = 1 in the RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
7 This formula applies to bus operation up to 50 MHz.
8
The timing B30 refers to CS when ACS = 00 and to CS and WE(0:3) when CSNT = 0.
9
The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified in B37 and
B38 are specified to enable the freeze of the UPM output signals as described in Figure 21.
10 The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior specified
in Figure 24.
2
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
23
Bus Signal Timing
Figure 6 provides the control timing diagram.
CLKOUT
A
B
Outputs
A
B
Outputs
D
C
Inputs
D
C
Inputs
A
Maximum output delay specification.
B
Minimum output hold time.
C
Minimum input setup time specification.
D
Minimum input hold time specification.
Figure 6. Control Timing
Figure 7 provides the timing for the external clock.
CLKOUT
B1
B3
B1
B4
B2
B5
Figure 7. External Clock Timing
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
24
Freescale Semiconductor
Bus Signal Timing
Figure 8 provides the timing for the synchronous output signals.
CLKOUT
B8
B7
B9
Output
Signals
B8a
B7a
B9
Output
Signals
B8b
B7b
Output
Signals
Figure 8. Synchronous Output Signals Timing
Figure 9 provides the timing for the synchronous active pull-up and open-drain output signals.
CLKOUT
B13
B11
B12
TS, BB
B13a
B11a
B12a
TA, BI
B14
B15
TEA
Figure 9. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
25
Bus Signal Timing
Figure 10 provides the timing for the synchronous input signals.
CLKOUT
B16
B17
TA, BI
B16a
B17a
TEA, KR,
RETRY, CR
B16b
B17
BB, BG, BR
Figure 10. Synchronous Input Signals Timing
Figure 11 provides normal case timing for input data. It also applies to normal read accesses under the
control of the user-programmable machine (UPM) in the memory controller.
CLKOUT
B16
B17
TA
B18
B19
D[0:31]
Figure 11. Input Data Timing in Normal Case
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
26
Freescale Semiconductor
Bus Signal Timing
Figure 12 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in
the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
CLKOUT
TA
B20
B21
D[0:31]
Figure 12. Input Data Timing when Controlled by UPM in the Memory Controller and DLT3 = 1
Figure 13 through Figure 16 provide the timing for the external bus read controlled by various GPCM
factors.
CLKOUT
B11
B12
TS
B8
A[0:31]
B22
B23
CSx
B25
B26
OE
B28
WE[0:3]
B19
B18
D[0:31]
Figure 13. External Bus Read Timing (GPCM Controlled—ACS = 00)
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
27
Bus Signal Timing
CLKOUT
B11
B12
TS
B8
A[0:31]
B23
B22a
CSx
B24
B25
B26
OE
B18
B19
D[0:31]
Figure 14. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10)
CLKOUT
B11
B12
TS
B8
B22b
A[0:31]
B22c
B23
CSx
B24a
B25
B26
OE
B18
B19
D[0:31]
Figure 15. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11)
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
28
Freescale Semiconductor
Bus Signal Timing
CLKOUT
B11
B12
TS
B8
A[0:31]
B23
B22a
CSx
B27
OE
B26
B27a
B22b B22c
B18
B19
D[0:31]
Figure 16. External Bus Read Timing (GPCM Controlled—TRLX = 1, ACS = 10, ACS = 11)
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
29
Bus Signal Timing
Figure 17 through Figure 19 provide the timing for the external bus write controlled by various GPCM
factors.
CLKOUT
B11
B12
TS
B8
B30
A[0:31]
B22
B23
CSx
B25
B28
WE[0:3]
B29b
B26
OE
B29
B8
B9
D[0:31]
Figure 17. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 0)
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
30
Freescale Semiconductor
Bus Signal Timing
CLKOUT
B11
B12
TS
B30a B30c
B8
A[0:31]
B22
B23
B28b B28d
CSx
B29c B29g
B25
WE[0:3]
B29a B29f
B26
OE
B28a B28c
B8
B9
D[0:31]
Figure 18. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1)
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
31
Bus Signal Timing
CLKOUT
B11
B12
TS
B8
B30b B30d
A[0:31]
B22
B28b B28d
B23
CSx
B25
B29e B29i
WE[0:3]
B29d B29h
B26
OE
B29b
B8
B28a B28c
B9
D[0:31]
Figure 19. External Bus Write Timing (GPCM Controlled—TRLX = 1, CSNT = 1)
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
32
Freescale Semiconductor
Bus Signal Timing
Figure 20 provides the timing for the external bus controlled by the UPM.
CLKOUT
B8
A[0:31]
B31a
B31d
B31c
B31b
B31
CSx
B34
B34a
B34b
B32a B32d
B32c
B32b
B32
BS_A[0:3],
BS_B[0:3]
B35 B36
B35a
B33a
B35b
B33
GPL_A[0:5],
GPL_B[0:5]
Figure 20. External Bus Timing (UPM-Controlled Signals)
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
33
Bus Signal Timing
Figure 21 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM.
CLKOUT
B37
UPWAIT
B38
CSx
BS_A[0:3],
BS_B[0:3]
GPL_A[0:5],
GPL_B[0:5]
Figure 21. Asynchronous UPWAIT Asserted Detection in UPM-Handled Cycles Timing
Figure 22 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM.
CLKOUT
B37
UPWAIT
B38
CSx
BS_A[0:3],
BS_B[0:3]
GPL_A[0:5],
GPL_B[0:5]
Figure 22. Asynchronous UPWAIT Negated Detection in UPM-Handled Cycles Timing
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
34
Freescale Semiconductor
Bus Signal Timing
Figure 23 provides the timing for the synchronous external master access controlled by the GPCM.
CLKOUT
B41
B42
TS
B40
A[0:31],
TSIZ[0:1],
R/W, BURST
B22
CSx
Figure 23. Synchronous External Master Access Timing (GPCM Handled—ACS = 00)
Figure 24 provides the timing for the asynchronous external master memory access controlled by the
GPCM.
CLKOUT
B39
AS
B40
A[0:31],
TSIZ[0:1],
R/W
B22
CSx
Figure 24. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00)
Figure 25 provides the timing for the asynchronous external master control signals negation.
AS
B43
CSx, WE[0:3],
OE, GPLx,
BS[0:3]
Figure 25. Asynchronous External Master—Control Signals Negation Timing
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
35
Bus Signal Timing
Table 10 provides the interrupt timing for the MPC885/MPC880.
Table 10. Interrupt Timing
All Frequencies
Characteristic1
Num
Unit
Min
1
Max
I39
IRQx valid to CLKOUT rising edge (setup time)
6.00
ns
I40
IRQx hold time after CLKOUT
2.00
ns
I41
IRQx pulse width low
3.00
ns
I42
IRQx pulse width high
3.00
ns
I43
IRQx edge-to-edge time
4 × TCLOCKOUT
—
The I39 and I40 timings describe the testing conditions under which the IRQ lines are tested when being defined as level
sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference to the CLKOUT.
The I41, I42, and I43 timings are specified to allow correct functioning of the IRQ lines detection circuitry and have no direct
relation with the total system interrupt latency that the MPC885/MPC880 is able to support.
Figure 26 provides the interrupt detection timing for the external level-sensitive lines.
CLKOUT
I39
I40
IRQx
Figure 26. Interrupt Detection Timing for External Level Sensitive Lines
Figure 27 provides the interrupt detection timing for the external edge-sensitive lines.
CLKOUT
I41
I42
IRQx
I43
I43
Figure 27. Interrupt Detection Timing for External Edge Sensitive Lines
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
36
Freescale Semiconductor
Bus Signal Timing
Table 11 shows the PCMCIA timing for the MPC885/MPC880.
Table 11. PCMCIA Timing
33 MHz
Num
1
40 MHz
66 MHz
80 MHz
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
P44
A(0:31), REG valid to PCMCIA strobe
asserted1 (MIN = 0.75 × B1 – 2.00)
20.70
—
16.70
—
9.40
—
7.40
—
ns
P45
A(0:31), REG valid to ALE negation1
(MIN = 1.00 × B1 – 2.00)
28.30
—
23.00
—
13.20
—
10.50
—
ns
P46
CLKOUT to REG valid
(MAX = 0.25 × B1 + 8.00)
7.60
15.60
6.30
14.30
3.80
11.80
3.13
11.13
ns
P47
CLKOUT to REG invalid
(MIN = 0.25 – B1 + 1.00)
8.60
—
7.30
—
4.80
—
4.13
—
ns
P48
CLKOUT to CE1, CE2 asserted
(MAX = 0.25 × B1 + 8.00)
7.60
15.60
6.30
14.30
3.80
11.80
3.13
11.13
ns
P49
CLKOUT to CE1, CE2 negated
(MAX = 0.25 × B1 + 8.00)
7.60
15.60
6.30
14.30
3.80
11.80
3.13
11.13
ns
P50
CLKOUT to PCOE, IORD, PCWE, IOWR
assert time (MAX = 0.00 × B1 + 11.00)
—
11.00
—
11.00
—
11.00
—
11.00
ns
P51
CLKOUT to PCOE, IORD, PCWE, IOWR
negate time (MAX = 0.00 × B1 + 11.00)
2.00
11.00
2.00
11.00
2.00
11.00
2.00
11.00
ns
P52
CLKOUT to ALE assert time
(MAX = 0.25 × B1 + 6.30)
7.60
13.80
6.30
12.50
3.80
10.00
3.13
9.40
ns
P53
CLKOUT to ALE negate time
(MAX = 0.25 × B1 + 8.00)
—
15.60
—
14.30
—
11.80
—
11.13
ns
P54
PCWE, IOWR negated to D(0:31) invalid 1
(MIN = 0.25 × B1 – 2.00)
5.60
—
4.30
—
1.80
—
1.13
—
ns
P55
WAITA and WAITB valid to CLKOUT rising
edge1 (MIN = 0.00 × B1 + 8.00)
8.00
—
8.00
—
8.00
—
8.00
—
ns
P56
CLKOUT rising edge to WAITA and WAITB
invalid1 (MIN = 0.00 × B1 + 2.00)
2.00
—
2.00
—
2.00
—
2.00
—
ns
PSST = 1. Otherwise add PSST times cycle time.
PSHT = 0. Otherwise add PSHT times cycle time.
These synchronous timings define when the WAITx signals are detected in order to freeze (or relieve) the PCMCIA current
cycle. The WAITx assertion will be effective only if it is detected 2 cycles before the PSL timer expiration. See Chapter 16,
“PCMCIA Interface,” in the MPC885 PowerQUICC™ Family Reference Manual.
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
37
Bus Signal Timing
Figure 28 provides the PCMCIA access cycle timing for the external bus read.
CLKOUT
TS
P44
A[0:31]
P46
P45
P47
REG
P48
P49
CE1/CE2
P50
P51
P53
P52
PCOE, IORD
P52
ALE
B18
B19
D[0:31]
Figure 28. PCMCIA Access Cycles Timing External Bus Read
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
38
Freescale Semiconductor
Bus Signal Timing
Figure 29 provides the PCMCIA access cycle timing for the external bus write.
CLKOUT
TS
P44
A[0:31]
P46
P45
P47
REG
P48
P49
CE1/CE2
P50
P51
P53
P52
B8
B9
P54
PCWE, IOWR
P52
ALE
D[0:31]
Figure 29. PCMCIA Access Cycles Timing External Bus Write
Figure 30 provides the PCMCIA WAIT signals detection timing.
CLKOUT
P55
P56
WAITx
Figure 30. PCMCIA WAIT Signals Detection Timing
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
39
Bus Signal Timing
Table 12 shows the PCMCIA port timing for the MPC885/MPC880.
Table 12. PCMCIA Port Timing
33 MHz
Num
40 MHz
66 MHz
80 MHz
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
—
19.00
—
19.00
—
19.00
—
19.00
ns
P57
CLKOUT to OPx valid
(MAX = 0.00 × B1 + 19.00)
P58
HRESET negated to OPx drive1
(MIN = 0.75 × B1 + 3.00)
25.70
—
21.70
—
14.40
—
12.40
—
ns
P59
IP_Xx valid to CLKOUT rising edge
(MIN = 0.00 × B1 + 5.00)
5.00
—
5.00
—
5.00
—
5.00
—
ns
P60
CLKOUT rising edge to IP_Xx invalid
(MIN = 0.00 × B1 + 1.00)
1.00
—
1.00
—
1.00
—
1.00
—
ns
1
OP2 and OP3 only.
Figure 31 provides the PCMCIA output port timing for the MPC885/MPC880.
CLKOUT
P57
Output
Signals
HRESET
P58
OP2, OP3
Figure 31. PCMCIA Output Port Timing
Figure 32 provides the PCMCIA input port timing for the MPC885/MPC880.
CLKOUT
P59
P60
Input
Signals
Figure 32. PCMCIA Input Port Timing
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
40
Freescale Semiconductor
Bus Signal Timing
Table 13 shows the debug port timing for the MPC885/MPC880.
Table 13. Debug Port Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
3 × TCLOCKOUT
—
—
D61
DSCK cycle time
D62
DSCK clock pulse width
1.25 × TCLOCKOUT
—
—
D63
DSCK rise and fall times
0.00
3.00
ns
D64
DSDI input data setup time
8.00
—
ns
D65
DSDI data hold time
5.00
—
ns
D66
DSCK low to DSDO data valid
0.00
15.00
ns
D67
DSCK low to DSDO invalid
0.00
2.00
ns
Figure 33 provides the input timing for the debug port clock.
DSCK
D61
D62
D61
D62
D63
D63
Figure 33. Debug Port Clock Input Timing
Figure 34 provides the timing for the debug port.
DSCK
D64
D65
DSDI
D66
D67
DSDO
Figure 34. Debug Port Timings
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
41
Bus Signal Timing
Table 14 shows the reset timing for the MPC885/MPC880.
Table 14. Reset Timing
33 MHz
Num
40 MHz
66 MHz
80 MHz
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
R69
CLKOUT to HRESET high impedance
(MAX = 0.00 × B1 + 20.00)
—
20.00
—
20.00
—
20.00
—
20.00
ns
R70
CLKOUT to SRESET high impedance
(MAX = 0.00 × B1 + 20.00)
—
20.00
—
20.00
—
20.00
—
20.00
ns
R71
RSTCONF pulse width
(MIN = 17.00 × B1)
515.20
—
425.00
—
257.60
—
212.50
—
ns
—
—
—
—
—
—
—
—
—
R72
—
R73
Configuration data to HRESET rising
edge setup time
(MIN = 15.00 × B1 + 50.00)
504.50
—
425.00
—
277.30
—
237.50
—
ns
R74
Configuration data to RSTCONF rising
edge setup time
(MIN = 0.00 × B1 + 350.00)
350.00
—
350.00
—
350.00
—
350.00
—
ns
R75
Configuration data hold time after
RSTCONF negation
(MIN = 0.00 × B1 + 0.00)
0.00
—
0.00
—
0.00
—
0.00
—
ns
R76
Configuration data hold time after
HRESET negation
(MIN = 0.00 × B1 + 0.00)
0.00
—
0.00
—
0.00
—
0.00
—
ns
R77
HRESET and RSTCONF asserted to
data out drive
(MAX = 0.00 × B1 + 25.00)
—
25.00
—
25.00
—
25.00
—
25.00
ns
R78
RSTCONF negated to data out high
impedance (MAX = 0.00 × B1 + 25.00)
—
25.00
—
25.00
—
25.00
—
25.00
ns
R79
CLKOUT of last rising edge before chip
three-states HRESET to data out high
impedance (MAX = 0.00 × B1 + 25.00)
—
25.00
—
25.00
—
25.00
—
25.00
ns
R80
DSDI, DSCK setup (MIN = 3.00 × B1)
90.90
—
75.00
—
45.50
—
37.50
—
ns
R81
DSDI, DSCK hold time
(MIN = 0.00 × B1 + 0.00)
0.00
—
0.00
—
0.00
—
0.00
—
ns
R82
SRESET negated to CLKOUT rising
edge for DSDI and DSCK sample
(MIN = 8.00 × B1)
242.40
—
200.00
—
121.20
—
100.00
—
ns
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
42
Freescale Semiconductor
Bus Signal Timing
Figure 35 shows the reset timing for the data bus configuration.
HRESET
R71
R76
RSTCONF
R73
R74
R75
D[0:31] (IN)
Figure 35. Reset Timing—Configuration from Data Bus
Figure 36 provides the reset timing for the data bus weak drive during configuration.
CLKOUT
R69
HRESET
R79
RSTCONF
R77
R78
D[0:31] (OUT)
(Weak)
Figure 36. Reset Timing—Data Bus Weak Drive During Configuration
Figure 37 provides the reset timing for the debug port configuration.
CLKOUT
R70
R82
SRESET
R80
R80
R81
R81
DSCK, DSDI
Figure 37. Reset Timing—Debug Port Configuration
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
43
IEEE 1149.1 Electrical Specifications
11 IEEE 1149.1 Electrical Specifications
Table 15 provides the JTAG timings for the MPC885/MPC880 shown in Figure 38 through Figure 41.
Table 15. JTAG Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
J82
TCK cycle time
100.00
—
ns
J83
TCK clock pulse width measured at 1.5 V
40.00
—
ns
J84
TCK rise and fall times
0.00
10.00
ns
J85
TMS, TDI data setup time
5.00
—
ns
J86
TMS, TDI data hold time
25.00
—
ns
J87
TCK low to TDO data valid
—
27.00
ns
J88
TCK low to TDO data invalid
0.00
—
ns
J89
TCK low to TDO high impedance
—
20.00
ns
J90
TRST assert time
100.00
—
ns
J91
TRST setup time to TCK low
40.00
—
ns
J92
TCK falling edge to output valid
—
50.00
ns
J93
TCK falling edge to output valid out of high impedance
—
50.00
ns
J94
TCK falling edge to output high impedance
—
50.00
ns
J95
Boundary scan input valid to TCK rising edge
50.00
—
ns
J96
TCK rising edge to boundary scan input invalid
50.00
—
ns
TCK
J82
J83
J82
J83
J84
J84
Figure 38. JTAG Test Clock Input Timing
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
44
Freescale Semiconductor
IEEE 1149.1 Electrical Specifications
TCK
J85
J86
TMS, TDI
J87
J88
J89
TDO
Figure 39. JTAG Test Access Port Timing Diagram
TCK
J91
J90
TRST
Figure 40. JTAG TRST Timing Diagram
TCK
J92
J94
Output
Signals
J93
Output
Signals
J95
J96
Output
Signals
Figure 41. Boundary Scan (JTAG) Timing Diagram
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
45
CPM Electrical Characteristics
12 CPM Electrical Characteristics
This section provides the AC and DC electrical specifications for the communications processor module
(CPM) of the MPC885/MPC880.
12.1
PIP/PIO AC Electrical Specifications
Table 16 provides the PIP/PIO AC timings as shown in Figure 42 through Figure 46.
Table 16. PIP/PIO Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
21
Data-in setup time to STBI low
0
—
ns
22
Data-In hold time to STBI high
0
—
clk
23
STBI pulse width
1.5
—
clk
24
STBO pulse width
1 clk – 5 ns
—
ns
25
Data-out setup time to STBO low
2
—
clk
26
Data-out hold time from STBO high
5
—
clk
27
STBI low to STBO low (Rx interlock)
—
4.5
clk
28
STBI low to STBO high (Tx interlock)
2
—
clk
29
Data-in setup time to clock high
15
—
ns
30
Data-in hold time from clock high
7.5
—
ns
31
Clock low to data-out valid (CPU writes data, control, or direction)
—
25
ns
DATA-IN
21
22
23
STBI
27
24
STBO
Figure 42. PIP Rx (Interlock Mode) Timing Diagram
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
46
Freescale Semiconductor
CPM Electrical Characteristics
DATA-OUT
25
26
24
STBO
(Output)
28
23
STBI
(Input)
Figure 43. PIP Tx (Interlock Mode) Timing Diagram
DATA-IN
21
22
23
STBI
(Input)
24
STBO
(Output)
Figure 44. PIP Rx (Pulse Mode) Timing Diagram
DATA-OUT
25
26
24
STBO
(Output)
23
STBI
(Input)
Figure 45. PIP TX (Pulse Mode) Timing Diagram
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
47
CPM Electrical Characteristics
CLKO
29
30
DATA-IN
31
DATA-OUT
Figure 46. Parallel I/O Data-In/Data-Out Timing Diagram
12.2
Port C Interrupt AC Electrical Specifications
Table 17 provides the timings for port C interrupts.
Table 17. Port C Interrupt Timing
33.34 MHz
Num
Characteristic
Unit
Min
Max
35
Port C interrupt pulse width low (edge-triggered mode)
55
—
ns
36
Port C interrupt minimum time between active edges
55
—
ns
Figure 47 shows the port C interrupt detection timing.
36
Port C
(Input)
35
Figure 47. Port C Interrupt Detection Timing
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
48
Freescale Semiconductor
CPM Electrical Characteristics
12.3
IDMA Controller AC Electrical Specifications
Table 18 provides the IDMA controller timings as shown in Figure 48 tthrough Figure 51.
Table 18. IDMA Controller Timing
All Frequencies
Num
1
Characteristic
Unit
Min
Max
7
—
ns
TBD
—
ns
40
DREQ setup time to clock high
41
DREQ hold time from clock high 1
42
SDACK assertion delay from clock high
—
12
ns
43
SDACK negation delay from clock low
—
12
ns
44
SDACK negation delay from TA low
—
20
ns
45
SDACK negation delay from clock high
—
15
ns
46
TA assertion to rising edge of the clock setup time (applies to external TA)
7
—
ns
Applies to high-to-low mode (EDM = 1).
CLKO
(Output)
41
40
DREQ
(Input)
Figure 48. IDMA External Requests Timing Diagram
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
49
CPM Electrical Characteristics
CLKO
(Output)
TS
(Output)
R/W
(Output)
42
43
DATA
46
TA
(Input)
SDACK
Figure 49. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA
CLKO
(Output)
TS
(Output)
R/W
(Output)
42
44
DATA
TA
(Output)
SDACK
Figure 50. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
50
Freescale Semiconductor
CPM Electrical Characteristics
CLKO
(Output)
TS
(Output)
R/W
(Output)
42
45
DATA
TA
(Output)
SDACK
Figure 51. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA
12.4
Baud Rate Generator AC Electrical Specifications
Table 19 provides the baud rate generator timings as shown in Figure 52.
Table 19. Baud Rate Generator Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
50
BRGO rise and fall time
—
10
ns
51
BRGO duty cycle
40
60
%
52
BRGO cycle
40
—
ns
50
50
BRGOX
51
51
52
Figure 52. Baud Rate Generator Timing Diagram
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
51
CPM Electrical Characteristics
12.5
Timer AC Electrical Specifications
Table 20 provides the general-purpose timer timings as shown in Figure 53.
Table 20. Timer Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
61
TIN/TGATE rise and fall time
10
—
ns
62
TIN/TGATE low time
1
—
clk
63
TIN/TGATE high time
2
—
clk
64
TIN/TGATE cycle time
3
—
clk
65
CLKO low to TOUT valid
3
25
ns
CLKO
60
61
63
62
TIN/TGATE
(Input)
61
64
65
TOUT
(Output)
Figure 53. CPM General-Purpose Timers Timing Diagram
12.6
Serial Interface AC Electrical Specifications
Table 21 provides the serial interface timings as shown in Figure 54 through Figure 58.
Table 21. SI Timing
All Frequencies
Num
Characteristic
70
L1RCLK, L1TCLK frequency (DSC = 0)1, 2
71
L1RCLK, L1TCLK width low (DSC = 0)2
0)3
Unit
Min
Max
—
SYNCCLK/2.5
MHz
P + 10
—
ns
P + 10
—
ns
—
15.00
ns
71a
L1RCLK, L1TCLK width high (DSC =
72
L1TXD, L1ST(1–4), L1RQ, L1CLKO rise/fall time
73
L1RSYNC, L1TSYNC valid to L1CLK edge (SYNC setup time)
20.00
—
ns
74
L1CLK edge to L1RSYNC, L1TSYNC, invalid (SYNC hold time)
35.00
—
ns
75
L1RSYNC, L1TSYNC rise/fall time
—
15.00
ns
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
52
Freescale Semiconductor
CPM Electrical Characteristics
Table 21. SI Timing (continued)
All Frequencies
Num
Characteristic
Unit
Min
Max
76
L1RXD valid to L1CLK edge (L1RXD setup time)
17.00
—
ns
77
L1CLK edge to L1RXD invalid (L1RXD hold time)
13.00
—
ns
78
L1CLK edge to L1ST(1–4) valid4
10.00
45.00
ns
78A
L1SYNC valid to L1ST(1–4) valid
10.00
45.00
ns
79
L1CLK edge to L1ST(1–4) invalid
10.00
45.00
ns
80
L1CLK edge to L1TXD valid
10.00
55.00
ns
L1TSYNC valid to L1TXD valid4
10.00
55.00
ns
81
L1CLK edge to L1TXD high impedance
0.00
42.00
ns
82
L1RCLK, L1TCLK frequency (DSC =1)
—
16.00 or
SYNCCLK/2
MHz
83
L1RCLK, L1TCLK width low (DSC =1)
P + 10
—
ns
83a
L1RCLK, L1TCLK width high (DSC = 1)3
P + 10
—
ns
84
L1CLK edge to L1CLKO valid (DSC = 1)
—
30.00
ns
85
L1RQ valid before falling edge of L1TSYNC 4
1.00
—
L1TCLK
42.00
—
ns
42.00
—
ns
—
0.00
ns
80A
time2
86
L1GR setup
87
L1GR hold time
88
L1CLK edge to L1SYNC valid (FSD = 00) CNT = 0000, BYT = 0,
DSC = 0)
1
The ratio SyncCLK/L1RCLK must be greater than 2.5/1.
These specs are valid for IDL mode only.
3 Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate, P = 40 ns.
4 These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever comes later.
2
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
53
CPM Electrical Characteristics
L1RCLK
(FE = 0, CE = 0)
(Input)
71
70
71a
72
L1RCLK
(FE = 1, CE = 1)
(Input)
RFSD=1
75
L1RSYNC
(Input)
73
74
L1RXD
(Input)
77
BIT0
76
78
79
L1ST(4-1)
(Output)
Figure 54. SI Receive Timing Diagram with Normal Clocking (DSC = 0)
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
54
Freescale Semiconductor
CPM Electrical Characteristics
L1RCLK
(FE = 1, CE = 1)
(Input)
72
83a
82
L1RCLK
(FE = 0, CE = 0)
(Input)
RFSD=1
75
L1RSYNC
(Input)
73
74
L1RXD
(Input)
77
BIT0
76
78
79
L1ST(4-1)
(Output)
84
L1CLKO
(Output)
Figure 55. SI Receive Timing with Double-Speed Clocking (DSC = 1)
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
55
CPM Electrical Characteristics
L1TCLK
(FE = 0, CE = 0)
(Input)
71
70
72
L1TCLK
(FE = 1, CE = 1)
(Input)
73
TFSD=0
75
L1TSYNC
(Input)
74
80a
L1TXD
(Output)
81
BIT0
80
78
79
L1ST(4-1)
(Output)
Figure 56. SI Transmit Timing Diagram (DSC = 0)
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
56
Freescale Semiconductor
CPM Electrical Characteristics
L1RCLK
(FE = 0, CE = 0)
(Input)
72
83a
82
L1RCLK
(FE = 1, CE = 1)
(Input)
TFSD=0
75
L1RSYNC
(Input)
73
74
L1TXD
(Output)
81
BIT0
80
78a
79
L1ST(4-1)
(Output)
78
84
L1CLKO
(Output)
Figure 57. SI Transmit Timing with Double Speed Clocking (DSC = 1)
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
57
58
L1GR
(Input)
L1RQ
(Output)
L1ST(4-1)
(Output)
L1RXD
(Input)
L1TXD
(Output)
L1RSYNC
(Input)
L1RCLK
(Input)
80
77
74
2
3
5
72
B15 B14 B13
71
71
4
86
85
76
6
87
B17 B16 B15 B14 B13
B17 B16
73
1
8
78
B12 B11 B10
B12 B11 B10
7
9
D1
D1
10
A
A
11
14
15
16
17
18
B25 B24 B23 B22 B21 B20
13
B27 B26 B25 B24 B23 B22 B21 B20
81
B27 B26
12
19
D2
D2
20
M
M
CPM Electrical Characteristics
Figure 58. IDL Timing
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
CPM Electrical Characteristics
12.7
SCC in NMSI Mode Electrical Specifications
Table 22 provides the NMSI external clock timing.
Table 22. NMSI External Clock Timing
All Frequencies
Num
1
2
Characteristic
Unit
Min
Max
1/SYNCCLK
—
ns
1/SYNCCLK + 5
—
ns
—
15.00
ns
100
RCLK1 and TCLK1 width high1
101
RCLK1 and TCLK1 width low
102
RCLK1 and TCLK1 rise/fall time
103
TXD1 active delay (from TCLK1 falling edge)
0.00
50.00
ns
104
RTS1 active/inactive delay (from TCLK1 falling edge)
0.00
50.00
ns
105
CTS1 setup time to TCLK1 rising edge
5.00
—
ns
106
RXD1 setup time to RCLK1 rising edge
5.00
—
ns
107
RXD1 hold time from RCLK1 rising edge2
5.00
—
ns
108
CD1 setup time to RCLK1 rising edge
5.00
—
ns
The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 2.25/1.
Also applies to CD and CTS hold time when they are used as external sync signals.
Table 23 provides the NMSI internal clock timing.
Table 23. NMSI Internal Clock Timing
All Frequencies
Num
1
2
Characteristic
Unit
Min
Max
100
RCLK1 and TCLK1 frequency1
0.00
SYNCCLK/3
MHz
102
RCLK1 and TCLK1 rise/fall time
—
—
ns
103
TXD1 active delay (from TCLK1 falling edge)
0.00
30.00
ns
104
RTS1 active/inactive delay (from TCLK1 falling edge)
0.00
30.00
ns
105
CTS1 setup time to TCLK1 rising edge
40.00
—
ns
106
RXD1 setup time to RCLK1 rising edge
40.00
—
ns
107
RXD1 hold time from RCLK1 rising edge2
0.00
—
ns
108
CD1 setup time to RCLK1 rising edge
40.00
—
ns
The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 3/1.
Also applies to CD and CTS hold time when they are used as external sync signals
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
59
CPM Electrical Characteristics
Figure 59 through Figure 61 show the NMSI timings.
RCLK1
102
102
101
106
100
RxD1
(Input)
107
108
CD1
(Input)
107
CD1
(SYNC Input)
Figure 59. SCC NMSI Receive Timing Diagram
TCLK1
102
102
101
100
TxD1
(Output)
103
105
RTS1
(Output)
104
104
CTS1
(Input)
107
CTS1
(SYNC Input)
Figure 60. SCC NMSI Transmit Timing Diagram
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
60
Freescale Semiconductor
CPM Electrical Characteristics
TCLK1
102
102
101
100
TxD1
(Output)
103
RTS1
(Output)
104
107
104
105
CTS1
(Echo Input)
Figure 61. HDLC Bus Timing Diagram
12.8
Ethernet Electrical Specifications
Table 24 provides the Ethernet timings as shown in Figure 62 through Figure 64.
Table 24. Ethernet Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
120
CLSN width high
40
—
ns
121
RCLK1 rise/fall time
—
15
ns
122
RCLK1 width low
40
—
ns
123
RCLK1 clock period1
80
120
ns
124
RXD1 setup time
20
—
ns
125
RXD1 hold time
5
—
ns
126
RENA active delay (from RCLK1 rising edge of the last data bit)
10
—
ns
127
RENA width low
100
—
ns
128
TCLK1 rise/fall time
—
15
ns
129
TCLK1 width low
40
—
ns
99
101
ns
period1
130
TCLK1 clock
131
TXD1 active delay (from TCLK1 rising edge)
—
50
ns
132
TXD1 inactive delay (from TCLK1 rising edge)
6.5
50
ns
133
TENA active delay (from TCLK1 rising edge)
10
50
ns
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
61
CPM Electrical Characteristics
Table 24. Ethernet Timing (continued)
All Frequencies
Num
134
1
2
Characteristic
Unit
TENA inactive delay (from TCLK1 rising edge)
Min
Max
10
50
ns
138
CLKO1 low to SDACK asserted
2
—
20
ns
139
CLKO1 low to SDACK negated 2
—
20
ns
The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 2/1.
SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
CLSN(CTS1)
(Input)
120
Figure 62. Ethernet Collision Timing Diagram
RCLK1
121
121
124
123
RxD1
(Input)
Last Bit
125
126
127
RENA(CD1)
(Input)
Figure 63. Ethernet Receive Timing Diagram
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
62
Freescale Semiconductor
CPM Electrical Characteristics
TCLK1
128
128
131
129
121
TxD1
(Output)
132
133
134
TENA(RTS1)
(Input)
RENA(CD1)
(Input)
(Note 2)
Notes:
1. Transmit clock invert (TCI) bit in GSMR is set.
2. If RENA is negated before TENA or RENA is not asserted at all during transmit, then the
CSL bit is set in the buffer descriptor at the end of the frame transmission.
Figure 64. Ethernet Transmit Timing Diagram
12.9
SMC Transparent AC Electrical Specifications
Table 25 provides the SMC transparent timings as shown in Figure 65.
Table 25. SMC Transparent Timing
All Frequencies
Num
1
Characteristic
Unit
Min
Max
150
SMCLK clock period1
100
—
ns
151
SMCLK width low
50
—
ns
151A
SMCLK width high
50
—
ns
152
SMCLK rise/fall time
—
15
ns
153
SMTXD active delay (from SMCLK falling edge)
10
50
ns
154
SMRXD/SMSYNC setup time
20
—
ns
155
RXD1/SMSYNC hold time
5
—
ns
SyncCLK must be at least twice as fast as SMCLK.
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
63
CPM Electrical Characteristics
SMCLK
152
152
151
151A
150
SMTXD
(Output)
Note 1
154
153
155
SMSYNC
154
155
SMRXD
(Input)
Note:
1. This delay is equal to an integer number of character-length clocks.
Figure 65. SMC Transparent Timing Diagram
12.10 SPI Master AC Electrical Specifications
Table 26 provides the SPI master timings as shown in Figure 66 and Figure 67.
Table 26. SPI Master Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
160
MASTER cycle time
4
1024
tcyc
161
MASTER clock (SCK) high or low time
2
512
tcyc
162
MASTER data setup time (inputs)
15
—
ns
163
Master data hold time (inputs)
0
—
ns
164
Master data valid (after SCK edge)
—
10
ns
165
Master data hold time (outputs)
0
—
ns
166
Rise time output
—
15
ns
167
Fall time output
—
15
ns
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
64
Freescale Semiconductor
CPM Electrical Characteristics
SPICLK
(CI = 0)
(Output)
161
167
166
161
160
SPICLK
(CI = 1)
(Output)
163
167
162
SPIMISO
(Input)
msb
166
Data
lsb
165
msb
164
167
SPIMOSI
(Output)
166
msb
Data
lsb
msb
Figure 66. SPI Master (CP = 0) Timing Diagram
SPICLK
(CI = 0)
(Output)
161
167
166
161
160
SPICLK
(CI = 1)
(Output)
163
167
162
SPIMISO
(Input)
166
msb
Data
165
lsb
msb
164
167
SPIMOSI
(Output)
msb
166
Data
lsb
msb
Figure 67. SPI Master (CP = 1) Timing Diagram
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
65
CPM Electrical Characteristics
12.11 SPI Slave AC Electrical Specifications
Table 27 provides the SPI slave timings as shown in Figure 68 and Figure 69.
Table 27. SPI Slave Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
170
Slave cycle time
2
—
tcyc
171
Slave enable lead time
15
—
ns
172
Slave enable lag time
15
—
ns
173
Slave clock (SPICLK) high or low time
1
—
tcyc
174
Slave sequential transfer delay (does not require deselect)
1
—
tcyc
175
Slave data setup time (inputs)
20
—
ns
176
Slave data hold time (inputs)
20
—
ns
177
Slave access time
—
50
ns
SPISEL
(Input)
172
171
174
SPICLK
(CI = 0)
(Input)
173
182
173
181
170
SPICLK
(CI = 1)
(Input)
177
181
182
180
SPIMISO
(Output)
msb
178
Data
175
msb
Undef
msb
179
176
SPIMOSI
(Input)
lsb
181 182
Data
lsb
msb
Figure 68. SPI Slave (CP = 0) Timing Diagram
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
66
Freescale Semiconductor
CPM Electrical Characteristics
SPISEL
(Input)
172
171
174
170
SPICLK
(CI = 0)
(Input)
173
182
181
173
181
SPICLK
(CI =1)
(Input)
177
182
180
SPIMISO
(Output)
msb
Undef
175
Data
178
msb
lsb
179
176
SPIMOSI
(Input)
msb
181 182
Data
msb
lsb
Figure 69. SPI Slave (CP = 1) Timing Diagram
12.12 I2C AC Electrical Specifications
Table 28 provides the I2C (SCL < 100 kHz) timings.
Table 28. I2C Timing (SCL < 100 kHZ)
All Frequencies
Num
200
Characteristic
SCL clock frequency (slave)
(master)1
Unit
Min
Max
0
100
kHz
1.5
100
kHz
200
SCL clock frequency
202
Bus free time between transmissions
4.7
—
μs
203
Low period of SCL
4.7
—
μs
204
High period of SCL
4.0
—
μs
205
Start condition setup time
4.7
—
μs
206
Start condition hold time
4.0
—
μs
207
Data hold time
0
—
μs
208
Data setup time
250
—
ns
209
SDL/SCL rise time
—
1
μs
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
67
CPM Electrical Characteristics
Table 28. I2C Timing (SCL < 100 kHZ) (continued)
All Frequencies
Num
1
Characteristic
Unit
Min
Max
210
SDL/SCL fall time
—
300
ns
211
Stop condition setup time
4.7
—
μs
SCL frequency is given by SCL = BRGCLK_frequency/((BRG register + 3) × pre_scaler × 2).
The ratio SyncClk/(BRGCLK/pre_scaler) must be greater or equal to 4/1.
Table 29 provides the I2C (SCL > 100 kHz) timings.
Table 29. I2C Timing (SCL > 100 kHZ)
All Frequencies
Num
1
Characteristic
Expression
Unit
Min
Max
200
SCL clock frequency (slave)
fSCL
0
BRGCLK/48
Hz
200
SCL clock frequency (master)1
fSCL
BRGCLK/16512
BRGCLK/48
Hz
202
Bus free time between transmissions
—
1/(2.2 × fSCL)
—
s
203
Low period of SCL
—
1/(2.2 × fSCL)
—
s
204
High period of SCL
—
1/(2.2 × fSCL)
—
s
205
Start condition setup time
—
1/(2.2 × fSCL)
—
s
206
Start condition hold time
—
1/(2.2 × fSCL)
—
s
207
Data hold time
—
0
—
s
208
Data setup time
—
1/(40 × fSCL)
—
s
209
SDL/SCL rise time
—
—
1/(10 × fSCL)
s
210
SDL/SCL fall time
—
—
1/(33 × fSCL)
s
211
Stop condition setup time
—
1/2(2.2 × fSCL)
—
s
SCL frequency is given by SCL = BrgClk_frequency/((BRG register + 3) × pre_scaler × 2).
The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1.
Figure 70 shows the I2C bus timing.
SDA
202
203
205
204
208
207
SCL
206
209
210
211
Figure 70. I2C Bus Timing Diagram
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
68
Freescale Semiconductor
UTOPIA AC Electrical Specifications
13 UTOPIA AC Electrical Specifications
Table 30, Table 31, and Table 32, show the AC electrical specifications for the UTOPIA interface.
Table 30. UTOPIA Master (Muxed Mode) Electrical Specifications
Num
U1
Signal Characteristic
UtpClk rise/fall time (internal clock option)
Direction
Min
Output
Duty cycle
50
Frequency
U2
UTPB, SOC, RxEnb, TxEnb, RxAddr, and TxAddr active delay (PHREQ
and PHSEL active delay in multi-PHY mode)
U3
U4
Max
Unit
4
ns
50
%
33
MHz
16
ns
Output
2
UTPB, SOC, Rxclav, and Txclav setup time
Input
4
ns
UTPB, SOC, Rxclav, and Txclav hold time
Input
1
ns
Table 31. UTOPIA Master (Split Bus Mode) Electrical Specifications
Num
U1
Signal Characteristic
UtpClk rise/fall time (Internal clock option)
Direction
Min
Output
Duty cycle
50
Frequency
U2
UTPB, SOC, RxEnb, TxEnb, RxAddr, and TxAddr active delay (PHREQ
and PHSEL active delay in multi-PHY mode)
U3
U4
Max
Unit
4
ns
50
%
33
MHz
16
ns
Output
2
UTPB_Aux, SOC_Aux, Rxclav, and Txclav setup time
Input
4
ns
UTPB_Aux, SOC_Aux, Rxclav, and Txclav hold time
Input
1
ns
Table 32. UTOPIA Slave (Split Bus Mode) Electrical Specifications
Num
U1
Signal Characteristic
UtpClk rise/fall time (external clock option)
Direction
Min
Input
Duty cycle
40
Frequency
U2
UTPB, SOC, Rxclav, and Txclav active delay
U3
U4
Max
Unit
4
ns
60
%
33
MHz
16
ns
Output
2
UTPB_AUX, SOC_Aux, RxEnb, TxEnb, RxAddr, and TxAddr setup time
Input
4
ns
UTPB_AUX, SOC_Aux, RxEnb, TxEnb, RxAddr, and TxAddr hold time
Input
1
ns
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
69
UTOPIA AC Electrical Specifications
Figure 71 shows signal timings during UTOPIA receive operations.
U1
U1
UtpClk
U2
PHREQn
U3
3
U4
4
RxClav
High-Z at MPHY
High-Z at MPHY
U2
2
RxEnb
U3
3
UTPB
SOC
U4
Figure 71. UTOPIA Receive Timing
Figure 72 shows signal timings during UTOPIA transmit operations.
U1
U1
1
UtpClk
U2
5
PHSELn
U3
3
U4
4
TxClav
High-Z at MPHY
High-Z at Multi-PHYPHY
U2
2
TxEnb
U2
5
UTPB
SOC
Figure 72. UTOPIA Transmit Timing
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
70
Freescale Semiconductor
USB Electrical Characteristics
14 USB Electrical Characteristics
This section provides the AC timings for the USB interface.
14.1
USB Interface AC Timing Specifications
The USB Port uses the transmit clock on SCC1. Table 33 lists the USB interface timings.
Table 33. USB Interface AC Timing Specifications
All Frequencies
Name
Characteristic
Unit
Min
US1
US4
1
USBCLK frequency of operation1
Low speed
Full speed
Max
6
48
USBCLK duty cycle (measured at 1.5 V)
45
MHz
MHz
55
%
USBCLK accuracy should be ±500 ppm or better. USBCLK may be stopped to conserve power.
15 FEC Electrical Characteristics
This section provides the AC electrical specifications for the fast Ethernet controller (FEC). Note that the
timing specifications for the MII signals are independent of system clock frequency (part speed
designation). Also, MII signals use TTL signal levels compatible with devices operating at either 5.0 or
3.3 V.
15.1
MII and Reduced MII Receive Signal Timing
The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25 MHz + 1%. The
reduced MII (RMII) receiver functions correctly up to a RMII_REFCLK maximum frequency of
50 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency
must exceed the MII_RX_CLK frequency – 1%.
Table 34 provides information on the MII and RMII receive signal timing.
Table 34. MII Receive Signal Timing
Num
Characteristic
Min
Max
Unit
M1
MII_RXD[3:0], MII_RX_DV, MII_RX_ERR to MII_RX_CLK setup
5
—
ns
M2
MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold
5
—
ns
M3
MII_RX_CLK pulse width high
35%
65%
MII_RX_CLK period
M4
MII_RX_CLK pulse width low
35%
65%
MII_RX_CLK period
M1_RMII
RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR to RMII_REFCLK
setup
4
—
ns
M2_RMII
RMII_REFCLK to RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR
hold
2
—
ns
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
71
FEC Electrical Characteristics
Figure 73 shows MII receive signal timing.
M3
MII_RX_CLK (Input)
M4
MII_RXD[3:0] (Inputs)
MII_RX_DV
MII_RX_ER
M1
M2
Figure 73. MII Receive Signal Timing Diagram
15.2
MII and Reduced MII Transmit Signal Timing
The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz + 1%. The
RMII transmitter functions correctly up to a RMII_REFCLK maximum frequency of 50 MHz + 1%.
There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the
MII_TX_CLK frequency – 1%.
Table 35 provides information on the MII and RMII transmit signal timing.
Table 35. MII Transmit Signal Timing
Num
Characteristic
Min
Max
Unit
M5
MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid
5
—
ns
M6
MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid
—
25
ns
M20_RMII
RMII_TXD[1:0], RMII_TX_EN to RMII_REFCLK setup
4
—
ns
M21_RMII
RMII_TXD[1:0], RMII_TX_EN data hold from RMII_REFCLK rising
edge
2
—
ns
M7
MII_TX_CLK and RMII_REFCLK pulse width high
35%
65%
MII_TX_CLK or
RMII_REFCLK
period
M8
MII_TX_CLK and RMII_REFCLK pulse width low
35%
65%
MII_TX_CLK or
RMII_REFCLK
period
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
72
Freescale Semiconductor
FEC Electrical Characteristics
Figure 74 shows the MII transmit signal timing diagram.
M7
MII_TX_CLK (Input)
RMII_REFCLK
M5
M8
MII_TXD[3:0] (Outputs)
MII_TX_EN
MII_TX_ER
M6
Figure 74. MII Transmit Signal Timing Diagram
15.3
MII Async Inputs Signal Timing (MII_CRS, MII_COL)
Table 36 provides information on the MII async inputs signal timing.
Table 36. MII Async Inputs Signal Timing
Num
M9
Characteristic
Min
Max
Unit
MII_CRS, MII_COL minimum pulse width
1.5
—
MII_TX_CLK period
Figure 75 shows the MII asynchronous inputs signal timing diagram.
MII_CRS, MII_COL
M9
Figure 75. MII Async Inputs Timing Diagram
15.4
MII Serial Management Channel Timing (MII_MDIO, MII_MDC)
Table 37 provides information on the MII serial management channel signal timing. The FEC functions
correctly with a maximum MDC frequency in excess of 2.5 MHz.
Table 37. MII Serial Management Channel Timing
Num
Characteristic
Min
Max
Unit
M10
MII_MDC falling edge to MII_MDIO output invalid (minimum propagation
delay)
0
—
ns
M11
MII_MDC falling edge to MII_MDIO output valid (max prop delay)
—
25
ns
M12
MII_MDIO (input) to MII_MDC rising edge setup
10
—
ns
M13
MII_MDIO (input) to MII_MDC rising edge hold
0
—
ns
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
73
FEC Electrical Characteristics
Table 37. MII Serial Management Channel Timing (continued)
Num
Characteristic
Min
Max
Unit
M14
MII_MDC pulse width high
40%
60%
MII_MDC period
M15
MII_MDC pulse width low
40%
60%
MII_MDC period
Figure 76 shows the MII serial management channel timing diagram.
M14
MM15
MII_MDC (Output)
M10
MII_MDIO (Output)
M11
MII_MDIO (Input)
M12
M13
Figure 76. MII Serial Management Channel Timing Diagram
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
74
Freescale Semiconductor
Mechanical Data and Ordering Information
16 Mechanical Data and Ordering Information
Table 38 identifies the available packages and operating frequencies for the MPC885/MPC880 derivative
devices.
Table 38. Available MPC885/MPC880 Packages/Frequencies
Package Type
Plastic ball grid array
ZP suffix — Leaded
VR suffix — Lead-Free are available as needed
Plastic ball grid array
CZP suffix — Leaded
CVR suffix — Lead-Free are available as needed
Temperature (Tj)
Frequency (MHz)
Order Number
0°C to 95°C
66
KMPC885ZP66
KMPC880ZP66
MPC885ZP66
MPC880ZP66
80
KMPC885ZP80
KMPC880ZP80
MPC885ZP80
MPC880ZP80
133
KMPC885ZP133
KMPC880ZP133
MPC885ZP133
MPC880ZP133
66
KMPC885CZP66
KMPC880CZP66
MPC885CZP66
MPC880CZP66
133
KMPC885CZP133
KMPC880CZP133
MPC885CZP133
MPC880CZP133
-40°C to 100°C
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
75
Mechanical Data and Ordering Information
16.1
Pin Assignments
Figure 77 shows the top-view pinout of the PBGA package. For additional information, see the MPC885
PowerQUICC™ Family Reference Manual.
NOTE: This is the top view of the device.
W
TRST
PA10
PB23
PA8
TMS
PB25
PC11
PB22
PB27
PB14
TCK
PB24
PB29
PC12
TDO
TDI
PC15
PC14
PB26
GND
VDDL
MII_MDIO
PB30
PA14
PA12
VDDH
A2
A1
N/C
PA15
A3
A5
A4
A0
A7
A9
A8
A6
A10
A11
A12
A13
A14
A16
A15
A17
A27
A19
A20
A24
A21
A29
A23
TSIZ0
A25
A30
A22
BSA3
A18
A28
TSIZ1
WE1
A26
A31
BSA0
GPL_AB2
CS6
CS3
WR
BI
BR
IRQ6
IPB1
ALEB
AS
BSA2
BSA1
WE2
CS4
CE2_A
CS1
GPL_A5
TA
BG
BURST
IPB3
IPB2
IRQ4
OP1
BADDR28
WAIT_B VSSSYN1
IPA1
WE3
WE0
GPL_A0
CS7
CE1_A
CS0
GPL_A4
TEA
BB
IRQ2
IPB4
IPB7
ALEA
OP0
BADDR29 HRESET PORESETVDDLSYN
IPA0
OE
GPL_AB3
CS5
CS2
GPL_B4
BDIP
TS
IRQ3
IPB5
IPB0
IPB6
18
17
16
15
14
13
12
11
10
9
8
PC8
PA5
PB17
PA13
PC4
PA11
PE17
PE30
PE15
PD6
PD4
PD7
PA3
PB19
PC7
PB16
PC13
PE21
PE24
PE14
PD5
PE28
PE27
PB31
PE23
PE22
PA6
MII1_COL
PC6
PB15
PE31
PD15
PD14
PD13
PD12
PA4
PA0
PD9
PA1
PB20
PB18
MII1_CRS
PC5
PD3
PE29
PE16
PE19 MII1_TXEN
PA2
PE25
PD10
PE26
PE20
PD8
PD11
IRQ7
IRQ1
D0
D12
D13
V
PB28
PA7
U
PC10
PB21
T
PA9
PC9
R
VDDL
VDDL
VDDL
VDDH
PE18
P
VDDH
VDDH
GND
GND
D8
N
VDDL
GND
IRQ0
D4
M
VDDL
VDDH
D17
D23
D27
D1
D9
D10
D11
D2
D3
D15
L
VDDH
GND
GND
VDDL
K
VDDL
GND
VDDH
D5
D14
J
VDDL
D22
D19
D16
D18
D28
D6
D20
D21
CLKOUT
D26
D24
D25
IPA2
D31
D7
D29
VSSSYN
IPA3
IPA6
D30
IPA7
IPA4
IPA5
H
VDDH
GND
G
VDDL
GND
VDDH
GND
VDDH
F
VDDH
VDDL
VDDL
E
VDDL
VDDL
D
MODCK1 EXTAL RSTCONF
C
TEXP
B
A
19
BADDR30 MODCK2 EXTCLK
7
6
XTAL
5
4
SRESET WAIT_A
3
2
1
Figure 77. Pinout of the PBGA Package
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
76
Freescale Semiconductor
Mechanical Data and Ordering Information
Table 39 contains a list of the MPC885 input and output signals and shows multiplexing and pin
assignments.
Table 39. Pin Assignments
Name
Pin Number
Type
A[0:31]
M16, N18, N19, M19, M17, M18, L16, L19, L17, L18, K19, K18, K17, Bidirectional
K16, J19, J17, J18, J16, E19, H18, H17, G19, F17, G17, H16, F19, Three-state
D19, H19, E18, G18, F18, D18
D[0:31]
P2, M1, L1, K2, N1, K4, H3, F2, P1, L4, L3, L2, N3, N2, K3, K1, J2, Bidirectional
M4, J1, J3, H2, H1, J4, M3, G2, G1, G3, M2, H4, F1, E1, F3
Three-state
TSIZ0, REG
G16
Bidirectional
Three-state
TSIZ1
E17
Bidirectional
Three-state
RD/WR
D13
Bidirectional
Three-state
BURST
C10
Bidirectional
Three-state
BDIP, GPL_B5
A13
Output
TS
A12
Bidirectional
Active pull-up
TA
C12
Bidirectional
Active pull-up
TEA
B12
Open-drain
BI
D12
Bidirectional
Active pull-up
IRQ2, RSV
B10
Bidirectional
Three-state
IRQ4, KR, RETRY,
SPKROUT
C7
Bidirectional
Three-state
CR, IRQ3
A11
Input
BR
D11
Bidirectional
BG
C11
Bidirectional
BB
B11
Bidirectional
Active pull-up
FRZ, IRQ6
D10
Bidirectional
IRQ0
N4
Input
IRQ1
P3
Input
IRQ7
P4
Input
CS[0:5]
B14, C14, A15, D14, C16, A16
Output
CS6, CE1_B
D15
Output
CS7, CE2_B
B16
Output
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
77
Mechanical Data and Ordering Information
Table 39. Pin Assignments (continued)
Name
Pin Number
Type
WE0, BS_B0, IORD
B18
Output
WE1, BS_B1, IOWR
E16
Output
WE2, BS_B2, PCOE
C17
Output
WE3, BS_B3, PCWE
B19
Output
BS_A[0:3]
D17, C18, C19, F16
Output
GPL_A0, GPL_B0
B17
Output
OE, GPL_A1, GPL_B1
A18
Output
GPL_A[2:3], GPL_B[2:3],
CS[2:3]
D16, A17
Output
UPWAITA, GPL_A4
B13
Bidirectional
UPWAITB, GPL_B4
A14
Bidirectional
GPL_A5
C13
Output
PORESET
B3
Input
RSTCONF
D4
Input
HRESET
B4
Open-drain
SRESET
A3
Open-drain
XTAL
A4
Analog output
EXTAL
D5
Analog input (3.3 V only)
CLKOUT
G4
Output
EXTCLK
A5
Input (3.3 V only)
TEXP
C4
Output
ALE_A
B7
Output
CE1_A
B15
Output
CE2_A
C15
Output
WAIT_A, SOC_Split1
A2
Input
WAIT_B
C3
Input
UTPB_Split01
B1
Input
IP_A1, UTPB_Split11
C1
Input
IP_A2, IOIS16_A,
UTPB_Split21
F4
Input
IP_A3, UTPB_Split31
E3
Input
IP_A4,
UTPB_Split41
D2
Input
IP_A5,
UTPB_Split51
D1
Input
IP_A6, UTPB_Split61
E2
Input
IP_A7, UTPB_Split71
D3
Input
IP_A0,
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
78
Freescale Semiconductor
Mechanical Data and Ordering Information
Table 39. Pin Assignments (continued)
Name
Pin Number
Type
ALE_B, DSCK/AT1
D8
Bidirectional
Three-state
IP_B[0:1], IWP[0:1],
VFLS[0:1]
A9, D9
Bidirectional
IP_B2, IOIS16_B, AT2
C8
Bidirectional
Three-state
IP_B3, IWP2, VF2
C9
Bidirectional
IP_B4, LWP0, VF0
B9
Bidirectional
IP_B5, LWP1, VF1
A10
Bidirectional
IP_B6, DSDI, AT0
A8
Bidirectional
Three-state
IP_B7, PTR, AT3
B8
Bidirectional
Three-state
OP0, UtpClk_Split1
B6
Bidirectional
OP1
C6
Output
OP2, MODCK1, STS
D6
Bidirectional
OP3, MODCK2, DSDO
A6
Bidirectional
BADDR30, REG
A7
Output
BADDR[28:29]
C5, B5
Output
AS
D7
Input
PA15, USBRXD
N16
Bidirectional
PA14, USBOE
P17
Bidirectional
(Optional: open-drain)
PA13, RXD2
W11
Bidirectional
PA12, TXD2
P16
Bidirectional
(Optional: open-drain)
PA11, RXD4, MII1-TXD0,
RMII1-TXD0
W9
Bidirectional
(Optional: open-drain)
PA10, MII1-TXER, TIN4,
CLK7
W17
Bidirectional
(Optional: open-drain)
PA9, L1TXDA, RXD3
T15
Bidirectional
(Optional: open-drain)
PA8, L1RXDA, TXD3
W15
Bidirectional
(Optional: open-drain)
PA7, CLK1, L1RCLKA,
BRGO1, TIN1
V14
Bidirectional
PA6, CLK2, TOUT1
U13
Bidirectional
PA5, CLK3, L1TCLKA,
BRGO2, TIN2
W13
Bidirectional
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
79
Mechanical Data and Ordering Information
Table 39. Pin Assignments (continued)
Name
Pin Number
Type
PA4, CTS4, MII1-TXD1,
RMII1-TXD1
U4
Bidirectional
PA3, MII1-RXER,
RMII1-RXER, BRGO3
W2
Bidirectional
PA2, MII1-RXDV,
RMII1-CRS_DV, TXD4
T4
Bidirectional
PA1, MII1-RXD0,
RMII1-RXD0, BRGO4
U1
Bidirectional
PA0, MII1-RXD1,
RMII1-RXD1, TOUT4
U3
Bidirectional
PB31, SPISEL,
MII1-TXCLK,
RMII1-REFCLK
V3
Bidirectional
(Optional: open-drain)
PB30, SPICLK
P18
Bidirectional
(Optional: open-drain)
PB29, SPIMOSI
T19
Bidirectional
(Optional: open-drain)
PB28, SPIMISO, BRGO4
V19
Bidirectional
(Optional: open-drain)
PB27, I2CSDA, BRGO1
U19
Bidirectional
(Optional: open-drain)
PB26, I2CSCL, BRGO2
R17
Bidirectional
(Optional: open-drain)
PB25, RXADDR31,
TXADDR3, SMTXD1
V17
Bidirectional
(Optional: open-drain)
PB24, TXADDR31,
RXADDR3, SMRXD1
U16
Bidirectional
(Optional: open-drain)
PB23, TXADDR21,
RXADDR2, SDACK1,
SMSYN1
W16
Bidirectional
(Optional: open-drain)
PB22, TXADDR41,
RXADDR4, SDACK2,
SMSYN2
V15
Bidirectional
(Optional: open-drain)
PB21, SMTXD2,
TXADDR11, BRG01,
RXADDR1, PHSEL[1]
U14
Bidirectional
(Optional: open-drain)
PB20, SMRXD2,
L1CLKOA, TXADDR01,
RXADDR0, PHSEL[0]
T13
Bidirectional
(Optional: open-drain)
PB19, MII1-RXD3, RTS4
V13
Bidirectional
(Optional: open-drain)
PB18, RXADDR41,
TXADDR4, RTS2, L1ST2
T12
Bidirectional
(Optional: open-drain)
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
80
Freescale Semiconductor
Mechanical Data and Ordering Information
Table 39. Pin Assignments (continued)
Name
Pin Number
Type
PB17, L1ST3, BRGO2,
RXADDR11, TXADDR1,
PHREQ[1]
W12
Bidirectional
(Optional: open-drain)
PB16, L1RQa, L1ST4,
RTS4, RXADDR01,
TXADDR0, PHREQ[0]
V11
Bidirectional
(Optional: open-drain)
PB15, TXCLAV, BRG03,
RXCLAV
U10
Bidirectional
PB14RXADDR21,
TXADDR2
U18
Bidirectional
PC15, DREQ0, RTS3,
L1ST1, TXCLAV, RXCLAV
R19
Bidirectional
PC14, DREQ1, RTS2,
L1ST2
R18
Bidirectional
PC13, MII1-TXD3,
SDACK1
V10
Bidirectional
PC12, MII1-TXD2, TOUT1
T18
Bidirectional
PC11, USBRXP
V16
Bidirectional
PC10, USBRXN, TGATE1
U15
Bidirectional
PC9, CTS2
T14
Bidirectional
PC8, CD2, TGATE2
W14
Bidirectional
PC7, CTS4, L1TSYNCB,
USBTXP
V12
Bidirectional
PC6, CD4, L1RSYNCB,
USBTXN
U11
Bidirectional
PC5, CTS3, L1TSYNCA,
SDACK2
T10
Bidirectional
PC4, CD3, L1RSYNCA
W10
Bidirectional
PD15, L1TSYNCA, UTPB0 U8
Bidirectional
PD14, L1RSYNCA, UTPB1 U7
Bidirectional
PD13, L1TSYNCB, UTPB2 U6
Bidirectional
PD12, L1RSYNCB, UTPB3 U5
Bidirectional
PD11, RXD3, RXENB
R2
Bidirectional
PD10, TXD3, TXENB
T2
Bidirectional
PD9, TXD4, UTPCLK
U2
Bidirectional
PD8, RXD4, MII-MDC,
RMII-MDC
R3
Bidirectional
PD7, RTS3, UTPB4
W3
Bidirectional
PD6, RTS4, UTPB5
W5
Bidirectional
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
81
Mechanical Data and Ordering Information
Table 39. Pin Assignments (continued)
Name
Pin Number
Type
PD5, CLK8, L1TCLKB,
UTPB6
V6
Bidirectional
PD4, CLK4, UTPB7
W4
Bidirectional
PD3, CLK7, TIN4, SOC
T9
Bidirectional
PE31, CLK8, L1TCLKB,
MII1-RXCLK
U9
Bidirectional
(Optional: open-drain)
PE30, L1RXDB,
MII1-RXD2
W7
Bidirectional
(Optional: open-drain)
PE29, MII2-CRS
T8
Bidirectional
(Optional: open-drain)
PE28, TOUT3, MII2-COL
V5
Bidirectional
(Optional: open-drain)
PE27, RTS3, L1RQB,
MII2-RXER, RMII2-RXER
V4
Bidirectional
(Optional: open-drain)
PE26, L1CLKOB,
MII2-RXDV,
RMII2-CRS_DV
T1
Bidirectional
(Optional: open-drain)
PE25, RXD4, MII2-RXD3,
L1ST2
T3
Bidirectional
(Optional: open-drain)
PE24, SMRXD1, BRGO1,
MII2-RXD2
V8
Bidirectional
(Optional: open-drain)
PE23, SMSYN2, TXD4,
MII2-RXCLK, L1ST1
V2
Bidirectional
(Optional: open-drain)
PE22, TOUT2, MII2-RXD1, V1
RMII2-RXD1, SDACK1
Bidirectional
(Optional: open-drain)
PE21, SMRXD2, TOUT1,
MII2-RXD0, RMII2-RXD0,
RTS3
V9
Bidirectional
(Optional: open-drain)
PE20, L1RSYNCA,
SMTXD2, CTS3,
MII2-TXER
R4
Bidirectional
(Optional: open-drain)
PE19, L1TXDB,
MII2-TXEN, RMII2-TXEN
T6
Bidirectional
(Optional: open-drain)
PE18, L1TSYNCA,
SMTXD1, MII2-TXD3
R1
Bidirectional
(Optional: open-drain)
PE17, TIN3, CLK5,
BRGO3, SMSYN1,
MII2-TXD2
W8
Bidirectional
(Optional: open-drain)
PE16, L1RCLKB, CLK6,
TXD3, MII2-TXCLK,
RMII2-REFCLK
T7
Bidirectional
(Optional: open-drain)
PE15, TGATE1,
MII2-TXD1, RMII2-TXD1
W6
Bidirectional
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
82
Freescale Semiconductor
Mechanical Data and Ordering Information
Table 39. Pin Assignments (continued)
Name
Pin Number
Type
PE14, RXD3, MII2-TXD0,
RMII2-TXD0
V7
Bidirectional
TMS
V18
Input
TDI, DSDI
T16
Input
TCK, DSCK
U17
Input
TRST
W18
Input
TDO, DSDO
T17
Output
MII1_CRS
T11
Input
MII_MDIO
P19
Bidirectional
MII1_TXEN, RMII1_TXEN
T5
Output
MII1_COL
U12
Input
VSSSYN1
C2
PLL analog VDD and GND
VSSSYN
E4
Power
VDDLSYN
B2
Power
GND
G6, G7, G8, G9, G10, G11, G12, G13, H7, H8, H9, H10, H11, H12, Power
H13, H14, J7, J8, J9, J10, J11, J12, J13, K7, K8, K9, K10, K11, K12,
K13, L7, L8, L9, L10, L11, L12, L13, M7, M8, M9, M10, M11, M12,
M13, N7, N8, N9, N10, N11, N12, N13, N14, P7, P13, R16
VDDL
E5, E6, E9, E11, E14, G15, H5, J5, J15, K15, L5, M15, N5, R6, R9, Power
R10, R12, R15
VDDH
E7, E8, E10, E12, E13, E15, F5, F6, F7, F8, F9, F10, F11, F12, F13, Power
F14, F15, G5, G14, H6, H15, J6, J14, K5, K6, K14, L6, L14, L15, M5,
M6, M14, N6, N15, P5, P6, P8, P9, P10, P11, P12, P14, P15, R5,
R7, R8, R11, R13, R14
N/C
N17
1
No connect
ESAR mode only.
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
83
Mechanical Data and Ordering Information
16.2
Mechanical Dimensions of the PBGA Package
Figure 78 shows the mechanical dimensions of the PBGA package.
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M—1994.
3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.
Figure 78. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
84
Freescale Semiconductor
Document Revision History
17 Document Revision History
Table 40 lists significant changes between revisions of this hardware specification.
Table 40. Document Revision History
Revision
Number
Date
7
07/2010
In Table 9, “Bus Operation Timings,” changed the following:
• Updated TRLX condition value for B22a/b/c to “TRLX = [0 or 1]”
• Removed TRLX condition for B23
• Updated condition and equation for B30 to “Invalid GPCM read/write access
(MIN = 0.25 × B1 – 2.00)”
• Updated note 8 to “The timing B30 refers to CS when ACS = 00 and to CS and WE(0:3) when
CSNT = 0.”
6
05/2010
Added minimum load for CLKOUT in Section 10, “Bus Signal Timing.”
5
03/2009
Updated formatting of Table 12 , “PCMCIA Port Timing,” Table 13, “Debug Port Timing,” Table 14,
“Reset Timing,” and Table 15, “JTAG Timing.”
4
08/2007
• On page 1, updated first paragraph and added a second paragraph.
• After Table 2, inserted a new figure showing the undershoot/overshoot voltage (Figure 3) and
renumbered the rest of the figures.
• In Table 9, for reset timings B29f and B29g added footnote indicating that the formula only applies
to bus operation up to 50 MHz.
• In Figure 6, changed all reference voltage measurement points from 0.2 and 0.8 V to 50% level.
• In Table 18, changed num 46 description to read, “TA assertion to rising edge ...”
• In Figure 49, changed TA to reflect the rising edge of the clock.
3.0
7/22/2004
•
•
•
•
2.0
12/2003
•
•
•
•
•
•
•
Changed the maximum operating frequency to 133 MHz.
Put in the orderable part numbers that are orderable.
Put the timing in the 80 MHz column.
Rounded the timings to hundredths in the 80 MHz column.
Put the pin numbers in footnotes by the maximum currents in Table 6.
Changed 22 and 41 in the Timing.
Put in the Thermal numbers.
1.0
9/2003
•
•
•
•
Added the DSP information in the Features list
Fixed table formatting.
Nontechnical edits.
Released to the external web.
0.9
8/2003
Changed the USB description to full-/low-speed compatible.
0.8
8/2003
Added the Reference to USB 2.0 to the Features list and removed 1.1 from USB on the block
diagrams.
0.7
7/2003
Added the RxClav and TxClav signals to PC15.
0.6
6/2003
Changed the pin descriptions per the June 22 spec.
0.5
5/2003
Changed some more typos, put in the phsel and phreq pins. Corrected the USB timing.
Changes
Added sentence to Spec B1A about EXTCLK and CLKOUT being in Alignment for Integer Values
Added a footnote to Spec 41 specifying that EDM = 1
Added RMII1_EN under M1II_EN in Table 36 Pin Assignments
Added a tablefootnote to Table 6 DC Electrical Specifications about meeting the VIL Max of the
I2C Standard
• Put the new part numbers in the Ordering Information Section
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
85
Document Revision History
Table 40. Document Revision History (continued)
Revision
Number
Date
0.4
5/2003
Changed the pin descriptions for PD8 and PD9.
0.3
05/2003
Corrected the signals that had overlines on them.
0.2
05/2003
Made the changes to the RMII Timing, Made sure all the VDDL, VDDH, and GND show up on the
pinout diagram. Changed the SPI Master Timing Specs. 162 and 164.
0.1
04/2003
Added pinout and pinout assignments table. Added the USB timing to Section 14. Added the
Reduced MII to Section 15. Removed the Data Parity. Made some changes to the Features list.
0
02/2003
Initial revision.
Changes
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
86
Freescale Semiconductor
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