Data Sheet

Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MPC8535EEC
Rev. 7, 07/2015
MPC8535E
MPC8535E PowerQUICC III
Integrated Processor
Hardware Specifications
• High-performance, 32-bit e500 core, scaling up to
1.25 GHz, that implements the Power Architecture®
technology
– 36-bit physical addressing
– Double-precision embedded floating point APU using
64-bit operands
– Embedded vector and scalar single-precision
floating-point APUs using 32- or 64-bit operands
– Memory management unit (MMU)
• Integrated L1/L2 cache
– L1 cache—32-Kbyte data and 32-Kbyte instruction
– L2 cache—512-Kbyte (8-way set associative)
• DDR2/DDR3 SDRAM memory controller with full ECC
support
– One 64-bit/32-bit data bus
– Up to 250-MHz clock (500-MHz data rate)
– Supporting up to 16 Gbytes of main memory
– Using ECC, detects and corrects all single-bit errors and
detects all double-bit errors and all errors within a nibble
– Invoke a level of system power management by
asserting MCKE SDRAM signal on-the-fly to put the
memory into a low-power sleep mode
– Both hardware and software options to support
battery-backed main memory
• Integrated security engine (SEC) optimized to process all
the algorithms associated with IPsec, IKE, SSL/TLS,
iSCSI, SRTP, IEEE Std 802.16e™, and 3GPP.
– XOR engine for parity checking in RAID storage
applications
• Enhanced Serial peripheral interfaces (eSPI)
– Support boot capability from eSPI
• Two enhanced three-speed Ethernet controllers (eTSECs)
with SGMII support
– Three-speed support (10/100/1000 Mbps)
– Two IEEE Std 802.3®, IEEE 802.3u, IEEE 802.3x,
IEEE 802.3z, IEEE 802.3ac, IEEE 802.3ab, and
IEEE Std 1588™-compatible controllers
MAPBGA–783
29 mm x 29 mm
•
•
•
•
•
•
•
•
•
•
•
•
– Support for various Ethernet physical interfaces: GMII,
TBI, RTBI, RGMII, MII, RGMII, RMII, and SGMII
– Support TCP/IP acceleration and QOS features
– MAC address recognition and RMON statistics support
– Support ARP parsing and generating wake-up events
based on the parsing results while in deep sleep mode
– Support accepting and storing packets while in deep
sleep mode
High-speed interfaces (multiplexed) supporting:
– Two PCI Express interfaces
– PCI Express 1.0a compatible
– One x4/x2/x1 PCI Express interface
– Two x2/x1 ports
– One SGMII interface
– One Serial ATA (SATA) controller supports SATA I and
SATA I data rates
PCI 2.2 compatible PCI controller
Two universal serial bus (USB) dual-role controllers
comply with USB specification revision 2.0
133-MHz, 32-bit, enhanced local bus (eLBC) with memory
controller
Enhanced secured digital host controller (eSDHC) used for
SD/MMC card interface
– Support boot capability from eSDHC
Integrated four-channel DMA controller
Dual I2C and dual universal asynchronous
receiver/transmitter (DUART) support
Programmable interrupt controller (PIC)
Power management, low standby power
– Support Doze, Nap, Sleep, Jog, and Deep Sleep mode
– PMC wake on: LAN activity, USB connection or remote
wakeup, GPIO, internal timer, or external interrupt event
System performance monitor
IEEE Std 1149.1™-compatible, JTAG boundary scan
783-pin FC-PBGA package, 29 mm × 29 mm
Freescale reserves the right to change the detail specifications as may be required
to permit improvements in the design of its products.
© 2009-2011, 2014-2015 Freescale Semiconductor, Inc. All rights reserved.
Table of Contents
1
2
Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .3
1.1 Pin Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.1 Overall DC Electrical Characteristics . . . . . . . . . . . . . .21
2.2 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.3 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.4 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.5 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.6 DDR2 and DDR3 SDRAM . . . . . . . . . . . . . . . . . . . . . .31
2.7 eSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.8 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
2.9 Ethernet: Enhanced Three-Speed Ethernet (eTSEC),
MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
2.10 Ethernet Management Interface Electrical Characteristics
60
2.11 USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.12 Enhanced Local Bus Controller (eLBC) . . . . . . . . . . . .65
2.13 Enhanced Secure Digital Host Controller (eSDHC) . . .74
2.14 Programmable Interrupt Controller (PIC) . . . . . . . . . . .76
2.15 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
2.16 Serial ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
2.17 I2C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
2.18 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
2.19 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
2.20 High-Speed Serial Interfaces . . . . . . . . . . . . . . . . . . . .90
2.21 PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
3
4
5
6
7
2.23 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
2.24 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . 113
3.1 System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
3.2 Power Supply Design and Sequencing . . . . . . . . . . . 113
3.3 Pin States in Deep Sleep State . . . . . . . . . . . . . . . . . 114
3.4 Decoupling Recommendations . . . . . . . . . . . . . . . . . 114
3.5 SerDes
Block
Power
Supply
Decoupling
Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . 115
3.6 Connection Recommendations . . . . . . . . . . . . . . . . . 115
3.7 Pull-Up and Pull-Down Resistor Requirements . . . . . 115
3.8 Output Buffer DC Impedance . . . . . . . . . . . . . . . . . . 115
3.9 Configuration Pin Muxing . . . . . . . . . . . . . . . . . . . . . 116
3.10 JTAG Configuration Signals . . . . . . . . . . . . . . . . . . . 117
3.11 Guidelines for High-Speed Interface Termination . . . 119
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.1 Part Numbering Nomenclature . . . . . . . . . . . . . . . . . 121
4.2 Part Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.3 Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.1 Package Parameters for the FC-PBGA . . . . . . . . . . . 122
5.2 Mechanical Dimensions of the FC-PBGA . . . . . . . . . 124
Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . 125
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
2
Freescale Semiconductor
Pin Assignments and Reset States
This figure shows the major functional units within the chip.
e500 Core
32-Kbyte
D-Cache
MPC8535E
Performance
Monitor
Timers
SD
MMC
Enhanced
Local Bus
USB
Host/
Device
USB
Host/
Device
ULPI
ULPI
SEC
OpenPIC
Gigabit
Ethernet
w/ IEEE 1588
512-Kbyte
L2 Cache
32-Kbyte
I-Cache
Coherency
Module
Gigabit
Ethernet
w/ IEEE 1588
eSPI
DUART
2x I2C
Power
Management
64-bit
Async
DDR2/DDR3
Queue SDRAM Controller
with ECC
PCI 32
DMA
PCI-e
PCI-e
SATA
SGMII
SerDes
4 Lane SerDes
Figure 1. Chip Block Diagram
1
Pin Assignments and Reset States
NOTE
The naming convention of TSEC1 and TSEC3 is used to allow the splitting voltage rails
for the eTSEC blocks and to ease the port of existing PowerQUICC III software
NOTE
The UART_SOUT[0:1] and TEST_SEL pins must be set to a proper state during POR
configuration. See Table 1 for more details.
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
3
Pin Assignments and Reset States
1.1
Pin Map
See Table 1 for the MPC8535E pinout, which is a subset of the MPC8536E.
A
2
3
M
N
P
R
GND
GND
GVDD
MDQS
[7]
MDQ
[58]
MDQ
[59]
AVDD_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ USB1_D USB1_D USB1_ USB1_D USB1_D USB1_
RXD
SRDS2 RX_CLK RXD
TX_EN
RX_DV
STP
CLK
[7]
[0]
[2]
[5]
[3]
[1]
MDQ
[44]
MDQ
[40]
MDM
[5]
MDQS
[5]
GVDD
MDQ
[42]
MDQ
[43]
MDQ
[35]
MDQ
[60]
MDQ
[61]
MDM
[7]
MDQS
[7]
GND
MDM
[62]
MDQ
[63]
GND
MDQ
[45]
MDQ
[41]
MCS
[0]
GND
MDQ
[33]
GVDD
MDQ
[38]
MDQ
[52]
GVDD
MDM
[6]
MDQS
[6]
MDQ
[50]
MDQ
[51]
GVDD
USB1_
AGND_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ USB1_D USB1_D USB1_D USB1_D USB1_
OVDD
PWRRXD
SRDS2 RXD
RX_DV GTX_CLK RXD
NXT
[6]
[1]
[3]
[4]
FAULT
[1]
[0]
[3]
SD2_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ TSEC1_ USB1_
PCTL0/ USB2_D USB2_D GND USB3_D USB3_D
PLL_
RXD
RXD
TXD
RXD RX_CLK RXD
[1]
[0]
[0]
[1]
GPIO[6]
[2]
[0]
[3]
[2]
[7]
TPA
MAPAR_
OUT
GND
NC
MA
[0]
MCK
[3]
9
MCK
[0]
MCK
[0]
MCS
[2]
MRAS
GND
GVDD
GVDD
MDQ
[36]
GND
MDM
[4]
GND
MODT
[0]
GVDD
MODT
[2]
NC
MA
[2]
GND
GVDD
MA
[4]
MCAS
GND
MDQ
[39]
MDQ
[53]
MDQ
[49]
GVDD
MDQ
[37]
GVDD
MDQS
[4]
MDQS
[4]
MDQ
[48]
MODT
[3]
MCS
[3]
MCS
[1]
MCK
[2]
MCK
[2]
MA
[13]
GVDD
MODT
[1]
NC
SEE DETAIL
A
MCK
MCK
MA
GV
DD
MA
[8]
GND
MA
[7]
[1]
[5]
GVDD
MCKE
[3]
[5]
NC
GND
GND
NC
MDQS
[6]
GND
SD2_
SD2_
IMP_CAL REF_
_TX
CLK
SD2_
PLL_
TPD
SD2_
REF_
CLK
Rsvd
S2GND
Rsvd
S2VDD
MDQ
[54]
GVDD
MDQ
[55]
GND
TSEC1_
TXD
[1]
TSEC3_
RX_ER
Rvsd
TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ TSEC1_
TXD GTX_CLK TX_EN
TXD
TXD
TXD
TX_ER
[1]
[2]
[4]
[6]
GND
TVDD
GND
MA
[5]
NC
MA
[14]
MA
[15]
MCKE
[2]
MCKE
[0]
GVDD
MCKE
[1]
NC
X2GND
11
MA
[6]
GVDD
MECC
[3]
MA
[12]
GVDD
MECC
[2]
GVDD
MCK
[1]
MCK
[1]
GND
X2VDD
SD2_TX
[1]
12
MA
[11]
MA
[9]
GND
MECC
[7]
NC
MECC
[0]
GND
GVDD
TSEC3_ TSEC3_ MSRCID MSRCID UART_
X2GND SD2_TX X2VDD SD2_TX X2GND TXD
RXD
CTS
[0]
[2]
[1]
[0]
[7]
[7]
[1]
MAPAR_
ERR
MBA
[2]
MECC
[6]
MCK
[4]
VDD_
CORE
14
GND
MDQ
[27]
15
MDQ
[26]
16
MDQ
[30]
MDQS
[3]
MDQS
[8]
GVDD
MECC
[1]
MDQ
[31]
MDQS
[3]
MDM
[3]
MECC
[5]
GND
GVDD
GND
GVDD
MDQ
[19]
MDQ
[23]
MDQ
[18]
GVDD
GND
GND
LCS6/
DMA_
DACK2
LA
[28]
VDD_
CORE
GND
LCS
[4]
LCS5/
DMA_
DREQ2
LA
[30]
23
MDQS
[0]
GVDD
25
MDQ
[12]
MDQ
[5]
MDM
[0]
26
MDQ
[0]
MDQ
[1]
LAD
[25]
GND
GND
LAD
[27]
MDQS
[0]
[30]
LBS[1]
BVDD
LAD
[28]
LWE[2]/
LBS[2]
LAD
[23]
LAD
[26]
MDQ
[4]
LDP
[3]
LAD
[19]
GND
GND
LAD
[22]
LAD
[18]
LAD
[16]
LSYNC_
IN
AVDD_ LSYNC_
LBIU
OUT
C
LAD
[24]
[29]
D
LAD
[21]
GND
LAD
[15]
LCLK
[0]
LCLK
[2]
BVDD
LAD
[14]
PCI1_
AD
[30]
VDD_
PLAT
SD1_TX
[6]
LAD
[1]
SD1_TX
[1]
XGND
SD1_TX
[3]
XGND
SD1_TX
[4]
XVDD
SD1_TX
[6]
XGND
SD1_TX
[2]
XGND
SD1_TX
[5]
XVDD
SD1_TX
[2]
XVDD
SD1_TX
[5]
BVDD
MDM
[1]
VDD_
PLAT
SENSEVDD_
PLAT
XGND
LWE[3]/
LBS[3]
MDQ
[9]
GND
SD1_TX
[4]
LAD
[31]
22
PCI1_
GNT
[1]
XVDD
GND
GVDD
SENSEVSS
PCI1_
REQ
[1]
SD1_TX
[3]
BVDD
SEE
DETAIL
C
LAD
LWE[1]/
LAD
MDQ
[6]
GND
VDD_
CORE
XVDD
MDQ
[7]
MDQ
[2]
CLK_
OUT
SD1_TX
[1]
LGPL0/
LFCLE
MDQS
[1]
GND
SENSEVDD_
CORE
LGPL4/
LGTA/
LGPL1/ LUPWAIT/
XGND
LFALE LPBSE/
LFRB
LCS
[3]
MDQS
[1]
GND
VDD_
CORE
VDD_
PLAT
VDD_
CORE
LGPL5
BVDD
MDQ
[3]
GND
MSRCID
[3]
BVDD
GND
GVDD
GND
VDD_
CORE
GND
VDD_
PLAT
LGPL2/
LOE/
LFRE
MDQ
[14]
VDD_
CORE
LWE0/
LBS0/
LFWE
BVDD
LCLK
[1]
GND
LAD
[0]
LAD
[3]
LAD
[4]
LBCTL
LAD
[7]
LALE
LDP
[0]
GND
LAD
[20]
LAD
[17]
LDP
[1]
LAD
[13]
LAD
[12]
E
F
G
H
J
LAD
[11]
XVDD
LAD
[2]
SD1_TX
[0]
BVDD
SD1_TX
[0]
LAD
[5]
LAD
[6]
GND
LAD
[9]
XGND
GND
VDD_
PLAT
GND
GND
VDD_
PLAT
NC
SGND
SVDD
SD1_RX
[1]
SD1_
IMP_CAL SGND
_RX
SD1_RX
[1]
NC
SVDD
SD1_RX SGND
[0]
LAD
[10]
LAD
[8]
SGND
SD1_RX
[0]
SVDD
K
L
M
N
P
GND
VDD_
PLAT
GND
GND
VDD_
PLAT
XVDD
XGND
SVDD
Rsvd
Rsvd
SVDD
SGND
SD1_RX
[3]
SVDD
SD1_RX
[3]
SD1_RX
[2]
SVDD
SD1_RX
SGND
[2]
R
GND
VDD_
CORE
LA
[27]
NC
MDQ
[15]
GND
GND
LCS
[2]
21
VDD_
CORE
VDD_
PLAT
VDD_
CORE
LCS
[0]
LCS
[1]
GVDD
GND
GND
MDQ
[20]
GND
VDD_
CORE
GND
VDD_ TSEC3_
MDVAL MSRCID
RXD
CORE
[1]
[6]
LCS7/
DMA_
DDONE2
MDQ
[16]
20
GND
VDD_
CORE
LA
[29]
GND
MDQ
[17]
MDQ
[10]
B
GND
MDIC
[1]
MDIC
[0]
LGPL3/
LFWP
MDQ
[11]
A
GND
GVDD
LA
[31]
GND
VDD_
CORE
GND
GND
19
GND
GVDD
MDQ
[21]
MDQ
[28]
MVREF
MECC
[4]
GVDD
MDQ
[29]
LDP
[2]
MDQ
[22]
MCK
[4]
MDM
[2]
MDQ
[24]
GND
MDQS
[2]
GND
GND
MDQS
[2]
MDQ
[25]
MDQ
[13]
MDM
[8]
GVDD
18
MDQ
[8]
MDQS
[8]
VDD_
CORE
GND
T
GND
MCP
SGND
SGND
SVDD
NC
SGND
SD1_
PLL_
TPA
SD1_
REF_
CLK
SD1_
REF_
CLK
U
AGND_
SRDS
XGND
SVDD
GND
UART_
SIN
[0]
UART_
GND
RTS
[1]
IRQ[10]/
IRQ[9]/
DMA_
OVDD DDRCLK DMA_
DACK[3] DREQ[3]
IRQ[11]/
PCI1_GNT
OVDD
UDE [4]/GPIO DMA_
DDONE[3]
[3]
USB3_ USB3_D
[7]
NXT
7
USB3_
DIR
USB3_
STP
8
USB2_
PCTL0/
GPIO[8]
Rsvd
9
SDHC_ SDHC_
WP/GPIO CMD
[5]
SDHC_ SDHC_
CD/GPIO
DAT
[3]
[4]
12
PCI1_
REQ
[2]
SDHC_ SDHC_
DAT
CLK
[2]
13
PCI1_
GNT
[2]
IIC2_
SDA
SYSCLK
14
IIC2_
SCL
15
GND
RTC
OVDD
PCI1_
AD
[26]
OVDD
PCI1_
IDSEL
IRQ
[5]
AVDD_
HRESET
CORE
PCI1_
AD
[29]
PCI1_
AD
[27]
IRQ_
OUT
PCI1_
AD
[24]
PCI1_
AD
[23]
IRQ
[1]
PCI1_
C_BE
[3]
PCI1_
AD
[20]
17
PCI1_
AD
[18]
CKSTP_ AVDD_
PLAT
IN
18
IRQ
[3]
AVDD_
SRESET
DDR
19
OVDD ASLEEP AVDD_
PCI1
20
GND
PCI1_
TRDY
IIC1_
SCL
TRST
21
OVDD
PCI1_
SERR
IRQ
[0]
IIC1_
SDA
22
PCI1_
AD
[15]
GND
PCI1_
AD
[11]
23
OVDD
PCI1_
AD
[10]
PCI1_
AD
[12]
24
25
GND
GND
XVDD
L2_
TSTCLK
PCI1_
IRDY
PCI1_
AD
[16]
PCI1_
C_BE
[2]
PCI1_
FRAME
XGND
L1_
TSTCLK
PCI1_
PERR
C_BE
[1]
[6]
[8]
PAR
XVDD
IRQ
[2]
PCI1_
AD
[13]
GND
PCI1_
AD
[14]
SGND
PCI1_
AD
[5]
PCI1_
AD
[7]
PCI1_
AD
[9]
SGND
SD1_RX
[4]
SVDD
SD1_RX
SGND
[4]
SVDD
SD1_RX
[5]
PCI1_
AD
[1]
PCI1_
AD
[4]
PCI1_
AD
[8]
PCI1_
C_BE
[0]
GND
PCI1_
AD
[2]
PCI1_
AD
[3]
PCI1_
CLK
26
SD1_RX
[7]
SVDD POWER_ OVDD
EN
PCI1_
AD
[6]
TMS
27
SD1_
SGND IMP_CAL
_TX
TDO
TCK
TDI
28
AF
AG
AH
SD1_RX LSSD_
[6]
MODE
OVDD
SD1_RX POWER_ PCI1_
AD
[6]
OK
[0]
SGND
IRQ
[4]
16
CKSTP_
OUT
PCI1_
AD
[17]
PCI1_ PCI1_
DEVSEL STOP
11
SDHC_ SDHC_
DAT
DAT
[0]
[1]
PCI1_
REQ
[0]
SEEIRQDETAIL
DPCI1_
PCI1_
IRQ
SD1_TX
10
UART_
SIN
[1]
HRESET_
REQ
PCI1_
AD
[19]
SVDD
6
PCI1_REQ
[4]/GPIO
[1]
PCI1_
AD
[21]
SVDD
USB3_D USB3_D
[5]
[6]
PCI1_
AD
[28]
OVDD
[7]
3
5
PCI1_
AD
[22]
SD1_TX
[7]
2
4
PCI1_
AD
[31]
SGND
NC
UART_
RTS
[0]
1
USB2_ USB2_D USB2_D USB3_D USB3_
CLK
[4]
[4]
[5]
CLK
PCI1_
AD
[25]
GND
XVDD
TEST_
SEL
PCI1_REQ PCI1_GNT
[3]/GPIO [3]/GPIO
[0]
[2]
PCI1_
OVDD
GNT
[0]
TRIG_
IRQ
GND OUT/READY TRIG_IN
[7]
/QUIESCE
VDD_
PLAT
UART_
SOUT
[1]
USB1_
DIR
USB2_D USB2_D USB3_D USB3_D
[3]
[2]
[2]
[3]
OVDD
SEE DETAIL B
GND
GVDD
LVDD
DMA_
TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ EC_GTX_ TSEC1_ USB2_D
SD2_RX
DACK[0]/ USB2_D OVDD
S2VDD TXD
S2GND
RXD
RXD
TXD
RXD CLK125 COL
[0]
[6]
[7]
GPIO[10]
[0]
[5]
[4]
[0]
[4]
TSEC_
SD2_ TSEC3_
TSEC1_ USB2_ USB2_
USB2_
TVDD
LVDD
GND 1588_TRIG GND
GND
S2VDD SD2_RX IMP_CAL TXD
RXD
NXT
STP
DIR
[0]
_RX
[2]
_IN[1]
[6]
SDHC_
TSEC_
USB2_
TSEC1_ TSEC1_ TSEC1_
TSEC3_ TSEC3_ TSEC3_
SPI_
SPI_
SD2_RX
DAT[4]/SPI
NC
S2GND
PWRTXD
RXD
TXD
TXD
TXD 1588_TRIG TXD
MOSI
CLK
[1]
FAULT
_CS[0]
[7]
[5]
[5]
[3]
[5]
[6]
_IN[0]
SDHC_
USB2_
SPI_
TSEC3_ TSEC3_ TSEC3_ TSEC_ TSEC1_ TSEC1_
SD2_RX S2GND
PCTL1/
NC
GND DAT[6]/SPI
GND
1588_ RX_ER
TXD
COL
TX_ER
CRS
[1]
GPIO[9] MISO
_CS[2]
[4]
CLK
SDHC_ DMA_
SDHC_
DMA_ UART_
TSEC_ TSEC_
EC_
TSEC3_ TSEC3_ 1588_CLK
DAT[7]/SPI DREQ[0]/ DAT[5]/SPI OVDD DACK[1]/ SOUT
1588_TRIG
NC
NC
NC
MDC
CRS TX_CLK _OUT
GPIO[11]
_CS[3] GPIO[14] _CS[1]
_OUT[1]
[0]
TSEC_
TSEC_
TSEC_
DMA_ UART_
DMA_
DMA_
EC_
SD2_TX
MSRCID
1588_PULSE
1588_TRIG
1588_PULSE
OVDD
DDONE[0]/
DDONE[1]/
DREQ[1]/
X2GND
X2VDD
GND
CTS
MDIO GPIO[12] GPIO[13]
[4]
[0]
GPIO[15]
_OUT2 _OUT[0] _OUT1
[0]
MA
[3]
GND
USB1_
TSEC1_ PCTL1/
TX_CLK GPIO[7]
Rvsd
10
28
AH
L
MCK
[3]
27
AG
K
MDQ
[57]
8
24
AF
J
MDQ
[56]
5
17
AE
H
MBA
[1]
13
AD
G
MDQ
[34]
MA
[10]
7
AC
F
MDQ
[47]
MWE
6
AB
E
MDQ
[46]
MBA
[0]
V
AA
D
MDQ
[32]
4
U
Y
C
MDQS
[5]
1
T
W
B
GVDD
SD1_
PLL_
TPD
AVDD_
SRDS
SGND
SD1_RX
[5]
SVDD
SD1_RX
[7]
V
W
Y
AA
AB
AC
AD
AE
Figure 2. Chip Pin Map Bottom View
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
4
Freescale Semiconductor
Pin Assignments and Reset States
A
1
B
C
D
E
F
G
H
J
K
L
M
N
P
GVDD
MDQS
[5]
MDQ
[32]
MDQ
[46]
MDQ
[47]
MDQ
[34]
GND
MDQ
[56]
MDQ
[57]
GND
GVDD
MDQS
[7]
MDQ
[58]
2
MDQ
[44]
MDQ
[40]
MDM
[5]
MDQS
[5]
GVDD
MDQ
[42]
MDQ
[43]
MDQ
[35]
MDQ
[60]
MDQ
[61]
MDM
[7]
MDQS
[7]
GND
MDM
[62]
3
GND
MDQ
[45]
MDQ
[41]
MCS
[0]
GND
MDQ
[33]
GVDD
MDQ
[38]
MDQ
[52]
GVDD
MDM
[6]
MDQS
[6]
MDQ
[50]
MDQ
[51]
4
MBA
[0]
MWE
MCS
[2]
GVDD
MDQ
[36]
GND
MDM
[4]
GND
MDQ
[39]
MDQ
[53]
MDQ
[49]
MDQS
[6]
MDQ
[54]
MDQ
[55]
5
MA
[10]
MBA
[1]
MRAS
GND
MODT
[0]
GVDD
MDQ
[37]
GVDD
MDQS
[4]
MDQS
[4]
MDQ
[48]
GND
GVDD
GND
6
MAPAR_
OUT
NC
GND
GVDD
MODT
[2]
MODT
[3]
MCS
[3]
MCS
[1]
MCK
[2]
MCK
[2]
SD2_
IMP_CAL
_TX
SD2_
REF_
CLK
S2GND
SD2_RX
[0]
7
GND
MA
[0]
GVDD
NC
MCAS
MA
[13]
GVDD
MODT
[1]
NC
GND
SD2_
PLL_
TPD
SD2_
REF_
CLK
S2VDD
SD2_RX
[0]
8
MCK
[3]
MCK
[3]
MA
[2]
GND
GVDD
GND
MA
[1]
MCK
[5]
MCK
[5]
GND
Rsvd
S2GND
SD2_RX
[1]
S2GND
9
MCK
[0]
MCK
[0]
GVDD
MA
[4]
MA
[8]
MA
[7]
GVDD
MCKE
[3]
NC
NC
Rsvd
S2VDD
SD2_RX
[1]
S2GND
10
MA
[3]
GND
MA
[5]
NC
MA
[14]
MA
[15]
MCKE
[2]
MCKE
[0]
GVDD
MCKE
[1]
NC
X2GND
NC
NC
11
MA
[6]
GVDD
MECC
[3]
MA
[12]
GVDD
MECC
[2]
GVDD
MCK
[1]
MCK
[1]
GND
X2VDD
SD2_TX
[1]
X2GND
SD2_TX
[0]
12
MA
[11]
MA
[9]
GND
MECC
[7]
GND
NC
MECC
[0]
GVDD
GND
GVDD
X2GND
SD2_TX
[1]
X2VDD
SD2_TX
[0]
13
MAPAR_
ERR
MBA
[2]
MECC
[6]
MDQS
[8]
MDQS
[8]
MDM
[8]
GND
MCK
[4]
MCK
[4]
VDD_
CORE
GND
VDD_
CORE
GND
VDD_
CORE
14
GND
MDQ
[27]
GVDD
MECC
[1]
GVDD
MECC
[5]
MECC
[4]
GVDD
GND
GVDD
VDD_
CORE
GND
VDD_
CORE
GND
DETAIL A
Figure 3. Chip Pin Map Detail A
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
5
Pin Assignments and Reset States
AA
AB
AC
AD
AE
MDQ
[59]
AVDD_
SRDS2
TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ USB1_D USB1_D
RXD
RXD
RX_CLK
TX_EN
RX_DV
[0]
[2]
[3]
[1]
MDQ
[63]
AGND_
SRDS2
TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ USB1_D USB1_D USB1_D USB1_D
RXD
RXD
RX_DV GTX_CLK RXD
[1]
[3]
[4]
[6]
[1]
[0]
[3]
GVDD
SD2_
PLL_
TPA
Rvsd
S2VDD
TSEC3_
RX_ER
V
Y
T
Rvsd
U
W
R
TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ TSEC1_
RXD
RXD
TXD
RXD
RXD
RX_CLK
[2]
[0]
[3]
[2]
[7]
GND
TVDD
TSEC1_
TXD
[1]
GND
LVDD
TSEC1_
TX_CLK
TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ TSEC1_
TXD
TXD
TXD
TXD
GTX_CLK TX_EN
TX_ER
[1]
[2]
[4]
[6]
USB1_
PCTL0/
GPIO[6]
TSEC_
1588_TRIG
_IN[1]
USB1_D USB1_D
[5]
[7]
USB2_D USB2_D
[0]
[1]
USB1_
NXT
GND
AG
AH
USB1_
STP
USB1_
DIR
1
OVDD
USB1_
PWRFAULT
2
USB3_D USB3_D
[1]
[0]
3
USB1_
PCTL1/
GPIO[7]
OVDD
USB2_D USB2_D USB3_D USB3_D
[2]
[3]
[3]
[2]
4
GND
USB2_
CLK
USB2_D USB2_D USB3_D
[4]
[4]
[5]
USB3_
CLK
5
DMA_
DACK[0]/
GPIO[10]
USB2_D
[7]
OVDD
USB3_D USB3_D
[5]
[6]
6
TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ EC_GTX_ TSEC1_ USB2_D
TXD
RXD
RXD
TXD
RXD
COL
[6]
CLK125
[0]
[5]
[4]
[0]
[4]
SD2_ TSEC3_
IMP_CAL TXD
_RX
[2]
USB1_
CLK
AF
TSEC1_
RXD
[6]
USB2_
NXT
USB2_
STP
GND
USB2_
DIR
USB3_
NXT
USB3_D
[7]
7
NC
TSEC_
TSEC1_ TSEC1_ TSEC1_
TSEC3_ TSEC3_ TSEC3_
1588_TRIG TXD
TXD
RXD
TXD
TXD
TXD
_IN[0]
[7]
[5]
[5]
[3]
[5]
[6]
USB2_
PWRFAULT
SPI_
CLK
SDHC_
DAT[4]/SPI
_CS[0]
SPI_
MOSI
USB3_
DIR
USB3_
STP
8
NC
TSEC3_ TSEC3_ TSEC3_
TXD
COL
TX_ER
[4]
SPI_
MISO
GND
Rsvd
9
OVDD
DMA_
DACK[1]/
GPIO[11]
UART_
SOUT
[0]
SDHC_
WP/GPIO
[5]
SDHC_
CMD
10
GND
DMA_
DREQ[1]/
GPIO[15]
UART_
CTS
[0]
OVDD
SDHC_
DAT
[3]
SDHC_
CD/GPIO
[4]
11
NC
TVDD
GND
GND
LVDD
USB2_
TSEC_ TSEC1_ TSEC1_
PCTL1/
GND
1588_
RX_ER
CRS
GPIO[9]
CLK
TSEC_
SDHC_
SDHC_
TSEC_
DMA_
TSEC3_ TSEC3_ 1588_CLK 1588_TRIG EC_
DAT[7]/SPI DREQ[0]/ DAT[5]/SPI
MDC
CRS
TX_CLK
_OUT
_OUT[1]
_CS[3] GPIO[14]
_CS[1]
SDHC_ USB2_
DAT[6]/SPI PCTL0/
_CS[2] GPIO[8]
TSEC_
TSEC_
TSEC_
X2VDD 1588_PULSE 1588_TRIG 1588_PULSE MSRCID
[4]
_OUT[0]
_OUT2
_OUT1
EC_
MDIO
TSEC3_ TSEC3_ MSRCID MSRCID
TXD
RXD
[2]
[0]
[7]
[7]
UART_
CTS
[1]
UART_
SOUT
[1]
UART_
RTS
[0]
UART_
SIN
[0]
UART_
RTS
[1]
GND
UART_
SIN
[1]
SDHC_
DAT
[0]
SDHC_
DAT
[1]
12
DDRCLK
IRQ[10]/
DMA_
DACK[3]
IRQ[9]/
DMA_
DREQ[3]
PCI1_
REQ
[2]
SDHC_
CLK
SDHC_
DAT
[2]
13
PCI1_GNT IRQ[11]/
DMA_
[4]/GPIO
DDONE[3]
[3]
OVDD
PCI1_
GNT
[2]
IIC2_
SDA
SYSCLK
14
X2GND
DMA_
DMA_
DDONE[0]/ DDONE[1]/
GPIO[12] GPIO[13]
GND
VDD_
CORE
TSEC3_
RXD
[6]
MDVAL
MSRCID
[1]
GND
TEST_
SEL
OVDD
VDD_
CORE
GND
VDD_
CORE
GND
MSRCID
[3]
MCP
GND
UDE
DETAIL B
Figure 4. Chip Pin Map Detail B
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
6
Freescale Semiconductor
Pin Assignments and Reset States
DETAIL C
15
MDQ
[26]
MDQ
[31]
GND
GVDD
GND
GVDD
GND
MDIC
[0]
GND
MDIC
[1]
GND
VDD_
CORE
GND
VDD_
CORE
16
MDQ
[30]
MDQS
[3]
MDQ
[19]
MDQ
[23]
MDQ
[18]
GND
LCS
[4]
LCS5/
DMA_
DREQ2
LCS6/
DMA_
DACK2
LA
[28]
VDD_
CORE
GND
VDD_
CORE
GND
17
MDQS
[3]
MDM
[3]
GVDD
GND
MDQS
[2]
MDQ
[22]
LA
[31]
LA
[30]
GND
LA
[29]
GND
VDD_
PLAT
GND
VDD_
PLAT
18
MDQ
[25]
MDQ
[24]
MDQS
[2]
MDM
[2]
GVDD
MDQ
[21]
GND
LGPL3/
LFWP
BVDD
LCS
[0]
LCS7/
DMA_
DDONE2
GND
VDD_
PLAT
GND
19
MDQ
[29]
MDQ
[28]
NC
MDQ
[17]
MDQ
[16]
MDQ
[20]
LCS
[1]
LCS
[2]
BVDD
LGPL5
LA
[27]
VDD_
PLAT
GND
VDD_
PLAT
20
MDQ
[11]
MDQ
[10]
GND
GVDD
GND
BVDD
LGPL2/
LOE/
LFRE
LCS
[3]
LGPL0/
LFCLE
LGPL4/
LGTA/
LGPL1/
LUPWAIT/ XGND
LFALE LPBSE/
LFRB
SD1_TX
[1]
XVDD
21
MDQ
[15]
MDQ
[14]
GVDD
MDQ
[3]
MDQ
[7]
GND
LAD
[31]
LWE[3]/
LBS[3]
BVDD
GND
LAD
[1]
XVDD
SD1_TX
[1]
XGND
22
MDQS
[1]
MDQS
[1]
MDQ
[2]
MDQ
[6]
GVDD
LAD
[29]
LAD
[30]
LWE[1]/
LBS[1]
LWE0/
LBS0/
LFWE
LAD
[0]
LAD
[2]
SD1_TX
[0]
XGND
SD1_TX
[2]
23
MDQ
[9]
MDM
[1]
MDQS
[0]
GND
LAD
[27]
BVDD
LAD
[28]
LWE[2]/
LBS[2]
BVDD
LAD
[3]
BVDD
SD1_TX
[0]
XVDD
SD1_TX
[2]
24
MDQ
[8]
MDQ
[13]
GVDD
MDQS
[0]
LAD
[24]
LAD
[23]
LAD
[26]
LCLK
[0]
LCLK
[1]
LAD
[4]
LAD
[5]
XGND
NC
SGND
25
MDQ
[12]
MDQ
[5]
MDM
[0]
MDQ
[4]
LDP
[3]
LAD
[19]
GND
LCLK
[2]
LBCTL
LAD
[7]
LAD
[6]
NC
SVDD
SD1_RX
[1]
26
MDQ
[0]
MDQ
[1]
LAD
[25]
GND
LAD
[22]
LAD
[18]
LAD
[16]
BVDD
LALE
LDP
[0]
GND
SD1_
IMP_CAL
_RX
SGND
SD1_RX
[1]
27
GND
LDP
[2]
GND
LSYNC_
IN
LAD
[21]
GND
LAD
[15]
LAD
[14]
GND
LAD
[11]
LAD
[9]
SVDD
SD1_RX
[0]
SGND
28
MVREF
GND
AVDD_
LBIU
LSYNC_
OUT
LAD
[20]
LAD
[17]
LDP
[1]
LAD
[13]
LAD
[12]
LAD
[10]
LAD
[8]
SGND
SD1_RX
[0]
SVDD
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Figure 5. Chip Pin Map Detail C
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
7
Pin Assignments and Reset States
DETAIL D
GND
VDD_
CORE
GND
SENSEVDD_
CORE
CLK_
OUT
VDD_
CORE
GND
VDD_
CORE
SENSEVSS
PCI1_
REQ
[1]
PCI1_
GNT
[1]
GND
VDD_
PLAT
GND
VDD_
PLAT
SENSEVDD_
PLAT
VDD_
PLAT
GND
VDD_
PLAT
GND
PCI1_
GNT
[0]
GND
VDD_
PLAT
GND
SD1_TX
[3]
XVDD
SD1_TX
[4]
XGND
SD1_TX
[3]
XGND
SD1_TX
[4]
XVDD
Rsvd
XGND
PCI1_
AD
[31]
PCI1_
AD
[28]
GND
PCI1_REQ
[4]/GPIO
[1]
RTC
HRESET_
REQ
IIC2_
SCL
15
PCI1_
REQ
[0]
OVDD
PCI1_
AD
[26]
OVDD
PCI1_
IDSEL
IRQ
[5]
HRESET
AVDD_
CORE
16
PCI1_
AD
[30]
PCI1_
AD
[29]
PCI1_
AD
[27]
IRQ_
OUT
PCI1_
AD
[24]
PCI1_
AD
[23]
IRQ
[1]
IRQ
[4]
CKSTP_
OUT
17
OVDD
PCI1_
AD
[25]
PCI1_
AD
[22]
OVDD
PCI1_
C_BE
[3]
PCI1_
AD
[20]
PCI1_
AD
[18]
CKSTP_
IN
AVDD_
PLAT
18
IRQ
[7]
GND
PCI1_
AD
[21]
PCI1_
AD
[19]
GND
PCI1_
AD
[17]
IRQ
[3]
SRESET
AVDD_
DDR
19
SD1_TX
[6]
XVDD
L2_
TSTCLK
PCI1_
IRDY
PCI1_
AD
[16]
PCI1_
C_BE
[2]
PCI1_
FRAME
OVDD
ASLEEP
AVDD_
PCI1
20
XVDD
SD1_TX
[6]
XGND
L1_
TSTCLK
PCI1_
PERR
PCI1_
DEVSEL
PCI1_
STOP
GND
PCI1_
TRDY
IIC1_
SCL
TRST
21
XGND
SD1_TX
[5]
XVDD
SD1_TX
[7]
IRQ
[6]
IRQ
[8]
PCI1_
PAR
PCI1_
C_BE
[1]
OVDD
PCI1_
SERR
IRQ
[0]
IIC1_
SDA
22
Rsvd
XVDD
SD1_TX
[5]
XGND
SD1_TX
[7]
XVDD
IRQ
[2]
PCI1_
AD
[13]
GND
PCI1_
AD
[14]
PCI1_
AD
[15]
GND
PCI1_
AD
[11]
23
SVDD
SVDD
SGND
SGND
SVDD
SVDD
SGND
SGND
PCI1_
AD
[5]
PCI1_
AD
[7]
PCI1_
AD
[9]
OVDD
PCI1_
AD
[10]
PCI1_
AD
[12]
24
SGND
SD1_RX
[3]
SVDD
NC
SGND
SD1_RX
[4]
SVDD
SD1_RX
[6]
LSSD_
MODE
OVDD
PCI1_
AD
[1]
PCI1_
AD
[4]
PCI1_
AD
[8]
PCI1_
C_BE
[0]
25
SVDD
SD1_RX
[3]
SGND
SD1_
PLL_
TPA
SVDD
SD1_RX
[4]
SGND
SD1_RX POWER_
[6]
OK
PCI1_
AD
[0]
GND
PCI1_
AD
[2]
PCI1_
AD
[3]
PCI1_
CLK
26
SD1_RX
[2]
SVDD
SD1_
REF_
CLK
AGND_
SRDS
NC
SVDD
SD1_RX
[5]
SGND
SD1_RX
[7]
SVDD
POWER_
EN
OVDD
PCI1_
AD
[6]
TMS
27
SD1_RX
[2]
SGND
SD1_
REF_
CLK
SD1_
PLL_
TPD
AVDD_
SRDS
SGND
SD1_RX
[5]
SVDD
SD1_RX
[7]
SGND
SD1_
IMP_CAL
_TX
TDO
TCK
TDI
28
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
TRIG_
OUT/READY TRIG_IN
/QUIESCE
PCI1_REQ PCI1_GNT
[3]/GPIO [3]/GPIO
[0]
[2]
Figure 6. Chip Pin Map Detail D
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
8
Freescale Semiconductor
Pin Assignments and Reset States
This table provides the pin-out listing for the 783 FC-PBGA package.
3
Table 1. Pinout Listing
Signal
Signal Name
Package Pin Number
Pin Type
Power
Supply
Notes
PCI
PCI1_AD[31:0]
Muxed Address / data
AB15,Y17,AA17,AC15,
AB17,AC16,AA18,
AD17,AE17,AB18,
AB19,AE18,AC19,
AF18,AE19,AC20,
AF23,AE23,AC23,
AH24,AH23,AG24,
AE24,AG25,AD24,
AG27,AC24,AF25,
AG26,AF26,AE25,
AD26
I/O
OVDD
—
PCI1_C_BE[3:0]
Command/Byte Enable
AD18, AD20,AD22,
AH25
I/O
OVDD
29
PCI1_PAR
Parity
AC22
I/O
OVDD
29
PCI1_FRAME
Frame
AE20
I/O
OVDD
2,29
PCI1_TRDY
Target Ready
AF21
I/O
OVDD
2,29
PCI1_IRDY
Initiator Ready
AB20
I/O
OVDD
2,29
PCI1_STOP
Stop
AD21
I/O
OVDD
2,29
PCI1_DEVSEL
Device Select
AC21
I/O
OVDD
2,29
PCI1_IDSEL
Init Device Select
AE16
I
OVDD
29
PCI1_PERR
Parity Error
AB21
I/O
OVDD
2,29
PCI1_SERR
System Error
AF22
I/O
OVDD
2,4,29
PCI1_REQ[4:3]/GPIO[1:0]
Request
AE15,Y15
I
OVDD
—
PCI1_REQ[2:1]
Request
AF13,W16
I
OVDD
29
PCI1_REQ[0]
Request
AA16
I/O
OVDD
29
PCI1_GNT[4:3]/GPIO[3:2]
Grant
AC14, AA15
O
OVDD
PCI1_GNT[2:1]
Grant
AF14,Y16
O
OVDD
5,9,25,29
PCI1_GNT[0]
Grant
W18
I/O
OVDD
29
PCI1_CLK
PCI Clock
AH26
I
OVDD
29
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
9
Pin Assignments and Reset States
Table 1. Pinout Listing (continued)
Signal
Signal Name
Package Pin Number
Pin Type
Power
Supply
Notes
DDR SDRAM Memory Interface
MDQ[0:63]
Data
A26,B26,C22,D21,D25,
B25,D22,E21,A24,A23,
B20,A20,A25,B24,B21,
A21,E19,D19,E16,C16,
F19,F18,F17,D16,B18,
A18,A15,B14,B19,A19,
A16,B15,D1,F3,G1,H2,
E4,G5,H3,J4,B2,C3,F2,
G2,A2,B3,E1,F1,L5,L4,
N3,P3,J3,K4,N4,P4,J1,
K1,P1,R1,J2,K2,P2,R2
I/O
GVDD
—
MECC[0:7]
Error Correcting Code
G12,D14,F11,C11,
G14,F14,C13,D12
I/O
GVDD
—
MAPAR_ERR
Address Parity Error
A13
I
GVDD
—
MAPAR_OUT
Address Parity Out
A6
O
GVDD
—
MDM[0:8]
Data Mask
C25,B23,D18,B17,G4,
C2,L3,L2,F13
O
GVDD
—
MDQS[0:8]
Data Strobe
D24,B22,C18,A17,J5,
C1,M4,M2,E13
I/O
GVDD
—
MDQS[0:8]
Data Strobe
C23,A22,E17,B16,K5,
D2,M3,N1,D13
I/O
GVDD
—
MA[0:15]
Address
B7,G8,C8,A10,D9,C10,
A11,F9,E9,B12,A5,
A12,D11,F7,E10,F10
O
GVDD
—
MBA[0:2]
Bank Select
A4,B5,B13
O
GVDD
—
MWE
Write Enable
B4
O
GVDD
—
MRAS
Row Address Strobe
C5
O
GVDD
—
MCAS
Column Address Strobe
E7
O
GVDD
—
MCS[0:3]
Chip Select
D3,H6,C4,G6
O
GVDD
—
MCKE[0:3]
Clock Enable
H10,K10,G10,H9
O
GVDD
11
MCK[0:5]
Differential Clock 3 Pairs /
DIMM
A9,J11,J6,A8,J13,H8
O
GVDD
—
MCK[0:5]
Differential Clock 3 Pairs /
DIMM
B9,H11,K6,B8,H13,J8
O
GVDD
—
MODT[0:3]
On Die Termination
E5,H7,E6,F6
O
GVDD
—
MDIC[0:1]
Calibration
H15,K15
I/O
GVDD
26
Local Bus Controller Interface
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
10
Freescale Semiconductor
Pin Assignments and Reset States
Table 1. Pinout Listing (continued)
Signal Name
Package Pin Number
Pin Type
Power
Supply
Notes
LAD[0:31]
Muxed data / address
K22,L21,L22,K23,K24,
L24,L25,K25,L28,L27,
K28,K27,J28,H28,H27,
G27,G26,F28,F26,F25,
E28,E27,E26,F24,E24,
C26,G24,E23,G23,F22,
G22,G21
I/O
BVDD
5,9,29
LDP[0:3]
Data parity
K26,G28,B27,E25
I/O
BVDD
29
LA[27]
Burst address
L19
O
BVDD
5,9,29
LA[28:31]
Port address
K16,K17,H17,G17
O
BVDD
5,7,9,29
LCS[0:4]
Chip selects
K18,G19,H19,H20,G16
O
BVDD
29
LCS5/DMA_DREQ2
Chips selects / DMA Request H16
I/O
BVDD
1,29
LCS6/DMA_DACK2
Chips selects / DMA Ack
J16
O
BVDD
1,29
LCS7/DMA_DDONE2
Chips selects / DMA Done
L18
O
BVDD
1,29
LWE0/LBS0/LFWE
Write enable / Byte select
J22
O
BVDD
5,9,29
LWE[1:3]/LBS[1:3]
Write enable / Byte select
H22,H23,H21
O
BVDD
5,9,29
LBCTL
Buffer control
J25
O
BVDD
5,8,9,29
LALE
Address latch enable
J26
O
BVDD
5,8,9,29
LGPL0/LFCLE
UPM general purpose line 0 / J20
FLash command latch enable
O
BVDD
5,9,29
LGPL1/LFALE
UPM general purpose line 1 / K20
Flash address latch enable
O
BVDD
5,9,29
LGPL2/LOE/LFRE
UPM general purpose line 2 / G20
Output enable/Flash read
enable
O
BVDD
5,8,9,29
LGPL3/LFWP
UPM general purpose line 3 / H18
Flash write protect
O
BVDD
5,9,29
LGPL4/LGTA/LUPWAIT
/LPBSE/LFRB
UPM general purpose line 4 / L20
Target Ack/Wait/SDRAM
parity byte select/Flash
Ready-busy
I/O
BVDD
29, 35
LGPL5
UPM general purpose line 5 / K19
Amux
O
BVDD
5,9,29
LCLK[0:2]
Local bus clock
H24,J24,H25
O
BVDD
29
LSYNC_IN
Synchronization
D27
I
BVDD
29
LSYNC_OUT
Local bus DLL
D28
O
BVDD
29
O
OVDD
—
Signal
DMA
DMA_DACK[0:1]
/GPIO[10:11]
DMA Acknowledge
AD6,AE10
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
11
Pin Assignments and Reset States
Table 1. Pinout Listing (continued)
Signal
Signal Name
Package Pin Number
Pin Type
Power
Supply
Notes
DMA_DREQ[0:1]
/GPIO[14:15]
DMA Request
AB10,AD11
I
OVDD
—
DMA_DDONE[0:1]
/GPIO[12:13]
DMA Done
AA11,AB11
O
OVDD
—
DMA_DREQ[2]/LCS[5]
Chips selects / DMA Request H16
I/O
BVDD
1,29
DMA_DACK[2]/LCS[6]
Chips selects / DMA Ack
J16
O
BVDD
1,29
DMA_DDONE[2]/LCS[7]
Chips selects / DMA Done
L18
O
BVDD
1,29
DMA_DREQ[3]/IRQ[9]
External interrupt/DMA
request
AE13
I
OVDD
1
DMA_DACK[3]/IRQ[10]
External interrupt/DMA Ack
AD13
I/O
OVDD
1
DMA_DDONE[3]/IRQ[11]
External interrupt/DMA done AD14
I/O
OVDD
1
I/O
OVDD
—
USB Port 1
USB1_D[7:0]
USB1 Data bits
AF1,AE2,AE1,AD2,
AC2,AC1,AB2,AB1
USB1_NXT
USB1 Next data
AF2
I
OVDD
—
USB1_DIR
USB1 Data Direction
AH1
I
OVDD
—
USB1_STP
USB1 Stop
AG1
O
OVDD
5,9
USB1_PWRFAULT
USB1 bus power fault.
AH2
I
OVDD
—
USB1_PCTL0/GPIO[6]
USB1 Port control 0
AC3
O
OVDD
—
USB1_PCTL1/GPIO[7]
USB1 Port control 1
AC4
O
OVDD
—
USB1_CLK
USB1 bus clock
AD1
I
OVDD
—
I/O
OVDD
—
USB Port 2
USB2_D[7:0]
USB2 Data bits
AE6,AC6,AF5,AE5,
AF4,AE4,AE3,AD3
USB2_NXT
USB2 Next data
AC7
I
OVDD
—
USB2_DIR
USB2 Data Direction
AF7
I
OVDD
—
USB2_STP
USB2 Stop
AD7
O
OVDD
5,9
USB2_PWRFAULT
USB2 bus power fault.
AC8
I
OVDD
—
USB2_PCTL0/GPIO[8]
USB2 Port control 0
AG9
O
OVDD
—
USB2_PCTL1/GPIO[9]
USB2 Port control 1
AC9
O
OVDD
—
USB2_CLK
USB2 bus clock
AD5
I
OVDD
—
—
Reserved
—
AH8
—
—
—
Reserved
—
AH7,AG6,AH6,AG5,
AG4,AH4,AG3,AH3,
AG7, AG8, AH9,AH5
—
—
27
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
12
Freescale Semiconductor
Pin Assignments and Reset States
Table 1. Pinout Listing (continued)
Signal
Signal Name
Package Pin Number
Pin Type
Power
Supply
Notes
Programmable Interrupt Controller
MCP
Machine check processor
Y14
I
OVDD
—
UDE
Unconditional debug event
AB14
I
OVDD
—
IRQ[0:8]
External interrupts
AG22,AF17,AB23,
AF19,AG17,AF16,
AA22,Y19,AB22
I
OVDD
—
IRQ[9]/DMA_DREQ[3]
External interrupt/DMA
request
AE13
I
OVDD
1
IRQ[10]/DMA_DACK[3]
External interrupt/DMA Ack
AD13
I/O
OVDD
1
IRQ[11]/DMA_DDONE[3]
External interrupt/DMA done AD14
I/O
OVDD
1
IRQ_OUT
Interrupt output
O
OVDD
2,4
AC17
Ethernet Management Interface
EC_MDC
Management data clock
Y10
O
OVDD
5,9,22
EC_MDIO
Management data In/Out
Y11
I/O
OVDD
—
I
LVDD
31
Gigabit Reference Clock
EC_GTX_CLK125
Reference clock
AA6
Three-Speed Ethernet Controller (Gigabit Ethernet 1)
TSEC1_TXD[7:0]
Transmit data
AA8,AA5,Y8,Y5,W3,
W5,W4,W6
O
LVDD
5,9,22
TSEC1_TX_EN
Transmit Enable
W1
O
LVDD
23
TSEC1_TX_ER
Transmit Error
AB5
O
LVDD
5,9
TSEC1_TX_CLK
Transmit clock In
AB4
I
LVDD
—
TSEC1_GTX_CLK
Transmit clock Out
W2
O
LVDD
—
TSEC1_CRS
Carrier sense
AA9
I/O
LVDD
17
TSEC1_COL
Collision detect
AB6
I
LVDD
—
TSEC1_RXD[7:0]
Receive data
AB3,AB7,AB8,Y6,AA2,
Y3,Y1,Y2
I
LVDD
—
TSEC1_RX_DV
Receive data valid
AA1
I
LVDD
—
TSEC1_RX_ER
Receive data error
Y9
I
LVDD
—
TSEC1_RX_CLK
Receive clock
AA3
I
LVDD
—
Three-Speed Ethernet Controller (Gigabit Ethernet 3)
TSEC3_TXD[7:0]
Transmit data
T12,V8,U8,V9,T8,T7,
T5,T6
O
TVDD
5,9,22
TSEC3_TX_EN
Transmit Enable
V5
O
TVDD
23
TSEC3_TX_ER
Transmit Error
U9
O
TVDD
5,9
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
13
Pin Assignments and Reset States
Table 1. Pinout Listing (continued)
Signal
Signal Name
Package Pin Number
Pin Type
Power
Supply
Notes
TSEC3_TX_CLK
Transmit clock In
U10
I
TVDD
—
TSEC3_GTX_CLK
Transmit clock Out
U5
O
TVDD
—
TSEC3_CRS
Carrier sense
T10
I/O
TVDD
17
TSEC3_COL
Collision detect
T9
I
TVDD
—
TSEC3_RXD[7:0]
Receive data
U12,U13,U6,V6,V1,U3,
U2,V3
I
TVDD
—
TSEC3_RX_DV
Receive data valid
V2
I
TVDD
—
TSEC3_RX_ER
Receive data error
T4
I
TVDD
—
TSEC3_RX_CLK
Receive clock
U1
I
TVDD
—
IEEE 1588
TSEC_1588_CLK
Clock In
W9
I
LVDD
29
TSEC_1588_TRIG_IN[0:1]
Trigger In
W8,W7
I
LVDD
29
TSEC_1588_TRIG_OUT[0:1] Trigger Out
U11,W10
O
LVDD
5,9,29
TSEC_1588_CLK_OUT
Clock Out
V10
O
LVDD
5,9,29
TSEC_1588_PULSE_OUT1
Pulse Out1
V11
O
LVDD
5,9,29
TSEC_1588_PULSE_OUT2
Pulse Out2
T11
O
LVDD
5,9,29
eSDHC
SDHC_CMD
Command line
AH10
I/O
OVDD
29
SDHC_CD/GPIO[4]
Card detection
AH11
I
OVDD
—
SDHC_DAT[0:3]
Data line
AG12,AH12,AH13,
AG11
I/O
OVDD
29
SDHC_DAT[4:7] /
SPI_CS[0:3]
8-bit MMC Data line / SPI chip AE8,AC10,AF9,AA10
select
I/O
OVDD
29
SDHC_CLK
SD/MMC/SDIO clock
AG13
I/O
OVDD
29
SDHC_WP/GPIO[5]
Card write protection
AG10
I
OVDD
1, 32
eSPI
SPI_MOSI
Master Out Slave In
AF8
I/O
OVDD
29
SPI_MISO
Master In Slave Out
AD9
I
OVDD
29
SPI_CLK
eSPI clock
AD8
I/O
OVDD
29
SPI_CS[0:3] /
SDHC_DAT[4:7]
eSPI chip select / SDHC 8-bit AE8,AC10,AF9,AA10
MMC data
I/O
OVDD
29
DUART
UART_CTS[0:1]
Clear to send
AE11,Y12
I
OVDD
29
UART_RTS[0:1]
Ready to send
AB12,AD12
O
OVDD
29
UART_SIN[0:1]
Receive data
AC12,AF12
I
OVDD
29
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
14
Freescale Semiconductor
Pin Assignments and Reset States
Table 1. Pinout Listing (continued)
Signal
Signal Name
UART_SOUT[0:1]
Transmit data
Package Pin Number
AF10,AA12
Pin Type
Power
Supply
O
OVDD
5,9,22,
10,29
Notes
I2C interface
IIC1_SCL
Serial clock
AG21
I/O
OVDD
4,21,29
IIC1_SDA
Serial data
AH22
I/O
OVDD
4,21,29
IIC2_SCL
Serial clock
AH15
I/O
OVDD
4,21,29
IIC2_SDA
Serial data
AG14
I/O
OVDD
4,21,29
SerDes1(x4)
SD1_TX[7:4]
Transmit Data (+)
Y23,W21,V23,U21
O
XVDD
—
SD1_TX[7:4]
Transmit Data(-)
Y22,W20,V22,U20
O
XVDD
—
SD1_RX[7:4]
Receive Data(+)
AC28,AB26,AA28,Y26
I
XVDD
—
SD1_RX[7:4]
Receive Data(–)
AC27,AB25,AA27,Y25
I
XVDD
—
Reserved
—
R21,P23,N21,M23,
R20,P22,N20,M22
—
—
18
Reserved
—
T26,R28,P26,N28,
T25,R27,P25,N27
—
—
33
SD1_PLL_TPD
PLL test point Digital
V28
O
XVDD
18
SD1_REF_CLK
PLL Reference clock
U28
I
XVDD
—
SD1_REF_CLK
PLL Reference clock
complement
U27
I
XVDD
—
T22
—
—
18
T23
—
—
18
Reserved
—
Reserved
—
SerDes2(x1)
SD2_TX[0]
Transmit data(+)
P11
O
X2VDD
—
SD2_TX[0]
Transmit data(-)
P12
O
X2VDD
—
SD2_RX[0]
Receive data(+)
P6
I
X2VDD
—
SD2_RX[0]
Receive data(-)
P7
I
X2VDD
—
Reserved
—
M11,M12
—
—
18
Reserved
—
N8, N9
—
—
34
SD2_PLL_TPD
PLL test point Digital
L7
O
X2VDD
18
SD2_REF_CLK
PLL Reference clock
M6
I
X2VDD
—
SD2_REF_CLK
PLL Reference clock
complement
M7
I
X2VDD
—
Reserved
—
L8
—
X2VDD
18
Reserved
—
L9
—
X2VDD
18
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
15
Pin Assignments and Reset States
Table 1. Pinout Listing (continued)
Signal
Signal Name
Package Pin Number
Pin Type
Power
Supply
Notes
General-Purpose Input/Output
GPIO[0:1]/PCI1_REQ[3:4]
GPIO/PCI request
Y15,AE15
I/O
OVDD
—
GPIO[2:3]/PCI1_GNT[3:4]
GPIO/PCI grant
AA15,AC14
I/O
OVDD
—
GPIO[4]/SDHC_CD
GPIO/SDHC card detection
AH11
I/O
OVDD
—
GPIO[5]/SDHC_WP
GPIO/SDHC write protection AG10
I/O
OVDD
32
GPIO[6]/USB1_PCTL0
GPIO/USB1 PCTL0
AC3
I/O
OVDD
—
GPIO[7]/USB1_PCTL1
GPIO/USB1 PCTL1
AC4
I/O
OVDD
—
GPIO[8]/USB2_PCTL0
GPIO/USB2 PCTL0
AG9
I/O
OVDD
—
GPIO[9]/USB2_PCTL1
GPIO/USB2 PCTL1
AC9
I/O
OVDD
—
GPIO[10:11]
/DMA_DACK[0:1]
GPIO/DMA Ack
AD6,AE10
I/O
OVDD
—
GPIO[12:13]
/DMA_DDONE[0:1]
GPIO/DMA done
AA11,AB11
I/O
OVDD
—
GPIO[14:15]
/DMA_DREQ[0:1]
GPIO/DMA request
AB10,AD11
I/O
OVDD
—
System Control
HRESET
Hard reset
AG16
I
OVDD
—
HRESET_REQ
Hard reset - request
AG15
O
OVDD
22
SRESET
Soft reset
AG19
I
OVDD
—
CKSTP_IN
CheckStop in
AG18
I
OVDD
—
CKSTP_OUT
CheckStop Output
AH17
O
OVDD
2,4
Debug
TRIG_IN
Trigger in
W19
I
OVDD
—
TRIG_OUT/READY
/QUIESCE
Trigger out/Ready/Quiesce
V19
O
OVDD
22
MSRCID[0:1]
Memory debug source port ID W12,W13
O
OVDD
6,9
MSRCID[2:4]
Memory debug source port ID V12, W14,W11
O
OVDD
6,9,22
MDVAL
Memory debug data valid
V13
O
OVDD
6,22
CLK_OUT
Clock Out
W15
O
OVDD
11
Clock
RTC
Real time clock
AF15
I
OVDD
—
SYSCLK
System clock / PCI clock
AH14
I
OVDD
—
DDRCLK
DDR clock
AC13
I
OVDD
30
JTAG
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
16
Freescale Semiconductor
Pin Assignments and Reset States
Table 1. Pinout Listing (continued)
Signal
Signal Name
Package Pin Number
Pin Type
Power
Supply
Notes
TCK
Test clock
AG28
I
OVDD
—
TDI
Test data in
AH28
I
OVDD
12
TDO
Test data out
AF28
O
OVDD
11
TMS
Test mode select
AH27
I
OVDD
12
TRST
Test reset
AH21
I
OVDD
12
DFT
L1_TSTCLK
L1 test clock
AA21
I
OVDD
19
L2_TSTCLK
L2 test clock
AA20
I
OVDD
19
LSSD_MODE
LSSD Mode
AC25
I
OVDD
19
TEST_SEL
Test select
AA13
I
OVDD
19
Power Management
ASLEEP
Asleep
AG20
O
OVDD
9,16,22
POWER_OK
Power OK
AC26
I
OVDD
—
POWER_EN
Power enable
AE27
O
OVDD
—
—
OVDD
—
Power and Ground Signals
OVDD
General I/O supply
Y18,AG2,AD4,AB16,
AF6,AC18,AB13,AD10,
AE14,AD16,AD25,
AF27,AE22,AF11,
AF20,AF24
LVDD
GMAC 1 I/O supply
AA7, AA4
Power for
TSEC1
interfaces
LVDD
—
TVDD
GMAC 3 I/O supply
V4,U7
Power for
TSEC3
interfaces
TVDD
—
GVDD
SSTL2 DDR supply
B1,B11,C7,C9,C14,
C17,D4,D6,R3,D15,E2,
E8,C24,E18,F5,E14,
C21,G3,G7,G9,G11,
H5,H12,E22,F15,J10,
K3,K12,K14,H14,D20,
E11,M1,N5
Power for
DDR
DRAM I/O
GVDD
—
BVDD
Local bus I/O supply
L23,J18,J23,J19,F20,
F23,H26,J21
Power for
Local Bus
BVDD
—
SVDD
SerDes 1 core logic supply
M27,N25,P28,R24,
R26,T24,T27,U25,
W24,W26,Y24,Y27,
AA25,AB28,AD27
—
SVDD
—
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
17
Pin Assignments and Reset States
Table 1. Pinout Listing (continued)
Signal
Signal Name
Package Pin Number
Pin Type
Power
Supply
Notes
XVDD
SerDes 1 transceiver supply
M21,N23,P20,R22,T20,
U23,V21,W22,Y20,
AA23
—
XVDD
—
S2VDD
SerDes 2 core logic supply
R6,N7,M9
—
S2VDD
—
X2VDD
SerDes 2 transceiver supply
R11,N12,L11
—
X2VDD
—
VDD_CORE
Core, L2 logic supply
P13,U16,L16,M15,N14,
R14,P15,N16,M13,
U14,T13,L14,T15,R16,
K13
—
VDD_CORE
—
VDD_PLAT
Platform logic supply
T19,T17,V17,U18,R18,
N18,M19,P19,P17,M17
—
VDD_PLAT
—
AVDD_CORE
CPU PLL supply
AH16
—
AVDD_CORE
20,28
AVDD_PLAT
Platform PLL supply
AH18
—
AVDD_PLAT
20
AVDD_DDR
DDR PLL supply
AH19
—
AVDD_DDR
20
AVDD_LBIU
Local Bus PLL supply
C28
—
AVDD_LBIU
20
AVDD_PCI1
PCI PLL supply
AH20
—
AVDD_PCI1
20
AVDD_SRDS
SerDes 1 PLL supply
W28
—
AVDD_SRDS
20
AVDD_SRDS2
SerDes 2 PLL supply
T1
—
AVDD_SRDS2
20
SENSEVDD_CORE
—
V15
—
VDD_CORE
13
SENSEVDD_PLAT
—
W17
—
VDD_PLAT
13
GND
Ground
D5,AE7,F4,D26,D23,
C12,C15,E20,D8,B10,
AF3,E3,J14,K21,F8,A3,
F16,E12,E15,D17,L1,
F21,H1,G13,G15,G18,
C6,A14,A7,G25,H4,
C20,J12,J15,J17,F27,
M5,J27,K11,L26,K7,
K8,T14,V14,M16,M18,
P14,N15,N17,N19,N2,
P5,P16,P18,M14,R15,
R17,R19,T16,T18,L17,
U15,U17,U19,V18,C27,
Y13,AE26,AA19,AE21,
B28,AC11,AD19,AD23,
L15,AD15,AG23,AE9,
A27,V7,Y7,AC5,U4,Y4,
AE12,AB9,AA14,N13,
R13,L13
—
—
—
XGND
SerDes 1Transceiver pad
GND (xpadvss)
M20,M24,N22,P21,
R23,T21,U22,V20,
W23, Y21
—
—
—
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
18
Freescale Semiconductor
Pin Assignments and Reset States
Table 1. Pinout Listing (continued)
Signal
Signal Name
Package Pin Number
Pin Type
Power
Supply
Notes
SGND
SerDes 1 Transceiver core
logic GND (xcorevss)
M28,N26,P24,P27,
R25,T28,U24,U26,V24,
W25,Y28,AA24,AA26,
AB24,AB27,AD28
—
—
—
X2GND
SerDes 2 Transceiver pad
GND (xpadvss)
R12,M10,N11,L12
—
—
—
S2GND
SerDes 2 Transceiver core
logic GND (xcorevss)
P8,P9,N6,M8
—
—
—
AGND_SRDS
SerDes 1 PLL GND
V27
—
—
—
AGND_SRDS2
SerDes 2 PLL GND
T2
—
—
—
SENSEVSS
GND Sensing
V16
—
—
13
Analog Signals
MVREF
SSTL2 reference voltage
A28
Reference
voltage for
DDR
GVDD/2
—
SD1_IMP_CAL_RX
Rx impedance calibration
M26
—
200Ω (±1%)
to GND
—
SD1_IMP_CAL_TX
Tx impedance calibration
AE28
—
100Ω (±1%)
to GND
—
SD1_PLL_TPA
PLL test point analog
V26
—
AVDD_SRD
S analog
18
SD2_IMP_CAL_RX
Rx impedance calibration
R7
—
200Ω (±1%)
to GND
—
SD2_IMP_CAL_TX
Tx impedance calibration
L6
—
100Ω (±1%)
to GND
—
SD2_PLL_TPA
PLL test point analog
T3
—
AVDD_SRD
S2 analog
18
Reserved
—
R4
—
—
—
Reserved
—
R5
—
—
—
—
—
—
No Connect Pins
NC
—
C19,D7,D10,L10,R10,
B6,F12,J7,P10,M25,
W27,N24,N10,R8,J9,
K9,V25,R9
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
19
Pin Assignments and Reset States
Table 1. Pinout Listing (continued)
Signal
Signal Name
Package Pin Number
Pin Type
Power
Supply
Notes
Notes:
1. All multiplexed signals may be listed only once and may not re-occur.
2. Recommend a weak pull-up resistor (2–10 KΩ) be placed on this pin to OVDD.
3. This pin must always be pulled-high.
4. This pin is an open drain signal.
5. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the
reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ pull-down resistor. However, if
the signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net
at reset, then a pullup or active driver is needed.
6. Treat these pins as no connects (NC) unless using debug address functionality.
7. The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-kΩ pull-up or pull-down
resistors. See Section 22.2, “CCB/SYSCLK PLL Ratio.”
8. The value of LALE, LGPL2 and LBCTL at reset set the e500 core clock to CCB Clock PLL ratio. These pins require 4.7-kΩ
pull-up or pull-down resistors. See the Section 22.3, “e500 Core PLL Ratio.”
9. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or
because it has other manufacturing test functions. This pin will therefore be described as an I/O for boundary scan.
10.For proper state of these signals during reset, UART_SOUT[1] must be pulled down to GND through a resistor.
UART_SOUT[0] can be pulled up or left without a resistor. However, if there is any device on the net which might pull down
the value of the net at reset, then a pullup is needed on UART_SOUT[0].
11.This output is actively driven during reset rather than being three-stated during reset.
12.These JTAG pins have weak internal pull-up P-FETs that are always enabled.
13.These pins are connected to the VDD_CORE/VDD_PLAT/GND planes internally and may be used by the core power supply to
improve tracking and regulation.
15. These pins have other manufacturing or debug test functions. It’s recommended to add both pull-up resistor pads to OVDD
and pull-down resistor pads to GND on board to support future debug testing when needed.
16. If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe
state during reset.
17. This pin is only an output in FIFO mode when used as Rx Flow Control.
18. Do not connect.
19.These must be pulled up (100 Ω- 1 kΩ) to OVDD.
20. Independent supplies derived from board VDD.
21. Recommend a pull-up resistor (1 KΩ) be placed on this pin to OVDD.
22. The following pins must NOT be pulled down during power-on reset: MDVAL, UART_SOUT[0], EC_MDC, TSEC1_TXD[3],
TSEC3_TXD[7], HRESET_REQ, TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP.
23. This pin requires an external 4.7-kΩ pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is
actively driven.
24. General-Purpose POR configuration of user system.
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
20
Freescale Semiconductor
Electrical Characteristics
Table 1. Pinout Listing (continued)
Signal
Signal Name
Package Pin Number
Pin Type
Power
Supply
Notes
25. When a PCI block is disabled, either the POR config pin that selects between internal and external arbiter must be pulled
down to select external arbiter if there is any other PCI device connected on the PCI bus, or leave the address pins as “No
Connect” or terminated through 2–10 KΩ pull-up resistors with the default of internal arbiter if the address pins are not
connected to any other PCI device. The PCI block will drive the address pins if it is configured to be the PCI arbiter—through
POR config pins—irrespective of whether it is disabled via the DEVDISR register or not. It may cause contention if there is
any other PCI device connected on the bus.
26. When operating in DDR2 mode, connect MDIC[0] to ground through an 18.2-Ω (full-strength mode) or 36.4-Ω (half-strength
mode) precision 1% resistor, and connect MDIC[1] to GVDD through an 18.2-Ω (full-strength mode) or 36.4-Ω (half-strength
mode) precision 1% resistor. When operating in DDR3 mode, connect MDIC[0] to ground through an 20-Ω (full-strength
mode) or 40-Ω (half-strength mode) precision 1% resistor, and connect MDIC[1] to GVDD through an 20-Ω (full-strength
mode) or 40-Ω (half-strength mode) precision 1% resistor. These pins are used for automatic calibration of the DDR IOs.
27. Connect to GND through a pull down 1 kΩ resistor.
28. It must be the same as VDD_CORE
29. The output pads are tristated and the receivers of pad inputs are disabled during the Deep Sleep state when
GCR[DEEPSLEEP_Z] =1.
30. DDRCLK input is only required when the DDR controller is running in asynchronous mode. When the DDR controller is
configured to run in synchronous mode via POR setting cfg_ddr_pll[0:2]=111, the DDRCLK input is not required. It is
recommended to tie it off to GND when DDR controller is running in synchronous mode. See the MPC8536E PowerQUICC
III Integrated Host Processor Family Reference Manual , Table 4-3 in section 4.2.2 “Clock Signals”, section 4.4.3.2 “DDR
PLL Ratio” and Table 4-10 “DDR Complex Clock PLL Ratio” for more detailed description regarding DDR controller
operation in asynchronous and synchronous modes.
31. EC_GTX_CLK125 is a 125-MHz input clock shared among all eTSEC ports in the following modes: GMII, TBI, RGMII and
RTBI. If none of the eTSEC ports is operating in these modes, the EC_GTX_CLK125 input can be tied off to GND.
32. SDHC_WP is active low signal, which follows SDHC Host controller specification. However, it is reversed polarity for
SD/MMC card specification.
33. Must connect to XGND.
34. Must connect to X2GND
35. For systems which boot from Local Bus(GPCM)-controlled NOR flash or (FCM) controlled NAND flash, a pullup on LGPL4
is required.
2
Electrical Characteristics
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
21
Electrical Characteristics
2.1.1
Absolute Maximum Ratings
This table provides the absolute maximum ratings.
Table 2. Absolute Maximum Ratings1
Characteristic
Symbol
Max Value
Core supply voltage
VDD_CORE
–0.3 to 1.21
V
—
Platform supply voltage
VDD_PLAT
–0.3 to 1.1
V
—
PLL core supply voltage
AVDD_CORE
–0.3 to 1.21
V
—
PLL other supply voltage
AVDD
–0.3 to 1.1
V
—
Core power supply for SerDes transceivers
SVDD, S2VDD
–0.3 to 1.1
V
—
Pad power supply for SerDes transceivers and PCI Express
XVDD, X2VDD
–0.3 to 1.1
V
—
GVDD
–0.3 to 1.98
V
—
DDR SDRAM
Controller I/O
supply voltage
DDR2 SDRAM Interface
DDR3 SDRAM Interface
Three-speed Ethernet I/O
Unit Notes
–0.3 to 1.65
LVDD (eTSEC1)
–0.3 to 3.63
–0.3 to 2.75
V
2
TVDD (eTSEC3)
–0.3 to 3.63
–0.3 to 2.75
V
2
PCI, DUART, system control and power management, I2C, USB,
eSDHC, eSPI and JTAG I/O voltage, MII management voltage
OVDD
–0.3 to 3.63
V
—
Local bus I/O voltage
BVDD
–0.3 to 3.63
–0.3 to 2.75
–0.3 to 1.98
V
—
Input voltage
MVIN
–0.3 to (GVDD + 0.3)
V
3
DDR2/DDR3 DRAM reference
MVREF
–0.3 to (GVDD + 0.3)
V
—
Three-speed Ethernet signals
LVIN
TVIN
–0.3 to (LVDD + 0.3)
–0.3 to (TVDD + 0.3)
V
3
Local bus signals
BVIN
–0.3 to (BVDD + 0.3)
—
—
PCI, DUART, SYSCLK, system control and
power management, I2C, and JTAG signals
OVIN
–0.3 to (OVDD + 0.3)
V
3
TSTG
–55 to 150
0C
—
DDR2/DDR3 DRAM signals
Storage temperature range
Notes:
1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect chip reliability or cause
permanent damage to the chip.
2. The 3.63-V maximum is only supported when the port is configured in GMII, MII, RMII or TBI modes; otherwise the 2.75V
maximum applies. See Section 2.9.2, “FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications,” for details on
the recommended operating conditions per protocol.
3. (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 7.
2.1.2
Recommended Operating Conditions
This table provides the recommended operating conditions for this chip. Note that the values in this table are the recommended
and tested operating conditions. Proper chip operation outside these conditions is not guaranteed.
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
22
Freescale Semiconductor
Electrical Characteristics
Table 3. Recommended Operating Conditions
Characteristic
Symbol
Recommended Value Unit Notes
Core supply voltage
VDD_CORE
1.0 ± 50 mV
V
—
Platform supply voltage
VDD_PLAT
1.0 ± 50 mV
V
—
PLL core supply voltage
AVDD_CORE
1.0 ± 50 mV
V
2
PLL other supply voltage
AVDD
1.0 ± 50 mV
V
2
Core power supply for SerDes transceivers
SVDD
1.0 ± 50 mV
V
—
Pad power supply for SerDes transceivers and PCI Express
XVDD
1.0 ± 50 mV
V
—
DDR SDRAM
DDR2 SDRAM Interface
Controller I/O supply
DDR3 SDRAM Interface
voltage
GVDD
1.8 V ± 90 mV
V
3
V
5
1.5 V ± 75 mV
LVDD
(eTSEC1)
3.3 V ± 165 mV
2.5 V ± 125 mV
TVDD
(eTSEC3)
3.3 V ± 165 mV
2.5 V ± 125 mV
PCI, DUART, system control and power management, I2C, USB, eSDHC,
eSPI and JTAG I/O voltage, MII management voltage
OVDD
3.3 V ± 165 mV
V
4
Local bus I/O voltage
BVDD
3.3 V ± 165 mV
2.5 V ± 125 mV
1.8 V ± 90 mV
V
—
MVIN
GND to GVDD
V
3
MVREF
GVDD/2 ± 1%
V
—
Three-speed Ethernet signals
LVIN
TVIN
GND to LVDD
GND to TVDD
V
5
Local bus signals
BVIN
GND to BVDD
V
—
PCI, Local bus, DUART, SYSCLK, system control
and power management, I2C, and JTAG signals
OVIN
GND to OVDD
V
4
°C
6
Three-speed Ethernet I/O voltage
Input voltage
DDR2 and DDR3 SDRAM Interface signals
DDR2 and DDR3 SDRAM Interface reference
Operating
Temperature range
Commercial
TA= 0 (min) to
TJ= 90(max)
Industrial
standard temperature range
Extended temperature range
TA
TJ
TA= 0 (min) to
TJ= 105 (max)
TA= -40 (min) to
TJ= 105 (max)
Notes:
2. This voltage is the input to the filter discussed in Section 3.2.1, “PLL Power Supply Filtering,” and not necessarily the voltage
at the AVDD pin, which may be reduced from VDD by the filter.
3. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
4. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
5. Caution: L/TVIN must not exceed L/TVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
6. Minimum temperature is specified with TA; maximum temperature is specified with TJ.
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
23
Electrical Characteristics
This figure shows the undershoot and overshoot voltages at the interfaces of the chip.
B/G/L/OVDD + 20%
B/G/L/OVDD + 5%
B/G/L/OVDD
VIH
GND
GND – 0.3 V
VIL
GND – 0.7 V
Not to Exceed 10%
of tCLOCK1
Note:
1. tCLOCK refers to the clock period associated with the respective interface:
For I2C and JTAG, tCLOCK references SYSCLK.
For DDR, tCLOCK references MCLK.
For eTSEC, tCLOCK references EC_GTX_CLK125.
For eLBC, tCLOCK references LCLK.
For PCI, tCLOCK references PCI1_CLK or SYSCLK.
2. With the PCI overshoot allowed (as specified above), the device
does not fully comply with the maximum AC ratings and device protection
guideline outlined in the PCI rev. 2.2 standard (section 4.2.2.3).
Figure 7. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD
The core voltage must always be provided at nominal 1.0 V . (See Table 3 for actual recommended core voltage). Voltage to the
processor interface I/Os are provided through separate sets of supply pins and must be provided at the voltages shown in Table 3.
The input voltage threshold scales with respect to the associated I/O supply voltage. OVDD and LVDD based receivers are simple
CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR2 and DDR3 SDRAM interface uses
differential receivers referenced by the externally supplied MVREFn signal (nominally set to GVDD/2) as is appropriate for the
SSTL_1.8 electrical signaling standard for DDR2 or 1.5-V electrical signaling for DDR3. The DDR DQS receivers cannot be
operated in single-ended fashion. The complement signal must be properly driven and cannot be grounded.
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
24
Freescale Semiconductor
Electrical Characteristics
2.1.3
Output Driver Characteristics
This table provides information on the characteristics of the output driver strengths. The values are preliminary estimates.
Table 4. Output Drive Capability
Driver Type
Local bus interface utilities signals
PCI signals
Programmable
Output Impedance
(Ω)
Supply
Voltage
25
35
BVDD = 3.3 V
BVDD = 2.5 V
45(default)
45(default)
125
BVDD = 3.3 V
BVDD = 2.5 V
BVDD = 1.8 V
25
OVDD = 3.3 V
2
Notes
1
42 (default)
DDR2 signal
16
32 (half strength mode)
GVDD = 1.8 V
3
DDR3 signal
20
40 (half strength mode)
GVDD = 1.5 V
2
TSEC signals
42
LVDD = 2.5/3.3 V
—
DUART, system control, JTAG
42
OVDD = 3.3 V
—
I2C
150
OVDD = 3.3 V
—
Notes:
1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR.
2. The drive strength of the PCI interface is determined by the setting of the PCI1_GNT1 signal at reset.
3. The drive strength of the DDR2 or DDR3 interface in half-strength mode is at Tj = 105°C and at GVDD (min)
2.2
Power Sequencing
The chip requires its power rails to be applied in a specific sequence in order to ensure proper chip operation. These
requirements are as follows for power up:
1.
2.
3.
VDD_PLAT, VDD_CORE (if POWER_EN is not used to control VDD_CORE), AVDD, BVDD, LVDD, OVDD,
SVDD,S2VDD, TVDD, XVDD and X2VDD
[Wait for POWER_EN to assert], then VDD_CORE (if POWER_EN is used to control VDD_CORE)
GVDD
All supplies must be at their stable values within 50 ms.
Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered
sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step
reach 10% of theirs.
In order to guarantee MCKE low during power-up, the above sequencing for GVDD is required. If there is no concern about any
of the DDR signals being in an indeterminate state during power-up, then the sequencing for GVDD is not required.
From a system standpoint, if any of the I/O power supplies ramp prior to the VDD platform supply, the I/Os associated with
that I/O supply may drive a logic one or zero during power-up, and extra current may be drawn by the chip.
During the Deep Sleep state, the VDD core supply is removed. But all other power supplies remain applied. Therefore, there is
no requirement to apply the VDD core supply before any other power rails when the silicon waking from Deep Sleep.
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
25
Electrical Characteristics
2.3
Power Characteristics
The estimated power dissipation for the core complex bus (CCB) versus the core frequency for this family of PowerQUICC III
chips is shown in the following table.
Table 5. Power Dissipation 5
Core
CCB
DDR
VDD
Frequen Frequen Frequen Platfor
Power Mode
m
cy
cy
cy
VDD
Core
Junction
Tempera
ture
(V)
(°C)
mean7
Max
mean7
Max
105
/90
—
4.1/3.3
—
4.7/3.7
1, 3, 8
—
3.7/2.9
—
4.7/3.7
1, 4, 8
1.5
—
1.5
—
1, 2
1.2
1.9
1.4
1.9
1
Nap (W)
0.8
1.5
1.4
1.9
1
Sleep (W)
0.8
1.5
1.0
1.6
1
(MHz)
(MHz)
(MHz)
(V)
Maximum (A)
Thermal (W)
Typical (W)
Doze (W)
600
400
400
1.0
1.0
65
Core Power
Platform Power9
Notes
Deep Sleep
(W)
35
0
0
0.6
1.1
6
Maximum (A)
105
/ 90
—
4.5/3.7
—
4.7/3.7
1, 3, 8
—
3.9/3.1
—
4.7/3.7
1, 4, 8
1.7
—
1.5
—
1, 2
1.3
2.1
1.4
1.9
1
Nap (W)
0.8
1.5
1.4
1.9
1
Sleep (W)
0.8
1.5
1.0
1.6
1
Thermal (W)
Typical (W)
Doze (W)
800
400
400
1.0
1.0
65
Deep Sleep
(W)
35
0
0
0.6
1.1
1,6
Maximum (A)
105
/ 90
—
4.8/4.0
—
4.7/3.7
1, 3, 8
—
4.1/3.3
—
4.7/3.7
1, 4, 8
1.9
—
1.5
—
1, 2
1.4
2.2
1.4
1.9
1
Nap (W)
0.8
1.6
1.4
1.9
1
Sleep (W)
0.8
1.6
1.0
1.6
1
0
0
0.6
1.1
1, 6
Thermal (W)
Typical (W)
Doze (W)
Deep Sleep
(W)
1000
400
400
1.0
1.0
65
35
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
26
Freescale Semiconductor
Electrical Characteristics
Table 5. Power Dissipation (continued)5
Core
CCB
DDR
VDD
Frequen Frequen Frequen Platfor
Power Mode
m
cy
cy
cy
VDD
Core
Junction
Tempera
ture
Platform Power9
Notes
(MHz)
(MHz)
(MHz)
(V)
(V)
(°C)
mean7
Max
mean7
Max
5.3/4.4
—
5.0/4.0
1, 3, 8
500
500
1.0
1.0
105
/ 90
—
1250
—
4.4/3.6
—
5.0/4.0
1, 4, 8
65
2.2
Maximum (A)
Thermal (W)
Core Power
Typical (W)
1.7
1
Doze (W)
1.6
2.4
1.5
2.1
1
Nap (W)
0.8
1.6
1.5
2.1
1
Sleep (W)
0.8
1.6
1.1
1.7
1
0
0
0.6
1.2
1, 6
Deep Sleep
(W)
35
Notes:
1. These values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and
configurations. The values do not include power dissipation for I/O supplies.
2. Typical power is an average value measured at the nominal recommended core voltage (VDD) and 65°C junction temperature
(see Table 3) while running the Dhrystone benchmark.
3. Maximum power is the maximum power measured with the worst process and recommended core and platform voltage (VDD)
at maximum operating junction temperature (see Table 3) while running a smoke test which includes an entirely
L1-cache-resident, contrived sequence of instructions which keep the execution unit maximally busy.
4. Thermal power is the maximum power measured with worst case process and recommended core and platform voltage (VDD)
at maximum operating junction temperature (see Table 3) while running the Dhrystone benchmark.
6. Maximum power is the maximum number measured with USB1, eTSEC1, and DDR blocks enabled. The Mean power is the
mean power measured with only external interrupts enabled and DDR in self refresh.
7. Mean power is provided for information purposes only and is the mean power consumed by a statistically significant range of
devices.
8. Maximum operating junction temperature (see Table 3) for Commercial Tier is 90 0C, for Industrial Tier is 105 0C.
9. Platform power is the power supplied to all the VDD_PLAT pins.
See Section 2.23.6.1, “SYSCLK to Platform Frequency Options,” for the full range of CCB frequencies that the chip supports.
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
27
Electrical Characteristics
2.4
Input Clocks
2.4.1
System Clock Timing
This table provides the system clock (SYSCLK) AC timing specifications for the chip.
Table 6. SYSCLK AC Timing Specifications
At recommended operating conditions (see Table 2) with OVDD = 3.3 V ± 165 mV.
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
SYSCLK frequency
fSYSCLK
33
—
133
MHz
1
SYSCLK cycle time
tSYSCLK
7.5
—
30
ns
—
SYSCLK rise and fall time
tKH, tKL
0.6
1.0
2.1
ns
2
tKHK/tSYSCLK
40
—
60
%
—
—
—
—
+/-150
ps
3, 4
SYSCLK duty cycle
SYSCLK jitter
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum
operating frequencies. See Section 2.23.2, “CCB/SYSCLK PLL Ratio,” and Section 2.23.3, “e500 Core PLL Ratio,” for ratio
settings.
2. Rise and fall times for SYSCLK are measured at 0.6 V and 2.7 V.
3. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to allow
cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter.
4. For spread spectrum clocking, guidelines are +0% to -1% down spread at a modulation rate between 20 KHz and 60 KHz on
SYSCLK.
2.4.2
PCI Clock Timing
When the PCI controller is configured for asynchronous operation, the reference clock for the PCI controller is not the SYSCLK
input, but instead the PCI_CLK. This table provides the PCI reference clock AC timing specifications for the chip.
Table 7. PCICLK AC Timing Specifications
At recommended operating conditions (see Table 2) with OVDD = 3.3 V ± 165 mV.
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
PCICLK frequency
fPCICLK
33
—
66
MHz
—
PCICLK cycle time
tPCICLK
15
—
30
ns
—
PCICLK rise and fall time
tKH, tKL
0.6
1.0
2.1
ns
1
tKHK/tPCICLK
40
—
60
%
—
PCICLK duty cycle
Notes:
1. Rise and fall times for PCICLK are measured at 0.6 V and 2.7 V.
2.4.3
Real Time Clock Timing
The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then used as an input to the
counters of the PIC and the TimeBase unit of the e500. There is no jitter specification. The minimum pulse width of the RTC
signal should be greater than 2x the period of the CCB clock. That is, minimum clock high time is 2 × tCCB, and minimum clock
low time is 2 × tCCB. There is no minimum RTC frequency; RTC may be grounded if not needed.
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
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Freescale Semiconductor
Electrical Characteristics
2.4.4
eTSEC Gigabit Reference Clock Timing
This table provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications for the chip.
Table 8. EC_GTX_CLK125 AC Timing Specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
EC_GTX_CLK125 frequency
fG125
—
125
—
MHz
—
EC_GTX_CLK125 cycle time
tG125
—
8
—
ns
—
EC_GTX_CLK rise and fall time
LVDD, TVDD = 2.5V
LVDD, TVDD = 3.3V
tG125R/tG125F
—
—
ns
1
EC_GTX_CLK125 duty cycle
tG125H/tG125
%
2
0.75
1.0
GMII, TBI
1000Base-T for RGMII, RTBI
—
45
47
55
53
Notes:
1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5V and 2.0V for L/TVDD=2.5V, and from 0.6 and 2.7V for
L/TVDD=3.3V at 0.6 V and 2.7 V.
2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. EC_GTX_CLK125
duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC
GTX_CLK. See Section 2.9.2.6, “RGMII and RTBI AC Timing Specifications,” for duty cycle for 10Base-T and 100Base-T
reference clock.
2.4.5
DDR Clock Timing
This table provides the DDR clock (DDRCLK) AC timing specifications for the chip.
Table 9. DDRCLK AC Timing Specifications
At recommended operating conditions with OVDD of 3.3V ± 5%.
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
DDRCLK frequency
fDDRCLK
66
—
166
MHz
1
DDRCLK cycle time
tDDRCLK
6.0
—
15.15
ns
—
DDRCLK rise and fall time
tKH, tKL
0.6
1.0
1.2
ns
2
tKHK/tDDRCLK
40
—
60
%
—
—
—
—
+/– 150
ps
3, 4
DDRCLK duty cycle
DDRCLK jitter
Notes:
1. Caution: The DDR complex clock to DDRCLK ratio settings must be chosen such that the resulting DDR complex
clock frequency does not exceed the maximum or minimum operating frequencies. See Section 2.23.4,
“DDR/DDRCLK PLL Ratio,” for ratio settings.
2. Rise and fall times for DDRCLK are measured at 0.6 V and 2.7 V.
3. The DDRCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to
allow cascade-connected PLL-based devices to track DDRCLK drivers with the specified jitter.
4. For spread spectrum clocking, guidelines are +0% to –1% down spread at a modulation rate between 20 kHz and
60 kHz on DDRCLK.
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
29
Electrical Characteristics
2.4.6
Platform to FIFO Restrictions
Please note the following FIFO maximum speed restrictions based on platform speed. The “platform clock (CCB) frequency”
in the following formula refers to the maximum platform (CCB) frequency of the speed bins the part belongs to, which is
defined in Table 73.
For FIFO GMII mode:
FIFO TX/RX clock frequency <= platform clock frequency/3.2
For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency should be no more than 167 MHz
For FIFO encoded mode:
FIFO TX/RX clock frequency <= platform clock frequency/3.2
For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency should be no more than
167 MHz
2.4.7
Other Input Clocks
For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC, see the specific
section of this document.
2.5
RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements of the chip. This table
provides the RESET initialization AC timing specifications for the DDR SDRAM component(s).
Table 10. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
100
—
μs
—
3
—
Sysclk
1
100
—
μs
—
Input setup time for POR configurations (other than PLL config) with respect to negation of
HRESET
4
—
SYSCLKs
1
Input hold time for all POR configurations (including PLL config) with respect to negation of
HRESET
2
—
SYSCLKs
1
Maximum valid-to-high impedance time for actively driven POR configurations with respect to
negation of HRESET
—
5
SYSCLKs
1
HRESET rise time
—
1
SYSCLK
—
Required assertion time of HREST
Minimum assertion time for SRESET
PLL input setup time with stable SYSCLK before HRESET negation
Notes:
1. SYSCLK is the primary clock input for the chip.
This table provides the PLL lock times.
Table 11. PLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
PLL lock times
—
100
μs
—
Local bus PLL
—
50
μs
—
PCI bus lock time
—
50
μs
—
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
30
Freescale Semiconductor
Electrical Characteristics
2.6
DDR2 and DDR3 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the chip. Note that DDR2
SDRAM is GVDD(type) = 1.8 V and DDR3 SDRAM is GVDD(type) = 1.5 V.
2.6.1
DDR2 and DDR3 SDRAM DC Electrical Characteristics
This table provides the recommended operating conditions for the DDR SDRAM component(s) of the chip when interfacing to
DDR2 SDRAM.
Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O supply voltage
GVDD
1.7
1.9
V
1
I/O reference voltage
MVREF
0.49 × GVDD
0.51 × GVDD
V
2
I/O termination voltage
VTT
MVREF – 0.04
MVREF + 0.04
V
3
Input high voltage
VIH
MVREF+ 0.125
GVDD + 0.3
V
—
Input low voltage
VIL
–0.3
MVREF – 0.125
V
—
Output leakage current
IOZ
–50
50
μA
4
Output high current (VOUT = 1.420 V)
IOH
–13.4
—
mA
—
Output low current (VOUT = 0.280 V)
IOL
13.4
—
mA
—
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver.
Peak-to-peak noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the chip. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.
This table provides the recommended operating conditions for the DDR SDRAM controller of the chip when interfacing to
DDR3 SDRAM.
Table 13. DDR3 SDRAM Interface DC Electrical Characteristics for GVDD(typ) = 1.5 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
GVDD
1.425
1.575
V
1
MVREFn
0.49 × GVDD
0.51 × GVDD
V
2
Input high voltage
VIH
MVREFn + 0.100
GVDD
V
—
Input low voltage
VIL
GND
MVREFn – 0.100
V
—
Output leakage current
IOZ
–50
50
μA
3
I/O supply voltage
I/O reference voltage
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREFn is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver.
Peak-to-peak noise on MVREFn may not exceed ±1% of the DC value.
3. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
31
Electrical Characteristics
This table provides the DDR capacitance when GVDD(type) = 1.8 V.
Table 14. DDR2 SDRAM Capacitance for GVDD(typ)=1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS, DQS
CIO
6
8
pF
1, 2
Delta input/output capacitance: DQ, DQS, DQS
CDIO
—
0.5
pF
1, 2
Note:
1. This parameter is sampled. GVDD = 1.8 V ± 0.090 V (for DDR2), f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT
(peak-to-peak) = 0.2 V.
2. This parameter is sampled. GVDD = 1.5 V ± 0.075 V (for DDR3), f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT
(peak-to-peak) = 0.175 V.
This table provides the current draw characteristics for MVREF.
Table 15. Current Draw Characteristics for MVREF
Parameter/Condition
Current draw for MVREFn
DDR2 SDRAM
Symbol
Min
Max
Unit
Note
IMVREFn
—
1500
μA
1
DDR3 SDRAM
1250
1.The voltage regulator for MVREF must be able to supply up to 1500 μA or 1250 uA current for DDR2 or DDR3 respectively.
2.6.2
DDR2 and DDR3 SDRAM Interface AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM Controller interface. The DDR controller supports
both DDR2 and DDR3 memories. Please note that although the minimum data rate for most off-the-shelf DDR3 DIMMs
available is 800 MHz, JEDEC specification does allow the DDR3 to run at the data rate as low as 606 MHz. Unless otherwise
specified, the AC timing specifications described in this section for DDR3 is applicable for data rate between 606 MHz and
667 MHz, as long as the DC and AC specifications of the DDR3 memory to be used are compliant to both JEDEC specifications
as well as the specifications and requirements described in this document.
2.6.2.1
DDR2 and DDR3 SDRAM Interface Input AC Timing Specifications
These tables provide the input AC timing specifications for the DDR controller.
Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
At recommended operating conditions with GVDD of 1.8 V ± 5%
Parameter
AC input low voltage
667
Symbol
Min
Max
Unit
VILAC
—
MVREF – 0.20
V
—
MVREF – 0.25
V
MVREF + 0.20
—
V
MVREF + 0.25
—
V
<=533
AC input high voltage
667
<=533
VIHAC
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
32
Freescale Semiconductor
Electrical Characteristics
Table 17. DDR3 SDRAM Input AC Timing Specifications for 1.5-V Interface
At recommended operating conditions with GVDD of 1.5 V ± 5%. DDR3 data rate is between 606MHz and 667MHz.
Parameter
Symbol
Min
Max
Unit
Notes
AC input low voltage
VIL
—
MVREF – 0.175
V
—
AC input high voltage
VIH
MVREF + 0.175
—
V
—
Table 18. DDR2 and DDR3 SDRAM Interface Input AC Timing Specifications
At recommended operating conditions with GVDD of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3.
Parameter
Symbol
Min
Max
Unit
Notes
tCISKEW
—
—
ps
1, 2
667 MHz
—
–240
240
—
3
533 MHz
—
–300
300
—
—
400 MHz
—
–365
365
—
—
Controller Skew for MDQS—MDQ/MECC
Note:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that will
be captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be determined
by the following equation: tDISKEW =+/-(T/4 - abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the absolute value
of tCISKEW.
3. Maximum DDR2 and DDR3 frequency is 667MHz.
This figure shows the DDR2 and DDR3 SDRAM interface input timing diagram.
MCK[n]
MCK[n]
tMCK
MDQS[n]
MDQ[x]
D0
D1
tDISKEW
tDISKEW
Figure 8. DDR SDRAM Input Timing Diagram
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
33
Electrical Characteristics
2.6.2.2
DDR2 and DDR3 SDRAM Interface Output AC Timing Specifications
This table contains the output AC timing targets for the DDR2 and DDR3 SDRAM interface.
Table 19. DDR SDRAM Output AC Timing Specifications
At recommended operating conditions with GVDD of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3.
Parameter
MCK[n] cycle time, MCK[n]/MCK[n] crossing
ADDR/CMD output setup with respect to MCK
Symbol 1
Min
Max
Unit
Notes
tMCK
3.0
5
ns
2
ns
3
tDDKHAS
667 MHz
1.10
—
533 MHz
1.48
—
400 MHz
1.95
—
ADDR/CMD output hold with respect to MCK
tDDKHAX
1.10
—
533 MHz
1.48
—
400 MHz
1.95
—
tDDKHCS
1.10
—
533 MHz
1.48
—
400 MHz
1.95
—
tDDKHCX
1.10
—
533 MHz
1.48
—
400 MHz
1.95
—
MCK to MDQS Skew
<= 667 MHz
MDQ/MECC/MDM output setup with respect to
MDQS
–0.6
0.6
667 MHz
450
—
533 MHz
538
—
400 MHz
700
—
MDQ/MECC/MDM output hold with respect to
MDQS
667 MHz
450
—
533 MHz
538
—
400 MHz
700
—
tDDKHMP
5
7
ps
tDDKHDX,
tDDKLDX
4
7
ps
tDDKHDS,
tDDKLDS
3
7
ns
tDDKHMH
3
7
ns
667 MHz
3
7
ns
667 MHz
MCS[n] output hold with respect to MCK
MDQS preamble start
ns
667 MHz
MCS[n] output setup with respect to MCK
7
5
7
ns
6
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
34
Freescale Semiconductor
Electrical Characteristics
Table 19. DDR SDRAM Output AC Timing Specifications (continued)
At recommended operating conditions with GVDD of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3.
Symbol 1
Parameter
Max
ns
0.4 × tMCK
Notes
7
tDDKHME
<= 667 MHz
Unit
0.9 × tMCK
<= 667 MHz
MDQS epilogue end
Min
0.6 × tMCK
6
7
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD)
from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control
of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the
CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same
adjustment value. See the MPC8536E PowerQUICC III Integrated Processor Reference Manual for a description and
understanding of the timing modifications enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that tDDKHMP follows the
symbol conventions described in note 1.
7. Maximum DDR2 and DDR3 frequency is 667 MHz
NOTE
For the ADDR/CMD setup and hold specifications in Table 19, it is assumed that the Clock
Control register is set to adjust the memory clocks by 1/2 applied cycle.
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
35
Electrical Characteristics
This figure shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH).
MCK[n]
MCK[n]
tMCK
tDDKHMHmax) = 0.6 ns
MDQS
tDDKHMH(min) = –0.6 ns
MDQS
Figure 9. Timing Diagram for tDDKHMH
This figure shows the DDR SDRAM output timing diagram.
MCK[n]
MCK[n]
tMCK
tDDKHAS ,tDDKHCS
tDDKHAX ,tDDKHCX
ADDR/CMD
Write A0
NOOP
tDDKHMP
tDDKHMH
MDQS[n]
tDDKHME
tDDKHDS
tDDKLDS
MDQ[x]
D0
D1
tDDKLDX
tDDKHDX
Figure 10. DDR SDRAM Output Timing Diagram
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Freescale Semiconductor
Electrical Characteristics
This figure provides the AC test load for the DDR bus.
Z0 = 50 Ω
Output
GVDD/2
RL = 50 Ω
Figure 11. DDR AC Test Load
2.7
eSPI
This section describes the DC and AC electrical specifications for the eSPI of the chip.
2.7.1
eSPI DC Electrical Characteristics
This table provides the DC electrical characteristics for the chip eSPI.
Table 20. SPI DC Electrical Characteristics
Characteristic
2.7.2
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH = –6.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 6.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
0 V ≤ VIN ≤ OVDD
—
±10
μA
eSPI AC Timing Specifications
This table and provide the eSPI input and output AC timing specifications.
Table 21. SPI AC Timing Specifications1
Characteristic
SPI_MOSI output—Master data hold time
Symbol 2
Min
tNIKHOX
0.5
tNIKHOX
SPI_MOSI output—Master data delay
tNIKHOV
tNIKHOV
SPI_CS outputs—Master data hold time
4.0
tNIKHOX2
Max
Unit
—
ns
3
6.0
—
0
Note
7.4
—
4
3
ns
ns
4
—
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Electrical Characteristics
Table 21. SPI AC Timing Specifications1 (continued)
Symbol 2
Min
Max
Unit
Note
tNIKHOV2
—
6.0
ns
—
SPI inputs—Master data input setup time
tNIIVKH
5
—
ns
—
SPI inputs—Master data input hold time
tNIIXKH
0
—
ns
—
Characteristic
SPI_CS outputs—Master data delay
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.
Timings are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tNIKHOV symbolizes the NMSI outputs internal timing (NI) for the time tSPI memory clock reference (K) goes from
the high state (H) until outputs (O) are valid (V).
3. SPCOM[RxDelay] is set to 0.
4. SPCOM[RxDelay] is set to 1.
This figure provides the AC test load for the SPI.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 12. SPI AC Test Load
This figure represents the AC timing from Table 21. Note that although the specifications generally reference the rising edge of
the clock, these AC timing diagrams also apply when the falling edge is the active edge.
SPICLK (output)
Input Signals:
SPIMISO
(See Note)
Output Signals:
SPIMOSI
(See Note)
tNIIVKH
tNIIXKH
tNIKHOX
tNIKHOV
tNIKHOV2
tNIKHOX2
Output Signals:
SPI_CS[0:3]
(See Note)
Note: The clock edge is selectable on SPI.
Figure 13. SPI AC Timing in Master mode (Internal Clock) Diagram
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Freescale Semiconductor
Electrical Characteristics
2.8
DUART
This section describes the DC and AC electrical specifications for the DUART interface of the chip.
2.8.1
DUART DC Electrical Characteristics
This table provides the DC electrical characteristics for the DUART interface.
Table 22. DUART DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2
OVDD + 0.3
V
Low-level input voltage
VIL
– 0.3
0.8
V
Input current
(VIN 1 = 0 V or VIN = VDD)
IIN
—
±5
μA
High-level output voltage
(OVDD = min, IOH = –2 mA)
VOH
2.4
—
V
Low-level output voltage
(OVDD = min, IOL = 2 mA)
VOL
—
0.4
V
Note:
1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
2.8.2
DUART AC Electrical Specifications
This table provides the AC timing parameters for the DUART interface.
Table 23. DUART AC Timing Specifications
Parameter
Value
Unit
Notes
Minimum baud rate
CCB clock/1,048,576
baud
2
Maximum baud rate
CCB clock/16
baud
2,3
16
—
4
Oversample rate
Notes:
2. CCB clock refers to the platform clock.
3. Actual attainable baud rate will be limited by the latency of interrupt processing.
4. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit.
Subsequent bit values are sampled each 16th sample.
2.9
Ethernet: Enhanced Three-Speed Ethernet (eTSEC),
MII Management
This section provides the AC and DC electrical characteristics for enhanced three-speed and MII management.
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
39
Electrical Characteristics
2.9.1
Enhanced Three-Speed Ethernet Controller (eTSEC)
(10/100/1000 Mbps) — FIFO/GMII/MII/TBI/RGMII/RTBI/RMII Electrical
Characteristics
The electrical characteristics specified here apply to all FIFO mode, gigabit media independent interface (GMII), media
independent interface (MII), ten-bit interface (TBI), reduced gigabit media independent interface (RGMII), reduced ten-bit
interface (RTBI), and reduced media independent interface (RMII) signals except management data input/output (MDIO) and
management data clock (MDC), and serial gigabit media independent interface (SGMII). The RGMII, RTBI and FIFO mode
interfaces are defined for 2.5 V, while the GMII, MII, RMII, and TBI interfaces can operate at 3.3V.
The GMII, MII, or TBI interface timing is compliant with IEEE 802.3. The RGMII and RTBI interfaces follow the Reduced
Gigabit Media-Independent Interface (RGMII) Specification Version 1.3 (12/10/2000). The RMII interface follows the RMII
Consortium RMII Specification Version 1.2 (3/20/1998).
The electrical characteristics for MDIO and MDC are specified in Section 2.10, “Ethernet Management Interface Electrical
Characteristics.”
The electrical characteristics for SGMII is specified in Section 2.9.3, “SGMII Interface Electrical Characteristics.” The SGMII
interface conforms (with exceptions) to the Serial-GMII Specification Version 1.8.
2.9.1.1
GMII, MII, TBI, RGMII, RMII and RTBI DC Electrical Characteristics
All GMII, MII, TBI, RGMII, RMII and RTBI drivers and receivers comply with the DC parametric attributes specified in the
following tables. The RGMII and RTBI signals are based on a 2.5-V CMOS interface voltage as defined by JEDEC
EIA/JESD8-5.
Table 24. GMII, MII, RMII, and TBI DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
Notes
Supply voltage 3.3 V
LVDD
TVDD
3.13
3.47
V
1, 2
Output high voltage
(LVDD/TVDD = Min, IOH = –4.0 mA)
VOH
2.40
LVDD/TVDD + 0.3
V
—
Output low voltage
(LVDD/TVDD = Min, IOL = 4.0 mA)
VOL
GND
0.50
V
—
Input high voltage
VIH
1.90
LVDD/TVDD + 0.3
V
—
Input low voltage
VIL
–0.3
0.90
V
—
Input high current
(VIN = LVDD, VIN = TVDD)
IIH
—
40
μA
1, 2,3
Input low current
(VIN = GND)
IIL
–600
—
μA
3
Notes:
1
LVDD supports eTSECs 1.
TVDD supports eTSECs 3.
3
The symbol VIN, in this case, represents the LVIN and TVIN symbols referenced in Table 1 and Table 2.
2
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Freescale Semiconductor
Electrical Characteristics
Table 25. RGMII, RTBI, and FIFO DC Electrical Characteristics
Parameters
Symbol
Min
Max
Unit
Notes
LVDD/TVDD
2.37
2.63
V
1,2
Output high voltage
(LVDD/TVDD = Min, IOH = –1.0 mA)
VOH
2.00
LVDD/TVDD + 0.3
V
—
Output low voltage
(LVDD/TVDD = Min, IOL = 1.0 mA)
VOL
GND – 0.3
0.40
V
—
Input high voltage
VIH
1.70
LVDD/TVDD + 0.3
V
—
Input low voltage
VIL
–0.3
0.70
V
Input high current
(VIN = LVDD, VIN = TVDD)
IIH
—
10
μA
—
1, 2,3
Input low current
(VIN = GND)
IIL
–15
—
μA
3
Supply voltage 2.5 V
Note:
1
LVDD supports eTSECs 1.
TVDD supports eTSECs 3.
3 Note that the symbol V , in this case, represents the LV and TV symbols referenced in Table 1 and Table 2.
IN
IN
IN
2
2.9.2
FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications
The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI are presented in this section.
2.9.2.1
FIFO AC Specifications
The basis for the AC specifications for the eTSEC’s FIFO modes is the double data rate RGMII and RTBI specifications, since
they have similar performance and are described in a source-synchronous fashion like FIFO modes. However, the FIFO
interface provides deliberate skew between the transmitted data and source clock in GMII fashion.
When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the relevant eTSEC interface.
That is, the transmit clock must be applied to the eTSECn’s TSECn_TX_CLK, while the receive clock must be applied to pin
TSECn_RX_CLK. The eTSEC internally uses the transmit clock to synchronously generate transmit data and outputs an echoed
copy of the transmit clock back out onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for
example). It is intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a sourcesynchronous timing reference. Typically, the clock edge that launched the data can be used, since the clock is delayed by the
eTSEC to allow acceptable set-up margin at the receiver. Note that there is relationship between the maximum FIFO speed and
the platform speed. For more information see Section 2.4.6, “Platform to FIFO Restrictions.”
A summary of the FIFO AC specifications appears in the following tables.
Table 26. FIFO Mode Transmit AC Timing Specification
Parameter/Condition
Symbol
Min
Typ
Max
Unit
TX_CLK, GTX_CLK clock period2
tFIT
6.0
8.0
100
ns
TX_CLK, GTX_CLK duty cycle
tFITH
45
50
55
%
TX_CLK, GTX_CLK peak-to-peak jitter
tFITJ
—
—
250
ps
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Freescale Semiconductor
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Electrical Characteristics
Table 26. FIFO Mode Transmit AC Timing Specification (continued)
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Rise time TX_CLK (20%–80%)
tFITR
—
—
0.75
ns
Fall time TX_CLK (80%–20%)
tFITF
—
—
0.75
ns
tFITDX1
0.5
—
3.0
ns
GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time
Note:
1. Data valid tFITDV to GTX_CLK Min Setup time is a function of clock period and max hold time. (Min Setup = Cycle time
– Max Hold)
2. The minimum cycle period (or maximum frequency) of the RX_CLK is dependent on the maximum platform frequency
of the speed bins the part belongs to as well as the FIFO mode under operation. See Section 2.4.6, “Platform to FIFO
Restrictions,” for more detailed description.
Table 27. FIFO Mode Receive AC Timing Specification
Parameter/Condition
Symbol
Min
Typ
Max
Unit
tFIR
6.0
8.0
100
ns
tFIRH/tFIRH
45
50
55
%
RX_CLK peak-to-peak jitter
tFIRJ
—
—
250
ps
Rise time RX_CLK (20%–80%)
tFIRR
—
—
0.75
ns
Fall time RX_CLK (80%–20%)
tFIRF
—
—
0.75
ns
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
tFIRDV
1.5
—
—
ns
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
tFIRDX
0.5
—
—
ns
RX_CLK clock period1
RX_CLK duty cycle
Note:
1. The minimum cycle period (or maximum frequency) of the RX_CLK is dependent on the maximum platform frequency
of the speed bins the part belongs to as well as the FIFO mode under operation. See Section 2.4.6, “Platform to FIFO
Restrictions,” for more detailed description.
Timing diagrams for FIFO appear in the following figures.
tFITF
tFITR
tFIT
GTX_CLK
tFITH
tFITDV
tFITDX
TXD[7:0]
TX_EN
TX_ER
Figure 14. FIFO Transmit AC Timing Diagram
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Freescale Semiconductor
Electrical Characteristics
tFIRR
tFIR
RX_CLK
tFIRH
RXD[7:0]
RX_DV
RX_ER
tFIRF
valid data
tFIRDV
tFIRDX
Figure 15. FIFO Receive AC Timing Diagram
2.9.2.2
GMII AC Timing Specifications
This section describes the GMII transmit and receive AC timing specifications.
2.9.2.2.1
GMII Transmit AC Timing Specifications
This table provides the GMII transmit AC timing specifications.
Table 28. GMII Transmit AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.
Symbol 1
Min
Typ
Max
Unit
tGTK
—
8.0
—
ns
tGTKHDX3
0.5
—
5.0
ns
GTX_CLK data clock rise time (20%-80%)
tGTXR
—
—
1.0
ns
GTX_CLK data clock fall time (80%-20%)
tGTXF
—
—
1.0
ns
Parameter/Condition
GTX_CLK clock period
GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay
Notes:
1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV symbolizes GMII
transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input
signals (D) reaching the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit timing (GT) with respect
to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold
time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a
particular functional. For example, the subscript of tGTX represents the GMII(G) transmit (TX) clock. For rise and fall times,
the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. Data valid tGTKHDV to GTX_CLK Min Setup time is a function of clock period and max hold time. (Min Setup = Cycle time Max Hold)
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
43
Electrical Characteristics
This figure shows the GMII transmit AC timing diagram.
tGTXR
tGTX
GTX_CLK
tGTXF
tGTXH
TXD[7:0]
TX_EN
TX_ER
tGTKHDX
tGTKHDV
Figure 16. GMII Transmit AC Timing Diagram
2.9.2.2.2
GMII Receive AC Timing Specifications
This table provides the GMII receive AC timing specifications.
Table 29. GMII Receive AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.
Symbol 1
Min
Typ
Max
Unit
tGRX
—
8.0
—
ns
tGRXH/tGRX
35
—
65
%
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
tGRDVKH
2.0
—
—
ns
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
tGRDXKH
0
—
—
ns
RX_CLK clock rise (20%-80%)
tGRXR
—
—
1.0
ns
RX_CLK clock fall time (80%-20%)
tGRXF
—
—
1.0
ns
Parameter/Condition
RX_CLK clock period
RX_CLK duty cycle
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH symbolizes GMII
receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the tRX clock
reference (K) going to the high state (H) or setup time. Also, tGRDXKL symbolizes GMII receive timing (GR) with respect to the
time data input signals (D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L) state or hold time. Note
that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular
functional. For example, the subscript of tGRX represents the GMII (G) receive (RX) clock. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
This figure provides the AC test load for eTSEC.
Output
Z0 = 50 Ω
RL = 50 Ω
LVDD/2
Figure 17. eTSEC AC Test Load
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
44
Freescale Semiconductor
Electrical Characteristics
This figure shows the GMII receive AC timing diagram.
tGRXR
tGRX
RX_CLK
tGRXH
tGRXF
RXD[7:0]
RX_DV
RX_ER
tGRDXKH
tGRDVKH
Figure 18. GMII Receive AC Timing Diagram
2.9.2.3
MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
2.9.2.3.1
MII Transmit AC Timing Specifications
This table provides the MII transmit AC timing specifications.
Table 30. MII Transmit AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.
Symbol 1
Min
Typ
Max
Unit
TX_CLK clock period 10 Mbps
tMTX
—
400
—
ns
TX_CLK clock period 100 Mbps
tMTX
—
40
—
ns
tMTXH/tMTX
35
—
65
%
tMTKHDX
1
5
15
ns
TX_CLK data clock rise (20%-80%)
tMTXR
1.0
—
4.0
ns
TX_CLK data clock fall (80%-20%)
tMTXF
1.0
—
4.0
ns
Parameter/Condition
TX_CLK duty cycle
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII
transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in
general, the clock reference symbol representation is based on two to three letters representing the clock of a particular
functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
45
Electrical Characteristics
This figure shows the MII transmit AC timing diagram.
tMTXR
tMTX
TX_CLK
tMTXF
tMTXH
TXD[3:0]
TX_EN
TX_ER
tMTKHDX
Figure 19. MII Transmit AC Timing Diagram
2.9.2.3.2
MII Receive AC Timing Specifications
This table provides the MII receive AC timing specifications.
Table 31. MII Receive AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.
Symbol 1
Min
Typ
Max
Unit
RX_CLK clock period 10 Mbps
tMRX
—
400
—
ns
RX_CLK clock period 100 Mbps
tMRX
—
40
—
ns
tMRXH/tMRX
35
—
65
%
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
tMRDVKH
10.0
—
—
ns
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
tMRDXKH
10.0
—
—
ns
RX_CLK clock rise (20%–80%)
tMRXR
1.0
—
4.0
ns
RX_CLK clock fall time (80%–20%)
tMRXF
1.0
—
4.0
ns
Parameter/Condition
RX_CLK duty cycle
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going
to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals
(D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the
clock reference symbol representation is based on three letters representing the clock of a particular functional. For example,
the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the
appropriate letter: R (rise) or F (fall).
This figure provides the AC test load for eTSEC.
Output
Z0 = 50 Ω
RL = 50 Ω
LVDD/2
Figure 20. eTSEC AC Test Load
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
46
Freescale Semiconductor
Electrical Characteristics
This figure shows the MII receive AC timing diagram.
tMRXR
tMRX
RX_CLK
tMRXF
tMRXH
RXD[3:0]
RX_DV
RX_ER
Valid Data
tMRDVKH
tMRDXKL
Figure 21. MII Receive AC Timing Diagram
2.9.2.4
TBI AC Timing Specifications
This section describes the TBI transmit and receive AC timing specifications.
2.9.2.4.1
TBI Transmit AC Timing Specifications
This table provides the TBI transmit AC timing specifications.
Table 32. TBI Transmit AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.
Symbol 1
Min
Typ
Max
Unit
tTTX
—
8.0
—
ns
GTX_CLK duty cycle
tTTXH/tTTX
40
—
60
%
GTX_CLK to TCG[9:0] delay time
tTTKHDX2
1.0
—
5.0
ns
GTX_CLK rise (20%–80%)
tTTXR
—
—
1.0
ns
GTX_CLK fall time (80%–20%)
tTTXF
—
—
1.0
ns
Parameter/Condition
GTX_CLK clock period
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state )(reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV symbolizes the TBI
transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the valid
state (V) or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high
(H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference symbol
representation is based on three letters representing the clock of a particular functional. For example, the subscript of tTTX
represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R
(rise) or F (fall).
2. Data valid tTTKHDV to GTX_CLK Min Setup time is a function of clock period and max hold time. (Min Setup = Cycle time - Max
Hold)
This figure shows the TBI transmit AC timing diagram.
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
47
Electrical Characteristics
tTTXR
tTTX
GTX_CLK
tTTXH
tTTXF
tTTXF
TCG[9:0]
tTTKHDV
tTTXR
tTTKHDX
Figure 22. TBI Transmit AC Timing Diagram
2.9.2.4.2
TBI Receive AC Timing Specifications
This table provides the TBI receive AC timing specifications.
Table 33. TBI Receive AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.
Parameter/Condition2
Symbol 1
Min
Typ
Max
Unit
tTRX
—
16.0
—
ns
tSKTRX
7.5
—
8.5
ns
tTRXH/tTRX
40
—
60
%
RCG[9:0] setup time to rising edge of TBI Receive Clock 0, 1
tTRDVKH
2.5
—
—
ns
RCG[9:0] hold time to rising edge of TBI Receive Clock 0, 1
tTRDXKH
1.5
—
—
ns
Clock rise time (20%-80%) for TBI Receive Clock 0, 1
tTRXR
0.7
—
2.4
ns
Clock fall time (80%-20%) for TBI Receive Clock 0, 1
tTRXF
0.7
—
2.4
ns
Clock period for TBI Receive Clock 0, 1
Skew for TBI Receive Clock 0, 1
Duty cycle for TBI Receive Clock 0, 1
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTRDVKH symbolizes TBI receive
timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the tTRX clock reference (K) going
to the high (H) state or setup time. Also, tTRDXKH symbolizes TBI receive timing (TR) with respect to the time data input signals
(D) went invalid (X) relative to the tTRX clock reference (K) going to the high (H) state. Note that, in general, the clock reference
symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of
tTRX represents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter:
R (rise) or F (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (TRX).
2. The signals “TBI Receive Clock 0” and “TBI Receive Clock 1” refer to TSECn_RX_CLK and TSECn_TX_CLK pins respectively.
These two clock signals are also referred as PMA_RX_CLK[0:1].
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This figure shows the TBI receive AC timing diagram.
tTRXR
tTRX
TBI Receive Clock 1
(TSECn_TX_CLK)
tTRXH
tTRXF
Valid Data
RCG[9:0]
Valid Data
tTRDVKH
tSKTRX
tTRDXKH
TBI Receive Clock 0
(TSECn_RX_CLK)
tTRDXKH
tTRXH
tTRDVKH
Figure 23. TBI Receive AC Timing Diagram
2.9.2.5
TBI Single-Clock Mode AC Specifications
When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant eTSEC interface.
In single-clock TBI mode, when a 125-MHz TBI receive clock is supplied on TSECn pin (no receive clock is used on in this
mode, whereas for the dual-clock mode this is the PMA0 receive clock). The 125-MHz transmit clock is applied on the in all
TBI modes.
A summary of the single-clock TBI mode AC specifications for receive appears in the following table.
Table 34. TBI single-clock Mode Receive AC Timing Specification
At recommended operating conditions with LVDD/TVDD of 3.3 V ± 5%
Parameter/Condition
Symbol
Min
Typ
Max
Unit
RX_CLK clock period
tTRR
7.5
8.0
8.5
ns
RX_CLK duty cycle
tTRRH
40
50
60
%
RX_CLK peak-to-peak jitter
tTRRJ
—
—
250
ps
Rise time RX_CLK (20%–80%)
tTRRR
—
—
1.0
ns
Fall time RX_CLK (80%–20%)
tTRRF
—
—
1.0
ns
RCG[9:0] setup time to RX_CLK rising edge
tTRRDV
2.0
—
—
ns
RCG[9:0] hold time to RX_CLK rising edge
tTRRDX
1.0
—
—
ns
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Electrical Characteristics
A timing diagram for TBI receive appears in the following figure.
.
tTRRR
tTRR
RX_CLK
tTRRH
tTRRF
RCG[9:0]
valid data
tTRRDV
tTRRDX
Figure 24. TBI Single-Clock Mode Receive AC Timing Diagram
2.9.2.6
RGMII and RTBI AC Timing Specifications
This table presents the RGMII and RTBI AC timing specifications.
Table 35. RGMII and RTBI AC Timing Specifications
At recommended operating conditions with L/TVDD of 2.5 V ± 5%.
Symbol 1
Min
Typ
Max
Unit
tSKRGT_TX
–500
0
500
ps
tSKRGT_RX
1.0
—
2.8
ns
tRGT
7.2
8.0
8.8
ns
tRGTH/tRGT
45
—
55
%
tRGTH/tRGT
40
50
60
%
Rise time (20%–80%)
tRGTR
—
—
0.75
ns
Fall time (20%–80%)
tRGTF
—
—
0.75
ns
Parameter/Condition
Data to clock output skew (at transmitter)
Data to clock input skew (at receiver)
Clock period duration
2
3
Duty cycle for 1000BASE-T4
Duty cycle for 10BASE-T and 100BASE-TX
3, 4
Notes:
1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to
represent RGMII and RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Note
also that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols
representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than
1.5 ns will be added to the associated clock signal.
3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transition to a received packet's clock domains as
long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed
transitioned between.
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Freescale Semiconductor
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This figure shows the RGMII and RTBI AC timing and multiplexing diagrams.
tRGT
tRGTH
GTX_CLK
(At Transmitter)
tSKRGT_TX
TXD[8:5][3:0]
TXD[7:4][3:0]
TX_CTL
TXD[3:0]
TXD[8:5]
TXD[7:4]
TXD[4]
TXEN
TXD[9]
TXERR
tSKRGT_RX
TX_CLK
(At PHY)
RXD[8:5][3:0]
RXD[7:4][3:0]
RXD[8:5]
RXD[3:0] RXD[7:4]
tSKRGT_TX
RXD[4]
RXDV
RX_CTL
RXD[9]
RXERR
tSKRGT_RX
RX_CLK
(At PHY)
Figure 25. RGMII and RTBI AC Timing and Multiplexing Diagrams
2.9.2.7
RMII AC Timing Specifications
This section describes the RMII transmit and receive AC timing specifications.
2.9.2.7.1
RMII Transmit AC Timing Specifications
The RMII transmit AC timing specifications are in the following table.
Table 36. RMII Transmit AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.
Symbol 1
Min
Typ
Max
Unit
TSECn_TX_CLK clock period
tRMT
15.0
20.0
25.0
ns
TSECn_TX_CLK duty cycle
tRMTH
35
50
65
%
TSECn_TX_CLK peak-to-peak jitter
tRMTJ
—
—
250
ps
Parameter/Condition
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Electrical Characteristics
Table 36. RMII Transmit AC Timing Specifications (continued)
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.
Symbol 1
Min
Typ
Max
Unit
Rise time TSECn_TX_CLK (20%–80%)
tRMTR
1.0
—
2.0
ns
Fall time TSECn_TX_CLK (80%–20%)
tRMTF
1.0
—
2.0
ns
tRMTDX
2.0
—
10.0
ns
Parameter/Condition
TSECn_TX_CLK to RMII data TXD[1:0], TX_EN delay
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX
symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid
(X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock
of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
This figure shows the RMII transmit AC timing diagram.
tRMTR
tRMT
TSECn_TX_CLK
tRMTH
tRMTF
TXD[1:0]
TX_EN
TX_ER
tRMTDX
Figure 26. RMII Transmit AC Timing Diagram
2.9.2.7.2
RMII Receive AC Timing Specifications
Table 37. RMII Receive AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.
Symbol 1
Min
Typ
Max
Unit
TSECn_RX_CLK clock period
tRMR
15.0
20.0
25.0
ns
TSECn_RX_CLK duty cycle
tRMRH
35
50
65
%
TSECn_RX_CLK peak-to-peak jitter
tRMRJ
—
—
250
ps
Rise time TSECn_RX_CLK (20%–80%)
tRMRR
1.0
—
2.0
ns
Parameter/Condition
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Table 37. RMII Receive AC Timing Specifications (continued)
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.
Symbol 1
Min
Typ
Max
Unit
Fall time TSECn_RX_CLK (80%–20%)
tRMRF
1.0
—
2.0
ns
RXD[1:0], CRS_DV, RX_ER setup time to TSECn_RX_CLK rising edge
tRMRDV
4.0
—
—
ns
RXD[1:0], CRS_DV, RX_ER hold time to TSECn_RX_CLK rising edge
tRMRDX
2.0
—
—
ns
Parameter/Condition
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going
to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals
(D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock
reference symbol representation is based on three letters representing the clock of a particular functional. For example, the
subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the
appropriate letter: R (rise) or F (fall).
This figure provides the AC test load for eTSEC.
Output
Z0 = 50 Ω
RL = 50 Ω
LVDD/2
Figure 27. eTSEC AC Test Load
This figure shows the RMII receive AC timing diagram.
tRMRR
tRMR
TSECn_RX_CLK
tRMRH
RXD[1:0]
CRS_DV
RX_ER
tRMRF
Valid Data
tRMRDV
tRMRDX
Figure 28. RMII Receive AC Timing Diagram
2.9.3
SGMII Interface Electrical Characteristics
Each SGMII port features a 4-wire AC-Coupled serial link from the dedicated SerDes 2 interface of the chip as shown in
Figure 29, where CTX is the external (on board) AC-Coupled capacitor. Each output pin of the SerDes transmitter differential
pair features 50-Ω output impedance. Each input of the SerDes receiver differential pair features 50-Ω on-die termination to
S2GND (xcorevss). The reference circuit of the SerDes transmitter and receiver is shown in Figure 68.
When an eTSEC port is configured to operate in SGMII mode, the parallel interface’s output signals of this eTSEC port can be
left floating. The input signals should be terminated based on the guidelines described in Section 3.6, “Connection
Recommendations,” as long as such termination does not violate the desired POR configuration requirement on these pins, if
applicable.
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Electrical Characteristics
When operating in SGMII mode, the eTSEC EC_GTX_CLK125 clock is not required for this port. Instead, SerDes reference
clock is required on SD2_REF_CLK and SD2_REF_CLK pins.
2.9.3.1
DC Requirements for SGMII SD2_REF_CLK and SD2_REF_CLK
The characteristics and DC requirements of the separate SerDes reference clock are described in Section 2.20, “High-Speed
Serial Interfaces.”
2.9.3.2
AC Requirements for SGMII SD2_REF_CLK and SD2_REF_CLK
This table lists the SGMII SerDes reference clock AC requirements. Please note that SD2_REF_CLK and SD2_REF_CLK are
not intended to be used with, and should not be clocked by, a spread spectrum clock source.
Table 38. SD2_REF_CLK and SD2_REF_CLK AC Requirements
Symbol
Min
Typical
Max
REFCLK cycle time
—
10 (8)
—
ns
1
tREFCJ
REFCLK cycle-to-cycle jitter. Difference in the period of any two adjacent
REFCLK cycles
—
—
100
ps
—
tREFPJ
Phase jitter. Deviation in edge location with respect to mean edge location
–50
—
50
ps
2,3
tREF
Parameter Description
Units Notes
Notes:
1. 8 ns applies only when 125 MHz SerDes2 reference clock frequency is selected via cfg_srds_sgmii_refclk during POR.
2. In a frequency band from 150 kHz to 15 MHz, at BER of 10E-12.
3. Total peak-to-peak deterministic jitter “Dj” should be less than or equal to 50 ps.
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2.9.3.3
SGMII Transmitter and Receiver DC Electrical Characteristics
The following tables describe the SGMII SerDes transmitter and receiver AC-Coupled DC electrical characteristics.
Transmitter DC characteristics are measured at the transmitter outputs (SD2_TX[n] and SD2_TX[n]) as depicted in Figure 30.
Table 39. SGMII DC Transmitter Electrical Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Notes
X2VDD
0.95
1.0
1.05
V
—
Output high voltage
VOH
—
—
X2VDD-Typ/2 +
|VOD|-max/2
mV
1
Output low voltage
VOL
X2VDD-Typ/2 |VOD|-max/2
—
—
mV
1
VRING
—
—
10
%
—
323
500
725
Equalization
setting: 1.0x
296
459
665
Equalization
setting: 1.09x
269
417
604
Equalization
setting: 1.2x
243
376
545
215
333
483
Equalization
setting: 1.5x
189
292
424
Equalization
setting: 1.71x
162
250
362
Equalization
setting: 2.0x
Supply Voltage
Output ringing
Output differential voltage2, 3, 5
|VOD|
mV
Equalization
setting: 1.33x
Output offset voltage
VOS
425
500
575
mV
1, 4
Output impedance (single-ended)
RO
40
—
60
Ω
—
Δ RO
—
—
10
%
—
Change in VOD between “0” and “1”
Δ |VOD|
—
—
25
mV
—
Change in VOS between “0” and “1”
Δ VOS
—
—
25
mV
—
ISA, ISB
—
—
40
mA
—
Mismatch in a pair
Output current on short to GND
Notes:
1. This will not align to DC-coupled SGMII. X2VDD-Typ=1.0V.
2. |VOD| = |VSD2_TXn - VSD2_TXn|. |VOD| is also referred as output differential peak voltage. VTX-DIFFp-p = 2*|VOD|.
3. The |VOD| value shown in the table assumes the following transmit equalization setting in the XMITEQAB (for SerDes 2 lanes
A & B) or XMITEQEF (for SerDes 2 lanes E & E) bit field of the chip’s SerDes 2 control register:
• The MSbit (bit 0) of the above bit field is set to zero (selecting the full VDD-DIFF-p-p amplitude - power up default);
• The LSbits (bit [1:3]) of the above bit field is set based on the equalization setting shown in table.
4. VOS is also referred to as output common mode voltage.
• 5.The |VOD| value shown in the Typ column is based on the condition of X2VDD-Typ=1.0V, no common mode offset variation
(VOS =550mV), SerDes2 transmitter is terminated with 100-Ω differential load between SD2_TX[n] and SD2_TX[n].
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Electrical Characteristics
50 Ω SD2_TXn
CTX
SD_RXm
50 Ω
Transmitter
Receiver
50 Ω
CTX
SD2_TXn
SGMII
SerDes Interface
Receiver
SD2_RXn
50 Ω
SD_RXm
CTX
50 Ω
SD_TXm
50 Ω
Transmitter
50 Ω
50 Ω
CTX
SD2_RXn
SD_TXm
Figure 29. 4-Wire AC-Coupled SGMII Serial Link Connection Example
SGMII
SerDes Interface
50 Ω SD2_TXn
50 Ω
Transmitter
Vos
VOD
50 Ω
50 Ω
SD2_TXn
Figure 30. SGMII Transmitter DC Measurement Circuit
Table 40. SGMII DC Receiver Electrical Characteristics
Parameter
Supply Voltage
DC Input voltage range
Input differential voltage
Symbol
Min
Typ
Max
Unit
Notes
X2VDD
0.95
1.0
1.05
V
—
—
1
1200
mV
2, 4
mV
3, 4
mV
5
—
LSTS = 0
VRX_DIFFp-p
LSTS = 1
Loss of signal threshold
LSTS = 0
VLOS
LSTS = 1
Input AC common mode voltage
VCM_ACp-p
N/A
100
—
175
—
30
—
100
65
—
175
—
—
100
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Freescale Semiconductor
Electrical Characteristics
Table 40. SGMII DC Receiver Electrical Characteristics (continued)
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Receiver differential input impedance
ZRX_DIFF
80
100
120
Ω
—
Receiver common mode input
impedance
ZRX_CM
20
—
35
Ω
—
Common mode input voltage
VCM
—
Vxcorevss
—
V
6
Notes:
1. Input must be externally AC-coupled.
2. VRX_DIFFp-p is also referred to as peak to peak input differential voltage
3. The concept of this parameter is equivalent to the Electrical Idle Detect Threshold parameter in PCI Express. See Table 72
for further explanation.
4. The LSTS shown in the table refers to the LSTSA or LSTSE bit field of chip’s SerDes 2 control register.
5. VCM_ACp-p is also referred to as peak to peak AC common mode voltage.
6. On-chip termination to S2GND (xcorevss).
2.9.3.4
SGMII AC Timing Specifications
This section describes the SGMII transmit and receive AC timing specifications. Transmitter and receiver characteristics are
measured at the transmitter outputs (SD2_TX[n] and SD2_TX[n]) or at the receiver inputs (SD2_RX[n] and SD2_RX[n]) as
depicted in Figure 32 respectively.
2.9.3.4.1
SGMII Transmit AC Timing Specifications
This table provides the SGMII transmit AC timing targets. A source synchronous clock is not provided.
Table 41. SGMII Transmit AC Timing Specifications
At recommended operating conditions with X2VDD = 1.0V ± 5%.
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Deterministic Jitter
JD
—
—
0.17
UI p-p
—
Total Jitter
JT
—
—
0.35
UI p-p
—
Unit Interval
UI
799.92
800
800.08
ps
1
VOD fall time (80%-20%)
tfall
50
—
120
ps
—
VOD rise time (20%-80%)
trise
50
—
120
ps
—
Notes:
1. Each UI is 800 ps ± 100 ppm.
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Electrical Characteristics
2.9.3.4.2
SGMII Receive AC Timing Specifications
This table provides the SGMII receive AC timing specifications. Source synchronous clocking is not supported. Clock is
recovered from the data. Figure 31 shows the SGMII Receiver Input Compliance Mask eye diagram.
Table 42. SGMII Receive AC Timing Specifications
At recommended operating conditions with X2VDD = 1.0V ± 5%.
Parameter
Symbol
Min
Typ
Max
Unit
Notes
JD
0.37
—
—
UI p-p
1
Combined Deterministic and Random Jitter Tolerance
JDR
0.55
—
—
UI p-p
1
Sinusoidal Jitter Tolerance
JSIN
0.1
—
—
UI p-p
1
JT
0.65
—
—
UI p-p
1
BER
—
—
10-12
UI
799.92
800
800.08
ps
2
CTX
5
—
200
nF
3
Deterministic Jitter Tolerance
Total Jitter Tolerance
Bit Error Ratio
Unit Interval
AC Coupling Capacitor
—
Notes:
1. Measured at receiver.
2. Each UI is 800 ps ± 100 ppm.
3. The external AC coupling capacitor is required. It is recommended to be placed near the chip transmitter outputs.
Receiver Differential Input Voltage
VRX_DIFFp-p-max/2
VRX_DIFFp-p-min/2
0
- VRX_DIFFp-p-min/2
− VRX_DIFFp-p-max/2
0
0.275
0.4
0.6
1
0.725
Time (UI)
Figure 31. SGMII Receiver Input Compliance Mask
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Freescale Semiconductor
Electrical Characteristics
D+ Package
Pin
C = CTX
TX
Silicon
+ Package
D– Package
Pin
C = CTX
R = 50 Ω
R = 50 Ω
Figure 32. SGMII AC Test/Measurement Load
2.9.4
eTSEC IEEE 1588 AC Specifications
This figure shows the data and command output timing diagram.
tT1588CLKOUT
tT1588CLKOUTH
TSEC_1588_CLK_OUT
tT1588OV
TSEC_1588_PULSE_OUT
TSEC_1588_TRIG_OUT
Figure 33. eTSEC IEEE 1588 Output AC timing
1
The output delay is count starting rising edge if tT1588CLKOUT is non-inverting. Otherwise, it is count starting falling edge.
This figure provides the data and command input timing diagram.
tT1588CLK
tT1588CLKH
TSEC_1588_CLK
TSEC_1588_TRIG_IN
tT1588TRIGH
Figure 34. eTSEC IEEE 1588 Input AC timing
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
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Electrical Characteristics
The IEEE 1588 AC timing specifications are in the following table.
Table 43. eTSEC IEEE 1588 AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Note
TSEC_1588_CLK clock period
tT1588CLK
3.8
—
TTX_CLK*7
ns
1
TSEC_1588_CLK duty cycle
tT1588CLKH
/tT1588CLK
40
50
60
%
TSEC_1588_CLK peak-to-peak jitter
tT1588CLKINJ
—
—
250
ps
—
Rise time eTSEC_1588_CLK (20%–80%)
tT1588CLKINR
1.0
—
2.0
ns
—
Fall time eTSEC_1588_CLK (80%–20%)
tT1588CLKINF
1.0
—
2.0
ns
—
TSEC_1588_CLK_OUT clock period
tT1588CLKOUT
2*tT1588CLK
—
—
ns
—
TSEC_1588_CLK_OUT duty cycle
tT1588CLKOTH
/tT1588CLKOUT
30
50
70
%
tT1588OV
0.5
—
3.0
ns
—
tT1588TRIGH
2*tT1588CLK_MAX
—
—
ns
2
TSEC_1588_PULSE_OUT
TSEC_1588_TRIG_IN pulse width
—
—
Note:
1. When TMR_CTRL[CKSEL]=00, the external TSEC_1588_CLK input is selected as the 1588 timer reference clock source,
with the timing defined in the Table above. The maximum value of tT1588CLK is defined in terms of TTX_CLK, which is the
maximum clock cycle period of the equivalent interface speed that the eTSEC1 port is running.
When eTSEC1 is configured to operate in the parallel mode, the TTX_CLK is the maximum clock period of the
TSEC1_TX_CLK. When eTSEC1 operates in SGMII mode, the maximum value of tT1588CLK is defined in terms of the
recovered clock from SGMII SerDes. For example, for 10/100/1000 Mbps modes, the maximum value of tT1588CLK will be
2800, 280, and 56 ns respectively.
See the MPC8536E PowerQUICC III Integrated Communications Processor Reference Manual for a description of
TMR_CTRL registers.
2. It need to be at least two times of clock period of clock selected by TMR_CTRL[CKSEL]. See the MPC8536E PowerQUICC
III Integrated Processor Reference Manual for a description of TMR_CTRL registers.
2.10
Ethernet Management Interface Electrical Characteristics
The electrical characteristics specified here apply to MII management interface signals EC_MDIO (management data
input/output) and EC_MDC (management data clock). The electrical characteristics for GMII, SGMII, RGMII, RMII, TBI and
RTBI are specified in Section 2.9, “Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management”
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2.10.1
MII Management DC Electrical Characteristics
The EC_MDC and EC_MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for
EC_MDIO and EC_MDC are provided in the following table.
Table 44. MII Management DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
OVDD
3.13
3.47
V
Output high voltage
(OVDD = Min, IOH = –4.0 mA)
VOH
2.40
OVDD + 0.3
V
Output low voltage
(OVDD =Min, IOL = 4.0 mA)
VOL
GND
0.40
V
Input high voltage
VIH
2.0
—
V
Input low voltage
VIL
—
0.90
V
Input high current
(OVDD = Max, VIN 1 = 2.1 V)
IIH
—
40
μA
Input low current
(OVDD = Max, VIN = 0.5 V)
IIL
–600
—
μA
Supply voltage (3.3 V)
Note:
1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
2.10.2
MII Management AC Electrical Specifications
This table provides the MII management AC timing specifications.
Table 45. MII Management AC Timing Specifications
At recommended operating conditions with OVDD is 3.3 V ± 5%.
Symbol 1
Min
Typ
Max
Unit
Notes
EC_MDC frequency
fMDC
0.74
2.5
8.3
MHz
2
EC_MDC period
tMDC
120
400
1350
ns
—
EC_MDC clock pulse width high
tMDCH
32
—
—
ns
—
EC_MDC to EC_MDIO delay
tMDKHDX
(16 * tplb_clk)-3
—
(16 * tplb_clk)+3
ns
3,5,6
EC_MDIO to EC_MDC setup time
tMDDVKH
5
—
—
ns
—
Parameter/Condition
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Table 45. MII Management AC Timing Specifications (continued)
At recommended operating conditions with OVDD is 3.3 V ± 5%.
Symbol 1
Min
Typ
Max
Unit
Notes
tMDDXKH
0
—
—
ns
—
EC_MDC rise time
tMDCR
—
—
10
ns
—
EC_MDC fall time
tMDHF
—
—
10
ns
—
Parameter/Condition
EC_MDIO to EC_MDC hold time
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX
symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are
invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input
signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise
and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the eTSEC system clock speed, which is half of the Platform Frequency (fCCB). The actual
EC_MDC output clock frequency for a specific eTSEC port can be programmed by configuring the MgmtClk bit field of chip’s
MIIMCFG register, based on the platform (CCB) clock running for the chip. The formula is: Platform Frequency
(CCB)/(2*Frequency Divider determined by MIICFG[MgmtClk] encoding selection). For example, if MIICFG[MgmtClk] = 000
and the platform (CCB) is currently running at 533 MHz, fMDC = 533/(2*4*8) = 533/64 = 8.3 MHz. That is, for a system
running at a particular platform frequency (fCCB), the EC_MDC output clock frequency can be programmed between
maximum fMDC = fCCB/64 and minimum fMDC = fCCB/448. See the MPC8536E reference manual’s MIIMCFG register section
for more detail.
3. This parameter is dependent on the platform clock frequency. The delay is equal to 16 platform clock periods +/-3ns. For
example, with a platform clock of 333MHz, the min/max delay is 48ns +/-3ns. Similarly, if the platform clock is 400MHz, the
min/max delay is 40ns +/-3ns).
5. tCLKplb_clk is the platform (CCB) clock
6. EC_MDC to EC_MDIO Data valid tMDKHDV is a function of clock period and max delay time tMDKHDX. (Min Setup = Cycle
time - Max Hold)
This figure shows the MII management AC timing diagram.
tMDCR
tMDC
EC_MDC
tMDCF
tMDCH
EC_MDIO
(Input)
tMDDVKH
tMDDXKH
EC_MDIO
(Output)
tMDKHDX
Figure 35. MII Management Interface Timing Diagram
2.11
USB
This section provides the AC and DC electrical specifications for the USB interface of the chip.
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Electrical Characteristics
2.11.1
USB DC Electrical Characteristics
This table provides the DC electrical characteristics for the USB interface.
Table 46. USB DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2
OVDD + 0.3
V
Low-level input voltage
VIL
–0.3
0.8
V
Input current
IIN
—
±5
μA
High-level output voltage,
IOH = –100 μA
VOH
OVDD – 0.2
—
V
Low-level output voltage,
IOL = 100 μA
VOL
—
0.2
V
Note:
1. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
2.11.2
USB AC Electrical Specifications
This table describes the general timing parameters of the USB interface of the chip.
Table 47. USB General Timing Parameters6
Symbol 1
Min
Max
Unit
Notes
tUSCK
15
—
ns
2-5
Input setup to usb clock - all inputs
tUSIVKH
4
—
ns
2-5
input hold to usb clock - all inputs
tUSIXKH
1
—
ns
2-5
usb clock to output valid - all outputs
tUSKHOV
—
7
ns
2-5
Output hold from usb clock - all outputs
tUSKHOX
2
—
ns
2-5
Parameter
usb clock cycle time
Notes:
1. The symbols for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs
and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes usb timing (US) for
the input (I) to go invalid (X) with respect to the time the usb clock reference (K) goes high (H). Also, tUSKHOX symbolizes USB
timing (US) for the USB clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time.
2. All timings are in reference to USB clock.
3. All signals are measured from OVDD/2 of the rising edge of the USB clock to 0.4 × OVDD of the signal in question for 3.3 V
signaling levels.
4. Input timings are measured at the pin.
5. For active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the
component pin is less than or equal to that of the leakage current specification.
6. When switching the data pins from outputs to inputs using the USBn_DIR pin, the output timings will be violated on that cycle
because the output buffers are tristated asynchronously. This should not be a problem, because the PHY should not be
functionally looking at these signals on that cycle as per ULPI specifications
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This figures provide the AC test load and signals for the USB, respectively.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 36. USB AC Test Load
USB0_CLK/USB1_CLK/DR_CLK
tUSIVKH
tUSIXKH
Input Signals
tUSKHOV
tUSKHOX
Output Signals:
Figure 37. USB Signals
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2.12
Enhanced Local Bus Controller (eLBC)
This section describes the DC and AC electrical specifications for the local bus interface of the chip.
2.12.1
Local Bus DC Electrical Characteristics
This table provides the DC electrical characteristics for the local bus interface operating at BVDD = 3.3 V DC.
Table 48. Local Bus DC Electrical Characteristics (3.3 V DC)
Parameter
Symbol
Min
Max
Unit
BVDD
3.13
3.47
V
High-level input voltage
VIH
1.9
BVDD + 0.3
V
Low-level input voltage
VIL
–0.3
0.8
V
Input current
(BVIN 1 = 0 V or BVIN = BVDD)
IIN
—
±5
μA
High-level output voltage
(BVDD = min, IOH = –2 mA)
VOH
2.4
—
V
Low-level output voltage
(BVDD = min, IOL = 2 mA)
VOL
—
0.4
V
Supply voltage 3.3V
Note:
1. The symbol BVIN, in this case, represents the BVIN symbol referenced in Table 1.
This table provides the DC electrical characteristics for the local bus interface operating at BVDD = 2.5 V DC.
Table 49. Local Bus DC Electrical Characteristics (2.5 V DC)
Parameter
Symbol
Min
Max
Unit
BVDD
2.37
2.63
V
High-level input voltage
VIH
1.70
BVDD + 0.3
V
Low-level input voltage
VIL
–0.3
0.7
V
Input current
(BVIN 1 = 0 V or BVIN = BVDD)
IIH
—
10
μA
Supply voltage 2.5V
IIL
–15
High-level output voltage
(BVDD = min, IOH = –1 mA)
VOH
2.0
BVDD + 0.3
V
Low-level output voltage
(BVDD = min, IOL = 1 mA)
VOL
GND – 0.3
0.4
V
Note:
1. Note that the symbol BVIN, in this case, represents the BVIN symbol referenced in Table 1.
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This table provides the DC electrical characteristics for the local bus interface operating at BVDD = 1.8 V DC.
Table 50. Local Bus DC Electrical Characteristics (1.8 V DC)
Parameter
Symbol
Condition
Min
Max
Unit
BVDD
—
1.71
1.89
V
High-level input voltage
VIH
—
0.65*BVDD
0.3+BVDD
V
Low-level input voltage
VIL
—
–0.3
0.35*BVDD
V
Input current
(BVIN 1 = 0 V or BVIN = BVDD)
IIN
—
-15
10
μA
VOH
IOH = –100 μA
BVDD – 0.2
—
V
IOH = –2 mA
BVDD – 0.45
—
IOH = 100 μA
—
0.2
IOH = 2 mA
—
0.45
Supply voltage 1.8V
High-level output voltage
Low-level output voltage
VOL
V
Note:
1. Note that the symbol BVIN, in this case, represents the BVIN symbol referenced in Table 1.
2.12.2
Local Bus AC Electrical Specifications
This table describes the general timing parameters of the local bus interface at BVDD = 3.3 V DC. For information about the
frequency range of local bus see Section 2.23.1, “Clock Ranges.”
Table 51. Local Bus General Timing Parameters (BVDD = 3.3 V DC)
Symbol 1
Min
Max
Unit
Notes
Local bus cycle time
tLBK
7.5
12
ns
2
Local bus duty cycle
tLBKH/tLBK
43
57
%
—
LCLK[n] skew to LCLK[m] or LSYNC_OUT
tLBKSKEW
150
ps
7
Input setup to local bus clock (except LUPWAIT)
tLBIVKH1
1.8
—
ns
3, 4
LUPWAIT input setup to local bus clock
tLBIVKH2
1.7
—
ns
3, 4
Input hold from local bus clock (except LUPWAIT)
tLBIXKH1
1.0
—
ns
3, 4
LUPWAIT input hold from local bus clock
tLBIXKH2
1.0
—
ns
3, 4
LALE output transition to LAD/LDP output transition (LATCH setup and hold time)
tLBOTOT
1.5
—
ns
6
Local bus clock to output valid (except LAD/LDP and LALE)
tLBKHOV1
—
2.3
ns
—
Local bus clock to data valid for LAD/LDP
tLBKHOV2
—
2.4
ns
3
Local bus clock to address valid for LAD
tLBKHOV3
—
2.3
ns
3
Local bus clock to LALE assertion
tLBKHOV4
—
2.3
ns
3
Output hold from local bus clock (except LAD/LDP and LALE)
tLBKHOX1
0.7
—
ns
3
Parameter
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Table 51. Local Bus General Timing Parameters (BVDD = 3.3 V DC) (continued)
Symbol 1
Min
Max
Unit
Notes
Output hold from local bus clock for LAD/LDP
tLBKHOX2
0.7
—
ns
3
Local bus clock to output high Impedance (except LAD/LDP and LALE)
tLBKHOZ1
—
2.5
ns
5
Local bus clock to output high impedance for LAD/LDP
tLBKHOZ2
—
2.5
ns
5
Parameter
Note:
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for
clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the
output (O) going invalid (X) or output hold time.
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.
3. All signals are measured from BVDD/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL
bypass mode to 0.4 × BVDD of the signal in question for 3.3-V signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through
the component pin is less than or equal to the leakage current specification.
6.tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is guaranteed
with LBCR[AHD] = 0.
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at BVDD/2.
This table describes the general timing parameters of the local bus interface at BVDD = 2.5 V DC.
Table 52. Local Bus General Timing Parameters (BVDD = 2.5 V DC)
Parameter
Configuration Symbol 1
Min
Max
Unit
Notes
Local bus cycle time
—
tLBK
7.5
12
ns
2
Local bus duty cycle
—
tLBKH/tLBK
43
57
%
—
LCLK[n] skew to LCLK[m] or LSYNC_OUT
—
tLBKSKEW
—
150
ps
7
Input setup to local bus clock (except LUPWAIT)
—
tLBIVKH1
1.9
—
ns
3, 4
LUPWAIT input setup to local bus clock
—
tLBIVKH2
1.8
—
ns
3, 4
Input hold from local bus clock (except LUPWAIT)
—
tLBIXKH1
1.1
—
ns
3, 4
LUPWAIT input hold from local bus clock
—
tLBIXKH2
1.1
—
ns
3, 4
LALE output transition to LAD/LDP output transition (LATCH
setup and hold time)
—
tLBOTOT
1.5
—
ns
6
Local bus clock to output valid (except LAD/LDP and LALE)
—
tLBKHOV1
—
2.4
ns
—
Local bus clock to data valid for LAD/LDP
—
tLBKHOV2
—
2.5
ns
3
Local bus clock to address valid for LAD
—
tLBKHOV3
—
2.4
ns
3
Local bus clock to LALE assertion
—
tLBKHOV4
—
2.4
ns
3
Output hold from local bus clock (except LAD/LDP and LALE)
—
tLBKHOX1
0.8
—
ns
3
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Electrical Characteristics
Table 52. Local Bus General Timing Parameters (BVDD = 2.5 V DC) (continued)
Parameter
Configuration Symbol 1
Min
Max
Unit
Notes
Output hold from local bus clock for LAD/LDP
—
tLBKHOX2
0.8
—
ns
3
Local bus clock to output high Impedance (except LAD/LDP
and LALE)
—
tLBKHOZ1
—
2.6
ns
5
Local bus clock to output high impedance for LAD/LDP
—
tLBKHOZ2
—
2.6
ns
5
Note:
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for
clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the
output (O) going invalid (X) or output hold time.
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.
3. All signals are measured from BVDD/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL
bypass mode to 0.4 × BVDD of the signal in question for 2.5-V signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through
the component pin is less than or equal to the leakage current specification.
6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is guaranteed
with LBCR[AHD] = 0.
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at BVDD/2.
This table describes the general timing parameters of the local bus interface at BVDD = 1.8 V DC.
Table 53. Local Bus General Timing Parameters (BVDD = 1.8 V DC)
Parameter
Configuration Symbol 1
Min
Max
Unit
Notes
2
Local bus cycle time
—
tLBK
7.5
12
ns
Local bus duty cycle
—
tLBKH/tLBK
43
57
%
LCLK[n] skew to LCLK[m] or LSYNC_OUT
—
tLBKSKEW
150
ps
7
Input setup to local bus clock (except LUPWAIT)
—
tLBIVKH1
2.4
—
ns
3, 4
LUPWAIT input setup to local bus clock
—
tLBIVKH2
1.9
—
ns
3, 4
Input hold from local bus clock (except LUPWAIT)
—
tLBIXKH1
1.1
—
ns
3, 4
LUPWAIT input hold from local bus clock
—
tLBIXKH2
1.1
—
ns
3, 4
LALE output transition to LAD/LDP output transition (LATCH
setup and hold time)
—
tLBOTOT
1.2
—
ns
6
Local bus clock to output valid (except LAD/LDP and LALE)
—
tLBKHOV1
—
3.2
ns
—
Local bus clock to data valid for LAD/LDP
—
tLBKHOV2
—
3.2
ns
3
Local bus clock to address valid for LAD
—
tLBKHOV3
—
3.2
ns
3
Local bus clock to LALE assertion
—
tLBKHOV4
—
3.2
ns
3
Output hold from local bus clock (except LAD/LDP and LALE)
—
tLBKHOX1
0.9
—
ns
3
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Table 53. Local Bus General Timing Parameters (BVDD = 1.8 V DC) (continued)
Configuration Symbol 1
Parameter
Min
Max
Unit
Notes
Output hold from local bus clock for LAD/LDP
—
tLBKHOX2
0.9
—
ns
3
Local bus clock to output high Impedance (except LAD/LDP
and LALE)
—
tLBKHOZ1
—
2.6
ns
5
Local bus clock to output high impedance for LAD/LDP
—
tLBKHOZ2
—
2.6
ns
5
Note:
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for
clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the
output (O) going invalid (X) or output hold time.
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.
3. All signals are measured from BVDD/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL
bypass mode to 0.4 × BVDD of the signal in question for 1.8-V signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through
the component pin is less than or equal to the leakage current specification.
6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is guaranteed
with LBCR[AHD] = 0.
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at BVDD/2.
This figure provides the AC test load for the local bus.
Figure 38. Local Bus AC Test Load
Output
Z0 = 50 Ω
RL = 50 Ω
BVDD/2
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This figures show the local bus signals.
LSYNC_IN
tLBIXKH1
tLBIVKH1
Input Signals:
LAD[0:31]/LDP[0:3]
tLBIXKH2
tLBIVKH2
Input Signal:
LGTA
UPM Mode Input Signal:
LUPWAIT
tLBKHOV1
tLBKHOZ1
tLBKHOX1
tLBKHOV2
tLBKHOZ2
tLBKHOX2
Output Signals:
LA[27:31]/LBCTL/LOE
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
tLBKHOV3
tLBKHOZ2
tLBKHOX2
Output (Address) Signal:
LAD[0:31]
tLBOTOT
tLBKHOV4
LALE
Figure 39. Local Bus Signals, Non-Special Signals Only (PLL Enabled)
NOTE
In PLL bypass mode, some signals are launched and captured on the opposite edge of
LCLK[n] to that used in PLL Enable Mode. In this mode, output signals are launched at the
falling edge of the LCLK[n] and inputs signals are captured at the rising edge of LCLK[n]
with the exception of LGTA/LUPWAIT (which is captured at the falling edge of the
LCLK[n]).
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LCLK[n]
tLBIVKH1
tLBIXKH1
Input Signals:
LAD[0:31]/LDP[0:3]
Input Signal:
LGTA
tLBIVKL2
tLBIXKL2
UPM Mode Input Signal:
LUPWAIT
tLBKLOV1
tLBKLOZ1
tLBKLOX1
Output Signals:
LA[27:31]/LBCTL/LOE
tLBKLOZ2
tLBKLOV2
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
tLBKLOX2
tLBKLOV3
Output (Address) Signal:
LAD[0:31]
tLBKLOV4
tLBOTOT
LALE
Figure 40. Local Bus Signals (PLL Bypass Mode)
This table describes the general timing parameters of the local bus interface at VDD = 3.3 V DC with PLL disabled.
Table 54. Local Bus General Timing Parameters—PLL Bypassed
Symbol 1
Min
Max
Unit
Notes
Local bus cycle time
tLBK
12
—
ns
2
Local bus duty cycle
tLBKH/tLBK
43
57
%
—
Input setup to local bus clock (except LUPWAIT)
tLBIVKH1
5.1
—
ns
4, 5
LUPWAIT input setup to local bus clock
tLBIVKL2
4.2
—
ns
4, 5
Input hold from local bus clock (except LUPWAIT)
tLBIXKH1
-1.4
—
ns
4, 5
LUPWAIT input hold from local bus clock
tLBIXKL2
-2.0
—
ns
4, 5
LALE output transition to LAD/LDP output transition (LATCH hold time)
tLBOTOT
1.4
—
ns
6
Local bus clock to output valid (except LAD/LDP and LALE)
tLBKLOV1
—
0.5
ns
4
Parameter
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71
Electrical Characteristics
Table 54. Local Bus General Timing Parameters—PLL Bypassed (continued)
Symbol 1
Min
Max
Unit
Notes
Local bus clock to data valid for LAD/LDP
tLBKLOV2
—
0.5
ns
4
Local bus clock to address valid for LAD, and LALE
tLBKLOV3
—
0.5
ns
4
Local bus clock to LALE assertion
tLBKLOV4
—
0.5
ns
4
Output hold from local bus clock (except LAD/LDP and LALE)
tLBKLOX1
—
2.2
ns
4,8
Output hold from local bus clock for LAD/LDP
tLBKLOX2
—
2.2
ns
4,8
Local bus clock to output high Impedance (except LAD/LDP and LALE)
tLBKLOZ1
—
0.1
ns
7
Local bus clock to output high impedance for LAD/LDP
tLBKLOZ2
—
0.1
ns
7
Parameter
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for
clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the
output (O) going invalid (X) or output hold time.
2. All timings are in reference to local bus clock for PLL bypass mode.
3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at BVDD/2.
4. All signals are measured from BVDD/2 of the rising edge of local bus clock for PLL bypass mode to 0.4 x BVDD of the signal
in question for 3.3-V signaling levels.
5. Input timings are measured at the pin.
6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is guaranteed
with LBCR[AHD] = 0.
7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through
the component pin is less than or equal to the leakage current specification.
8. These timing parameters for PLL bypass mode are defined in the opposite direction of the PLL enabled output hold timing
parameters.
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Freescale Semiconductor
Electrical Characteristics
LSYNC_IN
T1
T3
tLBKHOV1
tLBKHOZ1
GPCM Mode Output Signals:
LCS[0:7]/LWE
GPCM Mode Input Signal:
LGTA
tLBIVKH2
tLBIXKH2
UPM Mode Input Signal:
LUPWAIT
tLBIVKH1
tLBIXKH1
Input Signals:
LAD[0:31]/LDP[0:3]
tLBKHOV1
tLBKHOZ1
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 41. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4(PLL Enabled)
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Freescale Semiconductor
73
Electrical Characteristics
LSYNC_IN
T1
T2
T3
T4
tLBKHOZ1
tLBKHOV1
GPCM Mode Output Signals:
LCS[0:7]/LWE
GPCM Mode Input Signal
LGTA
tLBIXKH2
tLBIVKH2
UPM Mode Input Signal:
LUPWAIT
tLBIXKH1
tLBIVKH1
Input Signals:
LAD[0:31]/LDP[0:3]
(PLL Bypass Mode)
tLBKHOZ1
tLBKHOV1
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 42. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 8 or 16(PLL Enabled)
2.13
Enhanced Secure Digital Host Controller (eSDHC)
This section describes the DC and AC electrical specifications for the eSDHC interface of the chip.
2.13.1
eSDHC DC Electrical Characteristics
This table provides the DC electrical characteristics for the eSDHC interface of the chip.
Table 55. eSDHC interface DC Electrical Characteristics
At recommended operating conditions (see Table 3)
Characteristic
Symbol
Condition
Min
Max
Unit
Notes
Input high voltage
VIH
—
0.625 * OVDD
OVDD+0.3
V
—
Input low voltage
VIL
—
–0.3
0.25 * OVDD
V
—
IIN/IOZ
—
–10
10
uA
—
—
V
—
Input/Output leakage current
Output high voltage
VOH
IOH = -100 uA @OVDDmin 0.75 * OVDD
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Freescale Semiconductor
Electrical Characteristics
Table 55. eSDHC interface DC Electrical Characteristics (continued)
At recommended operating conditions (see Table 3)
Characteristic
Symbol
Condition
Min
Max
Unit
Notes
Output low voltage
VOL
IOL = 100uA @OVDDmin
—
0.125 * OVDD
V
—
Output high voltage
VOH
IOH = -100 uA
OVDD - 0.2
—
—
2
Output low voltage
VOL
IOL = 2 mA
—
0.3
—
2
Notes:
1. The min VIL and VIH values are based on the respective min and max OVIN values found in Table 3.
2. Open drain mode for MMC cards only.
2.13.2
eSDHC AC Timing Specifications
This table provides the eSDHC AC timing specifications as defined in the following figure.
Table 56. eSDHC AC Timing Specifications
At recommended operating conditions (see Table 3)
Parameter
Symbol1
SD_CLK clock frequency:
SD/SDIO Full speed/high speed mode
MMC Full speed/high speed mode
fSHSCK
SD_CLK clock frequency - identification mode
Min
Max
Unit
Notes
0
25/50
20/52
MHz
2, 5
fSIDCK
0
100
400
KHz
3, 5
SD_CLK clock low time - High speed/Full speed mode
tSHSCKL
7/10
—
ns
5
SD_CLK clock high time - High speed/Full speed mode
tSHSCKH
7/10
—
ns
5
SD_CLK clock rise and fall times
tSHSCKR/
tSHSCKF
—
3
ns
5
Input setup times: SD_CMD, SD_DATx, SD_CD to
SD_CLK
tSHSIVKH
2.5
—
ns
4,5,6
Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK
tSHSIXKH
2.5
—
ns
5,6
Output delay time: SD_CLK to SD_CMD, SD_DATx valid
tSHSKHOV
–3
3
ns
5,6
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFHSKHOV symbolizes eSDHC
high speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the output (O) reaching
the invalid state (X) or output hold time. Note that, in general, the clock reference symbol representation is based on five letters
representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter:
R (rise) or F (fall).
2. In full speed mode, clock frequency value can be 0–25 MHz for a SD/SDIO card and 0–20 MHz for a MMC card. In high speed
mode, clock frequency value can be 0–50 MHz for a SD/SDIO card and 0–52MHz for a MMC card.
3. 0 Hz means to stop the clock. The given minimum frequency range is for cases were a continuous clock is required.
4. To satisfy setup timing, one way board routing delay between Host and Card, on SD_CLK, SD_CMD and SD_DATx should
not exceed 1 ns.
5. CCARD ≤10 pF, (1 card), and CL = CBUS + CHOST+CCARD ≤ 40 pF
6. The parameter values apply to both full speed and high speed modes.
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Freescale Semiconductor
75
Electrical Characteristics
This figure provides the eSDHC clock input timing diagram.
eSDHC
External Clock
operational mode
VM
VM
VM
tSHSCKL
tSHSCKH
tSHSCK
tSHSCKR
VM = Midpoint Voltage (OVDD/2)
tSHSCKF
Figure 43. eSDHC Clock Input Timing Diagram
This figure provides the data and command input/output timing diagram.
SD_CK
External Clock
VM
VM
VM
VM
tSHSIXKH
tSHSIVKH
SD_DAT/CMD
Inputs
SD_DAT/CMD
Outputs
tSHSKHOV
VM = Midpoint Voltage (OVDD/2)
Figure 44. eSDHC Data and Command Input/Output Timing Diagram Referenced to Clock
2.14
Programmable Interrupt Controller (PIC)
In IRQ edge trigger mode, when an external interrupt signal is asserted (according to the programmed polarity), it must remain
the assertion for at least 3 system clocks (SYSCLK periods).
2.15
JTAG
This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the chip.
2.15.1
JTAG DC Electrical Characteristics
This table provides the DC electrical characteristics for the JTAG interface.
Table 57. JTAG DC Electrical Characteristics
Symbol 1
Min
Max
Unit
High-level input voltage
VIH
2
OVDD + 0.3
V
Low-level input voltage
VIL
-0.3
0.8
V
Parameter
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Freescale Semiconductor
Electrical Characteristics
Table 57. JTAG DC Electrical Characteristics (continued)
Symbol 1
Min
Max
Unit
IIN
—
±5
μA
High-level output voltage
(OVDD = min, IOH = -2 mA)
VOH
2.4
—
V
Low-level output voltage
(OVDD = min, IOL = 2 mA)
VOL
—
0.4
V
Parameter
Input current
(VIN1 = 0 V or VIN = VDD)
Notes:
1. Note that the symbol VIN, in this case, represents the OVIN.
2.15.2
JTAG AC Electrical Specifications
This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the chip.
This table provides the JTAG AC timing specifications as defined in the following figures.
Table 58. JTAG AC Timing Specifications (Independent of SYSCLK)
At recommended operating conditions (see Table 3).
Symbol 1
Min
Max
Unit
Notes
JTAG external clock frequency of operation
fJTG
0
33.3
MHz
—
JTAG external clock cycle time
t JTG
30
—
ns
—
tJTKHKL
15
—
ns
—
tJTGR & tJTGF
0
2
ns
—
TRST assert time
tTRST
25
—
ns
2
Input setup times:
tJTDVKH
4
—
ns
Input hold times:
tJTDXKH
10
—
ns
Output Valid times:
tJTKLDV
—
10
ns
3
Output hold times:
tJTKLDX
0
—
ns
3
Parameter
JTAG external clock pulse width measured at 1.4 V
JTAG external clock rise and fall times
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG
device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference
(K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input
signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock
reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3.) The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays
must be added for trace lengths, vias, and connectors in the system.
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Freescale Semiconductor
77
Electrical Characteristics
This figure provides the AC test load for TDO and the boundary-scan outputs.
Z0 = 50 Ω
Output
RL = 50 Ω
OVDD/2
Figure 45. AC Test Load for the JTAG Interface
This figure provides the JTAG clock input timing diagram.
JTAG
External Clock
VM
VM
VM
tJTGR
tJTKHKL
tJTGF
tJTG
VM = Midpoint Voltage (OVDD/2)
Figure 46. JTAG Clock Input Timing Diagram
This figure provides the TRST timing diagram.
TRST
VM
VM
tTRST
VM = Midpoint Voltage (OVDD/2)
Figure 47. TRST Timing Diagram
This figure provides the boundary-scan timing diagram.
JTAG
External Clock
VM
VM
tJTDVKH
tJTDXKH
Boundary
Data Inputs
Input
Data Valid
tJTKLDV
tJTKLDX
Boundary
Data Outputs
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Figure 48. Boundary-Scan Timing Diagram
2.16
Serial ATA (SATA)
This section describes the DC and AC electrical specifications for the serial ATA (SATA) of the chip. Note that the external
cabled applications or long backplane applications (Gen1x & Gen2x) are not supported.
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78
Freescale Semiconductor
Electrical Characteristics
2.16.1
Requirements for SATA REF_CLK
The AC requirements for the SATA reference clock are listed in the following table.
Table 59. Reference Clock Input Requirements
Parameter
Symbol
Min
Typical
Max
Unit
Notes
SD2_REF_CLK/_B reference clock cycle time
tCLK_REF
100
—
150
MHz
1
SD2_REF_CLK/_B frequency tolerance
tCLK_TOL
–350
0
+350
ppm
—
tCLK_RISE/tCLK_FALL
—
—
1
ns
—
tCLK_DUTY
45
50
55
%
—
SD_REF_CLK/_B cycle to cycle clock jitter (period jitter)
tCLK_CJ
—
—
100
ps
—
SD_REF_CLK/_B phase jitter (peak-to-peak)
tCLK_PJ
–50
—
+50
ps
2,3
SD_REF_CLK/_B rise/fall time (80%-20%)
SD_REF_CLK/_B duty cycle (@50% X2VDD)
Note:
1. Only 100/125/150 MHz have been tested, other in between values will not work correctly with the rest of the system.
2. In a frequency band from 150 kHz to 15 MHz, at BER of 10E-12.
3. Total peak-to-peak deterministic jitter “Dj” should be less than or equal to 50 ps.
TH
Ref_CLK
TL
Figure 49. Reference Clock Timing Waveform
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
79
Electrical Characteristics
2.16.2
Differential Transmitter (TX) Output Characteristics
This table provides the differential transmitter (TX) output characteristics for the SATA interface.
Table 60. Differential Transmitter (TX) Output Characteristics
Parameter
Symbol
Min
Typical
Max
Units
tCH_SPEED
—
1.5
3.0
—
Gbps
TUI
666.4333
333.2167
666.4333
333.3333
670.2333
335.1167
ps
Vdc_cm
200
250
450
mV
TX Diff Output Voltage
1.5G
3.0G
VSATA_TXDIFF
400
400
500
—
600
700
mV
TX rise/fall time
1.5G
3.0G
tSATA_20-80TX
100
67
—
—
273
136
ps
TX differential skew
tSATA_TXSKEW
—
—
20
ps
TX Differential pair
impedance
1.5G
ZSATA_TXDIFFIM
Channel Speed
1.5G
3.0G
Unit Interval
1.5G
3.0G
Notes
—
—
DC Coupled
Common Mode
Voltage
TX Single ended
impedance
1.5G
TX AC common mode
voltage (peak to peak)
1.5G
3.0G
3
—
—
—
—
ohm
85
—
115
—
ZSATA_TXSEIM
ohm
40
—
—
—
VSATA_TXCMMOD
—
—
—
—
—
50
mV
OOB Differential Delta
VSATA_OOBvdoff
—
—
25
mV
1
OOB Common mode
Delta
VSATA_OOBcm
—
—
50
mV
1
TX Rise/Fall Imbalance
TSATA_TXR/Fbal
—
—
20
%
—
TX Amplitude Imbalance
TSATA_TXampbal
—
—
10
%
—
RLSATA_TXDD11
—
—
—
—
—
—
14
8
6
dB
—
—
—
—
—
—
TX Differential Mode
Return loss
150 MHz - 300 MHz
300 MHz - 600 MHz
600 MHz - 1.2 GHz
1.2 GHz - 2.4 GHz
2.4 GHz - 3.0 GHz
3.0 GHz - 5.0 GHz
1, 2
6
3
1
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Freescale Semiconductor
Electrical Characteristics
Table 60. Differential Transmitter (TX) Output Characteristics (continued)
Parameter
TX Common Mode Return
loss
150 MHz - 300 MHz
300 MHz - 600 MHz
600 MHz - 1.2 GHz
Symbol
Min
Typical
Max
Units
RLSATA_TXCC11
—
—
—
—
—
—
5
5
2
dB
—
—
—
—
—
—
2
1
1
—
—
—
—
—
—
30
20
10
—
—
—
—
—
—
10
4
4
1.2 GHz - 2.4 GHz
2.4 GHz - 3.0 GHz
3.0 GHz - 5.0 GHz
Notes
1, 2
TX Impedance Balance
150 MHz - 300 MHz
300 MHz - 600 MHz
600 MHz - 1.2 GHz
1, 2
dB
RLSATA_TXDC11
1.2 GHz - 2.4 GHz
2.4 GHz - 3.0 GHz
3.0 GHz - 5.0 GHz
—
Deterministic jitter
1.5G
3.0G
USATA_TXDJ
—
—
0.18
0.14
UI
Total Jitter
1.5G
3.0G
USATA_TXTJ
—
—
0.42
0.32
UI
—
Notes:
1. Only applies when operating in 3.0Gb data rate mode.
2. The max value stated for 3.0 GHz - 5.0 GHz range only applies to Gen2i mode and not to Gen2m mode.
3. Only applies to Gen1i mode.
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Freescale Semiconductor
81
Electrical Characteristics
80%
80%
Differential
data lines
20%
20%
tSATA_20-80TXfall
tSATA_20-80TXrise
TX+
TX+
TX-
TX-
tSAT_TXSKEW
tSAT_TXSKEW
EARLY (TX+ is early)
LATE (TX+ is late)
Figure 50. Signal Rise and Fall Times and Differential Skew
2.16.3
Differential Receiver (RX) Input Characteristics
This table provides the differential receiver (RX) input characteristics for the SATA interface.
Table 61. Differential Receiver (RX) Input Characteristics
Parameter
RX Differential Input
Voltage
1.5G
3.0G
Symbol
Min
Typical
Max
Units
240
240
400
—
600
750
mVp-p
ps
VSATA_RXDIFF
1
RX rise/fall time
1.5G
3.0G
tSATA_20-80RX
100
67
—
—
273
136
RX Differential skew
1.5G
3.0G
tSATA_RXSKEW
—
—
—
—
—
50
—
RX Differential pair
impedance
1.5G
RX Single-Ended
impedance
1.5G
DC Coupled
Common Mode
Voltage
Notes
—
ps
—
ZSATA_RXDIFFIM
85
—
115
ohm
—
ZSATA_RXSEIM
ohm
40
—
—
200
250
450
5
Vdc_cm
mV
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Freescale Semiconductor
Electrical Characteristics
Table 61. Differential Receiver (RX) Input Characteristics (continued)
Parameter
RX Differential Mode
Return loss
150 MHz - 300 MHz
300 MHz - 600 MHz
600 MHz - 1.2 GHz
Symbol
Typical
Max
Units
Notes
2, 3
RLSATA_RXDD11
1.2 GHz - 2.4 GHz
2.4 GHz - 3.0 GHz
3.0 GHz - 5.0 GHz
RX Common Mode
Return loss
150 MHz - 300 MHz
300 MHz - 600 MHz
600 MHz - 1.2 GHz
Min
—
—
—
—
—
—
18
14
10
—
—
—
—
—
—
8
3
1
dB
2, 3, 4
RLSATA_RXCC11
1.2 GHz - 2.4 GHz
2.4 GHz - 3.0 GHz
3.0 GHz - 5.0 GHz
—
—
—
—
—
—
5
5
2
—
—
—
—
—
—
2
2
1
dB
2, 3
RX Impedance Balance
150 MHz - 300 MHz
300 MHz - 600 MHz
600 MHz - 1.2 GHz
—
—
—
—
—
—
30
30
20
—
—
—
—
—
—
10
4
4
dB
RLSATA_RXDC11
1.2 GHz - 2.4 GHz
2.4 GHz - 3.0 GHz
3.0 GHz - 5.0 GHz
—
Deterministic jitter
1.5G
3.0G
USATA_RXDJ
—
—
0.4
0.47
UI
Total Jitter
1.5G
3.0G
USATA_RXTJ
—
—
0.65
0.65
UI
—
Notes:
1. The min values apply only to Gen1m, and Gen2m. the min values for Gen1i is 325 mVp-p and for Gen2i is 275 mVp-p.
2. Only applies when operating in 3.0Gb data rate mode.
3. The max value stated for 3.0 GHz - 5.0 GHz range only applies to Gen2i mode and not to Gen2m mode.
4. The max value stated for 2.4 GHz - 3.0 GHz range only applies to Gen2i mode for Gen2m the value is 1.
5. Only applies to Gen1i mode.
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Freescale Semiconductor
83
Electrical Characteristics
2.16.4
Out-of-Band (OOB) Electrical Characteristics
This table provides the Out-of-Band (OOB) electrical characteristics for the SATA interface of the chip.
Table 62. Out-of-Band (OOB) Electrical Characteristics
Parameter
Symbol
OOB Signal Detection Threshold
1.5G
3.0G
Min
Typical
Max
Units
—
UI During OOB Signaling
COMINIT/ COMRESET and COMWAKE
Transmit Burst Length
VSATA_OOBDETE
50
75
100
125
200
200
mVp-p
TSATA_UIOOB
646.67
666.67
686.67
ps
TSATA_UIOOBTXB
—
160
—
UI
—
480
—
UI
WakeGap
—
160
—
UI
TSATA_OOBDet
55
—
175
ns
—
175
—
525
ns
—
—
ap
COMWAKE Gap Detection Windows
—
—
COMINIT/ COMRESET Transmit Gap Length TSATA_UIOOBTXG
COMWAKE Transmit Gap Length
Notes
TSATA_UIOOBTX
—
WakeGap
COMINIT/ COMRESET
Gap Detection Windows
2.17
TSATA_OOBDet
COMGap
I2C
This section describes the DC and AC electrical characteristics for the I2C interfaces of the chip.
2.17.1
I2C DC Electrical Characteristics
This table provides the DC electrical characteristics for the I2C interfaces.
Table 63. I2C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
OVDD
3.13
3.47
V
—
Input high voltage level
VIH
0.7 × OVDD
OVDD + 0.3
V
—
Input low voltage level
VIL
–0.3
0.3 × OVDD
V
—
Low level output voltage
VOL
0
0.2 × OVDD
V
1
Supply voltage 3.3 V
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Freescale Semiconductor
Electrical Characteristics
Table 63. I2C DC Electrical Characteristics (continued)
At recommended operating conditions with OVDD of 3.3 V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
Pulse width of spikes which must be suppressed by the input
filter
tI2KHKL
0
50
ns
2
Input current each I/O pin (input voltage is between 0.1 ×
OVDD and 0.9 × OVDD(max)
II
–10
10
μA
3
Capacitance for each I/O pin
CI
—
10
pF
—
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. See the MPC8536E PowerQUICC III Integrated Processor Reference Manual for information on the digital filter used.
3. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.
2.17.2
I2C AC Electrical Specifications
This table provides the AC timing parameters for the I2C interfaces.
Table 64. I2C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 63).
Symbol 1
Min
Max
Unit
Notes
SCL clock frequency
fI2C
0
400
kHz
—
Low period of the SCL clock
tI2CL
1.3
—
μs
—
High period of the SCL clock
tI2CH
0.6
—
μs
—
Setup time for a repeated START condition
tI2SVKH
0.6
—
μs
—
Hold time (repeated) START condition (after this period, the first
clock pulse is generated)
tI2SXKL
0.6
—
μs
—
Data setup time
tI2DVKH
100
—
ns
—
μs
2
—
0
—
—
Parameter
tI2DXKL
Data hold time:
CBUS compatible masters
I2C bus devices
Data output delay time
tI2OVKL
—
0.9
μs
3
Set-up time for STOP condition
tI2PVKH
0.6
—
μs
—
Rise time of both SDA and SCL signals
tI2CR
—
300
ns
4
Fall time of both SDA and SCL signals
tI2CF
—
300
ns
4
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Table 64. I2C AC Electrical Specifications (continued)
All values refer to VIH (min) and VIL (max) levels (see Table 63).
Symbol 1
Min
Max
Unit
Notes
tI2KHDX
1.3
—
μs
—
Noise margin at the LOW level for each connected device
(including hysteresis)
VNL
0.1 × OVDD
—
V
—
Noise margin at the HIGH level for each connected device
(including hysteresis)
VNH
0.2 × OVDD
—
V
—
Parameter
Bus free time between a STOP and START condition
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing
(I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the
high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start condition
(S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
2. As a transmitter, the chip provides a delay time of at least 300 ns for the SDA signal (referred to the Vihmin of the SCL signal)
to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition. When the
chip acts as the I2C bus master while transmitting, the chip drives both SCL and SDA. As long as the load on SCL and SDA
are balanced, the chip would not cause unintended generation of Start or Stop condition. Therefore, the 300 ns SDA output
delay time is not a concern. For details of the I2C frequency calculation, refer to Determining the I2C Frequency Divider Ratio
for SCL (AN2919). Note that the I2C Source Clock Frequency is half of the CCB clock frequency for the chip.
3. The maximum tI2DVKH has only to be met if the chip does not stretch the LOW period (tI2CL) of the SCL signal.
4. CB = capacitance of one bus line in pF.
This figure provides the AC test load for the I2C.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 51. I2C AC Test Load
This figure shows the AC timing diagram for the I2C bus.
SDA
tI2CF
tI2DVKH
tI2CL
tI2KHKL
tI2SXKL
tI2CF
tI2CR
SCL
tI2SXKL
S
tI2CH
tI2DXKL, tI2OVKL
tI2SVKH
Sr
tI2PVKH
P
S
Figure 52. I2C Bus AC Timing Diagram
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2.18
GPIO
This section describes the DC and AC electrical specifications for the GPIO interface of the chip.
2.18.1
GPIO DC Electrical Characteristics
This table provides the DC electrical characteristics for the GPIO interface.
Table 65. GPIO DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2
OVDD + 0.3
V
Low-level input voltage
VIL
– 0.3
0.8
V
Input current
(VIN 1 = 0 V or VIN = VDD)
IIN
—
±5
μA
High-level output voltage
(OVDD = min, IOH = –2 mA)
VOH
2.4
—
V
Low-level output voltage
(OVDD = min, IOL = 2 mA)
VOL
—
0.4
V
Note:
1. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
2.18.2
GPIO AC Electrical Specifications
This table provides the GPIO input and output AC timing specifications.
Table 66. GPIO Input and Output AC Timing Specifications1
Characteristic
GPIO inputs—minimum pulse width
GPIO outputs—minimum pulse width
Symbol 2
Min
Unit
Notes
tPIWID
7.5
ns
3
tGTOWID
12
ns
—
Notes:
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings
are measured at the pin.
2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any
external synchronous logic. GPIO inputs are required to be valid for at least tPIWID ns to ensure proper operation.
3. The minimum pulse width is a function of the MPX/Platform clock. The minimum pulse width must be greater than or equal
to 4 times the MPX/Platform clock period.
This figure provides the AC test load for the GPIO.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 53. GPIO AC Test Load
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2.19
PCI
This section describes the DC and AC electrical specifications for the PCI bus of the chip.
2.19.1
PCI DC Electrical Characteristics
This table provides the DC electrical characteristics for the PCI interface.
Table 67. PCI DC Electrical Characteristics 1
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2
OVDD + 0.3
V
Low-level input voltage
VIL
–0.3
0.8
V
Input current
(VIN 2 = 0 V or VIN = VDD)
IIN
—
±5
μA
High-level output voltage
(OVDD = min, IOH = –2 mA)
VOH
2.4
—
V
Low-level output voltage
(OVDD = min, IOL = 2 mA)
VOL
—
0.4
V
Notes:
1. Ranges listed do not meet the full range of the DC specifications of the PCI 2.2 Local Bus Specifications.
2. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
2.19.2
PCI AC Electrical Specifications
This section describes the general AC timing parameters of the PCI bus. Note that the SYSCLK signal is used as the PCI input
clock. This table provides the PCI AC timing specifications at 66 MHz.
Table 68. PCI AC Timing Specifications at 66 MHz
Symbol 1
Min
Max
Unit
Notes
SYSCLK to output valid
tPCKHOV
—
6.0
ns
2, 3
Output hold from SYSCLK
tPCKHOX
2.0
—
ns
2
SYSCLK to output high impedance
tPCKHOZ
—
14
ns
2, 4
Input setup to SYSCLK
tPCIVKH
3.0
—
ns
2, 5
Input hold from SYSCLK
tPCIXKH
0
—
ns
2, 5
REQ64 to HRESET 9 setup time
tPCRVRH
10 × tSYS
—
clocks
6, 7
HRESET to REQ64 hold time
tPCRHRX
0
50
ns
7
Parameter
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Table 68. PCI AC Timing Specifications at 66 MHz (continued)
Symbol 1
Min
Max
Unit
Notes
HRESET high to first FRAME assertion
tPCRHFV
10
—
clocks
8
Rise time (20%–80%)
tPCICLK
0.6
2.1
ns
—
Failing time (20%–80%)
tPCICLK
0.6
2.1
ns
—
Parameter
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing
(PC) with respect to the time the input signals (I) reach the valid state (V) relative to the SYSCLK clock, tSYS, reference (K)
going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went
high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.
3. All PCI signals are measured from OVDD/2 of the rising edge of PCI_SYNC_IN to 0.4 × OVDD of the signal in question for 3.3-V
PCI signaling levels.
4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through
the component pin is less than or equal to the leakage current specification.
5. Input timings are measured at the pin.
6. The timing parameter tSYS indicates the minimum and maximum CLK cycle times for the various specified frequencies. The
system clock period must be kept within the minimum and maximum defined ranges. For values see Section 22, “Clocking.”
7. The setup and hold time is with respect to the rising edge of HRESET.
8. The timing parameter tPCRHFV is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local Bus
Specifications.
9. The reset assertion timing requirement for HRESET is 100 μs.
This figure provides the AC test load for PCI.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 54. PCI AC Test Load
This figure shows the PCI input AC timing conditions.
CLK
tPCIVKH
tPCIXKH
Input
Figure 55. PCI Input AC Timing Measurement Conditions
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This figure shows the PCI output AC timing conditions.
CLK
tPCKHOV
Output Delay
tPCKHOZ
High-Impedance
Output
Figure 56. PCI Output AC Timing Measurement Condition
2.20
High-Speed Serial Interfaces
This chip features two Serializer/Deserializer (SerDes) interfaces to be used for high-speed serial interconnect applications. The
SerDes1 interface is dedicated for PCI Express data transfers. The SerDes2 can be used for SGMII or SATA.
This section describes the common portion of SerDes DC electrical specifications, which is the DC requirement for SerDes
Reference Clocks. The SerDes data lane’s transmitter and receiver reference circuits are also shown.
2.20.1
Signal Terms Definition
The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms used in the description
and specification of differential signals.
Figure 57 shows how the signals are defined. For illustration purposes, only one SerDes lane is used for description. The figure
shows waveform for either a transmitter output (SDn_TX and SDn_TX) or a receiver input (SDn_RX and SDn_RX). Each
signal swings between A Volts and B Volts where A > B.
Using this waveform, the definitions are as follows. To simplify illustration, the following definitions assume that the SerDes
transmitter and receiver operate in a fully symmetrical differential signaling environment.
1. Single-Ended Swing
The transmitter output signals and the receiver input signals SDn_TX, SDn_TX, SDn_RX and SDn_RX each have a
peak-to-peak swing of A - B Volts. This is also referred as each signal wire’s Single-Ended Swing.
2. Differential Output Voltage, VOD (or Differential Output Swing):
The Differential Output Voltage (or Swing) of the transmitter, VOD, is defined as the difference of the two complimentary output
voltages: VSDn_TX - VSDn_TX. The VOD value can be either positive or negative.
3. Differential Input Voltage, VID (or Differential Input Swing):
The Differential Input Voltage (or Swing) of the receiver, VID, is defined as the difference of the two complimentary input
voltages: VSDn_RX - VSDn_RX. The VID value can be either positive or negative.
4. Differential Peak Voltage, VDIFFp
The peak value of the differential transmitter output signal or the differential receiver input signal is defined as Differential Peak
Voltage, VDIFFp = |A - B| Volts.
5. Differential Peak-to-Peak, VDIFFp-p
Since the differential output signal of the transmitter and the differential input signal of the receiver each range from A - B to
-(A - B) Volts, the peak-to-peak value of the differential transmitter output signal or the differential
receiver input signal is defined as Differential Peak-to-Peak Voltage, VDIFFp-p = 2*VDIFFp =
2 * |(A - B)| Volts, which is twice of differential swing in amplitude, or twice of the differential
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peak. For example, the output differential peak-peak voltage can also be calculated as VTX-DIFFp-p
= 2*|VOD|.
6. Common Mode Voltage, Vcm
The Common Mode Voltage is equal to one half of the sum of the voltages between each conductor of a balanced interchange
circuit and ground. In this example, for SerDes output, Vcm_out = VSDn_TX + VSDn_TX = (A + B)
/ 2, which is the arithmetic mean of the two complimentary output voltages within a differential
pair. In a system, the common mode voltage may often differ from one component’s output to the
other’s input. Sometimes, it may be even different between the receiver input and driver output
circuits within the same component. It is also referred as the DC offset in some occasion.
SDn_TX or
SDn_RX
A Volts
Vcm = (A + B) / 2
SDn_TX or
SDn_RX
B Volts
Differential Swing, VID or VOD = A – B
Differential Peak Voltage, VDIFFp = |A – B|
Differential Peak-Peak Voltage, VDIFFpp = 2*VDIFFp (not shown)
Figure 57. Differential Voltage Definitions for Transmitter or Receiver
To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common
mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5V and 2.0V. Using these values,
the peak-to-peak voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred as the single-ended swing for each
signal. In this example, since the differential signaling environment is fully symmetrical, the transmitter output’s differential
swing (VOD) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges between 500
mV and –500 mV, in other words, VOD is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage
(VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p.
2.20.2
SerDes Reference Clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding
SerDes lanes. The SerDes reference clocks for PCI Express are SD1_REF_CLK and, SD1_REF_CLK. The SerDes reference
clocks for the SATA and SGMII interfaces are SD2_REF_CLK and, SD2_REF_CLK.
The following sections describe the SerDes reference clock requirements and some application information.
2.20.2.1
SerDes Reference Clock Receiver Characteristics
Figure 58 shows a receiver reference diagram of the SerDes reference clocks.
•
•
The supply voltage requirements for X2VDD are specified in Table 2 and Table 3.
SerDes Reference Clock Receiver Reference Circuit Structure
— The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as shown in Figure 58.
Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a 50-Ω termination to SGND (xcorevss)
followed by on-chip AC-coupling.
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•
•
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. See the Differential Mode and
Single-ended Mode description below for further detailed requirements.
The maximum average current requirement that also determines the common mode voltage range
— When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the
maximum average current allowed for each input pin is 8mA. In this case, the exact common mode input voltage
is not critical as long as it is within the range allowed by the maximum average current of 8 mA (refer to the
following bullet for more detail), since the input is AC-coupled on-chip.
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V/50 = 8 mA)
while the minimum common mode input level is 0.1V above SnGND (xcorevss). For example, a clock with a
50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0mA to 16mA
(0–0.8 V), such that each phase of the differential input has a single-ended swing from 0 V to 800mV with the
common mode voltage at 400mV.
— If the device driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50 Ω to SnGND (xcorevss)
DC, or it exceeds the maximum input current limitations, then it must be AC-coupled off-chip.
The input amplitude requirement
— This requirement is described in detail in the following sections.
50 Ω
SDn_REF_CLK
Input
Amp
SDn_REF_CLK
50 Ω
Figure 58. Receiver of SerDes Reference Clocks
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2.20.2.2
DC Level Requirement for SerDes Reference Clocks
The DC level requirement for the chip’s SerDes reference clock inputs is different depending on the signaling mode used to
connect the clock driver chip and SerDes reference clock inputs as described below.
•
•
Differential Mode
— The input amplitude of the differential clock must be between 400mV and 1600mV differential peak-peak (or
between 200mV and 800mV differential peak). In other words, each signal wire of the differential pair must have
a single-ended swing less than 800mV and greater than 200mV. This requirement is the same for both external
DC-coupled or AC-coupled connection.
— For external DC-coupled connection, as described in Section 2.20.2.1, “SerDes Reference Clock Receiver
Characteristics,” the maximum average current requirements sets the requirement for average voltage (common
mode voltage) to be between 100 mV and 400 mV. Figure 59 shows the SerDes reference clock input requirement
for DC-coupled connection scheme.
— For external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Since
the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock receiver
operate in different command mode voltages. The SerDes reference clock receiver in this connection scheme has
its common mode voltage set to SnGND. Each signal wire of the differential inputs is allowed to swing below and
above the command mode voltage (SnGND). Figure 60 shows the SerDes reference clock input requirement for
AC-coupled connection scheme.
Single-ended Mode
— The reference clock can also be single-ended. The SDn_REF_CLK input amplitude (single-ended swing) must be
between 400mV and 800mV peak-peak (from Vmin to Vmax) with SDn_REF_CLK either left unconnected or
tied to ground.
— The SDn_REF_CLK input average voltage must be between 200 and 400 mV. Figure 61 shows the SerDes
reference clock input requirement for single-ended signaling mode.
— To meet the input amplitude requirement, the reference clock inputs might need to be DC or AC-coupled
externally. For the best noise performance, the reference of the clock could be DC or AC-coupled into the unused
phase (SDn_REF_CLK) through the same source impedance as the clock input (SDn_REF_CLK) in use.
SDn_REF_CLK
200 mV < Input Amplitude or Differential Peak < 800 mV
Vmax < 800 mV
100 mV < Vcm < 400 mV
SDn_REF_CLK
Vmin > 0 V
Figure 59. Differential Reference Clock Input DC Requirements (External DC-Coupled)
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200mV < Input Amplitude or Differential Peak < 800 mV
SDn_REF_CLK
Vmax < Vcm + 400 mV
Vcm
Vmin > Vcm – 400 mV
SDn_REF_CLK
Figure 60. Differential Reference Clock Input DC Requirements (External AC-Coupled)
400 mV < SDn_REF_CLK Input Amplitude < 800 mV
SDn_REF_CLK
0V
SDn_REF_CLK
Figure 61. Single-Ended Reference Clock Input DC Requirements
2.20.2.3
Interfacing With Other Differential Signaling Levels
With on-chip termination to SnGND (xcorevss), the differential reference clocks inputs are HCSL (High-Speed Current
Steering Logic) compatible DC-coupled.
Many other low voltage differential type outputs like LVDS (Low Voltage Differential Signaling) can be used but may need to
be AC-coupled due to the limited common mode input range allowed (100 to 400 mV) for DC-coupled connection.
LVPECL (Low Voltage Positive Emitter-Coupled Logic) outputs can produce signal with too large amplitude and may need to
be DC-biased at clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to
AC-coupling.
NOTE
Figure 62 to Figure 65 below are for conceptual reference only. Due to the fact that clock
driver chip's internal structure, output impedance and termination requirements are
different between various clock driver chip manufacturers, it is very possible that the clock
circuit reference designs provided by clock driver chip vendor are different from what is
shown below. They might also vary from one vendor to the other. Therefore, Freescale
Semiconductor can neither provide the optimal clock driver reference circuits, nor
guarantee the correctness of the following clock driver connection reference circuits. The
system designer is recommended to contact the selected clock driver chip vendor for the
optimal reference circuits with the chip’s SerDes reference clock receiver requirement
provided in this document.
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This figure shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It assumes that the DC
levels of the clock driver chip is compatible with chip’s SerDes reference clock input’s DC requirement.
HCSL CLK Driver Chip
CLK_Out
33 Ω
SDn_REF_CLK
50 Ω
SerDes Refer.
CLK Receiver
100 Ω differential PWB trace
Clock Driver
33 Ω
SDn_REF_CLK
CLK_Out
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
50 Ω
Clock driver vendor dependent
source termination resistor
Figure 62. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)
This figure shows the SerDes reference clock connection reference circuits for LVDS type clock driver. Since LVDS clock
driver’s common mode voltage is higher than the chip’s SerDes reference clock input’s allowed range (100 to 400mV),
AC-coupled connection scheme must be used. It assumes the LVDS output driver features 50-Ω termination resistor. It also
assumes that the LVDS transmitter establishes its own common mode level without relying on the receiver or other external
component.
LVDS CLK Driver Chip
CLK_Out
10 nF
50 Ω
SerDes Refer.
CLK Receiver
100 Ω differential PWB trace
Clock Driver
CLK_Out
SDn_REF_CLK
10 nF
SDn_REF_CLK
50 Ω
Figure 63. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)
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This figure shows the SerDes reference clock connection reference circuits for LVPECL type clock driver. Since LVPECL
driver’s DC levels (both common mode voltages and output swing) are incompatible with chip’s SerDes reference clock input’s
DC requirement, AC-coupling has to be used. This figure assumes that the LVPECL clock driver’s output impedance is 50Ω.
R1 is used to DC-bias the LVPECL outputs prior to AC-coupling. Its value could be ranged from 140Ω to 240Ω depending on
clock driver vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-Ω termination resistor to
attenuate the LVPECL output’s differential peak level such that it meets the chip’s SerDes reference clock’s differential input
amplitude requirement (between 200mV and 800mV differential peak). For example, if the LVPECL output’s differential peak
is 900mV and the desired SerDes reference clock input amplitude is selected as 600mV, the attenuation factor is 0.67, which
requires R2 = 25Ω. Please consult clock driver chip manufacturer to verify whether this connection scheme is compatible with
a particular clock driver chip.
LVPECL CLK
Driver Chip
CLK_Out
10nF
R2
SDn_REF_CLK
50 Ω
SerDes Refer.
CLK Receiver
R1 100 Ω differential PWB trace
Clock Driver
10 nF
R2
SDn_REF_CLK
CLK_Out
R1
50 Ω
Figure 64. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
This figure shows the SerDes reference clock connection reference circuits for a single-ended clock driver. It assumes the DC
levels of the clock driver are compatible with chip’s SerDes reference clock input’s DC requirement.
Single-Ended
CLK Driver Chip
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
SDn_REF_CLK
33 Ω
Clock Driver
CLK_Out
50 Ω
SerDes Refer.
CLK Receiver
100 Ω differential PWB trace
50 Ω
SDn_REF_CLK
50 Ω
Figure 65. Single-Ended Connection (Reference Only)
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2.20.2.4
AC Requirements for SerDes Reference Clocks
The clock driver selected should provide a high quality reference clock with low phase noise and cycle-to-cycle jitter. Phase
noise less than 100KHz can be tracked by the PLL and data recovery loops and is less of a problem. Phase noise above 15MHz
is filtered by the PLL. The most problematic phase noise occurs in the 1-15MHz range. The source impedance of the clock
driver should be 50 ohms to match the transmission line and reduce reflections which are a source of noise to the system.
This table describes some AC parameters common to SGMII and PCI Express protocols.
Table 69. SerDes Reference Clock Common AC Parameters
At recommended operating conditions with XVDD_SRDS1 or XVDD_SRDS2 = 1.0V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
Rising Edge Rate
Rise Edge Rate
1.0
4.0
V/ns
2, 3
Falling Edge Rate
Fall Edge Rate
1.0
4.0
V/ns
2, 3
Differential Input High Voltage
VIH
+200
—
mV
2
Differential Input Low Voltage
VIL
—
–200
mV
2
Rise-Fall
Matching
—
20
%
1, 4
Rising edge rate (SDn_REF_CLK) to falling edge rate
(SDn_REF_CLK) matching
Notes:
1. Measurement taken from single ended waveform.
2. Measurement taken from differential waveform.
3. Measured from –200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLK minus SDn_REF_CLK). The
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is
centered on the differential zero crossing. See Figure 66.
4. Matching applies to rising edge rate for SDn_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a 200
mV window centered on the median cross point where SDn_REF_CLK rising meets SDn_REF_CLK falling. The median cross
point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate
of SDn_REF_CLK should be compared to the Fall Edge Rate of SDn_REF_CLK, the maximum allowed difference should not
exceed 20% of the slowest edge rate. See Figure 67.
Rise Edge Rate
Fall Edge Rate
VIH = +200 mV
0.0 V
VIL = –200 mV
SDn_REF_CLK –
SDn_REF_CLK
Figure 66. Differential Measurement Points for Rise and Fall Time
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Electrical Characteristics
SDn_REF_CLK
TFALL
SDn_REF_CLK
TRISE
VCROSS MEDIAN + 100 mV
VCROSS MEDIAN
VCROSS MEDIAN
VCROSS MEDIAN – 100 mV
SDn_REF_CLK
SDn_REF_CLK
Figure 67. Single-Ended Measurement Points for Rise and Fall Time Matching
The other detailed AC requirements of the SerDes Reference Clocks is defined by each interface protocol based on application
usage. See the following sections for detailed information:
•
•
Section 2.9.3.2, “AC Requirements for SGMII SD2_REF_CLK and SD2_REF_CLK”
Section 2.21.2, “AC Requirements for PCI Express SerDes Clocks”
2.20.2.4.1
Spread Spectrum Clock
SD1_REF_CLK/SD1_REF_CLK were designed to work with a spread spectrum clock (+0 to -0.5% spreading at 30–33 kHz
rate is allowed), assuming both ends have same reference clock. For better results, a source without significant unintended
modulation should be used.
SD2_REF_CLK/SD2_REF_CLK are not intended to be used with, and should not be clocked by, a spread spectrum clock
source.
2.20.3
SerDes Transmitter and Receiver Reference Circuits
This figure shows the reference circuits for SerDes data lane’s transmitter and receiver.
50 Ω
SD1_TXn or
SD2_TXn
SD1_RXn or
SD2_RXn
50 Ω
Transmitter
Receiver
50 Ω
SD1_TXn or
SD2_TXn
SD1_RXn or
SD2_RXn
50 Ω
Figure 68. SerDes Transmitter and Receiver Reference Circuits
The DC and AC specification of SerDes data lanes are defined in each interface protocol section below (PCI Express, SATA or
SGMII) in this document based on the application usage:
•
•
•
Section 2.9.3, “SGMII Interface Electrical Characteristics”
Section 2.21, “PCI Express”
Section 2.16, “Serial ATA (SATA)”
Please note that external AC Coupling capacitor is required for the above three serial transmission protocols with the capacitor
value defined in specification of each protocol section.
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Electrical Characteristics
2.21
PCI Express
This section describes the DC and AC electrical specifications for the PCI Express bus of the chip.
2.21.1
DC Requirements for PCI Express SD1_REF_CLK and
SD1_REF_CLK
For more information, see Section 2.20.2, “SerDes Reference Clocks.”
2.21.2
AC Requirements for PCI Express SerDes Clocks
This table lists AC requirements.
Table 70. SD1_REF_CLK and SD1_REF_CLK AC Requirements
Symbol
Min
Typical
Max
Units
Notes
REFCLK cycle time
—
10
—
ns
1
tREFCJ
REFCLK cycle-to-cycle jitter. Difference in the period of any two
adjacent REFCLK cycles
—
—
100
ps
—
tREFPJ
Phase jitter. Deviation in edge location with respect to mean edge
location
–50
—
50
ps
1,2,3
tREF
Parameter Description
Notes:
1. Tj at BER of 10E-6 86 ps Max.
2. Total peak-to-peak deterministic jitter “Dj” should be less than or equal to 42 ps.
3. Limits from “PCI Express CEM Rev 2.0” and measured per “PCI Express Rj, D, and Bit Error Rates”.
2.21.3
Clocking Dependencies
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million 15 (ppm) of each other at all
times. This is specified to allow bit rate clock sources with a +/– 300 ppm tolerance.
2.21.4
Physical Layer Specifications
The following is a summary of the specifications for the physical layer of PCI Express on this chip. For further details as well
as the specifications of the transport and data link layer, please use the PCI Express Base Specification. REV. 1.0a document.
2.21.4.1
Differential Transmitter (TX) Output
This table defines the specifications for the differential output at all transmitters (TXs). The parameters are specified at the
component pins.
Table 71. Differential Transmitter (TX) Output Specifications
Symbol
Parameter
UI
Unit Interval
VTX-DIFFp-p
Differential
Peak-to-Peak
Output Voltage
Min
Nom
Max
Units
Comments
399.88
400
400.12
ps
Each UI is 400 ps ± 300 ppm. UI does not account for
Spread Spectrum Clock dictated variations. See Note
1.
0.8
—
1.2
V
VTX-DIFFp-p = 2*|VTX-D+ – VTX-D-| See Note 2.
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Electrical Characteristics
Table 71. Differential Transmitter (TX) Output Specifications (continued)
Symbol
Parameter
Min
Nom
Max
Units
Comments
VTX-DE-RATIO
De- Emphasized
Differential Output
Voltage (Ratio)
–3.0
–3.5
–4.0
dB
Ratio of the VTX-DIFFp-p of the second and following
bits after a transition divided by the VTX-DIFFp-p of the
first bit after a transition. See Note 2.
TTX-EYE
Minimum TX Eye
Width
0.70
—
—
UI
The maximum Transmitter jitter can be derived as
TTX-MAX-JITTER = 1 – TTX-EYE= 0.3 UI.
See Notes 2 and 3.
TTX-EYE-MEDIAN-to-
Maximum time
between the jitter
median and
maximum
deviation from the
median.
—
—
0.15
UI
Jitter is defined as the measurement variation of the
crossing points (VTX-DIFFp-p = 0 V) in relation to a
recovered TX UI. A recovered TX UI is calculated over
3500 consecutive unit intervals of sample data. Jitter
is measured using all edges of the 250 consecutive UI
in the center of the 3500 UI used for calculating the TX
UI. See Notes 2 and 3.
TTX-RISE, TTX-FALL
D+/D- TX Output
Rise/Fall Time
0.125
—
—
UI
See Notes 2 and 5
VTX-CM-ACp
RMS AC Peak
Common Mode
Output Voltage
—
—
20
mV
VTX-CM-ACp = RMS(|VTXD+ +VTXD-|/2 – VTX-CM-DC)
VTX-CM-DC = DC(avg) of |VTX-D+ +VTX-D-|/2
See Note 2
VTX-CM-DC-ACTIVE-
Absolute Delta of
DC Common
Mode Voltage
During L0 and
Electrical Idle
0
—
100
mV
|VTX-CM-DC (during L0) – VTX-CM-Idle-DC (During Electrical
mV
VTX-CM-DC = DC(avg) of |VTX-D+ +VTX-D-|/2 [L0]
VTX-CM-Idle-DC = DC(avg) of |VTX-D+ + VTX-D-|/2
[Electrical Idle]
See Note 2.
MAX-JITTER
IDLE-DELTA
Idle)|<=100
VTX-CM-DC-LINE-DELTA Absolute Delta of
DC Common
Mode between D+
and D–
0
—
25
mV
|VTX-CM-DC-D+ – VTX-CM-DC-D-| <= 25 mV
VTX-CM-DC-D+ = DC(avg) of |VTX-D+|
VTX-CM-DC-D- = DC(avg) of |VTX-D-|
See Note 2.
VTX-IDLE-DIFFp
Electrical Idle
differential Peak
Output Voltage
0
—
20
mV
VTX-IDLE-DIFFp = |VTX-IDLE-D+ -VTX-IDLE-D-| <= 20 mV
See Note 2.
VTX-RCV-DETECT
The amount of
voltage change
allowed during
Receiver Detection
—
—
600
mV
The total amount of voltage change that a transmitter
can apply to sense whether a low impedance
Receiver is present. See Note 6.
VTX-DC-CM
The TX DC
Common Mode
Voltage
0
—
3.6
V
The allowed DC Common Mode voltage under any
conditions. See Note 6.
ITX-SHORT
TX Short Circuit
Current Limit
—
—
90
mA
The total current the Transmitter can provide when
shorted to its ground
TTX-IDLE-MIN
Minimum time
spent in Electrical
Idle
50
—
—
UI
Minimum time a Transmitter must be in Electrical Idle
Utilized by the Receiver to start looking for an
Electrical Idle Exit after successfully receiving an
Electrical Idle ordered set
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Electrical Characteristics
Table 71. Differential Transmitter (TX) Output Specifications (continued)
Symbol
TTX-IDLE-SET-TO-IDLE
Parameter
Min
Nom
Max
Units
Comments
Maximum time to
transition to a valid
electrical idle after
sending an
electrical Idle
ordered set
—
—
20
UI
After sending an Electrical Idle ordered set, the
Transmitter must meet all Electrical Idle Specifications
within this time. This is considered a debounce time
for the Transmitter to meet Electrical Idle after
transitioning from L0.
—
—
20
UI
Maximum time to meet all TX specifications when
transitioning from Electrical Idle to sending differential
data. This is considered a debounce time for the TX to
meet all TX specifications after leaving Electrical Idle
TTX-IDLE-TO-DIFF-DATA Maximum time to
transition to valid
TX specifications
after leaving an
electrical idle
condition
RLTX-DIFF
Differential Return
Loss
12
—
—
dB
Measured over 50 MHz to 1.25 GHz. See Note 4
RLTX-CM
Common Mode
Return Loss
6
—
—
dB
Measured over 50 MHz to 1.25 GHz. See Note 4
ZTX-DIFF-DC
DC Differential TX
Impedance
80
100
120
Ω
TX DC Differential mode Low Impedance
ZTX-DC
Transmitter DC
Impedance
40
—
—
Ω
Required TX D+ as well as D- DC Impedance during
all states
LTX-SKEW
Lane-to-Lane
Output Skew
—
—
500 +
2 UI
ps
Static skew between any two Transmitter Lanes within
a single Link
CTX
AC Coupling
Capacitor
75
—
200
nF
All Transmitters shall be AC coupled. The AC coupling
is required either within the media or within the
transmitting component itself. See Note 8.
Tcrosslink
Crosslink Random
Timeout
0
—
1
ms
This random timeout helps resolve conflicts in
crosslink configuration by eventually resulting in only
one Downstream and one Upstream Port. See Note 7.
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 52 and measured over
any 250 consecutive TX UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 50)
3. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.30 UI for the
Transmitter collected over any 250 consecutive TX UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total
TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean.
The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed
to the averaged time value.
4. The Transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode
return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement
applies to all valid input levels. The reference impedance for return loss measurements is 50 ohms to ground for both the D+
and D- line (that is, as measured by a Vector Network Analyzer with 50 ohm probes—see Figure 52). Note that the series
capacitors CTX is optional for the return loss measurement.
5. Measured between 20-80% at transmitter package pins into a test load as shown in Figure 52 for both VTX-D+ and VTX-D-.
6. See Section 4.3.1.8 of the PCI Express Base Specifications Rev 1.0a
7. See Section 4.2.6.3 of the PCI Express Base Specifications Rev 1.0a
8. SerDes transmitter does not have CTX built-in. An external AC Coupling capacitor is required.
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Electrical Characteristics
2.21.4.2
Transmitter Compliance Eye Diagrams
The TX eye diagram in Figure 69 is specified using the passive compliance/test measurement load (see Figure 71) in place of
any real PCI Express interconnect + RX component.
There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in time using the jitter
median to locate the center of the eye diagram. The different eye diagrams will differ in voltage depending whether it is a
transition bit or a de-emphasized bit. The exact reduced voltage level of the de-emphasized bit will always be relative to the
transition bit.
The eye diagram must be valid for any 250 consecutive UIs.
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges
of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI.
NOTE
It is recommended that the recovered TX UI is calculated using all edges in the 3500
consecutive UI interval with a fit algorithm using a minimization merit function (that is,
least squares and median deviation fits).
VRX-DIFF = 0 mV
(D+ D– Crossing Point)
[Transition Bit]
VTX-DIFFp-p-MIN = 800 mV
VTX-DIFF = 0 mV
(D+ D– Crossing Point)
[De-Emphasized Bit]
566 mV (3 dB ) >= VTX-DIFFp-p-MIN >= 505 mV (4 dB )
0.07 UI = UI – 0.3 UI (JTX-TOTAL-MAX)
[Transition Bit]
VTX-DIFFp-p-MIN = 800 mV
Figure 69. Minimum Transmitter Timing and Voltage Output Compliance Specifications
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Freescale Semiconductor
Electrical Characteristics
2.21.4.3
Differential Receiver (RX) Input Specifications
This table defines the specifications for the differential input at all receivers (RXs). The parameters are specified at the
component pins.
Table 72. Differential Receiver (RX) Input Specifications
Symbol
Parameter
Min
Nom
Max
Units
Comments
UI
Unit Interval
399.8
8
400
400.12
ps
Each UI is 400 ps ± 300 ppm. UI does not
account for Spread Spectrum Clock dictated
variations. See Note 1.
VRX-DIFFp-p
Differential
Peak-to-Peak
Output Voltage
0.175
—
1.200
V
VRX-DIFFp-p = 2*|VRX-D+ – VRX-D-|
See Note 2.
TRX-EYE
Minimum
Receiver Eye
Width
0.4
—
—
UI
The maximum interconnect media and
Transmitter jitter that can be tolerated by the
Receiver can be derived as TRX-MAX-JITTER =
1 - TRX-EYE= 0.6 UI.
See Notes 2 and 3.
—
—
0.3
UI
Jitter is defined as the measurement variation
of the crossing points (VRX-DIFFp-p = 0 V) in
relation to a recovered TX UI. A recovered TX
UI is calculated over 3500 consecutive unit
intervals of sample data. Jitter is measured
using all edges of the 250 consecutive UI in
the center of the 3500 UI used for calculating
the TX UI. See Notes 2, 3 and 7.
TRX-EYE-MEDIAN-to-MAX Maximum time
between the jitter
-JITTER
median and
maximum
deviation from
the median.
VRX-CM-ACp
AC Peak
Common Mode
Input Voltage
—
—
150
mV
VRX-CM-ACp = |VRXD+ – VRXD-|/2 +VRX-CM-DC
VRX-CM-DC = DC(avg) of |VRX-D+ +VRX-D-|/2
See Note 2
RLRX-DIFF
Differential
Return Loss
15
—
—
dB
Measured over 50 MHz to 1.25 GHz with the
D+ and D- lines biased at +300 mV and –300
mV, respectively.
See Note 4
RLRX-CM
Common Mode
Return Loss
6
—
—
dB
Measured over 50 MHz to 1.25 GHz with the
D+ and D- lines biased at 0 V. See Note 4
ZRX-DIFF-DC
DC Differential
Input Impedance
80
100
120
Ω
RX DC Differential mode impedance. See
Note 5
ZRX-DC
DC Input
Impedance
40
50
60
Ω
Required RX D+ as well as D- DC Impedance
(50 ± 20% tolerance). See Notes 2 and 5.
ZRX-HIGH-IMP-DC
Powered Down
DC Input
Impedance
200 k
—
—
Ω
Required RX D+ as well as D– DC
Impedance when the Receiver terminations
do not have power. See Note 6.
VRX-IDLE-DET-DIFFp-p
Electrical Idle
Detect Threshold
65
—
175
mV
VRX-IDLE-DET-DIFFp-p = 2*|VRX-D+ –VRX-D-|
Measured at the package pins of the Receiver
TRX-IDLE-DET-DIFF-
Unexpected
Electrical Idle
Enter Detect
Threshold
Integration Time
—
—
10
ms
An unexpected Electrical Idle (VRX-DIFFp-p <
VRX-IDLE-DET-DIFFp-p) must be recognized no
longer than TRX-IDLE-DET-DIFF-ENTERING to
signal an unexpected idle condition.
ENTERTIME
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Electrical Characteristics
Table 72. Differential Receiver (RX) Input Specifications (continued)
Symbol
LTX-SKEW
Parameter
Total Skew
Min
Nom
Max
Units
Comments
—
—
20
ns
Skew across all lanes on a Link. This includes
variation in the length of SKP ordered set (for
example, COM and one to five Symbols) at
the RX as well as any delay differences
arising from the interconnect itself.
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 71 should be used
as the RX device when taking measurements (also refer to the Receiver compliance eye diagram shown in Figure 70). If the
clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must
be used as a reference for the eye diagram.
3. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the Transmitter and
interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in
which the median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any
250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point
in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the
clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must
be used as the reference for the eye diagram.
4. The Receiver input impedance shall result in a differential return loss greater than or equal to 15 dB with the D+ line biased to
300 mV and the D- line biased to -300 mV and a common mode return loss greater than or equal to 6 dB (no bias required)
over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The
reference impedance for return loss measurements for is 50 ohms to ground for both the D+ and D- line (that is, as measured
by a Vector Network Analyzer with 50 ohm probes - see Figure 71). Note: that the series capacitors CTX is optional for the
return loss measurement.
5. Impedance during all LTSSM states. When transitioning from a Fundamental Reset to Detect (the initial state of the LTSSM)
there is a 5 ms transition time before Receiver termination values must be met on all un-configured Lanes of a Port.
6. The RX DC Common Mode Impedance that exists when no power is present or Fundamental Reset is asserted. This helps
ensure that the Receiver Detect circuit will not falsely assume a Receiver is powered on when it is not. This term must be
measured at 300 mV above the RX ground.
7. It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm
using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated
data.
2.22
Receiver Compliance Eye Diagrams
The RX eye diagram in Figure 70 is specified using the passive compliance/test measurement load (see Figure 71) in place of
any real PCI Express RX component.
Note: In general, the minimum Receiver eye diagram measured with the compliance/test measurement load (see Figure 71) will
be larger than the minimum Receiver eye diagram measured over a range of systems at the input Receiver of any real PCI
Express component. The degraded eye diagram at the input Receiver is due to traces internal to the package as well as silicon
parasitic characteristics which cause the real PCI Express component to vary in impedance from the compliance/test
measurement load. The input Receiver eye diagram is implementation specific and is not specified. RX component designer
should provide additional margin to adequately compensate for the degraded minimum Receiver eye diagram (shown in
Figure 70) expected at the input Receiver based on some adequate combination of system simulations and the Return Loss
measured looking into the RX package and silicon. The RX eye diagram must be aligned in time using the jitter median to locate
the center of the eye diagram.
The eye diagram must be valid for any 250 consecutive UIs.
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
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Freescale Semiconductor
Electrical Characteristics
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges
of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI.
NOTE
The reference impedance for return loss measurements is 50. to ground for both the D+ and
D- line (that is, as measured by a Vector Network Analyzer with 50. probes—see
Figure 71). Note that the series capacitors, CTX, are optional for the return loss
measurement.
VRX-DIFF = 0 mV
(D+, D– Crossing Point
VRX-DIFF = 0 mV
(D+, D– Crossing Point
VRX-DIFFp-p-MIN > 175 mV
0.4 UI = TRX-EYE-MIN
Figure 70. Minimum Receiver Eye Timing and Voltage Compliance Specification
2.22.1
Compliance Test and Measurement Load
The AC timing and voltage parameters must be verified at the measurement point, as specified within 0.2 inches of the package
pins, into a test/measurement load shown in the following figure.
NOTE
The allowance of the measurement point to be within 0.2 inches of the package pins is
meant to acknowledge that package/board routing may benefit from D+ and D– not being
exactly matched in length at the package pin boundary.
D+ Package
Pin
C = CTX
TX
Silicon
+ Package
D– Package
Pin
C = CTX
R = 50 Ω
R = 50 Ω
Figure 71. Compliance Test/Measurement Load
2.23
Clocking
This section describes the PLL configuration of the chip. Note that the platform clock is identical to the core complex bus (CCB)
clock.
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
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105
Electrical Characteristics
2.23.1
Clock Ranges
This table provides the clocking specifications for the processor cores and Table 74 provides the clocking specifications for the
memory bus.
Table 73. Processor Core Clocking Specifications
Maximum Processor Core Frequency
Characteristic
600 MHz
800 MHz
1000 MHz
1250 MHz
Min
Max
Min
Max
Min
Max
Min
Max
e500 core processor frequency
600
600
600
800
600
1000
600
1250
CCB frequency
400
400
400
400
333
400
333
500
DDR Data Rate
400
400
400
400
400
400
400
667
Unit
Notes
MHz
1, 2, 3
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies. See Section 2.23.2, “CCB/SYSCLK PLL Ratio,” Section 2.23.3, “e500 Core PLL Ratio,“and Section 2.23.4,
“DDR/DDRCLK PLL Ratio,” for ratio settings.
2. The processor core frequency speed bins listed also reflect the maximum platform (CCB) and DDR data rate frequency
supported by production test. Running CCB and/or DDR data rate higher than the limit shown above, although logically possible
via valid clock ratio setting in some condition, is not supported.
3. As defined by JEDEC, the minimum allowed data rate for DDR3 is 606 MHz data rate. Therefore, only the processors with a
DDR data rate of 667 MHz support DDR3.
The DDR memory controller can run in either synchronous or asynchronous mode. When running in synchronous mode, the
memory bus is clocked relative to the platform clock frequency. When running in asynchronous mode, the memory bus is
clocked with its own dedicated PLL. This table provides the clocking specifications for the memory bus.
Table 74. Memory Bus Clocking Specifications
Characteristic
DDR Memory bus clock speed
Min
Max
Unit
Notes
200
250
MHz
1, 2, 3, 4, 5
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum
operating frequencies. See Section 2.23.2, “CCB/SYSCLK PLL Ratio,” Section 2.23.3, “e500 Core PLL Ratio,” and
Section 2.23.4, “DDR/DDRCLK PLL Ratio,” for ratio settings.
2. The Memory bus clock refers to the chip’s memory controllers’ MCK[0:5] and MCK[0:5] output clocks, running at half of the
DDR data rate.
3. In synchronous mode, the memory bus clock speed is half the platform clock frequency. In other words, the DDR data rate is
the same as the platform (CCB) frequency. If the desired DDR data rate is higher than the platform (CCB) frequency,
asynchronous mode must be used.
4. In asynchronous mode, the memory bus clock speed is dictated by its own PLL. See Section 2.23.4, “DDR/DDRCLK PLL
Ratio.” The memory bus clock speed must be less than or equal to the CCB clock rate which in turn must be less than the DDR
data rate.
5. See Table 73 for a list of supported ranges of DDR data to corresponding processor frequency.
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Electrical Characteristics
2.23.2
CCB/SYSCLK PLL Ratio
The CCB clock is the clock that drives the e500 core complex bus (CCB), and is also called the platform clock. The frequency
of the CCB is set using the following reset signals, as shown in the following table:
•
•
SYSCLK input signal
Binary value on LA[28:31] at power up
Note that there is no default for this PLL ratio; these signals must be pulled to the desired values.
Table 75. CCB Clock Ratio
2.23.3
Binary Value of
LA[28:31] Signals
CCB:SYSCLK Ratio
Binary Value of
LA[28:31] Signals
CCB:SYSCLK Ratio
0000
Reserved
1000
8:1
0001
Reserved
1001
9:1
0010
Reserved
1010
10:1
0011
3:1
1011
Reserved
0100
4:1
1100
12:1
0101
5:1
1101
Reserved
0110
6:1
1110
Reserved
0111
Reserved
1111
Reserved
e500 Core PLL Ratio
This table describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock. This ratio is determined
by the binary value of LBCTL, LALE and LGPL2 at power up, as shown in this table.
Table 76. e500 Core to CCB Clock Ratio
2.23.4
Binary Value of
LBCTL, LALE,
LGPL2 Signals
e500 core: CCB Clock Ratio
Binary Value of
LBCTL, LALE,
LGPL2 Signals
e500 core: CCB Clock Ratio
000
4:1
100
2:1
001
9:2
101
5:2
010
Reserved
110
3:1
011
3:2
111
7:2
DDR/DDRCLK PLL Ratio
The DDR memory controller complex can be synchronous with, or asynchronous to, the CCB, depending on configuration.
The following table describes the clock ratio between the DDR memory controller complex and the DDR/DDRCLK PLL
reference clock, DDRCLK, which is not the memory bus clock.
When synchronous mode is selected, the memory buses are clocked at half the CCB clock rate. The default mode of operation
is for the DDR data rate for the DDR controller to be equal to the CCB clock rate in synchronous mode, or the resulting DDR
PLL rate in asynchronous mode.
In asynchronous mode, the DDR PLL rate to DDRCLK ratios listed in Table 77 reflects the DDR data rate to DDRCLK ratio,
since the DDR PLL rate in asynchronous mode means the DDR data rate resulting from DDR PLL output.
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Electrical Characteristics
Please note that the DDR PLL reference clock input, DDRCLK, is only required in asynchronous mode.
The DDRCLKDR configuration register in the Global Utilities block allows the DDR controller to be run in a divided down
mode where the DDR bus clock is half the speed of the default configuration. Changing of these defaults must be completed
prior to initialization of the DDR controller.
Table 77. DDR Clock Ratio
Functional Signals
TSEC_1588_TRIG_OUT[0:1],
TSEC1_1588_CLK_OUT
2.23.5
Reset Configuration
Name
Value (Binary)
DDR:DDRCLK Ratio
000
3:1
001
4:1
010
6:1
011
8:1
100
10:1
101
12:1
110
Reserved
111
Synchronous mode
cfg_ddr_pll[0:2]
PCI Clocks
The integrated PCI controller in this chip supports PCI input clock frequency in the range of 33–66 MHz. The PCI input clock
can be applied from SYSCLK in synchronous mode or PCI1_CLK in asynchronous mode. For specifications on the PCI1_CLK,
refer to the PCI 2.2 Specification.
The use of PCI1_CLK is optional if SYSCLK is in the range of 33–66 MHz. If SYSCLK is outside this range then use of
PCI1_CLK is required as a separate PCI clock source, asynchronous with respect to SYSCLK.
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Electrical Characteristics
2.23.6
Frequency Options
2.23.6.1
SYSCLK to Platform Frequency Options
This table shows the expected frequency values for the platform frequency when using a CCB clock to SYSCLK ratio in
comparison to the memory bus clock speed.
Table 78. Frequency Options of SYSCLK with Respect to Memory Bus Speeds
CCB to
SYSCLK Ratio
SYSCLK (MHz)
33.33
41.66
66.66
83
100
111
133.33
333
400
Platform /CCB Frequency (MHz)
3
4
400
500
5
333
415
6
400
500
8
2.24
333
444
333
10
333
417
12
400
500
Thermal
This section describes the thermal specifications of the chip.
2.24.1
Thermal Characteristics
This table provides the package thermal characteristics.
Table 79. Package Thermal Characteristics
Characteristic
JEDEC Board
Symbol
Value
Unit
Notes
Junction-to-ambient Natural Convection
Single layer board (1s)
RθJA
23
°C/W
1, 2
Junction-to-ambient Natural Convection
Four layer board (2s2p)
RθJA
18
°C/W
1, 2
Junction-to-ambient (@200 ft/min)
Single layer board (1s)
RθJA
18
°C/W
1, 2
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Electrical Characteristics
Table 79. Package Thermal Characteristics (continued)
Characteristic
JEDEC Board
Symbol
Value
Unit
Notes
Four layer board (2s2p)
RθJA
14
°C/W
1, 2
Junction-to-board thermal
—
RθJB
10
°C/W
3
Junction-to-case thermal
—
RθJC
< 0.1
°C/W
4
Junction-to-ambient (@200 ft/min)
Notes
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JESD51-2 and JESD51-6 with the board (JESD51-9) horizontal.
3. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
4. Thermal resistance between the active surface of the die and the case top surface determined by the cold plate method
(MIL SPEC-883 Method 1012.1) with the calculated case temperature. Actual thermal resistance is less than 0.1 °C/W
Simulations with heat sinks were done with the package mounted on the 2s2p thermal test board. The thermal interface material
was a typical thermal grease such as Dow Corning 340 or Wakefield 120 grease.For system thermal modeling, the chip’s thermal
model without a lid is shown in Figure 72 The substrate is modeled as a block 29 x 29 x 1.2 mm with an in-plane conductivity
of 19.8 W/m•K and a through-plane conductivity of 1.13 W/m•K. The solder balls and air are modeled as a single block
29 x 29 x 0.5 mm with an in-plane conductivity of 0.034 W/m•K and a through plane conductivity of 12.1 W/m•K. The die is
modeled as 9.6 x 9.57 mm with a thickness of 0.75 mm. The bump/underfill layer is modeled as a collapsed thermal resistance
between the die and substrate assuming a conductivity of 7.5 W/m•K in the thickness dimension of 0.07 mm. The die is centered
on the substrate. The thermal model uses approximate dimensions to reduce grid. Please refer to the case outline for actual
dimensions.
2.24.2
Recommended Thermal Model
This table shows the chip’s thermal model.
Table 80. Thermal Model
Conductivity
Value
Units
Die (9.6x9.6 × 0.85 mm)
Silicon
Temperature dependent
—
Bump/Underfill (9.6 x 9.6 × 0.07 mm) Collapsed Thermal Resistance
Kz
7.5
W/m•K
Substrate (29 × 29 × 1.2 mm)
Kx
19.8
Ky
19.8
Kz
1.13
W/m•K
Solder and Air (29 × 29 × 0.5 mm)
Kx
0.034
Ky
0.034
Kz
12.1
W/m•K
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Freescale Semiconductor
Electrical Characteristics
Figure 72. System-Level Thermal Model for the Chip (Not to Scale)
The Flotherm library files of the parts have a dense grid to accurately capture the laminar boundary layer for flow over the part
in standard JEDEC environments, as well as the heat spreading in the board under the package. In a real system, however, the
part will require a heat sink to be mounted on it. In this case, the predominant heat flow path will be from the die to the heat
sink. Grid density lower than currently in the package library file will suffice for these simulations. The user will need to
determine the optimal grid for their specific case.
2.24.3
Thermal Management Information
This section provides thermal management information for the flip chip plastic ball grid array (FC-PBGA) package for
air-cooled applications. Proper thermal control design is primarily dependent on the system-level design—the heat sink, airflow,
and thermal interface material.
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Electrical Characteristics
The recommended attachment method to the heat sink is illustrated in the following figure. The heat sink should be attached to
the printed-circuit board with the spring force centered over the die. This spring force should not exceed 10 pounds force (45
Newton).
FC-PBGA Package
Heat Sink
Heat Sink
Clip
Thermal Interface Material
Die
Printed-Circuit Board
Figure 73. Package Exploded Cross-Sectional View with Several Heat Sink Options
The system board designer can choose between several types of heat sinks to place on the chip. Ultimately, the final selection
of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass,
attachment method, assembly, and cost. Several heat sinks offered by Aavid Thermalloy, Advanced Thermal Solutions, Alpha
Novatech, IERC, Chip Coolers, Millennium Electronics, and Wakefield Engineering offer different heat sink-to-ambient
thermal resistances, that will allow the chip to function in various environments.
2.24.3.1
Internal Package Conduction Resistance
For the packaging technology, shown in Table 70, the intrinsic internal conduction thermal resistance paths are as follows:
•
•
The die junction-to-case thermal resistance
The die junction-to-board thermal resistance
This figure depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board.
External Resistance
Radiation
Convection
Heat Sink
Thermal Interface Material
Die/Package
Die Junction
Package/Solder Spheres
Internal Resistance
Printed-Circuit Board
External Resistance
Radiation
Convection
(Note the internal versus external package resistance)
Figure 74. Package with Heat Sink Mounted to a Printed-Circuit Board
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Freescale Semiconductor
Hardware Design Considerations
The heat sink removes most of the heat from the chip for most applications. Heat generated on the active side of the chip is
conducted through the silicon and through the heat sink attach material (or thermal interface material), and finally to the heat
sink. The junction-to-case thermal resistance is low enough that the heat sink attach material and heat sink thermal resistance
are the dominant terms.
2.24.3.2
Thermal Interface Materials
A thermal interface material is required at the package-to-heat sink interface to minimize the thermal contact resistance. The
performance of thermal interface materials improves with increased contact pressure. This performance characteristic chart is
generally provided by the thermal interface vendors.
3
Hardware Design Considerations
This section provides electrical and thermal design recommendations for successful application of the chip.
3.1
System Clocking
This chip includes seven PLLs:
•
•
•
•
•
•
•
3.2
3.2.1
The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency ratio
between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in
Section 2.23.2, “CCB/SYSCLK PLL Ratio.”
The e500 core PLL generates the core clock as a slave to the platform clock. The frequency ratio between the e500
core clock and the platform clock is selected using the e500 PLL ratio configuration bits as described in Section 2.23.3,
“e500 Core PLL Ratio.”
The PCI PLL generates the clocking for the PCI bus
The local bus PLL generates the clock for the local bus.
There is a PLL for the SerDes1 block to be used for PCI Express interface
There is a PLL for the SerDes2 block to be used for SGMII and SATA interfaces.
The DDR PLL generates the DDR clock from the externally supplied DDRCLK input in asynchronous mode. The
frequency ratio between the DDR clock and DDRCLK is described in Section 2.23.4, “DDR/DDRCLK PLL Ratio.”
Power Supply Design and Sequencing
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins (AVDD_PLAT, AVDD_CORE,
AVDD_PCI, AVDD_LBIU, and AVDD_SRDS respectively). The AVDD level should always be equivalent to VDD, and
preferably these voltages will be derived directly from VDD through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide independent
filter circuits per PLL power supply as illustrated in Figure 75, one to each of the AVDD pins. By providing independent filters
to each PLL the opportunity to cause noise injection from one PLL to the other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It should be built
with surface mount capacitors with minimum Effective Series Inductance (ESL). Consistent with the recommendations of Dr.
Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors
of equal value are recommended over a single large value capacitor.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from
nearby circuits. It should be possible to route directly from the capacitors to the AVDD pin, which is on the periphery of 783
FC-PBGA the footprint, without the inductance of vias.
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Hardware Design Considerations
This figure shows the PLL power supply filter circuit.
10 Ω
VDD
AVDD
2.2 µF
2.2 µF
GND
Low ESL Surface Mount Capacitors
Figure 75. Chip PLL Power Supply Filter Circuit
The AVDD_SRDSn signals provides power for the analog portions of the SerDes PLL. To ensure stability of the internal clock,
the power supplied to the PLL is filtered using a circuit similar to the one shown in following Figure 76. For maximum
effectiveness, the filter circuit is placed as closely as possible to the AVDD_SRDSn balls to ensure it filters out as much noise
as possible. The ground connection should be near the AVDD_SRDSn balls. The 0.003-µF capacitor is closest to the balls,
followed by the 1-µF capacitor, and finally the 1 ohm resistor to the board supply plane. The capacitors are connected from
AVDD_SRDSn to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces
should be kept short, wide and direct.
SnVDD
1.0 Ω
AVDD - SRDS
2.2 µF
1
2.2 µF
1
0.003 µF
GND
1. An 0805 sized capacitor is recommended for system initial bring-up
Figure 76. SerDes PLL Power Supply Filter Circuit
Note the following:
•
•
3.3
AVDD should be a filtered version of SVDD.
Signals on the SerDes interface are fed from the XVDD power plane.
Pin States in Deep Sleep State
In all low power mode by default, all input and output pads remain driven as per normal functional operation. The inputs remain
enabled.
The exception is that in Deep Sleep mode, GCR[DEEPSLEEP_Z] can be used to tristate a subset of output pads, and disable
the receivers of input pads as defined in Table 1. See the MPC8536E PowerQUICC III Integrated Processor Reference Manual
for details.
3.4
Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, this chip can generate transient power surges and high
frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching
other components in the chip system, and the chip itself requires a clean, tightly regulated source of power. Therefore, it is
recommended that the system designer place at least one decoupling capacitor at each VDD, TVDD, BVDD, OVDD, GVDD, and
LVDD pin of the chip. These decoupling capacitors should receive their power from separate VDD,TVDD, BVDD, OVDD, GVDD,
and LVDD, and GND power planes in the PCB, utilizing short low impedance traces to minimize inductance. Capacitors must
be placed directly under the chip using a standard escape pattern as much as possible. If some caps are to be placed surrounding
the part it should be routed with short and large trace to minimize the inductance.
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Hardware Design Considerations
These capacitors should have a value of 0.1 µF. Only ceramic SMT (surface mount technology) capacitors should be used to
minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, TVDD,
BVDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should
have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected
to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS
tantalum or Sanyo OSCON). However, customers should work directly with their power regulator vendor for best values types
and quantity of bulk capacitors.
3.5
SerDes Block Power Supply Decoupling Recommendations
he SerDes1 and SerDes2 blocks require a clean, tightly regulated source of power (SnVDD and XnVDD) to ensure low jitter on
transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below.
Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections from all capacitors to
power and ground should be done with multiple vias to further reduce inductance.
•
•
•
3.6
First, the board should have at least 10 x 10-nF SMT ceramic chip capacitors as close as possible to the supply balls
of the chip. Where the board has blind vias, these capacitors should be placed directly below the chip supply and
ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the
chip as close to the supply and ground connections as possible.
Second, there should be a 1-µF ceramic chip capacitor from each SerDes supply (SnVDD and XnVDD) to the board
ground plane on each side of the chip. This should be done for all SerDes supplies.
Third, between the chip and any SerDes voltage regulator there should be a 10-µF, low equivalent series resistance
(ESR) SMT tantalum chip capacitor and a 100-µF, low ESR SMT tantalum chip capacitor. This should be done for all
SerDes supplies.
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. All unused active
low inputs should be tied to VDD,TVDD, BVDD, OVDD, GVDD, and LVDD as required. All unused active high inputs should be
connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all
external VDD,TVDD, BVDD, OVDD, GVDD, and LVDD and GND pins of the chip.
3.7
Pull-Up and Pull-Down Resistor Requirements
The chip requires weak pull-up resistors (2–10 kΩ is recommended) on open drain type pins including I2C pins and MPIC
interrupt pins.
Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 78.
Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most
have asynchronous behavior and spurious assertion will give unpredictable results.
The following pins must NOT be pulled down during power-on reset: TSEC1_TXD[3], HRESET_REQ,
TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP. The UART_SOUT[0:1] and TEST_SEL pins must be set to a
proper state during POR configuration. Please refer to the pinlist table (see Table 62) of the individual chip for more details.
See the PCI 2.2 specification for all pull-ups required for PCI.
3.8
Output Buffer DC Impedance
The chip drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended
driver type (open drain for I2C).
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
115
Hardware Design Considerations
To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD or GND. Then, the
value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 77). The output impedance is the average of two
components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and
RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN
are designed to be close to each other in value. Then, Z0 = (RP + RN)/2.
OVDD
RN
SW2
Pad
Data
SW1
RP
OGND
Figure 77. Driver Impedance Measurement
This table summarizes the signal impedance targets. The driver impedances are targeted at minimum VDD, nominal OVDD,
105°C.
Table 81. Impedance Characteristics
Impedance
Local Bus, Ethernet, DUART,
Control, Configuration, Power
Management
RN
RP
PCI
DDR DRAM
Symbol Unit
45 Target
45 Target (cfg_pci_impd=1)
25 Target (cfg_pci_impd=0)
18 Target (full strength mode)
36 Target (full strength mode)
Z0
Ω
45 Target
45 Target (cfg_pci_impd=1)
25 Target (cfg_pci_impd=0)
18 Target (full strength mode)
36 Target (full strength mode)
Z0
Ω
Note: Nominal supply voltages. See Table 1.
3.9
Configuration Pin Muxing
The chip provides the user with power-on configuration options which can be set through the use of external pull-up or
pull-down resistors of 4.7 kΩ on certain output pins (see customer visible configuration pins). These pins are generally used as
output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins while HRESET is
asserted, is latched when HRESET deasserts, at which time the input receiver is disabled and the I/O circuit takes on its normal
function. Most of these sampled configuration pins are equipped with an on-chip gated resistor of approximately 20 kΩ. This
value should permit the 4.7-kΩ resistor to pull the configuration pin to a valid logic low level. The pull-up resistor is enabled
only during HRESET (and for platform /system clocks after HRESET deassertion to ensure capture of the reset value). When
the input receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with minimal signal
quality or delay disruption. The default value for all configuration bits treated this way has been encoded such that a high voltage
level puts the chip into the default state and external resistors are needed only when non-default settings are required by the user.
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
116
Freescale Semiconductor
Hardware Design Considerations
Careful board layout with stubless connections to these pull-down resistors coupled with the large value of the pull-down
resistor should minimize the disruption of signal quality or speed for output pins thus configured.
The platform PLL ratio and e500 PLL ratio configuration pins are not equipped with these default pull-up devices.
3.10
JTAG Configuration Signals
Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 78.
Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most
have asynchronous behavior and spurious assertion will give unpredicatable results.
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1
specification, but it is provided on all processors built on Power Architecture technology. The chip requires TRST to be asserted
during power-on reset flow to ensure that the JTAG boundary logic does not interfere with normal chip operation. While the
TAP controller can be forced to the reset state using only the TCK and TMS signals, generally systems assert TRST during the
power-on reset flow. Simply tying TRST to HRESET is not practical because the JTAG interface is also used for accessing the
common on-chip processor (COP), which implements the debug interface to the chip.
The COP function of these processors allow a remote computer system (typically, a PC with dedicated hardware and debugging
software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG
port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert
HRESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage
monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into
these signals with logic.
The arrangement shown in Figure 78 allows the COP port to independently assert HRESET or TRST, while ensuring that the
target can drive HRESET as well.
The COP interface has a standard header, shown in Figure 79, for connection to the target system, and is based on the 0.025"
square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a
connector key.
The COP header adds many benefits such as breakpoints, watchpoints, register and memory examination/modification, and
other standard debugger features. An inexpensive option can be to leave the COP header unpopulated until needed.
There is no standardized way to number the COP header; consequently, many different pin numbers have been observed from
emulator vendors. Some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while
still others number the pins counter clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement
recommended in Figure 79 is common to all known emulators.
3.10.1
Termination of Unused Signals
If the JTAG interface and COP header will not be used, Freescale recommends the following connections:
•
•
TRST should be tied to HRESET through a 0 kΩ isolation resistor so that it is asserted when the system reset signal
(HRESET) is asserted, ensuring that the JTAG scan chain is initialized during the power-on reset flow. Freescale
recommends that the COP header be designed into the system as shown in Figure 78. If this is not possible, the
isolation resistor will allow future access to TRST in case a JTAG interface may need to be wired onto the system in
future debug situations.
No pull-up/pull-down is required for TDI, TMS, or TDO.
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Freescale Semiconductor
117
Hardware Design Considerations
OVDD
SRESET
From Target
Board Sources
(if any)
HRESET
13
11
10 kΩ
SRESET 6
10 kΩ
HRESET1
COP_HRESET
10 kΩ
COP_SRESET
10 kΩ
5
10 kΩ
10 kΩ
2
3
4
5
6
7
8
9
10
11
12
6
53
COP Header
1
4
KEY
13 No
pin
15
15
COP_TRST
COP_VDD_SENSE2
TRST1
10 Ω
NC
COP_CHKSTP_OUT
CKSTP_OUT
10 kΩ
14 3
10 kΩ
COP_CHKSTP_IN
CKSTP_IN
8
COP_TMS
16
9
COP Connector
Physical Pinout
1
3
TMS
COP_TDO
TDO
COP_TDI
TDI
COP_TCK
7
TCK
2
NC
10
NC
12
4
10 kΩ
16
Notes:
1. The COP port and target board should be able to independently assert HRESET and TRST to the processor in
order to fully control the processor as shown here.
2. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection.
3. The KEY location (pin 14) is not physically present on the COP header.
4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for
improved signal integrity.
5. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing
to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed to
position B.
6. Asserting SRESET causes a machine check interrupt to the e500 core.
Figure 78. JTAG Interface Connection
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Freescale Semiconductor
Hardware Design Considerations
COP_TDO
1
2
NC
COP_TDI
3
4
COP_TRST
NC
5
6
COP_VDD_SENSE
COP_TCK
7
8
COP_CHKSTP_IN
COP_TMS
9
10
NC
COP_SRESET
11
12
NC
COP_HRESET
13
KEY
No pin
COP_CHKSTP_OUT
15
16
GND
Figure 79. COP Connector Physical Pinout
3.11
Guidelines for High-Speed Interface Termination
3.11.1
SerDes1 Interface Entirely Unused
If the high-speed SerDes interface is not used at all, the unused pin should be terminated as described in this section. However,
the SerDes must always have power applied to its supply pins. There are several reserved pins that need to be either left floating
or connected to XGND. See SerDes1 in Table 1 for details.
The following pins must be left unconnected (float):
•
•
•
SD1_TX[7:4]
SD1_TX[7:4]
Reserved pins T22, T23
The following pins must be connected to XGND:
•
•
•
•
SD1_RX[7:4]
SD1_RX[7:4]
SD1_REF_CLK
SD1_REF_CLK
The POR configuration pin cfg_io_ports[0:2] on TSEC3_TXD[6:3] can be used to power down SerDes 1 block for power
saving. Note that both SVDD and XVDD must remain powered.
3.11.2
SerDes 1 Interface Partly Unused
If only part of the high speed SerDes interface pins are used, the remaining high-speed serial I/O pins should be terminated as
described in this section.
The following pins must be left unconnected (float) if not used:
•
•
•
SD1_TX[7:4]
SD1_TX[7:4]
Reserved pins: T22, T23
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Ordering Information
The following pins must be connected to XGND if not used:
•
•
•
•
SD1_RX[7:4]
SD1_RX[7:4]
SD1_REF_CLK
SD1_REF_CLK
3.11.3
SerDes 2 Interface Entirely Unused
If the high-speed SerDes 2 interface (SGMII/ SATA) is not used at all, the unused pin should be terminated as described in this
section. There are several Reserved pins that need to be either left floating or connected to X2GND. See SerDes2 in
Table 1Table 1 for details.
The following pins must be left unconnected (float):
•
•
•
SD2_TX[0]
SD2_TX[0]
Reserved pins L8, L9
The following pins must be connected to X2GND:
•
•
•
•
SD2_RX[0]
SD2_RX[0]
SD2_REF_CLK
SD2_REF_CLK
The POR configuration pin cfg_srds2_prtcl[0:2] on TSEC1_TXD[2], TSEC3_TXD[2], TSEC_1588_PUSLE_OUT1 can be
used to power down SerDes 2 block for power saving. Note that both S2VDD and X2VDD must remain powered.
4
Ordering Information
Ordering information for the parts fully covered by this specification document is provided in Section 4.1, “Part Numbering
Nomenclature.”
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Ordering Information
4.1
Part Numbering Nomenclature
This table shows the part numbering nomenclature.
Table 82. Part Numbering Nomenclature
MPC
nnnn
Product
Part
Code Identifier
MPC
8536
8535
E
C
VT
AA
X
R
Security
Engine
Tiers and Temperature
Range
Package 1
Processor
Frequency 2
DDR
Frequency3
Revision Level
• A = Commercial tier
• VT = FC-PBGA
standard temperature
(Pb-free)4
• PX = plastic
range (0° to 90°C)
standard
• B or Blank = industrial
• VJ = lead-free
E = included
tier standard
FC-PBGAs5
temperature range (0°
to 105°C)
• C = Industrial tier
extended temperature
range (–40° to 105°C)
Blank = not
included
•
•
•
•
•
•
AK = 600 MHz
AN = 800 MHz
AQ = 1000 MHz
AT = 1250 MHz
AU = 1333 MHz
AV = 1500 MHz
•
•
•
•
G = 400 MHz
H = 500 MHz • Blank = Ver.
J = 533 MHz
1.0 or 1.1
L = 667 MHz
(SVR =
0x803F0190,
0x803F0191)
• A = Ver. 1.2
(SVR =
0x803F0192)
• Blank = Ver.
1.0 or 1.1
(SVR =
0x80370190,
0x80370191)
• A = Ver. 1.2
(SVR =
0x80370192)
Notes:
1. See Section 5, “Package Information,” for more information on available package types.
2. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification support
all core frequencies. Additionally, parts addressed by part number specifications may support other maximum core frequencies.
3. See Table 84 for the corresponding maximum platform frequency.
4. The VT part number is ROHS-compliant, with the permitted exception of the C4 die bumps.
5. The VJ part number is entirely lead-free, including the C4 die bumps.
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Ordering Information
4.2
Part Marking
Parts are marked as in the example shown in the following figure.
MPC853nVTnnnn
ATWLYYWW
MMMMM CCCCC
YWWLAZ
FC-PBGA
Notes:
MMMMM is the 5-digit mask number.
ATWLYYWW is the traceability code.
CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States.
Figure 80. Part Marking for FC-PBGA
4.3
Part Numbering
This table lists all part numbers that are offered for the chip.
Table 83. MPC8535 Part Numbers Commercial Tier
Core/Platform/
DDR (MHz)
Standard Temp
Without Security
Standard Temp
With Security
Notes
600/400/400
MPC8535AVJAKG(A)
MPC8535EAVJAKG(A)
—
800/400/400
MPC8535AVJANG(A)
MPC8535EAVJANG(A)
—
1000/400/400
MPC8535AVJAQG(A)
MPC8535EAVJAQG(A)
—
1250/500/500
MPC8535AVJATH(A)
MPC8535EAVJATH(A)
—
1250/500/667
MPC8535AVJATLA
MPC8535EAVJATLA
—
Note:
1. The last letter A indicates a Rev 1.2 silicon. It would be Rev 1.0 or Rev 1.1 silicon without a letter A
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Package Information
Table 84. MPC8535 Part Numbers Industrial Tier
Core/Platform/
DDR (MHz)
Standard Temp
Without Security
Standard Temp
With Security
Extended Temp
Without Security
Extended Temp
With Security
600/400/400
MPC8535BVJAKG(A) MPC8535EBVJAKG(A) MPC8535CVJAKG(A) MPC8535ECVJAKG(A)
800/400/400
MPC8535BVJANG(A) MPC8535EBVJANG(A) MPC8535CVJANG(A) MPC8535ECVJANG(A)
1000/400/400
MPC8535BVJAQG(A) MPC8535EBVJAQG(A) MPC8535CVJAQG(A) MPC8535ECVJAQG(A)
1250/500/500
MPC8535BVJATH(A) MPC8535EBVJATH(A) MPC8535CVJATH(A) MPC8535ECVJATH(A)
1250/500/667
MPC8535BVJATLA
—
—
—
Notes
1
2
Note:
1. The last letter A indicates a Rev 1.2 silicon. It would be Rev 1.0 or Rev 1.1 silicon without a letter A.
2. Contact a Freescale sales representative for more information.
5
Package Information
This section details package parameters, pin assignments, and dimensions.
5.1
Package Parameters for the FC-PBGA
The package parameters are as provided in the following list. The package type is 29 mm × 29 mm, 783 flip chip plastic ball
grid array (FC-PBGA) without a lid.
Package outline
Interconnects
Pitch
Minimum module height
Maximum module height
Solder Balls
Ball diameter (typical)
29 mm × 29 mm
783
1 mm
2.23 mm
2.8 mm
96.5Sn/3.5Ag
0.6 mm
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Package Information
5.2
Mechanical Dimensions of the FC-PBGA
The mechanical dimensions and bottom surface nomenclature of the 783 FC-PBGA package are shown in the following figure.
Figure 81. Mechanical Dimensions and Bottom Surface Nomenclature of the FC-PBGA
NOTES for Figure 81
1.
2.
3.
4.
All dimensions are in millimeters.
Dimensions and tolerances per ASME Y14.5M-1994.
Maximum solder ball diameter measured parallel to datum A
Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
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Product Documentation
5.
6.
7.
Capacitors may not be present on all devices
Caution must be taken not to short exposed metal capacitor pads on package top.
All dimensions are symmetric across the package center lines, unless dimensioned otherwise.
6
Product Documentation
The following documents are required for a complete description of the chip and are needed to design properly with the part.
•
•
MPC8536E PowerQUICC III Integrated Processor Reference Manual (document number: MPC8536ERM)
e500 PowerPC Core Reference Manual (document number: E500CORERM)
7
Document Revision History
This table provides a revision history for this hardware specification.
Table 85. Document Revision History
Revision
Date
Substantive Change(s)
7
07/2015
• In Section 4, “Ordering Information,” added back the “A” temperature range parts and the MPC8535
Part Numbers Commercial Tier table.
6
09/2014
• In Table 82, “Part Numbering Nomenclature,” added footnotes 4 and 5, and updated the Package
and Tiers and Temperature Range columns.
• In Section 4, “Ordering Information,” removed the “A” temperature range parts and the MPC8535
Part Numbers Commercial Tier table.
• Updated Table 73 and added note 3.
• Updated and added note 5 to Table 74.
• Updated section title to Section 4.1, “Part Numbering Nomenclature.”
• In Table 73, updated the DDR data rate for the 1250 MHz maximum column.
• Updated Table 84 and added note 2.
5
09/2011
Removed PVDD from Table 1, “Pinout Listing.”
4
06/2011
• In Table 1, “Pinout Listing,” updated the power supply for TSEC3 pins to TVDD.
• Updated Table 56, “eSDHC AC Timing Specifications.”
• In Section 4.3, “Part Numbering,” added an extra bin (1250/500/667) to support DDR3.
3
11/2010
• In Table 1, “Pinout Listing,” added the following note: “For systems that boot from Local Bus
(GPCM)-controlled NOR flash or (FCM) controlled NAND flash, a pullup on LGPL4 is required...”
In addition, updated footnote 26 and added footnote 29 to PCI1_AD.
• Updated Table 21
• Updated Figure 25, “RGMII and RTBI AC Timing and Multiplexing Diagrams.”
• In Table 44, “MII Management DC Electrical Characteristics,” changed the Voh/Vol values for
MDIO/MDC.
• Added Note 6 regarding USBn_DIR pin to Table 47, “USB General Timing Parameters6.”
• In Table 64, “I2C AC Electrical Specifications,” updated footnote 2.
• In Table 82, ,Table 83, , Table 84,added the Revision Level A for Rev 1.2
2
09/2009
Note:
• In Section 1, “Pin Assignments and Reset States,”updated the first sentence of the note to say, “The
UART_SOUT[0:1] and TEST_SEL pins must be set to a proper state during POR configuration.”
• In Table 40, “SGMII DC Receiver Electrical Characteristics,” changed LSTSAB to LSTSA and
LSTSEF to LSTSE for Note 4.
• Updated Die value and Bump/Underfill value in Table 84
Note: Updated Figure 81, “Mechanical Dimensions and Bottom Surface Nomenclature of the
FC-PBGA,” and its notes.
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Document Revision History
Table 85. Document Revision History (continued)
Revision
Date
Substantive Change(s)
1
09/2009
• In Table 3, “Recommended Operating Conditions,” for VDD_CORE, removed 1.1 ± 55 mV.
• In Table 5, “Power Dissipation 5,” remove note 5.
• In Table 5, ”Power Dissipation 5,” changed an “—”’ to “0.”
0
08/2009
Initial public release.
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Document Number: MPC8535EEC
Rev. 7
07/2015
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