AN-1381:如何为ADF4355-2设置VCO旁路校准 (Rev. 0) PDF

AN-1381
应用笔记
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如何为ADF4355-2设置VCO旁路校准
作者:Robert Brennan
VCO校准
7. 重复第1步至第6步,为全部目标频率建立一个查找表。
旁路VCO校准以缩短锁定时间
对于第1步,仅在第一次迭代后再需要写R10、R7、
对于任意给定输出频率,ADF4355-2都会采用特定的电压控
R2、R1和R0。如果无变化,则R2和R1为可选。
制振荡器(VCO)内核、频段和偏置代码。这三种设置在VCO
CORE AND BAND (R10 DB[28:26] = 1):
LE
自动校准(AUTOCAL)过程中自动选择。设置从ADF4355-2
读取并存储在查找表中。用该查找表旁路AUTOCAL例程
CLK
MUXOUT
X
可以缩短更改频率时的总锁定时间。例如,在环路带宽为
X
59.7 kHz时,可实现不到30 µs的锁定时间。图1所示为一款
1 0 0
CORE = A
合适的环路滤波器示例。
R2
5.1kΩ
R1
2.4kΩ
C2
3.3nF
VTUNE
kVCO = 15MHz/V
fPFD = 61.44MHz
PM = 46.5°
0 0 0
1
BAND = 70
VALUE
CORE
001
010
011
100
D
C
B
A
1
0
BIAS CODE (R10 DB[28:26] = 3):
C3
100pF
LBW = 59.7kHz
1
LE
CLK
ICP = 0.9mA
MUXOUT
X
图1. 环路带宽为59.7 kHz的环路滤波器示例
由于每块ADF4355-2芯片都具有唯一性,因此必须为每块
芯片生成一个新的查找表。
X
X
X
X
X
X
X
X
0
1 1
0
BIAS CODE = 6
NOTES
1. X = DON’T CARE.
2. MUXOUT MUST BE SET TO VCO READBACK (R4, DB[29:27] = 7).
3. VCO READBACK MUST BE SET TO VCO READBACK (R7, DB[14:12] = 7).
4. DATA IS CLOCKED OUT ON THE POSITIVE EDGE OF CLK AND READ ON
THE NEGATIVE EDGE OF CLK. READBACK STARTS ON THE FIRST CLK
EDGE AFTER LE GOES HIGH. LE MUST STAY HIGH DURING A READ.
13647-002
C1
220pF
13647-001
CP
0
图2. VCO回读
VCO回读程序
VCO回读程序如下:
旁路自动校准(AUTOCAL),手动选择VCO和锁定
1. 加载全部寄存器,锁定为目标频率。
如果目标频率的所需VCO内核、频段和偏置代码是已知的
a. 确保VCO读已设为VCO内核和频段(R10, DB[28:26] =
0b001)(见图5)。
b. 确保VCO回读已设为VCO校准完成(R7, DB[14:12] =
(例如,在一个查找表中),则可通过下列步骤旁路VCO校
准例程,并手动设置VCO数据:
1. 加载R0,其中,AUTOCAL被禁用(R0, DB21 = 0b0)。如
0b110)(见图4)。
果AUTOCAL已经被禁用,则这一步为可选步骤。
c. 确保MUXOUT已设为VCO回读(R4, DB[29:27] = 0b111)
2. 加载R10,其中,VCO写设为VCO内核和频段(R10, DB
[31:29] = 0b001)。
(见图3)。
d. 确保AUTOCAL已启用(R0, DB21 = 0b1);见ADF4355-2
3. 加载R11,其中,目标VCO内核、VCO频段和VCO偏置
按图6的规定进行设置。注意,读和写操作在VCO内核
数据手册中的R0寄存器图。
2. 等到MUXOUT输出一个逻辑高电平(VCO校准完成)。
位方面是不同的。
3. 加载R7,其中,VCO回读设为VCO回读(R7, DB[14:12] =
4. 加载R10,其中,VCO写设为VCO偏置代码(R10, DB
[31:29] = 0b011)。
0b111)。
4. 脉冲SPI CLK,同时LE保持高电平。数据在MUXOUT上
5. 以与第3步中相同的值重新加载R11。
6. 通过编程R2、R1和R0,分别锁定至目标频率。
输出。抽取数据,如图2所示。
5. 加载R10,其中,VCO读设为VCO偏置代码(R10, DB
[28:26] = 0b011)。
6. 对偏置数据重复第4步。
Rev. 0 | Page 1 of 4
AN-1381
COUNTER
RESET
CP THREESTATE
DBR 1
PD
MUX LOGIC
CURRENT
SETTING
PD
POLARITY
DBR 1
10-BIT R COUNTER
REF MODE
DBR 1
DOUBLE BUFF
MUXOUT
RESERVED
RDIV2
REFERENCE
DOUBLER DBR 1
扩展版ADF4355-2寄存器图
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
0
M3
M2
M1
RD2
RD1
R10
RD2
REFERENCE
DOUBLER
0
DISABLED
1
ENABLED
R9
R8
R7
R6
R5
R4
R3
R2
R1
D1
CP4
CP3
DISABLED
0
DISABLED
ENABLED
1
DIFF
1
CP2
CP1
ICP (mA)
5.1k�
ENABLED
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
0
..........
0
1
1
0
..........
1
0
2
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
1020
1
1
..........
0
1
1021
1
1
..........
1
0
1022
1
1
..........
1
1
1023
M3
M2
M1
OUTPUT
0
0
0
THREE-STATE OUTPUT
0
0
1
DVDD
0
1
0
0
1
1
DGND
R DIVIDER OUTPUT
1
0
0
N DIVIDER OUTPUT
1
0
1
ANALOG LOCK DETECT
1
1
0
DIGITAL LOCK DETECT
1
1
1
VCO READBACK
C1(0)
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
C4(0) C3(1) C2(0)
0
CP3
0
U1
COUNTER
RESET
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
R DIVIDER (R)
U2
U1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
R1
U3
SINGLE
CP4
R2
U4
REFIN
DISABLED
..........
U5
DB0
0
0
R9
U6
DB1
U6
REFERENCE DIVIDE BY 2
R10
CP1
DB2
DOUBLE BUFFERED
REGISTER 6, BITS[DB23:DB21]
D1
RD1
1
CP2
DB3
ENABLED
U5
LDP
U2
0
1.8V
CP
THREE-STATE
0
DISABLED
1
3.3V
1
ENABLED
U4
PD POLARITY
U3
POWER DOWN
0
NEGATIVE
0
DISABLED
1
POSITIVE
1
ENABLED
13647-003
0
CONTROL
BITS
1DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0 1
LE
LE
0 0
0
0
0 0
0
0 0
0
0
0
VR3
VR2
VR1
0
VR3 VR2 VR1
VCO READBACK
0
0
0
0
1
1
1
1
NORMAL OPERATION
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
VCO CALIBRATION COMPLETE
VCO READBACK
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
LD5
LD4
DB7 DB6 DB5 DB4
DB3
DB2
DB1
DB0
LD2 LD1 C4(0) C3(1) C2(1) C1(1)
LOL LD3
LD1
LE SYNCHRONIZATION
CONTROL
BITS
LOCK DETECT MODE
0
FRACTIONAL-N
1
INTEGER-N (2.9ns)
LD3 LD2
FRACTIONAL-N
LD PRECISION
0
0
1
1
5.0ns
6.0ns
8.0ns
12.0ns
0
1
0
1
LOL LOSS OF LOCK MODE
0
DISABLED
0
DISABLED
1
LE SYNCED TO REFIN
1
ENABLED
图4. 寄存器7
Rev. 0 | Page 2 of 4
LD5
LD4
LOCK DETECT CYCLE COUNT
0
0
1024
0
1
2048
1
0
4096
1
1
8192
13647-004
0
LD MODE
VCO READBACK
FRAC-N LD
PRECISION
RESERVED
LD
CYCLE
COUNT
LOL MODE
RESERVED
RESERVED
LE SYNC
图3. 寄存器4
VCO READ
ADC
CLOCK DIVIDER
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
VW2
VR3
VW1
VR2
VR1
0
1
0
0
0
0
0
0
0
0
AD8
AD7
AD6
AD5
AD4
DB7 DB6
AD3 AD2
DB5 DB4
DB3
DB2
AE1
ADC
0
DISABLED
0
0
0
0
1
1
1
1
NORMAL OPERATION
VCO CORE AND BAND
RESERVED
VCO BIAS CODE
RESERVED
RESERVED
RESERVED
RESERVED
1
ENABLED
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VCO WRITE
NORMAL OPERATION
VCO CORE AND BAND
RESERVED
VCO BIAS CODE
RESERVED
RESERVED
RESERVED
RESERVED
AD7
..........
AD2
0
0
..........
0
1
1
0
0
..........
1
0
2
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
252
1
1
..........
0
1
253
1
1
..........
1
0
254
1
1
..........
1
1
255
AD8
DB1
DB0
AE2 AE1 C4(1) C3(0) C2(1) C1(0)
AD1
VCO READ
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
1
VR3 VR2 VR1
VW3 VW2 VW1
0
0
1
1
0
0
1
1
0
CONTROL
BITS
AE2
ADC CONVERSION
0
DISABLED
1
ENABLED
AD1 ADC CLK DIV
13647-005
VW3
ADC ENABLE
VCO WRITE
ADC
CONVERSION
AN-1381
图5. 寄存器10
VCO CORE
RESERVED
VCO BIAS
CONTROL
BITS
VCO BAND
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0 0
0
0 0
0
0
0
1
C4 C3 C2 C1
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
C4
C3
C2
C1
B4
B3
B2
B1
BA8
BA7 BA6 BA5 BA4 BA3 BA2
DB2
DB1
DB0
BA C4(1) C3(0) C2(1) C1(0)
VCO CORE
RESERVED
CORE D/NORMAL OPERATION
CORE C
CORE B
CORE A
B4 B3 B2 B1
VCO BIAS
BA8 BA7 .......... BA2 BA1
0
0
0
0
0
0
0
0
1
0
1
2
3/NORMAL OPERATION
4
5
6
7
8
0
0
.
.
.
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
图6. 寄存器11
Rev. 0 | Page 3 of 4
0
0
.
.
.
1
1
1
1
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
0
.
.
.
0
0
1
1
0
0
.
.
.
0
1
0
1
VCO BAND
0/NORMAL OPERATION
1
.
.
.
252
253
254
255
13647-006
0
AN-1381
读取时序特性
表1. 读取时序
参数
t1
t2
t3
t4
t5
在TMIN至TMAX时的限值
15
15
25
25
10
单位
ns min
ns min
ns min
ns min
ns min
描述
LE高电平至CLK高电平
CLK高电平至DATA就绪
CLK高电平持续时间
CLK低电平持续时间
CLK高电平至LE低电平(下次写)
读取时序图
t1
t3
t4
CLK
t2
X
MUXOUT
DB11
DB2
DB1
DB0
t5
13647-007
LE
NOTES
1. LE MUST BE KEPT HIGH DURING READBACK.
2. X = DON’T CARE.
图7. 读取时序图
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AN13647sc-0-11/15(0)
Rev. 0 | Page 4 of 4
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