TFDU5307 Vishay Semiconductors Fast Low Profile (2.5 mm) Infrared Transceiver Module (MIR, 1.152 Mbit/s) for IrDA® Applications Description The TFDU5307 is an infrared transceiver module compliant to the latest IrDA physical layer standard, supporting IrDA speeds up to 1.152 Mbit/s (MIR) and carrier based remote control modes up to 2 MHz. Integrated within the transceiver module are a PIN photodiode, an infrared emitter (IRED), and a low-power control IC to provide a total front-end solution in a single package. This Vishay MIR transceiver is built in a low profile package using the experiences of the lead frame babyface technology. The transceivers are capable of directly interfacing with a wide variety of I/O devices, which perform the modulation/ demodulation function. At a minimum, a VCC bypass capacitor and a serial resistor for current control are the only external components required implementing a complete solution. TFDU5307 has a tri-state output and is floating in shutdown mode with a weak pull-up. Features • Compliant to the latest IrDA physical layer specification (up to 1.152 Mbit/s) and TV Remote Control, bi-directional e3 operation included. • Sensitivity covers full IrDA range. Recommended operating range is from nose to nose to 70 cm • Operates from 2.7 V to 5.5 V within specification • Low power consumption (typ. 0.55 mA Supply current in receive mode, no signal) • Power shutdown mode (< 5 µA Shutdown Current in Full Temperature Range, up to 85 °C) • Surface mount package, low profile universal (L 8.5 mm x W 2.9 mm x H 2.5 mm) Capable of surface mount soldering to Side and top view orientation • Backward pin compatible to Vishay Semiconductors SIR and MIR infrared transceivers • High efficiency emitter • Directly interfaces with various super I/O and controller devices • Tri-state-receiver output, floating in shut down with a weak pull-up • Split power supply, transmitter and receiver can be operated from two power supplies with relaxed requirements saving costs, US Patent No. 6,157,476 • Logic voltage 1.5 V to 5.5 V is independent of IRED driver and analog supply voltage • Only one external component required • TV remote control supported • Transmitter intensity can be adjusted by an external resistor for extended range (> 0.7 m) or minimum low power (> 0.2 m) IrDA compliance. • Lead (Pb)-free device • Device in accordance to RoHS 2002/95/EC and WEEE 2002/96EC Applications • Telecommunication products (cellular phones, pagers) • Digital still and video cameras • Printers, fax machines, photocopiers, screen projectors • Low power consumption (typ. 0.55 mA Supply current in receive mode, no signal) Document Number 82616 Rev. 1.5, 07-Apr-06 • Medical and industrial data collection • Notebook computers, desktop PCs, Palmtop Computers (Win CE, Palm PC), PDAs • Internet TV boxes, video conferencing systems • External infrared adapters (dongles) • Kiosks, POS, Point and Pay devices including IrFM - applications www.vishay.com 1 TFDU5307 Vishay Semiconductors Parts Table Part Description Qty / Reel TFDU5307-TR1 Oriented in carrier tape for side view surface mounting 750 pcs TFDU5307-TR3 Oriented in carrier tape for side view surface mounting 2500 pcs TFDU5307-TT1 Oriented in carrier tape for top view surface mounting 750 pcs TFDU5307-TT3 Oriented in carrier tape for top view surface mounting 2500 pcs Functional Block Diagram Vlogic Vcc1 Tri-State Driver Amplifier SD TXD Comparator Logic & Vcc2 RXD IRED Driver Control IRED C GND 18509 Pin Description Pin Number Function Description 1 IRED Anode Connect IRED anode to the VCC2 power supply through an external current limiting resistor. A separate unregulated power supply can be used at this pin. 2 IRED Cathode IRED Cathode, internally connected to the driver transistor 3 TXD 4 5 Active This Schmitt-Trigger input is used to transmit serial data when SD is low. An onchip protection circuit disables the LED driver if the TXD pin is asserted for longer than 80 μs. When used in conjunction with the SD pin, this pin is also used to control receiver output pulse duration. The input threshold voltage adapts to and follows the logic voltage reference applied to the Vlogic pin (pin 7). I HIGH RXD Received Data Output, push-pull CMOS driver output capable of driving standard CMOS or TTL loads. No external pull-up or pull-down resistor is required. Floating with a weak pull-up of 500 kΩ (typ.) in shutdown mode. The voltage swing is defined by the applied Vlogic voltage O LOW SD Shutdown. Also used for setting the output pulse duration. Setting this pin active for more than 1.5 ms places the module into shutdown mode. Before that (t < 0.7 ms) on the falling edge of this signal, the state of the TXD pin is sampled and used to set the receiver output to long pulse duration (2 µs) or to short pulse duration (0.4 μs) mode. The input threshold voltage adapts to and follows the logic voltage reference applied to the Vlogic pin (pin 7). I HIGH 6 VCC1 Supply Voltage 7 Vlogic Vlogic defines the logic voltage levels for input and output. The RXD output range is from 0 V to Vlogic, for optimum noise suppression the inputs’ logic decision level is 0.5 x Vlogic 8 GND Ground www.vishay.com 2 I/O I Document Number 82616 Rev. 1.5, 07-Apr-06 TFDU5307 Vishay Semiconductors Pinout Definitions: TFDU5307 weight 75 mg In the Vishay transceiver data sheets the following nomenclature is used for defining the IrDA operating modes: SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared standard with the physical layer version IrPhy 1.0 MIR: 576 kbit/s to 1152 kbit/s FIR: 4 Mbit/s VFIR: 16 Mbit/s MIR and FIR were implemented with IrPhy 1.1, followed by IrPhy 1.2, adding the SIR Low Power Standard. IrPhy 1.3 extended the Low Power Option to MIR and FIR and VFIR was added with IrPhy 1.4.A new version of the standard in any case obsoletes the former version. With introducing the updated versions the old versions are obsolete. Therefore the only valid IrDA standard is the actual version IrPhy 1.4 (in Oct. 2002). 18101 5 6 1 2 3 4 8 7 IRED A IRED C TXD RXD SD Vcc Vlog GND Absolute Maximum Ratings Reference point Ground (pin 8) unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Symbol Min Max Unit Supply voltage range, transceiver Parameter - 0.3 V < VCC2 < 6 V - 0.5 V < Vlogic < 5.5 V Test Conditions VCC1 - 0.3 + 6.0 V Supply voltage range, transmitter - 0.5 V < VCC1 < 6 V - 0.5 V < Vlogic < 5.5 V VCC2 - 0.3 + 6.5 V Supply voltage range, Vlogic - 0.5 V < VCC1 < 6 V - 0.3 V < VCC2 < 6.5 V Vlogic - 0.3 + 5.5 V Input current for all pins, except IRED anode pin 10 mA Output sinking current Power dissipation see derating curve, figure 4 Junction temperature PD TJ Typ. 25 mA 500 mW 125 °C Ambient temperature range (operating) Tamb - 25 + 85 °C Storage temperature range Tstg - 25 + 85 °C 260 °C IIRED(DC) 125 mA IIRED(RP) 600 mA V Soldering temperature see recommended solder profile (figure 3) Average output current, pin 1 Repetitive pulsed output current, pin 1 to pin 2 t < 90 µs, ton < 20 % IRED anode voltage, pin 1 Voltage at all inputs and outputs Vin < VCC1 is allowed Load at mode pin when used as mode indicator Document Number 82616 Rev. 1.5, 07-Apr-06 VIREDA - 0.5 + 6.5 Vin - 0.5 + 5.5 V 50 pF www.vishay.com 3 TFDU5307 Vishay Semiconductors Eye safety information Symbol Min Typ. Virtual source size Parameter Method: (1-1/e) encircled energy d 1.8 2.0 Maximum intensity for class 1 IEC60825-1 or EN60825-1, edition Jan. 2001, operating below the absolute maximum ratings Ie *) Test Conditions Max Unit mm (500)*) **) mW/sr Max Unit Due to the internal limitation measures the device is a "class 1" device. **) IrDA specifies the max. intensity with 500 mW/sr. Electrical Characteristics Transceiver Tamb = 25 °C, VCC1 = VCC2 = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Supply voltage Symbol Min VCC1 2.7 Typ. 5.5 V Idle supply current SD = Low, Ee = 1 klx ICC1 550 900 µA Average dynamic supply current, transmitting IIRED = 500 mA, 25 % Duty Cycle ICC 1100 1500 µA Shutdown supply current SD = High, T = 25 °C, Ee = 0 klx ISD 1 µA SD = High, T = 25 °C, ISD 2.5 µA SD = High, T = 85 °C, not ambient light sensitive ISD 5 µA + 85 °C Output voltage low, RXD CLoad = 15 pF, IOL = 1 mA VOL 0.4 V Output voltage high, RXD IOH = - 500 µA VOH 0.8 x Vlogic VOH 0.9 x Vlogic RRXD 400 Ee = 1 klx*) Standby supply current Operating temperature range TA IOH = - 250 µA, CLoad = 15 pF RXD to VCC1 impedance Input voltage low (TXD, SD) - 25 V V 500 600 kΩ V VIL - 0.5 0.5 VIH Vlogic - 0.5 Vlogic + 0.5 V Input leakage current (TXD, SD) Vin = 0.9 x Vlogic IICH -2 +2 µA Controlled pull down current SD, TXD = "0" to "1", 0 < Vin < 0.15 Vlogic IIRTx + 150 µA SD, TXD = "0" to "1", Vin > 0.7 Vlogic IIRTx 1 µA 5 pF Input voltage high (TXD, SD) Input capacitance (TXD, SD) *) CMOS level**) CIN -1 0 Standard illuminant A **) The typical threshold level is 0.5 x Vlogic. It is recommended to use the specified min/max values to avoid increased operating current. The inputs in low state are actively loaded for noise protection. See for that the "Controlled pull down current" spec. Equivalently a pull up current stabilizes the state when the inputs are in high state. www.vishay.com 4 Document Number 82616 Rev. 1.5, 07-Apr-06 TFDU5307 Vishay Semiconductors Optoelectronic Characteristics Receiver Tamb = 25 °C, VCC = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Symbol Min Typ. Max Unit 40 (4) 90 (9) mW/m2 Minimum detection threshold irradiance 9.6 kbit/s to 1.152 Mbit/s λ = 850 nm - 900 nm Ee Maximum detection threshold irradiance λ = 850 nm - 900 nm Ee No detection receiver input irradiance Threshold! No RXD output below this irradiance value allowed Ee Rise time of output signal 10 % to 90 %, CL = 15 pF, Vlogic = VCC tr(RXD) 20 60 ns Fall time of output signal 90 % to 10 %, CL = 15 pF, Vlogic = VCC tf(RXD) 20 60 ns input pulse length RXD pulse width of output signal, default mode after power PWopt > 200 ns on or reset tPW 300 400 500 ns SIR ENDEC compatibility tPW 1.7 2.0 2.9 µs input irradiance = 100 mW/m2, 1.152 Mbit/s, 576 kbit/s 80 ns input irradiance = 100 mW/m2, ≤ 115.2 kbit/s 350 ns 1.5 ms 600 µs 300 µs 200 µs mode*): RXD pulse width of output signal Stochastic jitter, leading edge input pulse length PWopt > 200 ns, see chapter "Programming" Standby /Shutdown delay after shutdown active or (SD low to high transition) Shutdown active time window for programming During this time the pulse duration of the output can be programmed to the application mode. see chapter "Programming" tL kW/m2 (mW/cm2) 4 (0.4) 0.6 Receiver start up time power on after shutdown inactive (SD high delay shutdown recovery delay to low transition) and after power-on Latency 5 (500) (µW/cm2) mW/m2 (µW/cm2) *) Some ENDECs are not able to decode short pulses as valid SIR pulses. Therefore this additional mode was added in TFDU5307. TFDU5307 is set to the "short output pulse" as default after power on, also after recovering from the shutdown mode (SD must have been longer active than 1.5 ms). For mode changing see the chapter "Programming" Document Number 82616 Rev. 1.5, 07-Apr-06 www.vishay.com 5 TFDU5307 Vishay Semiconductors Transmitter Tamb = 25 °C, VCC = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions VCC2 = 3.3 V: RS = 2.0 Ω IRED operating current, recommended serial resistor for VCC2 = 5.0 V: RS = 5.6 Ω MIR applications Output leakage IRED current TXD = 0 V, 0 < VCC1 < 5.5 V Output radiant intensity recommended application circuit, see figure 1 α = 0 °, If =420 mA Symbol Min ID Typ. Max Unit 450 500 mA IIRED -1 1 µA Ie 110 500 mW/sr Ie 70 500 mW/sr 0.04 mW/sr TXD = High, SD = Low **) α = 0 °, 15 °, If =420 mA 120 TXD = High, SD = Low **) Output radiant intensity VCC1 = 5.0 V, α = 0 °, 15 ° TXD = Low or SD = High (Receiver is inactive as long as SD = High) Ie α Output radiant intensity, angle of half intensity Peak - emission wavelength*) λp Spectral bandwidth Δλ 880 6 topt 190 (147.6) input pulse width tTXD < 80 µs topt input pulse width tTXD ≥ 80 µs topt input pulse width 217 ns, 1.152 Mbit/s Note: IrDA specification for MIR Optical overshoot ° 900 45 tropt, tfopt Optical rise time, fall time Optical output pulse duration ± 24 nm nm 40 ns 240 (260) ns ns 20 tTXD µs 20 85 µs 25 % 217 *) Note: Due to this wavelength restriction compared to the IrDA spec of 850 nm to 900 nm the transmitter is able to operate as source for the standard Remote Control applications with codes as e.g. Philips RC5/RC6® or RECS 80. When operated under IrDA full range conditions (>120 mW/sr) the RC range to be covered is in the range from 8 m to 12 m, provided that state of the art remote control receivers are used. **) Typ. conditions for If = 420 mA, VCC2 = 3.3 V, Rs = 2.3 Ω, VCC2 = 5.0 V, Rs = 6.4 Ω www.vishay.com 6 Document Number 82616 Rev. 1.5, 07-Apr-06 TFDU5307 Vishay Semiconductors Recommended Circuit Diagram Used with a clean low impedance power supply the TFDU5307 only needs an external series current limiting resistor. However, depending on the entire system design and board layout, additional components may be required (see figure 1). V IRED R1 V cc IRED Anode V cc R2 C1 GND C2 Ground Vlogic Vlogic SD SD TXD TXD RXD RXD IRED Cathode 18147 Figure 1. Recommended Application Circuit The capacitor C1 is buffering the supply voltage and eliminates the inductance of the power supply line. This one should be a Tantalum or other fast capacitor to guarantee the fast rise time of the IRED current. The resistor R1 is the current limiting resistor and this is supply voltage dependent, see derating curve in figure 4, to avoid too high internal power dissipation. Vishay’s transceivers integrate a sensitive receiver and a built-in power driver. The combination of both needs a careful circuit board layout. The use of thin, long, resistive and inductive wiring should be avoided. The inputs (TXD, SD) and the output RXD should be directly (DC) coupled to the I/O circuit. The capacitor C2 combined with the resistor R2 is the low pass filter for smoothing the supply voltage. R2, C1 and C2 are optional and dependent on the quality of the supply voltages and injected noise. An unstable power supply with dropping voltage during transmission may reduce the sensitivity (and transmission range) of the transceiver. The placement of these parts is critical. It is strongly recommended to position C2 as close as possible to the transceiver power supply pins. A Tantalum capacitor should be used for C1 while a ceramic capacitor is used for C2. In addition, when connecting the described circuit to the power supply, low impedance wiring should be used. When extended wiring is used the inductance of the power supply can cause dynamically a voltage drop at VCC2. Often some power supplies are not apply to follow the fast current rise time. In that case another 4.7 µF (type, see table under C1) at VCC2 will be helpful. Under extreme EMI conditions as placing an RFtransmitter antenna on top of the transceiver, we recommend to protect all inputs by a low-pass filter, as a minimum a 12 pF capacitor, especially at the RXD port. Keep in mind that basic RF - design rules for circuit design should be taken into account. Especially longer signal lines should not be used without termination. See e.g. "The Art of Electronics" Paul Horowitz, Winfield Hill, 1989, Cambridge University Press, ISBN: 0521370957. Table 1. Recommended Application Circuit Components Component Recommended Value C1 4.7 µF, 16 V, Tantalum 293D 475X9 016B C2 0.1 µF, Ceramic VJ 1206 Y 104 J XXMT R1 5 V supply voltage: 5.6 Ω s. text 0.25 W (recommended e.g. 2 x CRCW-1206-2R0-F-RT1 for 3.3 V supply voltage using two 2.8 Ω, 0.125 W resistors in series). 3.3 V supply voltage: 2.0 Ω s. text 0.25 W R2 Document Number 82616 Rev. 1.5, 07-Apr-06 Vishay Part Number 47 Ω, 0.125 W CRCW-1206-47R0-F-RT1 www.vishay.com 7 TFDU5307 Vishay Semiconductors I/O and Software In the description, already different I/Os are mentioned. Different combinations are tested and the function verified with the special drivers available from the I/O suppliers. In special cases refer to the I/ O manual, the Vishay application notes, or contact directly Vishay Sales, Marketing or Application. Programming Pulse duration Switching After Power-on the TFDU5307 is in the default short RXD pulse duration mode. Some ENDECs are not able to decode short pulses as valid SIR pulses. Therefore an additional mode with extended pulse duration (same as in standard SIR transceivers) is added in TFDU5307. TFDU5307 is set to the "short output pulse" as default after power on, and after recovering from the shutdown mode (SD being active longer than 1.5 ms). To switch the transceivers from the short RXD pulse duration mode to the long pulse duration mode and vice versa, follow the procedure described below. Setting to the ENDEC compatibility mode with an RXD pulse duration of 2 µs 1. Set SD input to logic "HIGH". 2. Set TXD input to logic "LOW". Wait ts ≥ 200 ns. 3. Set SD to logic "LOW" (this negative edge latches state of TXD, which determines speed setting). 4. After waiting th ≥ 200 ns. After that TXD is enabled as normal TXD input and the RXD output is set for the longer RXD - pulse duration mode. Setting back to the default mode with a 400 ns pulse duration 1. Set SD input to logic "HIGH". 2. Set TXD input to logic "HIGH". Wait ts ≥ 200 ns. www.vishay.com 8 3. Set SD to logic "LOW" (this negative edge latches state of TXD, which determines speed setting). 4. After waiting th ≥ 200 ns TXD can be set to logic "LOW". The hold time of TXD is limited by the maximum allowed pulse length. After that TXD is now enabled as normal TXD input and the RXD output is set for the short RXD - pulse duration mode. The timing of the pulse duration changing procedure is quite uncritical. However, the whole change must not take more than 600 µs. See in the spec. "Shutdown Active Time Window for Programming" SD 50 % ts th High: TXD 50 % 400 ns 50 % Low: 2 µs 18150 Figure 2. Timing Diagram for changing the output pulse duration Simplified Method Setting the device to the long pulse duration is simply applying a short active (less than 600 µs) pulse to SD. In any case a short SD pulse will force the device to leave the default mode and go the compatibility mode. Vice versa applying a 1.5 ms (minimum) pulse at SD will cause the device to go back to the default mode by activating a power-on-reset and setting the device to the default short pulse mode. This simplified method takes more time but may be easier to handle. Document Number 82616 Rev. 1.5, 07-Apr-06 TFDU5307 Vishay Semiconductors Table 2. Truth table Inputs Outputs Remark SD TXD Optical input Irradiance mW/m2 RXD Transmitte r Operation high < 600 µs x x weakly pulled (500 kΩ) to VCC1 0 Time window for pulse duration setting high > 1.5 ms x x weakly pulled (500 kΩ) to VCC1 0 Shutdown low high x low (active) Ie Transmitting high > 80 ms x high inactive 0 Protection is active low <4 high inactive 0 Ignoring low signals below the IrDA defined threshold for noise immunity low > Minimum irradiance Ee < Maximum irradiance Ee low (active) 0 Response to an IrDA compliant optical input signal low > Maximum irradiance Ee undefined 0 Overload conditions can cause unexpected outputs Document Number 82616 Rev. 1.5, 07-Apr-06 www.vishay.com 9 TFDU5307 Vishay Semiconductors Recommended Solder Profile Solder Profile for Sn/Pb soldering 260 10 s max. at 230 °C 240 °C max. 240 Temperature/°C 220 2...4 °C/s 200 180 160 °C max. 160 140 120 s...180 s 120 90 s max. 100 80 2...4 °C/s 60 40 20 0 0 50 100 150 200 250 300 Time/s 350 19431_1 Figure 3. Recommended Solder Profile for Sn/Pb soldering Lead-Free, Recommended Solder Profile The lead-frame based transceivers (all types with the name TFDUxxxx) are lead (Pb)-free and qualified for lead (Pb)-free and lead - bearing processing. In case of using a lead-bearing process we recommend a solder profile as shown in figure 4. For lead (Pb)-free solder paste like Sn-(3.0-4.0)Ag(0.5-0.9)Cu, there are two standard reflow profiles: Ramp-Soak-Spike (RSS) and Ramp-To-Spike (RTS). The Ramp-Soak-Spike profile was developed primarily for reflow ovens heated by infrared radiation. With widespread use of forced convection reflow ovens the Ramp-To-Spike profile is used increasingly. Shown below in figure 5 and figure 6 are VISHAY’s recommende profiles for use with the TFDUxxxx transceivers for lead (Pb)-free processing. 280 T ≥ 255 °C for 20 s max 260 T peak = 260 °C max. 240 T ≥ 217 °C for 50 s max 220 200 Temperature/°C 180 160 20 s 140 120 90 s...120 s 100 50 s max. 2 °C...4 °C/s 80 60 2 °C...4 °C/s 40 20 0 0 50 100 150 200 250 300 350 19261 Time/s Figure 4. Solder Profile, RSS Recommendation www.vishay.com 10 Document Number 82616 Rev. 1.5, 07-Apr-06 TFDU5307 Vishay Semiconductors 280 Tpeak = 260 °C max 260 240 220 Temperature/°C 200 180 < 4 °C/s 160 1.3 °C/s 140 Time above 217 °C t ≤ 70 s Time above 250 °C t ≤ 40 s Peak temperature Tpeak = 260 °C 120 100 80 < 2 °C/s 60 40 20 0 0 50 100 150 200 250 300 Time/s Figure 5. Solder Profile, RTS Recommendation A ramp-up rate less than 0.9 °C/s is not recommended. Ramp-up rates faster than 1.3 °C/s damage an optical part because the thermal conductivity is less than compared to a standard IC. Current Derating Diagram Figure 6 shows the maximum operating temperature when the device is operated without external current limiting resistor. A power dissipating resistor of 2 Ω is recommended from the cathode of the IRED to Ground for supply voltages above 4 V. In that case the device can be operated up to 85 °C, too. Ambient Temperature (°C) 90 85 80 75 70 65 60 55 50 2.0 18097 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Operating Voltage [V] at duty cycle 20 % Figure 6. Temperature Derating Diagram Document Number 82616 Rev. 1.5, 07-Apr-06 www.vishay.com 11 TFDU5307 Vishay Semiconductors TFDU5307 - TinyFace (Universal) Package (Dimensions in mm) (Mechanical Dimensions) 18100 www.vishay.com 12 Document Number 82616 Rev. 1.5, 07-Apr-06 TFDU5307 Vishay Semiconductors Reel Dimensions 14017 Tape Width A max. N W1 min. W2 max. W3 min. mm mm mm mm mm mm mm 16 330 50 16.4 22.4 15.9 19.4 Document Number 82616 Rev. 1.5, 07-Apr-06 W3 max. www.vishay.com 13 TFDU5307 Vishay Semiconductors Tape Dimensions in mm 19855 Drawing-No.: 9.700-5280.01-4 Issue: 1; 03.11.03 Figure 7. Tape drawing, TFDU5307 for top view mounting www.vishay.com 14 Document Number 82616 Rev. 1.5, 07-Apr-06 TFDU5307 Vishay Semiconductors 19856 Drawing-No.: 9.700-5279.01-4 Issue: 1; 08.12.04 Figure 8. Tape drawing, TFDU5307 for side view mounting Document Number 82616 Rev. 1.5, 07-Apr-06 www.vishay.com 15 TFDU5307 Vishay Semiconductors Ozone Depleting Substances Policy Statement It is the policy of Vishay Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. Vishay Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Vishay Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use Vishay Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify Vishay Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Vishay Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany www.vishay.com 16 Document Number 82616 Rev. 1.5, 07-Apr-06 Legal Disclaimer Notice Vishay Notice Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies. Information contained herein is intended to provide a product description only. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Vishay for any damages resulting from such improper use or sale. Document Number: 91000 Revision: 08-Apr-05 www.vishay.com 1