ADP1043A Two Stage Buck + Full Bridge

ADP1043A Evaluation Board
Two Stage Buck + Full Bridge
PRD 1152
Reference Design
FEATURES
Voltage-Fed Buck+Full Bridge with Synchronous Rectifier
Voltage Feedback Loop
Dimensions: 116.8mm×61mm×12.7mm (Full Brick)
Input Voltage Range: -36V to -60VDC
28V/14A DC Output from -48V DC Input
94% Max. Efficiency
I2C serial interface
Software GUI
PRD 1152 OVERVIEW
This Evaluation Board allows the ADP1043A to be quickly evaluated in a switching power supply application. Using the evaluation
board and its accompanying software, the ADP1043A can be interfaced to any PC running Windows 2000, Windows NT, Windows XP
and Windows Vista via the computer's USB port.
The software allows control and monitoring of the ADP1043A internal registers. The board is set up for the ADP1043A to act as an
isolated switching power supply, outputting a 28V/14A DC voltage from a -36 to -60VDC input.
EVALUATION EQUIPMENT
To evaluate this demo board, a PC, oscilloscope, electronic load and a DC power source are required.
Figure 1 Voltage-Fed Buck+ Full Bridge Converter.
CS+
L
Q1
Q5
Q3
Lo
Vin
-36V ~ -60V
SR2
Cin
Q2
Cb
Co
Q4
5V’
Driver
Driver
12V
Q6
5V’
SR1
ADuM3200
ADuM3201
Vo
28V/14A
Co’
Rs
ADP3634
3.3V
OUTA SR1 SR2 CS2- CS2+
OUTB
VS3+
3.3V
OUTAUX
PSON
3.3V
12V
R1
R2
ADP1043A
VS3-
ADP1720
Aux Power
VDD
CS1 DGND AGND
CS+
12V’
5V’
SCL
SDA
Rev. Prelim.A, Oct 2009
10/30/2009 4:15:00 PM
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its
use. Specifications subject to change without notice. No license is granted by
implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2009 Analog Devices, Inc. All rights reserved.
Reference Design
PRD 1152
TABLE OF CONTENTS
Features ......................................................................................................................................................................................................... 1 PRD 1152 Overview ..................................................................................................................................................................................... 1 Evaluation Equipment ................................................................................................................................................................................... 1 Evaluation Board Hardware .......................................................................................................................................................................... 4 Specifications ............................................................................................................................................................................................ 4 Topology and operation waveforms .......................................................................................................................................................... 4 Connectors................................................................................................................................................................................................. 5 Interface Connector ................................................................................................................................................................................... 5 Test Results ................................................................................................................................................................................................... 7 Getting Started............................................................................................................................................................................................. 10 Equipment ............................................................................................................................................................................................... 10 Setup........................................................................................................................................................................................................ 10 Board Evaluation ......................................................................................................................................................................................... 12 Line and Load Voltage Regulation .......................................................................................................................................................... 12 Output Voltage Setting ............................................................................................................................................................................ 12 Soft Start.................................................................................................................................................................................................. 12 Digital Filter – Transient Analysis ........................................................................................................................................................... 13 PWM – Switching Frequency ................................................................................................................................................................. 14 Light Load Optimization ......................................................................................................................................................................... 14 Primary Side Current Sense and Secondary Side Current Sense ............................................................................................................. 14 Flags and Fault configurations ................................................................................................................................................................ 15 Flag and Fault Response Configuration: ............................................................................................................................................. 15 Appendix ..................................................................................................................................................................................................... 17 Schematic ................................................................................................................................................................................................ 17 Bill of Materials ...................................................................................................................................................................................... 21 PCB Layout ............................................................................................................................................................................................. 24 Board Setting ........................................................................................................................................................................................... 25 Register Setting ....................................................................................................................................................................................... 26 NOTES ........................................................................................................................................................................................................ 30 Rev. Prelim.A Oct.2009| Page 2 of 30
Reference Design
PRD 1152
TABLE OF FIGURES
Figure 1 Voltage-Fed Buck+ Full Bridge Converter. .................................................................................................................................... 1 Figure 2 Driver signal ................................................................................................................................................................................... 4 Figure 3 Pin Connection Diagram (Top View) ............................................................................................................................................. 5 Figure 4 Eval Board Picture(Top View)....................................................................................................................................................... 6 Figure 5 Test Configuration for the Evaluation Board .................................................................................................................................. 6 Figure 6 Efficiency ....................................................................................................................................................................................... 7 Figure 7 Output Voltage Response................................................................................................................................................................ 7 Figure 8 Output Voltage Response................................................................................................................................................................ 7 Figure 9 Output Voltage Ripple at No Load Current. ................................................................................................................................... 7 Figure 10 Output Voltage Ripple at Nominal Load Current. ........................................................................................................................ 8 Figure 11 Turn-on Transient at No Load Current.......................................................................................................................................... 8 Figure 12 Turn-on transient at Nominal Load Current. ................................................................................................................................ 8 Figure 13 Output Over Current ..................................................................................................................................................................... 8 Figure 14 Output Short Circuit (Latch Mode) .............................................................................................................................................. 9 Figure 15 Output Short Circuit (Recovery Mode). ....................................................................................................................................... 9 Figure 16 Connection with Computer ......................................................................................................................................................... 10 Figure 17 Getting Started ............................................................................................................................................................................ 10 Figure 18 Load Board Setting ......................................................................................................................................................................11 Figure 19 Graphical User Interface............................................................................................................................................................. 12 Figure 20 General Settings Window ........................................................................................................................................................... 13 Figure 21 Digital Filter Window ................................................................................................................................................................. 13 Figure 22 Timing Window .......................................................................................................................................................................... 14 Figure 23 Light Load Current Threshold .................................................................................................................................................... 14 Figure 24 Flags ........................................................................................................................................................................................... 15 Figure 25 Fault Configurations ................................................................................................................................................................... 16
Figure 26 Primary Main Circuit .................................................................................................................................................................. 17
Figure 27 Secondary Main Circuit .............................................................................................................................................................. 18
Figure 28 ADP1043A Control Circuit ........................................................................................................................................................ 19
Figure 29 ON/OFF Circuit .......................................................................................................................................................................... 19 Figure 30 Aux. Power Circuit ..................................................................................................................................................................... 20 Figure 31 Top View of Board...................................................................................................................................................................... 24
Figure 32 Bottom View of Board ................................................................................................................................................................ 24 Rev. Prelim.A Oct.2009| Page 3 of 30
Reference Design
PRD 1152
EVALUATION BOARD HARDWARE
SPECIFICATIONS
•
Nominal input voltage: -48 DC
•
Input voltage range: -36~-60V DC
•
Nominal output voltage: 28V DC
•
Nominal output current: 14A DC
•
Buck stage switching frequency: 300kHz
•
Full bridge switching frequency: 150kHz
•
Efficiency: 93% at full load
TOPOLOGY AND OPERATION WAVEFORMS
A typical DC/DC switching power supply is the basis for the eval board. It is a voltage-fed buck + full bridge topology, shown as Figure
1.The buck converter, as the first stage, regulates the output voltage. The full bridge is an isolated converter, which operates with 50%
duty cycle.
The primary side consists of the input terminals, buck and full bridge switches and the inductor and main transformer. The gate driver
signal for the switches comes from the ADP1043A, through the iCoupler and the drivers. There is also a current transformer (CT), to
transmit the primary side current information to the ADP1043A on the secondary side.
Figure 2 Driver Signal
The secondary side power stage consists of the synchronous rectifiers, output capacitor, sensing resistor. This provides 28V @ 14A at the
output. The ADP1043A is located on the secondary side. The ADP1043A provides the feedback signal that is used to regulate the
voltage, limit the current, and allow current sharing and shutdown to be implemented. Low side current sensing is used.
There is a 8pins connector on the board. 4pins of the connector is for I2C. This allows the PC software to communicate with the eval
board through the USB port of the PC. The user can readily change register settings on the ADP1043A this way, and also monitor the
status registers.
The eval board is designed with a 2mOhm RSENSE resistor. The power supply support a maximum continuous output of 14 A.
A variable load is required to perform a thorough evaluation. The output voltage is available between P4, P5, P6 and P7, P8, P9. This is
also where the load should be connected.
Rev. Prelim.A Oct.2009| Page 4 of 30
Reference Design
PRD 1152
The power supply will be in Continuous Conduction Mode. If the synchronous rectifiers are enabled, the power supply will remain in
CCM mode over the full load range.
Figure 3 Pin Connection Diagram (Top View)
CONNECTORS
The connections to the eval board are shown in Table 1.
Table 1. Power module pin assignment
Pin
Designation
Eval Board Function
P1
On/Off
Remote Control
P2
Vin+
Positive Input
P3
Vin-
Negative Input
P4-P6
Vo+
Positive Output
P7-P10
Vo-
Negative Output
P10
Interface
Interface
INTERFACE CONNECTOR
The signal pins are P10.1~P10.8 as shown in Table 2. Among them P10.7, P10.5, P10.3 and P10.1 are connected to USB dongle.
Table 2. Signal pins
Pin
Designation
Pin
Designation
P10.1
GND
P10.5
SCL
P10.2
PGOOD
P10.6
Vsen-
P10.3
SDA
P10.7
5V
P10.4
Vsen+
P10.8
Share
Rev. Prelim.A Oct.2009| Page 5 of 30
Reference Design
PRD 1152
Figure 4 shows the photo of eval board. Figure 5 provides a typical circuit diagram which details the filtering for normal operation and
output ripple test.
Figure 4 Eval Board Picture(Top View)
Figure 5 Test Configuration for the Evaluation Board
Rev. Prelim.A Oct.2009| Page 6 of 30
Reference Design
PRD 1152
TEST RESULTS
Figure 6 Efficiency at nominal output voltage vs. load current for
minimum, nominal, and maximum input voltage at 25°C.
Figure 7 Output voltage response to step-change in load current (25%50% of Iout(max): dI/dt = 1A/μs). Ch 2: Vout (200mV/div), Ch 4: Iout
(5A/div).
Figure 8 Output voltage response to step-change in load current (50%- Figure 9 Output voltage ripple at nominal input voltage and no load
current . Ch 1: Vout (50mV/div), Bandwidth: 20 MHz.
25% of Iout(max): dI/dt = 1A/μs). Ch 2: Vout (200mV/div), Ch 4: Iout
(5A/div).
Rev. Prelim.A Oct.2009| Page 7 of 30
Reference Design
PRD 1152
Figure 10 Output voltage ripple at nominal input voltage and nominal
load current. Ch 1: Vout (50mV/div), Bandwidth: 20 MHz
Figure 11 Turn-on transient at nominal input voltage and no load
current. Ch 1: Vout (10V/div), Ch 4: Load Current
Figure 12 Turn-on transient at nominal input voltage and nominal load Figure 13 Output over current protection function. Increase load
current. Ch 1: Vout (10V/div), Ch 4: Load Current (10A/div).
current at nominal input voltage to over current limit. Ch 3: Vout
(10V/div), Ch 4: Load Current (10A/div).
Rev. Prelim.A Oct.2009| Page 8 of 30
Reference Design
PRD 1152
Figure 14 Output short circuit protection function (Latch Mode). Turn
Figure 15 Output short circuit protection function (Recovery Mode).
on at nominal input voltage and nominal load current then short circuit. Turn on at nominal input voltage and nominal load current then short
Ch 3: Vout (10V/div), Ch 4: Load Current (10A/div).
circuit. Ch 3: Vout (10V/div), Ch 4: Load Current (10A/div).
Rev. Prelim.A Oct.2009| Page 9 of 30
Reference Design
PRD 1152
GETTING STARTED
EQUIPMENT
•
•
•
•
•
•
DC Power Supply 0-60V (Sorensen DLM150-20E)
Electronic Load capable of 28V/14A (Chroma 63112)
Oscilloscope (Tektronix TDS5054B)
PC with ADP1043A GUI installed
Precision Digital Multi-meters (Agilent 34401A)
Current Probe for measuring up to 14A DC (Tektronix TCP202)
SETUP
NOTE: DO NOT CONNECT THE USB CABLE TO THE EVAL BOARD UNTIL AFTER THE SOFTWARE HAS BEEN
INSTALLED.
Figure 16 Connection with Computer
1.
Install the ADP1043A software. Refer to the Quick Start Guide that comes on the CD (If already installed, skip to the next
step).
2.
Connect the evaluation board to the USB port on the computer, using the “USB to I2C interface” dongle. If the dongle driver
was not previously installed, run the software from the Start Menu under “Programs/Analog Devices/ADP1043A”.
3.
The software should report that the ADP1043A has been located on the board. Click Finish to proceed to the Main Software
Interface Window.
Figure 17 Getting Started
4.
Click on the
icon and “Load Board Setting”: select the “PRD1152.43b” file. This file contains all the board information
including values of shunt and voltage dividers.
Rev. Prelim.A Oct.2009| Page 10 of 30
Reference Design
PRD 1152
Figure 18 Load Board Setting
5.
The ADP1043A is pre-programmed and calibrated, so there is no programming necessary.
6.
Connect an electronic load at the output.
7.
For the input voltage source, a DC power supply can be used. The input voltage range is -36V to -60 VDC (-48VDC is
recommended). This input voltage is the signal which will be regulated to provide a 28V/14A supply at the output. Set the
voltage to -48VDC
8.
The evaluation board should now up and running, and ready to evaluate. The output should be 28 VDC.
Rev. Prelim.A Oct.2009| Page 11 of 30
Reference Design
PRD 1152
BOARD EVALUATION
The ADP1043A is optimized for improving the power supply design and evaluation process. The goal of this eval kit is to allow the user
to get an insight into the flexibility offered by the extensive programming options offered by the ADP1043A.
The ADP1043A performs many monitoring and housekeeping functions in the power supply. The eval board allows the user to simulate
various events that could affect the ADP1043A in a working system. The user can monitor how the ADP1043A handles this event in
many ways. One way is to use an oscilloscope and/or multi-meter, and probe the eval board, to see various conditions in the system. The
user can also use the software to monitor the conditions of the ADP1043A, and how it has reacted to the event. The following section
gives some experiments that the user might typically evaluate.
LINE AND LOAD VOLTAGE REGULATION
Vary the input voltage from -36 VDC to -60VDC. The output voltage remains 28V. Vary the load current from 0 to 14A. The output
voltage remains 28V. The line and load regulation are less than ±0.5%.
Figure 19 Graphical User Interface
OUTPUT VOLTAGE SETTING
The output voltage setting is programmable. Using the Voltage Setting window in the software, adjust the output voltage (using the o/p
trim menu). Monitor the actual output voltage of the power supply using the software or a multi-meter, or looking at the output voltage
reading on the electronic load. It should match the programmed value. This will be used to calibrate the power supply in the production
environment. By doing this evaluation, the user can see how the ADP1043A can be trimmed digitally to adjust the output voltage.
SOFT START
Once the input voltage is applied it is possible to test the Soft Start of the ADP1043A. The settings are located in the General Settings
Window. Please refer to the Software Reference Guide for a detailed explanation of all the controls (EVAL-ADP1043A-GUI-RG).
Rev. Prelim.A Oct.2009| Page 12 of 30
Reference Design
PRD 1152
Figure 20 General Settings Window
Soft Start is enabled and set to 40ms. You can experiment with different times.
DIGITAL FILTER – TRANSIENT ANALYSIS
The digital filter can be changed using the software. The effect on transient analysis can be evaluated this way. Connect a switching
electronic load to the output of the eval board. The load should be set to switch between 25%-50%, changing every 10msecs. Set up an
oscilloscope to capture the transient waveform of the power supply output.
Use a differential probe on the scope, connecting it to the eval board output. Turn on the load, and note the waveform response.
Now, vary the digital filter using the software. Click on “Filter Settings” the window shows the filter settings for Normal mode. Click on
the curve to move position of poles, zeroes and gains.
Figure 21 Digital Filter Window
The transient response will change. This evaluation shows the user how the digital filter can easily be programmed to optimize the
transient response of the power supply.
Rev. Prelim.A Oct.2009| Page 13 of 30
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PRD 1152
PWM – SWITCHING FREQUENCY
The converter switching frequency is programmable. In the “PWM & SR Settings” change the switching frequency.
The minimum and maximum modulation limits can also be modified.
Figure 22 Timing Window
NOTE: It is recommended to evaluate this feature with the power supply turned off. This prevents the chance of damaging the power
supply by introducing shoot-through.
LIGHT LOAD OPTIMIZATION
The ADP1043A can be programmed to optimize performance when an output current drops below a certain level.
The threshold for light load mode can be programmed in the digital filter window.
Once the current will drop below this level the sync rectifiers (SR1 and SR2) will be disabled. The “Light Load Mode Settings” will be
used. The response time for the ADP1043A to switch from one mode to another is between 10 and 20ms.
The light load mode can be disabled by selecting a Light Load Current Threshold of 0%.
Figure 23 Light Load Current Threshold
PRIMARY SIDE CURRENT SENSE AND SECONDARY SIDE CURRENT SENSE
Current sensing is available for both the primary side current and the secondary side current. Primary side current sensing is performed
using the current transformer, T1. Secondary side current sensing uses a low-side sense resistor.
Rev. Prelim.A Oct.2009| Page 14 of 30
Reference Design
PRD 1152
Open the Monitor window in the software. Click on the Flags and Readings tab. Adjust the load current from 0A to 14A. The input
current and output current values will change in the software, matching the changes being made at the load.
FLAGS AND FAULT CONFIGURATIONS
Open the Monitor window in the software. Click on the Flags and Readings tab. The window will show all of the fault flags. If a flag is
set, then there is a red box next to the flag. If the flag is ok, then there is a green box next to the flag.
Set the load current to 0.3A. The CS2 OCP flag should be green.
Figure 24 Flags
Now change the load to 17 A. The CS2 OCP flag should now have turned red, because the CS2 OCP threshold has been reached. The
board wills ender in hiccup mode and try and restart.
Set the load back to 2A, and the flag turns green again. This shows how the user can easily monitor the health of the power supply by
monitoring the status of the various flags.
Flag and Fault Response Configuration:
The ADP1043A is programmed to respond to the various fault conditions in the Fault Configuration Tab.
Rev. Prelim.A Oct.2009| Page 15 of 30
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PRD 1152
Figure 25 Fault Configurations
You can change the resolve issue to “Remain Disabled”. If the over current is applied again the ADP1043A will shut down and remain
off until PSON is cycled.
This evaluation shows how it is quite easy to configure the response to a fault condition. Change the load back to 2A, then toggle the
PS_ON switch to restart the power supply.
Rev. Prelim.A Oct.2009| Page 16 of 30
Reference Design
PRD 1152
APPENDIX
SCHEMATIC
3 CS+
JP1
1
1
1 AGND
Figure 26 Primary Main Circuit
Vin+
Q1
RJK1053DPB
L2
12uH
SW1
2
1
D2
1N5819
Gate1
C13
1uF
C12
1uF
SW1
VDD
HB
HO
HS
LO
VSS
LI
HI
8
7
6
5
C16
470pF
1
C75
470pF
10K
10K
R19
5V_PRI
Gate3
C19
1uF
C18
0.1uF
SW2
1
2
3
4
VDD
HB
HO
HS
U3
R20 1.2KOhm
1
2
3
4
Ven
C15
0.1uF
VDD1
VOA
VIB
GND1
VDD2
VIA
VOB
GND2
U6
SW3
C23
1uF
C22
0.1uF
1
2
3
4
HIP2101
R22
200Ohm
ADUM3201
CS+
AGND
12V_PRI
C17
0.1uF
5V_PRI
8
7
6
5
12V_SEC
3.6V_SEC
R25 0Ohm
5V_PRI
3.6V_SEC
U5
8
7
6
5
R24 0Ohm
LO
VSS
LI
HI
OUTAUX
PSON
0
C20
0.1uF
Gate6
VDD
HB
HO
HS
Vin-
8
7
6
5
R23 560Ohm
HIP2101
12V_PRI
Gate5
LO
VSS
LI
HI
Vin+
3.6V_SEC
1
2
Gate4
8
7
6
5
TR3
Gate6
1
2
D9
1N4148WS
U4
R15
10K
TR4
8
U2
NC7SZU04
4
HIP2101
12V_PRI
R14
2Ohm
TR5
6
Q9
ERJK0653DPB
10K
R18
Gate4
Q8
ERJK0653DPB
2
1
D6
R13
10K
4
5
5V_PRI
D7
1N4148WS
1
2
Gate2
U1
1
2
3
4
R12
2Ohm
10nF
5
D30 2
MURA110T3
12V_PRI
1
T2
PQ32
1
SW3
C11
3
1
Vin-
R6
10K
Gate5
D4
MURA110T3
R17
MMBT4403
JP2
R16
10K
R10
10K
MMBT4403
D5
1N5819
1
2
Q10
Vin-
Q6
RJK1053DPB
Gate2
1
Q5
Q7
R11
2Ohm
R5
2Ohm
SW2
D3
1N5819
1
2
RJK1053DPB
2
B2100
1.5uF/100V
1.5uF/100V
1.5uF/100V
1.5uF/100V
R9
2Ohm
R4
10K
Gate3
C7 C8 C9 C10
1.5uF/100V
1.5uF/100V
C5 C6
R3
2Ohm
Q3
ERJK0653DPB
C4
1.5uF/100V
10K
C3
1.5uF/100V
R8
Gate1
1.5uF/100V
R7
5.1Ohm
C2
1.5uF/100V
1
C1
R2
5.1Ohm
D1
1N5819
Q2
ERJK0653DPB
R1
10K
Q4
RJK1053DPB
PA1005.100NL
2
T1
8
7
Vin+
VDD2
VOA
VOB
GND2
VDD1
VIA
VIB
GND1
1
2
3
4
ADUM3200
R26 0Ohm
OUTA
OUTB
C21
0.1uF
0
R27 0Ohm
Rev. Prelim.A Oct.2009| Page 17 of 30
Vin+
VinCS+
AGND
12V_PRI
5V_PRI
12V_SEC
3.6V_SEC
Reference Design
PRD 1152
Figure 27 Secondary Main Circuit
JP3
Vout+
TR4
3.3uF/50V
3.3uF/50V
3.3uF/50V
3.3uF/50V
3.3uF/50V
3.3uF/50V
C79
C78
C26
C27
C76
C77
R28
D10 MMSD914
1
2
TR5
1
1
Vout+
10K
JP9
C24
10nF
R29
10K
R30
10K
R31
10K
1
1
Vout+
M1
RJK1053DPB
JP8
1
R32
10K
R34
10K
1
Vout+
M2
RJK1053DPB
3.3uF/50V
3.3uF/50V
3.3uF/50V
3.3uF/50V
3.3uF/50V
3.3uF/50V
10K
Vout+
VoutPGND
R39
10K
C35
10K
C34
R38
C33
10nF
PSON
12V_SEC
M3
RJK1053DPB
TR3
R37
C32
C25
10K
C31
2
MMSD914
R36
C30
D13 1
D12
1N5819
C29
R35
2Ohm
C28
D11
1N5819
3.3uF/50V
1
1
2
3V3_SEC
M4
RJK1053DPB
R40
10K
R41
10K
R43
2Ohm
2
R42
2Ohm
1
1
D14
1N5819
R100
NC
D15
1N5819
R44
2mOhm
2
2
3.3uF/50V
R33
2Ohm
PGND
JP4
Vout-
1
1
Vout-
3V3_SEC
R45
2.2K
D16
RED
JP10
1
PSON
R46
NC
8
7
6
5
12V_SEC
OTW
EN
OUTA
INA
VDD PGND
OUTB
INB
1
Vout-
U7
1
2
3
4
R47
0Ohm
SR1
SR2
ADP3634
C36
1uF
Rev. Prelim.A Oct.2009| Page 18 of 30
JP11
1
1
Vout-
Vout+
VoutPGND
PSON
12V_SEC
3V3_SEC
Reference Design
PRD 1152
D17
BAV70WT1
R48
680Ohm
R49
27k
R53
12Ohm
R52
12Ohm
R50
10Ohm
R54
10K
C38
100pF
Vout+
Vout+
C74
100pF
CS+
R51
4.7K
Vout-
TR4
PGND
Figure 28 ADP1043A Control Circuit
R55
10K
C37
NC
R56
27k
Vsen+
R57
1k
AGND
C40
NC
R59
1k
0
GATE
1
VS2
VS1
3
8
PGND
CS2+
16
CS2+
CS2CS2-
VS3+
VCORE
32
VDD
31
OUTC
AGND
14
OUTD
TPAD
15
OUTAUX
DGND
ADP1043A
PGOOD1
C42
0.1uF
C43
0.1uF
25
R104
R67
2.2K
3V3_SEC
R69
NC
5.1K
0
R103
NC
R70
10K
33
0
0
D22
RED
0
0
R63
2.2K
24
R64
100Ohm Share
3V3_SEC
D18
BAV70WT1
R65
2.2K
R66
100Ohm
C46
33pF
R71
R72
2.2K
JP5
Vout-
1
3
5
7
C47
33pF
0
R74
C48
33pF
0
2
4
6
8
D19
BAW56WT1
D20
1N4148WS
R75
0
12V_SEC
2Ohm
0
2
JP6
SHORTPIN
0
Figure 29 ON/OFF Circuit
Ven
R79
100k
5V_PRI
R77
220k
R81
10k
R78
1k
R80
5.1k
Vin+
Q12
MMBT2907AW1
Vin+
Vin-
R83
8.2k
D24
TLV431
Ven
Ven
CS+
R86
200Ohm
JP7
1
D25
BAV70WT1
R84
5.1k
C52
1uF
C53
10nF
5V_PRI
3V3_SEC
EN_LDO
1
ON/OFF
AGND
C55
10nF
ON/OFF&UVP CIRCUIT
Rev. Prelim.A Oct.2009| Page 19 of 30
PGOOD
Vsen+
VsenShare
Connector
0
100Ohm
C49
33pF
0
RT1
100KOhm
0
12V_SEC
3V3_SEC
23
0
D21
GREEN
TR4
12V_SEC
SCL
0
3V3_SEC
TR4
2
49.9K 0.1%
R73
NC
Q13
NC
PGND1
R68
2.2K
PGOOD
PSON
3V3_SEC
C44
0.1uF
SDA
C45
10nF
CS+
PSON
27
SDA
PSON
PGND
CS+
3V3_SEC
18
17
30
SCL
RES
ADD
RTD
29
3V3_SEC
28
22
PGOOD2
21
FLAGIN
20
PSON
19
SHAREi
AGND
PGND
26
OUTAUX
SHAREo
CS+
AGND
0
OUTB
13
Vout-
CS+
Vout-
Vsen-
OUTA
12
OUTB
Vout+
Vout-
CS1
11
Vout+
R62
10Ohm
3V3_SEC
OUTA
R61
1k
C41
10nF
VS37
R58
27k
R60
0Ohm
5
4
10
SR2
SR1
ACSNS
U8
SR2
9
6
SR1
C39
10nF
Vin+
VinVen
CS+
5V_PRI
3V3_SEC
EN_LDO
AGND
Reference Design
PRD 1152
Figure 30 Aux. Power Circuit
T3
2
3
5
R92
1M
12V_SEC
R21
1K
3.6V_SEC
3
D26
EGL34B
1
2
10uF/16V
R90
20k
6
10uF/16V
R89
20k
C57
0.1uF
D27
MMBD1504A
C56
470pF/250V
C59
1
C58
Vin+
ER14.5/6
D32
MMBZ5227BL/3.6V
10uF/16V
R93
20k
10uF/16V
1
2
3
4
R94
680Ohm
R95
680Ohm
Vin+
Vin-
R96
10K
12V_PRI
3
R97
5.1K
5V_PRI
C69
0.1uF
1
R98
55k
5V_PRI
C65
0.1uF
2
C66
NCP1031A
C68
VD GND
VCC CT
UV VFB
OV COM
0
C63
560pF
C67
8
7
6
5
2
1
2
1
U12
1nF
1N4148SW
C64
1uF
EGL34B
12V_PRI
2
D33
1
4
D28
C70
PGND
1000pF/2000V
12V_SEC
3V3_SEC
EN_LDO
C71
220pF
D29
MMBZ5231BLT/5.1V
R99
36k
AGND
PGND
3.6V_SEC
3V3_SEC
12V_SEC
U11
1uF
0.1uF
1uF
C61
C62
C60
1
2
3
EN_LDO 4
R91
10K
GND
IN
OUT
EN
GND4
GND3
GND2
GND1
8
7
6
5
ADP1720ARMZ-3.3-R7
0
Rev. Prelim.A Oct.2009| Page 20 of 30
Vin+
Vin12V_PRI
5V_PRI
12V_SEC
3V3_SEC
EN_LDO
AGND
PGND
3.6V_SEC
Reference Design
PRD 1152
BILL OF MATERIALS
Item Reference C1,C2,C3,C4,C5,C6 1 C7,C8,C9,C10 2 C11,C24,C25 3 C12 4 C13,C19,C23,C36 C15,C17,C18,C20,C21,C22 5 C42,C43,C44,C62,C65,C69 6 C16,C75 C26,C27,C28,C29,C30,C31,C32
7 C33,C34,C35,C76,C77,C78,C79 8 C37,C40 9 C38,C74 10 C39,C41 11 C45 12 C46,C47,C48,C49 13 C52,C60,C61,C64 14 C53,C55 15 C56 16 C57 17 C58,C59,C67,C68 18 C63 19 C66 Description Part Number Manufacture Qty CAP 1.5uF/100V X7R 1210 C3225X7R2A155K TDK 10 CAP 10nF/100V X7R 0805 CAP 1uF/16V X7R 0603 CAP 1uF/25V X7R 0805 C2012X7R2E103K C2012X7R1E105K TDK TDK TDK 3 1 4 CAP 0.1uF/50V X7R 0603 C1608X7R1H104K TDK 12 CAP 470pF/50V C0G 0603 C1608C0G1H471J TDK 2 CAP 3.3uF/50V X7R 1210 C3225X7R1H335K TDK 14 CAP 100pF/50V C0G 0603 CAP 100pF/50V C0G 0603 CAP 1nF/50V X7R 0603 CAP 33pF/16V X7R 0603 CAP 33pF/16V X7R 0603 CAP 1uF/16V X7R 0603 CAP 10nF/50V X7R 0603 CAP 470pF/250V X7R 0603 CAP 0.1uF/100V X7R 0805 CAP 10uF/16V X7R 1206 CAP 560pF/50V C0G 0603 CAP 1nF/50V X7R 0603 CAP 1000pF/2000V X7R 1808 CAP 220pF/100V C0G 0603 C1608X7R1H101K C1608X7R1H102K C1608COG1H330J C1608COG1H330J C1608X7R1C105K C1608X7R1H103J C1608C0G2E471J C2012X7R2A104K C3216X7R1C106K C1608X7R1H102K TDK TDK TDK TDK TDK TDK TDK TDK TDK TDK TDK TDK 2 2 2 1 4 4 2 1 1 4 1 1 C4520X7R3D102K TDK 1 C1608COG2A221J TDK 1 Diode 1A 40V 1N5819HW Fairchild 8 Diode 1A 100V Diode 1A 100V Diode 150mA 75V Diode 0.2A 100V MURA110T3 B2100 1N4148WS MMSD914 SML‐LXT0805IW‐
TR BAV70WT1 BAW56WT1 1N4148WS SML‐LXT0805IW‐
TR On Semi Diodes Diodes Diodes 1 1 2 2 Lumex 2 ON Semi ON Semi Diodes 3 1 1 Lumex 1 ON Semi 1 Diodes 2 20 C70 21 23 24 25 26 C71 D1,D2,D3,D5,D11 D12,D14,D15 D4 D6 D7,D9 D10,D13 27 D16,D22 RED LED 28 29 30 D17,D18,D25 D19 D20 Diode 200mA 70V Diode 200mA 70V Diode 150mA 75V 31 D21 GREEN LED 32 D24 33 D26,D28 22 Adjustable from Vref=1.25V; ZR431F01 1%; Diode 0.5A 100V EGL34B Rev. Prelim.A Oct.2009| Page 21 of 30
Reference Design
34 35 36 37 38 39 41 42 43 46 47 48 49 50 51 52 53 54 55 56 D27 D29 D30 D32 D33 JP1,JP2,JP6,JP7 JP3,JP8,JP9 JP4,JP10,JP11 JP5 L2 Q1,M1,M2,M3,Q4,M4,Q5,Q6 Q2,Q3,Q8,Q9 Q7,Q10 Q12 Q13 RT1 R1,R4,R6,R8,R10,R13,R15,R16 R32,R34,R40,R41,R81,R91,R96 R2,R7 R3,R5,R9,R11,R12,R14,R33 R35,R42,R43 R17,R18,R19,R28,R29,R30 R31,R36,R37,R38,R39 57 R20 58 R21 59 R22,R86 60 R23 61 62 R24,R25,R26,R27,R47,R60 R44 63 R45,R63,R65,R67,R68,R72 64 R46 65 R48 66 R49,R56,R58 67 R50,R62 68 R51 69 70 R52,R53 R54,R55,R70 PRD 1152
Diode 200mA 200V Zener 5.1V Diode 1A 100V Zener 3.6V Diode 0.5A 100V Vin+, Vin‐, ShortPin, ON/OFF Vout+ Vout‐ 8pin Header Inductor 12uH MOSFET MOSFET PNP ‐600mA ‐40V PNP ‐800mA ‐40V NPN 600mA 40V THERMISTOR 1% RES 10KOHM 5% 1/10W 0603 RES 5.1OHM 5% 1/10W 0603 MMBD1504A MMBZ5231BLT MURA110T3 MMBZ5227BL EGL34B BSC079N10NS BSC079N10NS MMBT4403 MMBT2907AWT1 MMBT4401 ON Semi ON Semi ON Semi ON Semi Diodes Any Any Any Any TDK Infineon Infineon ON Semi ON Semi ON Semi Vishay 1 1 1 1 1 1 3 3 1 1 8 4 2 1 1 1 Generic 15 Generic 2 RES 2OHM 5% 1/10W 0603 Generic 10 RES 10KOHM 5% 1/4W 1206 Generic 11 Generic 1 Generic 1 Generic 2 Generic 1 Generic Vishay 6 1 Generic 6 Generic 1 Generic 1 Generic 3 Generic 2 Generic 1 Generic Generic 2 3 RES 1.2KOHM 5% 1/10W 0603 RES 1KOHM 5% 1/8W 0805 RES 200OHM 5% 1/10W 0603 RES 560OHM 5% 1/10W 0603 RES 0OHM 5% 1/10W 0603 RES 2m OHM 1% 1W 1206 RES 2.2KOHM 5% 1/10W 0603 RES 2OHM 5% 1/10W 0603 RES 680OHM 5% 1/10W 0603 RES 27KOHM 5% 1/10W 0603 RES 10OHM 5% 1/10W 0603 RES 4.7KOHM 5% 1/10W 0603 RES 6OHM 5% 1/8W 0805 RES 10KOHM 1% 1/16W Rev. Prelim.A Oct.2009| Page 22 of 30
Reference Design
PRD 1152
0603 71 R57,R59,R61,R78 72 R64,R66,R74 73 R69 74 R71 75 76 R73 R75 77 R77 78 R79 79 R80,R84,R97,R104 80 R83 81 R89,R90 82 R92 83 84 R93 R94,R95 85 R98 86 R99 87 88 89 90 91 92 93 94 95 96 97 R100 R103 T1 T2 T3 U1,U4,U6 U2 U3 U5 U7 U8 RES 1KOHM 5% 1/10W 0603 RES 100OHM 5% 1/10W 0603 RES 5.1KOHM 5% 1/10W 0603 RES 49.9KOHM 0.1% 1/16W 0603 RES 1KOHM 5% 1/10W 0603 RES 2OHM 1% 1/10W 0603 RES 220KOHM 1% 1/10W 0603 RES 100KOHM 5% 1/10W 0603 RES 5.1KOHM 5% 1/10W 0603 RES 8.2KOHM 1% 1/10W 0603 RES 20KOHM 5% 1/8W 0805 RES 1MOHM 5% 1/10W 0603 RES 20KOHM 5% 1/8W 0805 RES 680OHM 5% 1/8W 0805 RES 55KOHM 5% 1/10W 0603 RES 36KOHM 5% 1/10W 0603 RES 2m OHM 1% 1W 1206 RES 0OHM 5% 1/10W 0603 20A 1:100 Main Transformer Aux Transformer Driver IC NOR Gate iCoupler iCoupler Dual channel driver IC Secondary PWM Controller 98 U11 LDO 99 U12 NCP1031 Rev. Prelim.A Oct.2009| Page 23 of 30
Generic 4 Generic 3 Generic 1 Generic 1 Generic Generic 1 1 Generic 1 Generic 1 Generic 4 Generic 1 Generic 2 Generic 1 Generic Generic 1 2 Generic 1 Generic 1 PA1005.100NL PQ32/PC95 ER14.5/6 HIP2101 NC7SZU04 ADuM3201 ADuM3200 ADP3634 ADP1043A ADP1720ARMZ‐
3.3‐R7 NCP1031A Generic Generic PULSE TDK TDK Intersil ON Semi ADI ADI ADI ADI 1 1 1 1 1 3 1 1 1 1 1 ADI 1 ON Semi 1 Reference Design
PRD 1152
PCB LAYOUT
Figure 31 Top View of Board
Figure 32 Bottom View of Board
Rev. Prelim.A Oct.2009| Page 24 of 30
Reference Design
PRD 1152
BOARD SETTING
Input Voltage = 48 V
N1 = 3
N2 = 3
R (CS2) = 2.2 mOhm
I (load) = 14 A
R1 = 27 KOhm
R2 = 1 KOhm
C3 = 0.001 uF
C4 = 0.001 uF
N1 (CS1) = 1
N2 (CS1) = 100
R (CS1) = 6 Ohm
ESR (L1) = 3 mOhm
L1 = 12 uH
C1 = 26.4 uF
ESR (C1) = 1 mOhm
ESR (L2) = 0 mOhm
L2 = 0 uH
C2 = 1000 uF
ESR (C2) = 20 mOhm
R (Normal-Mode) (Load) = 1.96 Ohm
R (Light-Load-Mode) (Load) = 28 Ohm
Cap Across R1 & R2 = 1 "(1 = Yes: 0 = No)"
Topology = 0 (0 = Full Bridge: 1 = Half Bridge: 2 = Two Switch Forward: 3 = Interleaved Two Switch Forward: 4 = Active Clamp Forward: 5 =
Resonant Mode: 6 = Custom)
Switches / Diodes = 0 (0 = Switches: 1 = Diodes)
High Side / Low Side Sense (CS2) = 0 (1 = High-Side: 0 = Low-Side Sense)
Second LC Stage = 1 (1 = Yes: 0 = No)
CS1 Input Type = 0 (1 = AC: 0 = DC)
R3 = 0 KOhm
R4 = 0 KOhm
PWM Main = 6 (0 = OUTA: 1 = OUTB: 2 = OUTC: 3 = OUTD: 4 = SR1: 5 = SR2: 6 = OUTAUX)
Rev. Prelim.A Oct.2009| Page 25 of 30
Reference Design
PRD 1152
REGISTER SETTING
Reg(0h) = F8h - Fault Register 1
Reg(1h) = 20h - Fault Register 2
Reg(2h) = 5h - Fault Register 3
Reg(3h) = 44h - Fault Register 4
Reg(4h) = F8h - Latched Fault Register 1
Reg(5h) = 20h - Latched Fault Register 2
Reg(6h) = 5h - Latched Fault Register 3
Reg(7h) = 45h - Latched Fault Register 4
Reg(8h) = 3Bh - Fault Configuration Register 1
Reg(9h) = BBh - Fault Configuration Register 2
Reg(Ah) = B4h - Fault Configuration Register 3
Reg(Bh) = FCh - Fault Configuration Register 4
Reg(Ch) = CCh - Fault Configuration Register 5
Reg(Dh) = CCh - Fault Configuration Register 6
Reg(Eh) = 1h - Flag Configuration
Reg(Fh) = E6h - Soft-Start Flag Blank
Reg(10h) = 0h - First Flag ID
Reg(11h) = FFh - Reserved
Reg(12h) = 0h - VS1 Value
Reg(13h) = 0h - CS1 Value
Reg(14h) = 0h - CS1 x VS1 Value
Reg(15h) = 0h - VS1 Voltage Value
Reg(16h) = 0h - VS2 Voltage Value
Reg(17h) = A8h - VS3 Voltage Value
Reg(18h) = 60h - CS2 Value
Reg(19h) = 0h - CS2 x VS3 Value
Reg(1Ah) = ADE0h - RTD Temperature Value
Reg(1Bh) = FFh - Reserved
Reg(1Ch) = FFh - Reserved
Reg(1Dh) = 0h - Share Bus Value
Reg(1Eh) = 3h - Modulation Value
Reg(1Fh) = 0h - Line Impedance Value
Reg(20h) = FFh - Reserved
Reg(21h) = 14h - CS1 Gain Trim
Reg(22h) = 31h - CS1 OCP Limit
Reg(23h) = 0h - CS2 Gain Trim
Reg(24h) = 1h - CS2 Offset Trim
Rev. Prelim.A Oct.2009| Page 26 of 30
Reference Design
PRD 1152
Reg(25h) = 6Dh - CS2 Digital Trim
Reg(26h) = 8Bh - CS2 OCP Limit
Reg(27h) = 3h - CS1 and CS2 OCP Setting
Reg(28h) = 3h - VS Balance Gain Setting
Reg(29h) = 1Fh - Share Bus Bandwidth
Reg(2Ah) = 40h - Share Bus Setting
Reg(2Bh) = 16h - Temperature Trim
Reg(2Ch) = 43h - PSON/Soft Start Setting
Reg(2Dh) = 3Ch - Pin Polarity Setting
Reg(2Eh) = 41h - Modulation Limit
Reg(2Fh) = Dh - OTP Threshold
Reg(30h) = 5h - OrFET
Reg(31h) = A4h - VS3 Voltage Setting
Reg(32h) = 18h - VS1 Overvoltage Limit
Reg(33h) = 18h - VS3 Overvoltage Limit
Reg(34h) = 0h - VS1 Undervoltage Limit
Reg(35h) = 3h - Line Impedance Limit
Reg(36h) = 7h - Load Line Impedance
Reg(37h) = FFh - Reserved
Reg(38h) = 8Bh - VS1 Trim
Reg(39h) = Dh - VS2 Trim
Reg(3Ah) = 95h - VS3 Trim
Reg(3Bh) = 0h - Light Load Disable Setting
Reg(3Ch) = 5h - Silicon Revision ID
Reg(3Dh) = 41h - Manufacturer ID
Reg(3Eh) = 43h - Device ID
Reg(3Fh) = 2Bh - OUTAUX Switching Frequency Setting
Reg(40h) = 1Bh - PWM Switching Frequency Setting
Reg(41h) = 1h - PWM 1 Positive Edge Timing
Reg(42h) = 0h - PWM 1 Positive Edge Setting
Reg(43h) = 29h - PWM 1 Negative Edge Timing
Reg(44h) = 4h - PWM 1 Negative Edge Setting
Reg(45h) = 2Bh - PWM 2 Positive Edge Timing
Reg(46h) = 0h - PWM 2 Positive Edge Setting
Reg(47h) = 53h - PWM 2 Negative Edge Timing
Reg(48h) = 4h - PWM 2 Negative Edge Setting
Reg(49h) = 2Bh - PWM 3 Positive Edge Timing
Reg(4Ah) = 0h - PWM 3 Positive Edge Setting
Reg(4Bh) = 53h - PWM 3 Negative Edge Timing
Rev. Prelim.A Oct.2009| Page 27 of 30
Reference Design
PRD 1152
Reg(4Ch) = 4h - PWM 3 Negative Edge Setting
Reg(4Dh) = 1h - PWM 4 Positive Edge Timing
Reg(4Eh) = 0h - PWM 4 Positive Edge Setting
Reg(4Fh) = 29h - PWM 4 Negative Edge Timing
Reg(50h) = 4h - PWM 4 Negative Edge Setting
Reg(51h) = 1h - SR 1 Positive Edge Timing
Reg(52h) = 64h - SR 1 Positive Edge Setting
Reg(53h) = 29h - SR 1 Negative Edge Timing
Reg(54h) = 40h - SR 1 Negative Edge Setting
Reg(55h) = 2Bh - SR 2 Positive Edge Timing
Reg(56h) = 64h - SR 2 Positive Edge Setting
Reg(57h) = 53h - SR 2 Negative Edge Timing
Reg(58h) = 40h - SR 2 Negative Edge Setting
Reg(59h) = 0h - PWM AUX Positive Edge Timing
Reg(5Ah) = 20h - PWM AUX Positive Edge Setting
Reg(5Bh) = 15h - PWM AUX Negative Edge Timing
Reg(5Ch) = 2Ah - PWM AUX Negative Edge Setting
Reg(5Dh) = 0h - PWM and SR Pin Disable Setting
Reg(5Eh) = 0h - Password Lock
Reg(5Fh) = 3h - Soft-Start Digital Filter LF Gain Setting
Reg(60h) = 4h - Normal Mode Digital Filter LF Gain Setting
Reg(61h) = F6h - Normal Mode Digital Filter Zero Setting
Reg(62h) = CAh - Normal Mode Digital Filter Pole Setting
Reg(63h) = Fh - Normal Mode Digital Filter HF Gain Setting
Reg(64h) = 1h - Light Load Digital Filter LF Gain Setting
Reg(65h) = F8h - Light Load Digital Filter Zero Setting
Reg(66h) = D7h - Light Load Digital Filter Pole Setting
Reg(67h) = 4h - Light Load Digital Filter HF Gain Setting
Reg(68h) = 0h - Dead Time Threshold
Reg(69h) = 88h - Dead Time 1
Reg(6Ah) = 88h - Dead Time 2
Reg(6Bh) = 88h - Dead Time 3
Reg(6Ch) = 88h - Dead Time 4
Reg(6Dh) = 88h - Dead Time 5
Reg(6Eh) = 88h - Dead Time 6
Reg(6Fh) = 88h - Dead Time 7
Reg(70h) = 19h Reg(71h) = 1Bh Reg(72h) = 46h Rev. Prelim.A Oct.2009| Page 28 of 30
Reference Design
PRD 1152
Reg(73h) = 12h Reg(74h) = 0h Reg(75h) = FFh Reg(76h) = FFh Reg(77h) = 0h Reg(78h) = 0h Reg(79h) = 1Bh Reg(7Ah) = 2h Reg(7Bh) = FFh - Factory Default Settings
Reg(7Ch) = 1h - EEPROM X Address
Reg(7Dh) = 35h - EEPROM Y Address
Reg(7Eh) = 35h - EEPROM Register
Reg(7Fh) = FFh Reg(80h) = 35h Reg(81h) = 35h Reg(82h) = 35h -
Rev. Prelim.A Oct.2009| Page 29 of 30
Reference Design
PRD 1152
NOTES
Rev. Prelim.A Oct.2009| Page 30 of 30
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