FSLNISTCAVP

Freescale Semiconductor
White Paper
Document Number: FSLNISTCAVP
Rev. 1.7, 03/2015
NIST Cryptographic Algorithm
Validation Program (CAVP)
Certifications for Freescale
Cryptographic Accelerators
This document provides a consolidated list of the
Cryptographic Algorithm Validation Program (CAVP)
certificates obtained by the Freescale hardware crypto
acceleration blocks used in PowerQUICC and QorIQ
embedded communications processors as well as StarCore
digital signal processors.
These hardware accelerators, documented as execution units
(EUs) in older products and as crypto-hardware accelerators
(CHAs) in more recent devices, define the cryptographic
boundary for the purposes of CAVP certification.
OEMs pursuing Cryptographic Module Validation Program
(CMVP) certification on modules using Freescale devices to
perform cryptographic functions may reference the
Freescale CAVP certificates in Section 1, “Certificates of
validation for Freescale devices.” However, it is important to
note that the National Institute of Standards and Technology
(NIST) requires a rationale for algorithm testing that is not
performed on the actual cryptographic module.
For details on these requirements, see the Implementation
Guidance for FIPS PUB 140-2 and the Cryptographic
Module Validation Program.
© 2010-2012, 2014-2015 Freescale Semiconductor, Inc. All rights reserved.
Contents
1. Certificates of validation for Freescale devices. . . . . . .2
1.1. Triple DES (3DES) . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
1.2. Advanced Encryption Standard (AES) . . . . . . . . . . . . .4
1.3. Secure Hash Standard (SHS) . . . . . . . . . . . . . . . . . . . .10
1.4. Keyed-Hash Message Authentication Code (HMAC).15
1.5. Random Number Generator (RNG). . . . . . . . . . . . . . .18
1.6. Deterministic Random Bit Generators (DRBG) . . . . .19
1.7. RSA algorithms (RSA) . . . . . . . . . . . . . . . . . . . . . . . .21
1.8. Digital Signature Algorithms (DSA) . . . . . . . . . . . . . .28
1.9. Elliptic Curve Digital Signature Algorithm (ECDSA) 32
1.10. Key agreement and key derivation functions . . . . . . .37
2. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Certificates of validation for Freescale devices
Freescale recommends that module developers work with their CMVP testing lab to document an
acceptable rationale.
1
Certificates of validation for Freescale devices
Use the table below to locate specific certificates in this section.
Table 1. Certificates of validation for Freescale devices
Standard
Triple DES (3DES)
Validation
number(s)
Access the validated implementations (Freescale devices)
csrc.nist.gov/groups/STM/cavp/documents/des/tripledesval.html
• 757-8
• 1075
Advanced Encryption Standard
(AES)
csrc.nist.gov/groups/STM/cavp/documents/aes/aesval.html
•
•
•
•
962
1645
1648-9
2490-2
Secure Hash Standard (SHS)
csrc.nist.gov/groups/STM/cavp/documents/shs/shaval.htm
•
•
•
•
933-4
1446
1455
2108-12
Keyed-Hash Message
Authentication Code (HMAC)
csrc.nist.gov/groups/STM/cavp/documents/mac/hmacval.html
• 537-8
• 967
• 1532-34
Random Number Generator
(RNG)
csrc.nist.gov/groups/STM/cavp/documents/rng/rngval.html
• 544
• 818
csrc.nist.gov/groups/STM/cavp/documents/drbg/drbgval.html
• 94
• 348-9
csrc.nist.gov/groups/STM/cavp/documents/dss/rsaval.htm
• 465-6
• 813
• 1428-34
Deterministic Random Bit
Generators (DRBG)
RSA algorithms (RSA)
Digital Signature Algorithms (DSA) csrc.nist.gov/groups/STM/cavp/documents/dss/dsaval.htm
Elliptic Curve Digital Signature
Algorithm (ECDSA)
csrc.nist.gov/groups/STM/cavp/documents/dss/ecdsaval.html
• 516
• 769-75
• 209
• 418-24
Key agreement and key derivation csrc.nist.gov/groups/STM/cavp/documents/components/compone 271-284
functions
ntnewval.html
1.1
Triple DES (3DES)
Table 2. 3DES Certificate 757
Validation No.
757
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DEU 2.0.0
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
2
Freescale Semiconductor
Certificates of validation for Freescale devices
Validation No.
757
Operational
Environment
Freescale Semiconductor MPC8548E
Val.Date
12/18/2008
Description/
Notes
TECB(e/d; KO 1,2);
TCBC(e/d; KO 1,2)
Freescale's DEU r2.0.0 is included in multiple PowerQUICC integrated communications processors and
StarCore DSPs, including:
MPC8548E, MPC8547E, MPC8545E, MPC8543E, MPC8568E, MPC8567E, MPC8533E, MPC8544E,
MSC8144E, MPC8323E, MPC8321E, MPC8313E, MPC8349EA, MPC8347EA, MPC8343EA,
MPC8360E, and MPC8358E.
Table 3. 3DES Certificate 758
Validation No.
758
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DEU 3.0.0
Operational
Environment
Freescale Semiconductor MPC8572E
Val.Date
12/18/2008
Description/
Notes
TECB(e/d; KO 1,2)
TCBC(e/d; KO 1,2)
TOFB(e/d; KO 1,2)
Freescale's DEU r3.0.0 is included in multiple PowerQUICC and QorIQ integrated communications
processors and StarCore DSPs, including:
MPC8379E, MPC8378E, MPC8377E, MPC8572E, MPC8571E, MPC8536E, MPC8315E, MPC8314E,
MPC8569E, P2020, P2010, P1020, P1011, P1021, P1012, P1022, P1013, P1024, P1015, P1025, P1016,
MSC8156E, and MSC8154E.
Table 4. 3DES Certificate 1075
Validation No.
1075
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DESA 0.0
Operational
Environment
Freescale Semiconductor P4080 Rev. 2 silicon
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
Freescale Semiconductor
3
Certificates of validation for Freescale devices
Validation No.
1075
Val.Date
05/24/2011
Description/
Notes
TECB(e/d; KO 1,2)
TCBC(e/d; KO 1,2)
TOFB(e/d; KO 1,2)
TCFB(e/d; KO 1,2; 64b)
Freescale's DESA 0.0 is included in multiple QorIQ integrated communications processors, including:
P4080 (all silicon revisions), P4040 (all silicon revisions), P5020, P5040 (all silicon revisions), P3041,
P2041, P2040, P1010, P1023, T4240 (all silicon revisions), T2080, T1040, and QorIQ Qonverge products
B4860, BSC9131, and BSC9132.
1.2
Advanced Encryption Standard (AES)
Table 5. AES Certificate 962
Validation No.
962
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
AESU 2.1.5
Operational
Environment
Freescale Semiconductor MPC8548E
Val.Date
12/18/2008
Description/
Notes
ECB (e/d; 128,256)
CBC(e/d; 128,256);
CTR (ext only; 128,256)
CCM (KS: 128, 256)
– Assoc. Data Len Range: 0 - 32
– Payload Length Range: 1 - 32
– Nonce Length(s): 7, 8, 9, 10, 11, 12, 13
– Tag Length(s): 8, 12, 16
Freescale's AESU r2.1.5 is included in multiple PowerQUICC integrated communications processors and
StarCore DSPs, including:
MPC8548E, MPC8547E, MPC8545E, MPC8543E, MPC8568E, MPC8567E, MPC8533E, MPC8544E,
MSC8144E, MPC8323E, MPC8321E, MPC8313E, MPC8349EA, MPC8347EA, MPC8343EA,
MPC8360E, and MPC8358E.
Table 6. AES Certificate 963
Validation No.
963
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
AESU 3.0.0
Operational
Environment
Freescale Semiconductor MPC8572E
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
4
Freescale Semiconductor
Certificates of validation for Freescale devices
Validation No.
963
Val.Date
12/18/2008
Description/
Notes
ECB (e/d; 128,256)
CBC (e/d; 128,256)
CFB128 (e/d; 128,256)
OFB (e/d; 128,256)
CTR (ext only; 128,256)
CCM (KS: 128, 256)
– Assoc. Data Len Range: 0 - 32
– Payload Length Range: 1 - 32
– Nonce Length(s): 7, 8, 9, 10, 11, 12, 13
– Tag Length(s): 8, 12, 16
CMAC (Generation/Verification)
(KS: 128; Block Size(s)
– Msg Len(s) Min: 0 Max: 2^16
– Tag Len(s) Min: 1 Max: 16)
(KS: 256; Block Size(s)
– Msg Len(s) Min: 0 Max: 2^16
– Tag Len(s) Min: 1 Max: 16)
Freescale's AESU r3.0.0 is included in multiple PowerQUICC and QorIQ integrated communications
processors and StarCore DSPs, including:
MPC8379E, MPC8378E, MPC8377E, MPC8572E, MPC8571E,MPC8315E, and MPC8314E.
The AESU 3.0.0 was later also certified for GCM mode.
Table 7. AES Certificate 1645
Validation No.
1645
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
AESU 3.0.0
Operational
Environment
Freescale Semiconductor MPC8572E
Val.Date
05/24/2011
Description/
Notes
GCM (KS: 128,192, 256)
- Assoc. Data Len Range (B): 0 - 1024
- Plaintext Length Range (B): 0 - 1024
- IV Length(B): 1-1024
- Tag Length(s) bits: 32, 64, 96, 104, 112, 120, 128
Freescale's AESU 3.0.0 is included in multiple PowerQUICC communications processors, including:
MPC8379E, MPC8378E, MPC8377E, MPC8572E, MPC8571E, MPC8315E, and MPC8314E.
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
Freescale Semiconductor
5
Certificates of validation for Freescale devices
Table 8. AES Certificate 1648
Validation No.
1648
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
AESU 3.0.1
Operational
Environment
Freescale Semiconductor MPC8569E
Val.Date
05/24/2011
Description/
Notes
ECB( e/d; 128,192, 256)
CBC (e/d; 128,192, 256)
CFB128 (e/d; 128,192, 256)
OFB (e/d; 128,192, 256)
CTR (ext only; 128,192, 256)
CCM (KS: 128,192, 256)
- Assoc. Data Len Range: 0 - 32
- Payload Length Range: 0 - 32
- Nonce Length(s): 7, 8, 9, 10, 11, 12, 13
- Tag Length(s): 4, 6, 8, 10, 12, 14, 16
CMAC (Generation/Verification)
(KS: 128, 192, 256; Block Size(s)
- Msg Len(s) Min: 0 Max: 2^16
- Tag Len(s) Min: 1 Max: 16)
GCM (KS: 128,192, 256)
- Assoc. Data Len Range (B): 0 - 1024
- Plaintext Length Range (B): 0 - 1024
- IV Length(B): 1-1024
- Tag Length(s) bits: 32, 64, 96, 104, 112, 120, 128
XTS (KS: 128, 256; Data Unit Sequence Number)
Data unit lengths divisible by 128, 256. Not divisible by 64, 192.
Data Len(s) Min: 0 Max: 2^16
Freescale's AESU 3.0.1 is included in multiple PowerQUICC and QorIQ communications processors, and
StarCore DSPs, including: MPC8536E, MPC8569E, P2020, P2010, P1020, P1011, P1021, P1012, P1022,
P1013, P1024, P1015, P1025, P1016, and MSC8156.
Table 9. AES Certificate 1649
Validation No.
1649
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
AESA 4.0
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
6
Freescale Semiconductor
Certificates of validation for Freescale devices
Validation No.
1649
Operational
Environment
Freescale Semiconductor P4080 Rev. 2 silicon
Val.Date
05/24/2011
Description/
Notes
ECB( e/d; 128,192, 256)
CBC (e/d; 128,192, 256)
CFB128 (e/d; 128,192, 256)
OFB (e/d; 128,192, 256)
CTR (ext only; 128,192, 256)
CCM (KS: 128,192, 256)
- Assoc. Data Len Range: 0 - 32
- Payload Length Range: 0 - 32
- Nonce Length(s): 7, 8, 9, 10, 11, 12, 13
- Tag Length(s): 4, 6, 8, 10, 12, 14, 16
CMAC (Generation/Verification)
(KS: 128, 192, 256; Block Size(s)
- Msg Len(s) Min: 0 Max: 2^16
- Tag Len(s) Min: 1 Max: 16)
GCM (KS: 128,192, 256)
- Assoc. Data Len Range (B): 0 - 1024
- Plaintext Length Range (B): 0 - 1024
- IV Length(B): 1-1024
- Tag Length(s) bits: 32, 64, 96, 104, 112, 120, 128
XTS (KS: 128, 256; Data Unit Sequence Number)
Data unit lengths divisible by 128, 256. Not divisible by 64, 192.
Data Len(s) Min: 0 Max: 2^16
Freescale's AESA 4.0 is included in multiple QorIQ integrated communications processors, including:
P4080 Rev. 2 silicon, P4040 Rev. 2 silicon, P3041, P5020, P2041, P2040, P1010, and P1023.
Table 10. AES Certificate 2490
Validation No.
2490
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
AESA 4.1
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
Freescale Semiconductor
7
Certificates of validation for Freescale devices
Validation No.
2490
Val.Date
06/20/2013
Description/
Notes
ECB (e/d; 128,192, 256)
CBC (e/d; 128,192, 256)
CFB128 (e/d; 128,192, 256)
OFB (e/d; 128,192, 256)
CTR (ext only; 128,192, 256)
CCM (KS: 128,192, 256)
- Assoc. Data Len Range: 0 - 32
- Payload Length Range: 0 - 32
- Nonce Length(s): 7, 8, 9, 10, 11, 12, 13
- Tag Length(s): 4, 6, 8, 10, 12, 14, 16
CMAC (Generation/Verification )
(KS: 128, 192, 256; Block Size(s)
- Msg Len(s) Min: 0 Max: 2^16
- Tag Len(s) Min: 4 Max: 16)
GCM (KS: 128,192, 256)
- Assoc. Data Len Range supported (B): 0 - 1024; tested (0, 64, 128, 192, 1024)
- Plaintext Length Range supported (B): 0 - 1024; tested (0, 64, 128, 192, 1024)
- IV Length supported (B): 1-1024; tested (8, 1024)
- Tag Length(s) bits: 32, 64, 96, 112,128
- OtherIVLen_Supported
- GMAC_Supported
XTS (KS: 128, 256; Data Unit Sequence Number)
Data unit lengths divisible by 128, 256. Not divisible by 64, 192.
Data Len(s) Min: 0 Max: 2^16
Freescale's AESA 4.1 is included in multiple QorIQ integrated communications processors, including:
T4240 Rev. 1 and Rev. 2 silicon, T2080, T1040, and QorIQ Qonverge products B4860, BSC9131, and
BSC9132.
Table 11. AES Certificate 2491
Validation No.
2491
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
AESA 4.2
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
8
Freescale Semiconductor
Certificates of validation for Freescale devices
Validation No.
2491
Val.Date
06/20/2013
Description/
Notes
ECB (e/d; 128,192, 256)
CBC (e/d; 128,192, 256)
CFB128 (e/d; 128,192, 256)
OFB (e/d; 128,192, 256)
CTR (ext only; 128,192, 256)
CCM (KS: 128,192, 256)
- Assoc. Data Len Range: 0 - 32
- Payload Length Range: 0 - 32
- Nonce Length(s): 7, 8, 9, 10, 11, 12, 13
- Tag Length(s): 4, 6, 8, 10, 12, 14, 16
CMAC (Generation/Verification )
(KS: 128, 192, 256; Block Size(s)
- Msg Len(s) Min: 0 Max: 2^16
- Tag Len(s) Min: 4 Max: 16)
GCM (KS: 128,192, 256)
- Assoc. Data Len Range supported (B): 0 - 1024; tested ( 0, 64, 128, 192, 1024)
- Plaintext Length Range supported (B): 0 - 1024; tested ( 0, 64, 128, 192, 1024)
- IV Length supported (B): 1-1024; tested (8, 1024)
- Tag Length(s) bits: 32, 64, 96, 112,128
- OtherIVLen_Supported
- GMAC_Supported
XTS (KS: 128, 256; Data Unit Sequence Number)
Data unit lengths divisible by 128, 256. Not divisible by 64, 192.
Data Len(s) Min: 0 Max: 2^16
Freescale's AESA 4.2 is included in multiple QorIQ integrated communications processors, including:
P4080 Rev. 3 silicon, and P5040.
Table 12. AES Certificate 2492
Validation No.
2492
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
AESA 4.3
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
Freescale Semiconductor
9
Certificates of validation for Freescale devices
Validation No.
2492
Val.Date
06/20/2013
Description/
Notes
ECB (e/d; 128,192, 256)
CBC (e/d; 128,192, 256)
CFB128 (e/d; 128,192, 256)
OFB (e/d; 128,192, 256)
CTR (ext only; 128,192, 256)
CCM (KS: 128,192, 256)
- Assoc. Data Len Range: 0 - 32
- Payload Length Range: 0 - 32
- Nonce Length(s): 7, 8, 9, 10, 11, 12, 13
- Tag Length(s): 4, 6, 8, 10, 12, 14, 16
CMAC (Generation/Verification )
(KS: 128, 192, 256; Block Size(s)
- Msg Len(s) Min: 0 Max: 2^16
- Tag Len(s) Min: 4 Max: 16)
GCM (KS: 128,192, 256)
- Assoc. Data Len Range supported (B): 0 - 1024; tested ( 0, 64, 128, 192, 1024)
- Plaintext Length Range supported (B): 0 - 1024; tested ( 0, 64, 128, 192, 1024)
- IV Length supported (B): 1-1024; tested (8, 1024)
- Tag Length(s) bits: 32, 64, 96, 112,128
- OtherIVLen_Supported
- GMAC_Supported
XTS (KS: 128, 256; Data Unit Sequence Number)
Data unit lengths divisible by 128, 256. Not divisible by 64, 192.
Data Len(s) Min: 0 Max: 2^16
Freescale's AESA 4.3 is included in the C29x family of security co-processors.
1.3
Secure Hash Standard (SHS)
Table 13. SHS Certificate 933
Validation No.
933
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
Message Digest Execution Unit (MDEU) r2.1.2
Operational
Environment
Freescale Semiconductor MPC8548E
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
10
Freescale Semiconductor
Certificates of validation for Freescale devices
Validation No.
933
Val.Date
12/18/2008
Description/
Notes
SHA-1
(BYTE-only)
SHA-224 (BYTE-only)
SHA-256 (BYTE-only)
Freescale's MDEU r2.1.2 is included in multiple PowerQUICC integrated communications processors and
StarCore DSPs, including:
MPC8548E, MPC8547E, MPC8545E, MPC8543E, MPC8568E, MPC8567E, MPC8533E, MPC8544E,
MSC8144E, MPC8323E, MPC8321E, MPC8313E, MPC8349EA, MPC8347EA, MPC8343EA,
MPC8360E, MPC8358E
Table 14. SHS Certificate 934
Validation No.
934
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
Message Digest Execution Unit (MDEU) r3.0.0
Operational
Environment
Freescale Semiconductor MPC8572E
Val.Date
12/18/2008
Description/
Notes
SHA-1
SHA-224
SHA-256
SHA-384
SHA-512
(BYTE-only)
(BYTE-only)
(BYTE-only)
(BYTE-only)
(BYTE-only)
Freescale's MDEU r3.0.0 is included in multiple PowerQUICC, and QorIQ integrated communications,
processors as well as StarCore DSPs, including:
MPC8379E, MPC8378E, MPC8377E, MPC8572E, MPC8571E, MPC8536E, MPC8315E, MPC8314E,
MPC8569E, P2020, P2010, P1020, P1011, P1021, P1012, P1022, P1013, P1024, P1015, P1025, P1016,
MSC8156E, MSC8154E
Table 15. SHS Certificate 1446
Validation No.
1446
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
MDHA 2.0
Operational
Environment
Freescale Semiconductor P4080 Rev. 2 silicon
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
Freescale Semiconductor
11
Certificates of validation for Freescale devices
Validation No.
1446
Val.Date
05/24/2011
Description/
Notes
SHA-1 (BYTE-only)
SHA-224 (BYTE-only)
SHA-256 (BYTE-only)
SHA-384 (BYTE-only)
SHA-512 (BYTE-only)
Accepts byte length of 0 for all above.
HMAC-SHA1 (Key Sizes Ranges Tested: KS<BS KS=BS KS>BS ), MAC sizes 10, 12, 16, 20
HMAC-SHA224 ( Key Size Ranges Tested: KS<BS KS=BS KS>BS ), MAC sizes 14, 16, 20, 24, 28
HMAC-SHA256 ( Key Size Ranges Tested: KS<BS KS=BS KS>BS ), MAC sizes 16, 24, 32
HMAC-SHA384 ( Key Size Ranges Tested: KS<BS KS=BS KS>BS ), MAC sizes 24, 32, 40, 48
HMAC-SHA512 ( Key Size Ranges Tested: KS<BS KS=BS KS>BS ), MAC sizes 32, 40, 48, 56, 64
Freescale's MDHA 2.0 is included in multiple QorIQ integrated communications processors, including:
P4080 Rev. 2 silicon, P4040 Rev. 2 silicon, P3041, P5020, P2041, P2040, P1010, and P1023.
Table 16. SHS Certificate 1455
Validation No.
1455
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
RNG4 4.0
Operational
Environment
Freescale Semiconductor i.MX61
Val.Date
06/07/2011
Description/
Notes
SHA-256 with Prediction Resistance Support. See DRBG #94
Entropy input: 256
Nonce: 128
Personalization string: 0-256
Additional input: 0-256
This SHA implementation is part of Freescale's RNG4 4.0, which is included in the following products:
i.MX6, QorIQ Qonverge processors, BSC9131 and BSC9132.
Table 17. SHS Certificate 2108
Validation No.
2108
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
MDHA 2.1
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
12
Freescale Semiconductor
Certificates of validation for Freescale devices
Validation No.
2108
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
06/20/2013
Description/
Notes
SHA-1 (BYTE-only)
SHA-224 (BYTE-only)
SHA-256 (BYTE-only)
SHA-384 (BYTE-only)
SHA-512 (BYTE-only)
Accepts byte length of 0 for all above.
Freescale's MDHA 2.1 is included in the QorIQ Qonverge processors, BSC9131 and BSC9132.
Table 18. SHS Certificate 2109
Validation No.
2109
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
MDHA 2.2
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
06/20/2013
Description/
Notes
SHA-1 (BYTE-only)
SHA-224 (BYTE-only)
SHA-256 (BYTE-only)
SHA-384 (BYTE-only)
SHA-512 (BYTE-only)
Accepts byte length of 0 for all above.
Freescale's MDHA 2.2 is included in multiple QorIQ integrated communications processors, including:
P4080 Rev. 3 silicon, P5040, T4240 Rev. 1 silicon, and QorIQ Qonverge products B4860 Rev. 1 silicon.
Table 19. SHS Certificate 2110
Validation No.
2110
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
MDHA 2.3
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
Freescale Semiconductor
13
Certificates of validation for Freescale devices
Validation No.
2110
Val.Date
06/20/2013
Description/
Notes
SHA-1 (BYTE-only)
SHA-224 (BYTE-only)
SHA-256 (BYTE-only)
SHA-384 (BYTE-only)
SHA-512 (BYTE-only)
Accepts byte length of 0 for all above.
Freescale's MDHA 2.3 is included in multiple QorIQ integrated communications processors, including:
T4240 Rev. 2 silicon, T2080, T1040, and the C29x family of security co-processors.
Table 20. SHS Certificate 2111
Validation No.
2111
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
RNG4 4.1
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
06/20/2013
Description/
Notes
SHA-256 with Prediction Resistance Support. See DRBG #94
Entropy input: 256
Nonce: 128
Personalization string: 0-256
Additional input: 0-256
This SHA implementation is part of Freescale's RNG4 4.1, which is included in multiple QorIQ integrated
communications processors, including: T4240 Rev. 1 silicon, P5040, and QorIQ Qonverge product B4860
Rev. 1 silicon.
Table 21. SHS Certificate 2112
Validation No.
2112
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
RNG4 4.2
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
14
Freescale Semiconductor
Certificates of validation for Freescale devices
Validation No.
2112
Val.Date
06/20/2013
Description/
Notes
SHA-256 with Prediction Resistance Support. See DRBG #94
Entropy input: 256
Nonce: 128
Personalization string: 0-256
Additional input: 0-256
This SHA implementation is part of Freescale's RNG4 4.2, which is included in multiple QorIQ integrated
communications processors, including: T4240 Rev. 2 silicon, T2080, T1040, and the C29x family of security
co-processors
1.4
Keyed-Hash Message Authentication Code (HMAC)
Table 22. HMAC Certificate 537
Validation No.
537
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
Message Digest Execution Unit (DEU) r2.1.2
Operational
Environment
Freescale Semiconductor MPC8548E
Val.Date
12/18/2008
Description/
Notes
HMAC-SHA1 (Key Sizes Ranges Tested: KS<BS KS=BS KS>BS ) SHS Val#933
HMAC-SHA224 ( Key Size Ranges Tested: KS<BS KS=BS KS>BS ) SHS Val#933
HMAC-SHA256 ( Key Size Ranges Tested: KS<BS KS=BS KS>BS ) SHS Val#933
Freescale's MDEU r2.1.2 is included in multiple PowerQUICC integrated communications processors and
StarCore DSPs, including:
MPC8548E, MPC8547E, MPC8545E, MPC8543E, MPC8568E, MPC8567E, MPC8533E, MPC8544E,
MSC8144E, MPC8323E, MPC8321E, MPC8313E, MPC8349EA, MPC8347EA, MPC8343EA,
MPC8360E, MPC8358E
Table 23. HMAC Certificate 538
Validation No.
538
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
Message Digest Execution Unit (DEU) r3.0.0
Operational
Environment
Freescale Semiconductor MPC8572E
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
Freescale Semiconductor
15
Certificates of validation for Freescale devices
Validation No.
538
Val.Date
12/18/2008
Description/
Notes
HMAC-SHA1 (Key Sizes Ranges Tested: KS<BS KS=BS KS>BS ) SHS Val#934
HMAC-SHA224 ( Key Size Ranges Tested: KS<BS KS=BS KS>BS ) SHS Val#934
HMAC-SHA256 ( Key Size Ranges Tested: KS<BS KS=BS KS>BS ) SHS Val#934
HMAC-SHA384 ( Key Size Ranges Tested: KS<BS KS=BS KS>BS ) SHS Val#934
HMAC-SHA512 ( Key Size Ranges Tested: KS<BS KS=BS KS>BS ) SHS Val#934
Freescale's MDEU r3.0.0 is included in multiple PowerQUICC and QorIQ integrated communications
processors and StarCore DSPs, including:
MPC8379E, MPC8378E, MPC8377E, MPC8572E, MPC8571E, MPC8536E, MPC8315E, MPC8314E,
MPC8569E, P2020, P2010, P1020, P1011, P1021, P1012, P1022, P1013, P1024, P1015, P1025, P1016,
MSC8156E, MSC8154E
Table 24. HMAC Certificate 967
Validation No.
967
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
MDHA 2.0
Operational
Environment
Freescale Semiconductor P4080 Rev. 2 silicon
Val.Date
05/24/2011
Description/
Notes
SHS Certificate Val#1446
SHA-1 (BYTE-only)
SHA-224 (BYTE-only)
SHA-256 (BYTE-only)
SHA-384 (BYTE-only)
SHA-512 (BYTE-only)
Accepts byte length of 0 for all above.
HMAC-SHA1 (Key Sizes Ranges Tested: KS<BS KS=BS KS>BS ), MAC sizes 10,12,16,20
HMAC-SHA224 ( Key Size Ranges Tested: KS<BS KS=BS KS>BS ), MAC sizes 14,16,20,24,28
HMAC-SHA256 ( Key Size Ranges Tested: KS<BS KS=BS KS>BS ), MAC sizes 16,24,32
HMAC-SHA384 ( Key Size Ranges Tested: KS<BS KS=BS KS>BS ), MAC sizes 24,32,40,48
HMAC-SHA512 ( Key Size Ranges Tested: KS<BS KS=BS KSsBS ), MAC sizes 32,40,48,56,64
Freescale's MDHA 2.0 is included in multiple QorlQ integrated communications processors, including:
P4080 Rev. 2 silicon, P4040 Rev. 2 silicon, P3041, P5020, P2041, P2040, P1010, and P1023.
Table 25. HMAC Certificate 1532
Validation No.
1532
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
MDHA 2.1
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
16
Freescale Semiconductor
Certificates of validation for Freescale devices
Validation No.
1532
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
06/20/2013
Description/
Notes
See SHS 2108.
HMAC-SHA1 (Key Sizes Ranges Tested: KS<BS KS=BS KS>BS ), MAC sizes 10, 12, 16, 20
HMAC-SHA224 ( Key Size Ranges Tested: KS<BS KS=BS KS>BS ), MAC sizes 14, 16, 20, 24, 28
HMAC-SHA256 ( Key Size Ranges Tested: KS<BS KS=BS KS>BS ), MAC sizes 16, 24, 32
HMAC-SHA384 ( Key Size Ranges Tested: KS<BS KS=BS KS>BS ), MAC sizes 24, 32, 40, 48
HMAC-SHA512 ( Key Size Ranges Tested: KS<BS KS=BS KS>BS ), MAC sizes 32, 40, 48, 56, 64
Freescale's MDHA 2.1 is included in the BSC9131 and BSC9132 QorIQ Qonverge processors.
Table 26. HMAC Certificate 1533
Validation No.
1533
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
MDHA 2.2
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
06/20/2013
Description/
Notes
See SHS 2109.
HMAC-SHA1 (Key Sizes Ranges Tested: KS<BS KS=BS KS>BS ), MAC sizes 10, 12, 16, 20
HMAC-SHA224 ( Key Size Ranges Tested: KS<BS KS=BS KS>BS ), MAC sizes 14, 16, 20, 24, 28
HMAC-SHA256 ( Key Size Ranges Tested: KS<BS KS=BS KS>BS ), MAC sizes 16, 24, 32
HMAC-SHA384 ( Key Size Ranges Tested: KS<BS KS=BS KS>BS ), MAC sizes 24, 32, 40, 48
HMAC-SHA512 ( Key Size Ranges Tested: KS<BS KS=BS KS>BS ), MAC sizes 32, 40, 48, 56, 64
Freescale's MDHA 2.2 is included in multiple QorIQ integrated communications processors, including:
P4080 Rev. 3 silicon, P5040, T4240 Rev. 1 silicon, as well as the B4860, Rev. 1 silicon, QorIQ Qonverge
processor.
Table 27. HMAC Certificate 1534
Validation No.
1534
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
MDHA 2.3
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
Freescale Semiconductor
17
Certificates of validation for Freescale devices
Validation No.
1534
Val.Date
06/20/2013
Description/
Notes
See SHS 2110.
HMAC-SHA1 (Key Sizes Ranges Tested: KS<BS KS=BS KS>BS ), MAC sizes 10, 12, 16, 20
HMAC-SHA224 ( Key Size Ranges Tested: KS<BS KS=BS KS>BS ), MAC sizes 14, 16, 20, 24, 28
HMAC-SHA256 ( Key Size Ranges Tested: KS<BS KS=BS KS>BS ), MAC sizes 16, 24, 32
HMAC-SHA384 ( Key Size Ranges Tested: KS<BS KS=BS KS>BS ), MAC sizes 24, 32, 40, 48
HMAC-SHA512 ( Key Size Ranges Tested: KS<BS KS=BS KS>BS ), MAC sizes 32, 40, 48, 56, 64
Freescale's MDHA 2.3 is included in multiple QorIQ integrated communications processors, including:
T4240 Rev. 2 silicon, T2080, T1040, and the C29x family of security co-processors.
1.5
Random Number Generator (RNG)
Table 28. RNG Certificate 544
Validation No.
544
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
Random Number Generator (RNG-B, r3.1.0)
Operational
Environment
Synopsys Vera 6.3.30 simulation environment
Val.Date
12/18/2008
Description/
Notes
FIPS 186-2 General Purpose
[ (x-Original); (SHA-1) ]
Freescale's Deterministic Random Number Generator-B, revision 3.1.0 completed certification in a
simulation environment. The hardware implementation is included in multiple PowerQUICC and QorIQ
integrated communications processors and StarCore DSPs, including:
MPC8569E, MPC8536E, P2020, P2010, P2020, P2010, P1020, P1011, P1021, P1012, P1022, P1013,
P1024, P1015, P1025, P1016, MSC8156E, MSC8154E
NOTE: RNG-B revision 3.1.0 testing
Within the cryptographic boundary, the RNG-B revision 3.1.0, which is
used in all of the products listed above, is identical. Outside the core RNG-B
logic, there are differences in the seed-loading procedure between the
MPC8569E, MPC8536E, P2020, P2010, MSC8156E, and the P1020,
P1011, P1021, P1012, P1022, P1013, P1024, P1015, P1025, P1016.
Developers planning to conduct RNG-B r3.1.0 testing using a known seed
are advised to contact Freescale for the proper seed-loading procedure for
the MPC8569E, MPC8536E, P2020, P2010, and MSC8156E.
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
18
Freescale Semiconductor
Certificates of validation for Freescale devices
Table 29. RNG Certificate 818
Validation No.
818
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
Random Number Generator (RNG-B, r2.1.0)
Operational
Environment
Freescale Semiconductor P4080 Rev. 2 silicon
Val.Date
11/16/2010
Description/
Notes
FIPS 186-2 General Purpose
[ (x-Original); (SHA-1) ]
Freescale's RNG-B 2.1.0 is included in multiple QorlQ integrated communications processors and StarCore
DSPs, including: P4080 Rev. 2 and Rev. 3 silicon, P4040 Rev. 2 and Rev. 3 silicon, P3041, P5020, P2041,
P2040, P1010, and P1023.
1.6
Deterministic Random Bit Generators (DRBG)
NOTE
Deterministic random number generators, as specified in Special
Publication 800-90, Recommendation for Random Number Generation
Using Deterministic Random Bit Generators, are listed separately.
Table 30. DRBG Certificate 94
Validation No.
94
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
RNG4 4.0
Operational
Environment
Freescale Semiconductor i.MX61
Val.Date
06/07/2011
Description/
Notes
SHA-256 with Prediction Resistance Support. SHS 1455
Entropy input: 256
Nonce: 128
Personalization string: 0-256
Additional input: 0-256
Freescale's RNG4 4.0 is included in i.MX media processors, and in the BSC9131 and BSC9132 QorIQ
Qonverge processors.
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
Freescale Semiconductor
19
Certificates of validation for Freescale devices
Table 31. DRBG Certificate 348
Validation No.
348
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
RNG4 4.1
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
06/20/2013
Description/
Notes
SHA-256 with Prediction Resistance Support. SHS 2111.
Entropy input: 256
Nonce: 128
Personalization string: 0-256
Additional input: 0-256
Freescale's RNG4 4.1 is included in multiple QorIQ integrated communications processors, including:
T4240 Rev. 1 silicon, and P5040 as well as the B4860, Rev. 1 silicon, QorIQ Qonverge processor.
Table 32. DRBG Certificate 349
Validation No.
349
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
RNG4 4.2
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
06/20/2013
Description/
Notes
SHA-256 with Prediction Resistance Support. SHS 2112.
Entropy input: 256
Nonce: 128
Personalization string: 0-256
Additional input: 0-256
Freescale'’s RNG4 4.2 is included in multiple QorIQ integrated communications processors, including:
T4240 Rev. 2 silicon, T2080, T1040, and the C29x family of security co-processors.
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
20
Freescale Semiconductor
Certificates of validation for Freescale devices
1.7
RSA algorithms (RSA)
Table 33. RSA Certificate 465
Validation No.
465
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
Public Key Execution Unit (PKEU) r2.1.2
Operational
Environment
Freescale Semiconductor MPC8548E
Val.Date
12/18/2008
Description/
Notes
ALG [RSASSA-PKCS1_V1_5]
SIG(gen); SIG(ver);
1024 , 1536 , 2048
SHS: SHA-1 Val#933 , SHA-256 Val#933
Freescale's PKEU r2.1.2 is included in multiple PowerQUICC integrated communications processors and
StarCore DSPs, including:
MPC8548E, MPC8547E, MPC8545E, MPC8543E, MPC8568E, MPC8567E, MPC8533E, MPC8544E,
MSC8144E, MPC8323E, MPC8321E, MPC8313E, MPC8349EA, MPC8347EA, MPC8343EA,
MPC8360E, MPC8358E
Table 34. RSA Certificate 466
Validation No.
466
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
Public Key Execution Unit (PKEU) r3.0.0
Operational
Environment
Freescale Semiconductor MPC8572E
Val.Date
12/18/2008
Description/
Notes
ALG[RSASSA-PKCS1_V1_5]
SIG(gen); SIG(ver);
1024 , 1536 , 2048 , 3072 , 4096
SHS: SHA-1 Val#934 , SHA-256 Val#934 , SHA-384 Val#934 , SHA-512 Val#934
Freescale's PKEU r3.0.0 is included in multiple PowerQUICC and QorIQ integrated communications
processors and StarCore DSPs, including:
MPC8379E, MPC8378E, MPC8377E, MPC8572E, MPC8571E, MPC8536E, MPC8315E, MPC8314E,
MPC8569E, P2020, P2010, P1020, P1011, P1021, P1012, P1022, P1013, P1024, P1015, P1025, P1016,
MSC8156E, MSC8154E
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
Freescale Semiconductor
21
Certificates of validation for Freescale devices
Table 35. RSA Certificate 813
Validation No.
813
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
PKHA-XT 0.1
Operational
Environment
Freescale Semiconductor P4080r2
Val.Date
05/24/2011
Description/
Notes
ALG[RSASSA-PKCS1_V1_5]
SIG(gen); SIG(ver);
1024 , 1536 , 2048 , 3072 , 4096
SHS with MDHA 2.0: SHA-1, SHA-224, SHA-256, SHA-384, SHA-512
Freescale's PKHA-XT 0.1 is included in multiple QorIQ integrated communications processors, including:
P4080 Rev. 2 silicon, P4040 Rev. 2 silicon, P3041, P5020, P2041, P2040, P1010, and P1023.
The following RSA certificates include FIPS 186-3 Key Generation, a feature not available in previous
implementations, which are sign/verify only. The cryptographic boundary, and definition of the certified
implementation, for RSA key gen operations includes multiple “engines” within the SEC block; in
specific, the Descriptor Controller (DECO), PKHA, RNG, and MDHA. A Freescale QorIQ, QorIQ
Qonverge, or C29x product is only listed if it contains the tested combination of these engines.
Table 36. RSA Certificate 1428
Validation No.
1428
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 11200121
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
22
Freescale Semiconductor
Certificates of validation for Freescale devices
Validation No.
1428
Val.Date
12/20/2013
Description/
Notes
FIPS186-3:
186-3KEY(gen): FIPS186-3_Random_e
PGM(ProbRandom: ( 2048 , 3072 ) PPTT:( C.2 , C.3 )
PGM(ProbPrimeCondition): 1024 , 2048 , 3072 PPTT:( C.2 , C.3 )
ALG[RSASSA-PKCS1_V1_5] SIG(gen) (1024 SHA( 1 , 224 , 256 , 384 , 512 )) (2048 SHA( 1 , 224 , 256 ,
384 , 512 )) (3072 SHA( 1 , 224 , 256 , 384 , 512 ))
SIG(Ver) (1024 SHA( 1 , 224 , 256 , 384 , 512 )) (2048 SHA( 1 , 224 , 256 , 384 , 512 )) (3072 SHA( 1 , 224
, 256 , 384 , 512 ))
FIPS186_3 Component Test: ( SignGenModExp_PKCS15_SHA1 SHA224 SHA256 )
SHA Val#1446
Freescale's cryptographic boundary for DSA, ECDSA and RSA includes the following CHAs plus Descriptor
Controller: DECO 1.1, MDHA 2.0, PKHA-XT0.1, RNGB 2.1. Freescale's DMPR 11200121 is included in
multiple QorIQ integrated communications processors, including: P3041, P2041, P2040, P5020, P5010,
and P1010.
Table 37. RSA Certificate 1429
Validation No.
1429
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 12211040
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
12/20/2013
Description/
Notes
FIPS186-3:
186-3KEY(gen): FIPS186-3_Random_e
PGM(ProbRandom: ( 2048 , 3072 ) PPTT:( C.2 , C.3 )
PGM(ProbPrimeCondition): 1024 , 2048 , 3072 PPTT:( C.2 , C.3 )
ALG[RSASSA-PKCS1_V1_5] SIG(gen) (1024 SHA( 1 , 224 , 256 , 384 , 512 )) (2048 SHA( 1 , 224 , 256 ,
384 , 512 )) (3072 SHA( 1 , 224 , 256 , 384 , 512 ))
SIG(Ver) (1024 SHA( 1 , 224 , 256 , 384 , 512 )) (2048 SHA( 1 , 224 , 256 , 384 , 512 )) (3072 SHA( 1 , 224
, 256 , 384 , 512 ))
FIPS186_3 Component Test: ( SignGenModExp_PKCS15_SHA1 SHA224 SHA256 )
SHA Val#2108 DRBG: Val# 94
Freescale's cryptographic boundary for DSA, ECDSA and RSA includes the following CHAs and Descriptor
Controller: DECO 1.2, MDHA 2.1, PKHA-SD32 1.0, RNGB 4.0. Freescale's DMPR 12211040 is included
in the BSC9131 and BSC9132 QorIQ Qonverge processors.
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
Freescale Semiconductor
23
Certificates of validation for Freescale devices
Table 38. RSA Certificate 1430
Validation No.
1430
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 13221121
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
12/20/2013
Description/
Notes
FIPS186-3:
186-3KEY(gen): FIPS186-3_Random_e
PGM(ProbRandom: ( 2048 , 3072 ) PPTT:( C.2 , C.3 )
PGM(ProbPrimeCondition): 1024 , 2048 , 3072 PPTT:( C.2 , C.3 )
ALG[RSASSA-PKCS1_V1_5] SIG(gen) (1024 SHA( 1 , 224 , 256 , 384 , 512 )) (2048 SHA( 1 , 224 , 256 ,
384 , 512 )) (3072 SHA( 1 , 224 , 256 , 384 , 512 ))
SIG(Ver) (1024 SHA( 1 , 224 , 256 , 384 , 512 )) (2048 SHA( 1 , 224 , 256 , 384 , 512 )) (3072 SHA( 1 , 224
, 256 , 384 , 512 ))
FIPS186_3 Component Test: ( SignGenModExp_PKCS15_SHA1 SHA224 SHA256 )
SHA Val#2109
Freescale's cryptographic boundary for DSA, ECDSA and RSA includes the following CHAs and Descriptor
Controller: DECO 1.3, MDHA 2.2, PKHA-SD32 1.1, RNGB 2.1. Freescale's DMPR 13221121 is included
in the P4080, Rev. 3 silicon, QorIQ integrated communications processor.
Table 39. RSA Certificate 1431
Validation No.
1431
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 20222141
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
24
Freescale Semiconductor
Certificates of validation for Freescale devices
Validation No.
1431
Val.Date
12/20/2013
Description/
Notes
FIPS186-3:
186-3KEY(gen): FIPS186-3_Random_e
PGM(ProbRandom: ( 2048 , 3072 ) PPTT:( C.2 , C.3 )
PGM(ProbPrimeCondition): 1024 , 2048 , 3072 PPTT:( C.2 , C.3 )
ALG[RSASSA-PKCS1_V1_5] SIG(gen) (1024 SHA( 1 , 224 , 256 , 384 , 512 )) (2048 SHA( 1 , 224 , 256 ,
384 , 512 )) (3072 SHA( 1 , 224 , 256 , 384 , 512 ))
SIG(Ver) (1024 SHA( 1 , 224 , 256 , 384 , 512 )) (2048 SHA( 1 , 224 , 256 , 384 , 512 )) (3072 SHA( 1 , 224
, 256 , 384 , 512 ))
FIPS186_3 Component Test: ( SignGenModExp_PKCS15_SHA1 SHA224 SHA256 )
SHA Val#2109 DRBG: Val# 348
Freescale's cryptographic boundary for DSA, ECDSA and RSA includes the following CHAs and Descriptor
Controller: DECO 2.0, MDHA 2.2, PKHA-SD64 2.1, RNG4 4.1. Freescale's DMPR 20222141 is included in
multiple QorIQ integrated communications processors and co-processors, including: P5040, P5021, T4240
Rev. 1 silicon, T4160 Rev. 1 silicon, and B4860.
Table 40. RSA Certificate 1432
Validation No.
1432
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 30231242
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
12/20/2013
Description/
Notes
FIPS186-3:
186-3KEY(gen): FIPS186-3_Random_e
PGM(ProbRandom: ( 2048 , 3072 ) PPTT:( C.2 , C.3 )
PGM(ProbPrimeCondition): 1024 , 2048 , 3072 PPTT:( C.2 , C.3 )
ALG[RSASSA-PKCS1_V1_5] SIG(gen) (1024 SHA( 1 , 224 , 256 , 384 , 512 )) (2048 SHA( 1 , 224 , 256 ,
384 , 512 )) (3072 SHA( 1 , 224 , 256 , 384 , 512 ))
SIG(Ver) (1024 SHA( 1 , 224 , 256 , 384 , 512 )) (2048 SHA( 1 , 224 , 256 , 384 , 512 )) (3072 SHA( 1 , 224
, 256 , 384 , 512 ))
FIPS186_3 Component Test: ( SignGenModExp_PKCS15_SHA1 SHA224 SHA256 )
SHA Val#2110 DRBG: Val# 349
Freescale's cryptographic boundary for DSA, ECDSA and RSA includes the following CHAs and Descriptor
Controller: DECO 3.0, MDHA 2.3, PKHA-SD32 1.2, RNG4 4.2. Freescale's DMPR 30231242 is included in
the T1040 QorIQ integrated communications processor.
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
Freescale Semiconductor
25
Certificates of validation for Freescale devices
Table 41. RSA Certificate 1433
Validation No.
1433
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 30232242
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
12/20/2013
Description/
Notes
FIPS186-3:
186-3KEY(gen): FIPS186-3_Random_e
PGM(ProbRandom: ( 2048 , 3072 ) PPTT:( C.2 , C.3 )
PGM(ProbPrimeCondition): 1024 , 2048 , 3072 PPTT:( C.2 , C.3 )
ALG[RSASSA-PKCS1_V1_5] SIG(gen) (1024 SHA( 1 , 224 , 256 , 384 , 512 )) (2048 SHA( 1 , 224 , 256 ,
384 , 512 )) (3072 SHA( 1 , 224 , 256 , 384 , 512 ))
SIG(Ver) (1024 SHA( 1 , 224 , 256 , 384 , 512 )) (2048 SHA( 1 , 224 , 256 , 384 , 512 )) (3072 SHA( 1 , 224
, 256 , 384 , 512 ))
FIPS186_3 Component Test: ( SignGenModExp_PKCS15_SHA1 SHA224 SHA256 )
SHA Val#2110 DRBG: Val# 349
Freescale's cryptographic boundary for DSA, ECDSA and RSA includes the following CHAs and Descriptor
Controller: DECO 3.0, MDHA 2.3, PKHA-SD64 2.2, RNG4 4.2. Freescale's DMPR 30232242 is included in
the T2080 QorIQ integrated communications processor.
Table 42. RSA Certificate 1434
Validation No.
1434
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 30233242
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
26
Freescale Semiconductor
Certificates of validation for Freescale devices
Validation No.
1434
Val.Date
12/20/2013
Description/
Notes
FIPS186-3:
186-3KEY(gen): FIPS186-3_Random_e
PGM(ProbRandom: ( 2048 , 3072 ) PPTT:( C.2 , C.3 )
PGM(ProbPrimeCondition): 1024 , 2048 , 3072 PPTT:( C.2 , C.3 )
ALG[RSASSA-PKCS1_V1_5] SIG(gen) (1024 SHA( 1 , 224 , 256 , 384 , 512 )) (2048 SHA( 1 , 224 , 256 ,
384 , 512 )) (3072 SHA( 1 , 224 , 256 , 384 , 512 ))
SIG(Ver) (1024 SHA( 1 , 224 , 256 , 384 , 512 )) (2048 SHA( 1 , 224 , 256 , 384 , 512 )) (3072 SHA( 1 , 224
, 256 , 384 , 512 ))
FIPS186_3 Component Test: ( SignGenModExp_PKCS15_SHA1 SHA224 SHA256 )
SHA Val#2110 DRBG: Val# 349
Freescale's cryptographic boundary for DSA, ECDSA and RSA includes the following CHAs and Descriptor
Controller: DECO 3.0, MDHA 2.3, PKHA-SD128 3.2, RNG4 4.2. Freescale's DMPR 30233242 is included
in multiple QorIQ integrated communications processors and co-processors, including: C291, C292, C293,
T4240 Rev. 2 silicon, and T4160 Rev. 2 silicon.
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
Freescale Semiconductor
27
Certificates of validation for Freescale devices
1.8
Digital Signature Algorithms (DSA)
The cryptographic boundary, and definition of the certified implementation, for DSA operations includes
multiple “engines” within the SEC block, specifically the Descriptor Controller (DECO), PKHA, RNG,
and MDHA. A Freescale QorIQ, QorIQ Qonverge, or C29x product is only listed if it contains the tested
combination of these engines.
Table 43. DSA Certificate 516
Validation No.
516
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DHSA 0A10
Operational
Environment
Freescale Semiconductor P4080r2
Val.Date
05/24/2011
Description/
Notes
FIPS186-2:
KEYGEN(Y) MOD(1024);
SIG(gen) MOD(1024);
SIG(ver) MOD(1024);
SHS: Val# 1446
RNG: Val# 818
Freescale’s DSHA 0A10 is included in multiple QorIQ integrated communications processor, including:
P4080 Rev. 2 silicon, P4040 Rev. 2 silicon, and P1023.
Table 44. DSA Certificate 769
Validation No.
769
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 11200121
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
28
Freescale Semiconductor
Certificates of validation for Freescale devices
Validation No.
769
Val.Date
06/20/2013
Description/
Notes
FIPS186-4:
Key Pair: [ (2048,224) ; (2048,256) ; (3072,256) ]
SIG(gen)PARMS TESTED: [ (2048,224) SHA( 224 , 256 , 384 , 512 ); (2048,256) SHA( 224 , 256 , 384 ,
512 ); (3072,256) SHA( 224 , 256 , 384 , 512 ); ]
SIG(ver)PARMS TESTED: [ (1024,160) SHA( 1 , 224 , 256 , 384 , 512 ); (2048,224) SHA( 1 , 224 , 256 ,
384 , 512 ); (2048,256) SHA( 1 , 224 , 256 , 384 , 512 ); (3072,256) SHA( 1 , 224 , 256 , 384 , 512 ) ]
SHS: Val# 1446
RNG: Val# 818
Freescale's cryptographic boundary for DSA, ECDSA and RSA includes the following CHAs and Descriptor
Controller: DECO 1.1, MDHA 2.0, PKHA-XT0.1, RNGB 2.1. Freescale's DMPR 11200121 is included in
multiple QorIQ integrated communications processor, including: P3041, P2041, P2040, P5020, P5010, and
P1010.
Table 45. DSA Certificate 770
Validation No.
770
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 12211040
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
06/20/2013
Description/
Notes
FIPS186-4:
Key Pair: [ (2048,224) ; (2048,256) ; (3072,256) ]
SIG(gen)PARMS TESTED: [ (2048,224) SHA( 224 , 256 , 384 , 512 ); (2048,256) SHA( 224 , 256 , 384 ,
512 ); (3072,256) SHA( 224 , 256 , 384 , 512 ); ]
SIG(ver)PARMS TESTED: [ (1024,160) SHA( 1 , 224 , 256 , 384 , 512 ); (2048,224) SHA( 1 , 224 , 256 ,
384 , 512 ); (2048,256) SHA( 1 , 224 , 256 , 384 , 512 ); (3072,256) SHA( 1 , 224 , 256 , 384 , 512 ) ]
SHS: Val# 2108
RNG: Val# 94
Freescale's cryptographic boundary for DSA, ECDSA and RSA includes the following CHAs and Descriptor
Controller: DECO 1.2, MDHA 2.1, PKHA-SD32 1.0, RNGB 4.0. Freescale's DMPR 12211040 is included
in the QorIQ Qonverge processors, BSC9131 and BSC9132.
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
Freescale Semiconductor
29
Certificates of validation for Freescale devices
Table 46. DSA Certificate 771
Validation No.
771
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 13221121
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
06/20/2013
Description/
Notes
FIPS186-4:
Key Pair: [ (2048,224) ; (2048,256) ; (3072,256) ]
SIG(gen)PARMS TESTED: [ (2048,224) SHA( 224 , 256 , 384 , 512 ); (2048,256) SHA( 224 , 256 , 384 ,
512 ); (3072,256) SHA( 224 , 256 , 384 , 512 ); ]
SIG(ver)PARMS TESTED: [ (1024,160) SHA( 1 , 224 , 256 , 384 , 512 ); (2048,224) SHA( 1 , 224 , 256 ,
384 , 512 ); (2048,256) SHA( 1 , 224 , 256 , 384 , 512 ); (3072,256) SHA( 1 , 224 , 256 , 384 , 512 ) ]
SHS: Val# 2109
RNG: Val# 818
Freescale's cryptographic boundary for DSA, ECDSA and RSA includes the following CHAs and Descriptor
Controller: DECO 1.3, MDHA 2.2, PKHA-SD32 1.1, RNGB 2.1. Freescale's DMPR 13221121 is included
in the P4080, Rev. 3 silicon, QorIQ integrated communications processors.
Table 47. DSA Certificate 772
Validation No.
772
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 20222141
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
06/20/2013
Description/
Notes
FIPS186-4:
Key Pair: [ (2048,224) ; (2048,256) ; (3072,256) ]
SIG(gen)PARMS TESTED: [ (2048,224) SHA( 224 , 256 , 384 , 512 ); (2048,256) SHA( 224 , 256 , 384 ,
512 ); (3072,256) SHA( 224 , 256 , 384 , 512 ); ]
SIG(ver)PARMS TESTED: [ (1024,160) SHA( 1 , 224 , 256 , 384 , 512 ); (2048,224) SHA( 1 , 224 , 256 ,
384 , 512 ); (2048,256) SHA( 1 , 224 , 256 , 384 , 512 ); (3072,256) SHA( 1 , 224 , 256 , 384 , 512 ) ]
SHS: Val# 2109
DRBG: Val# 348
Freescale's cryptographic boundary for DSA, ECDSA and RSA includes the following CHAs and Descriptor
Controller: DECO 2.0, MDHA 2.2, PKHA-SD64 2.1, RNG4 4.1. Freescale's DMPR 20222141 is included in
multiple QorIQ integrated communications processors and co-processors, including: P5040, P5021, T4240
Rev. 1 silicon, T4160 Rev. 1 silicon, and B4860.
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
30
Freescale Semiconductor
Certificates of validation for Freescale devices
Table 48. DSA Certificate 773
Validation No.
773
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 30233242
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
06/20/2013
Description/
Notes
FIPS186-4:
Key Pair: [ (2048,224) ; (2048,256) ; (3072,256) ]
SIG(gen)PARMS TESTED: [ (2048,224) SHA( 224 , 256 , 384 , 512 ); (2048,256) SHA( 224 , 256 , 384 ,
512 ); (3072,256) SHA( 224 , 256 , 384 , 512 ); ]
SIG(ver)PARMS TESTED: [ (1024,160) SHA( 1 , 224 , 256 , 384 , 512 ); (2048,224) SHA( 1 , 224 , 256 ,
384 , 512 ); (2048,256) SHA( 1 , 224 , 256 , 384 , 512 ); (3072,256) SHA( 1 , 224 , 256 , 384 , 512 ) ]
SHS: Val# 2110
DRBG: Val# 349
Freescale's cryptographic boundary for DSA, ECDSA and RSA includes the following CHAs and Descriptor
Controller: DECO 3.0, MDHA 2.3, PKHA-SD128 3.2, RNG4 4.2. Freescale's DMPR 30233242 is included
in multiple QorIQ integrated communications processors and co-processors, including: C291, C292, C293,
T4240 Rev. 2 silicon, and T4160 Rev. 2 silicon.
Table 49. DSA Certificate 774
Validation No.
774
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 30231242
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
Freescale Semiconductor
31
Certificates of validation for Freescale devices
Validation No.
774
Val.Date
06/20/2013
Description/
Notes
FIPS186-4:
Key Pair: [ (2048,224) ; (2048,256) ; (3072,256) ]
SIG(gen)PARMS TESTED: [ (2048,224) SHA( 224 , 256 , 384 , 512 ); (2048,256) SHA( 224 , 256 , 384 ,
512 ); (3072,256) SHA( 224 , 256 , 384 , 512 ); ]
SIG(ver)PARMS TESTED: [ (1024,160) SHA( 1 , 224 , 256 , 384 , 512 ); (2048,224) SHA( 1 , 224 , 256 ,
384 , 512 ); (2048,256) SHA( 1 , 224 , 256 , 384 , 512 ); (3072,256) SHA( 1 , 224 , 256 , 384 , 512 ) ]
SHS: Val# 2110
DRBG: Val# 349
Freescale's cryptographic boundary for DSA, ECDSA and RSA includes the following CHAs and Descriptor
Controller: DECO 3.0, MDHA 2.3, PKHA-SD32 1.2, RNG4 4.2. Freescale's DMPR 30231242 is included in
the T2080 QorIQ integrated communications processors.
Table 50. DSA Certificate 775
Validation No.
775
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 30232242
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
06/20/2013
Description/
Notes
FIPS186-4:
Key Pair: [ (2048,224) ; (2048,256) ; (3072,256) ]
SIG(gen)PARMS TESTED: [ (2048,224) SHA( 224 , 256 , 384 , 512 ); (2048,256) SHA( 224 , 256 , 384 ,
512 ); (3072,256) SHA( 224 , 256 , 384 , 512 ); ]
SIG(ver)PARMS TESTED: [ (1024,160) SHA( 1 , 224 , 256 , 384 , 512 ); (2048,224) SHA( 1 , 224 , 256 ,
384 , 512 ); (2048,256) SHA( 1 , 224 , 256 , 384 , 512 ); (3072,256) SHA( 1 , 224 , 256 , 384 , 512 ) ]
SHS: Val# 2110
DRBG: Val# 349
Freescale's cryptographic boundary for DSA, ECDSA and RSA includes the following CHAs and Descriptor
Controller: DECO 3.0, MDHA 2.3, PKHA-SD64 2.2, RNG4 4.2. Freescale's DMPR 30232242 is included in
the T2080 QorIQ integrated communications processors.
1.9
Elliptic Curve Digital Signature Algorithm (ECDSA)
The cryptographic boundary, and definition of the certified implementation, for ECDSA operations
includes multiple “engines” within the SEC block, specifically the Descriptor Controller (DECO), PKHA,
RNG, and MDHA. A Freescale QorIQ, QorIQ Qonverge, or C29x product is only listed if it contains the
tested combination of these engines.
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
32
Freescale Semiconductor
Certificates of validation for Freescale devices
Table 51. ECDSA Certificate 209
Validation No.
209
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DHSA 0A10
Operational
Environment
Freescale Semiconductor P4080 Rev. 2 silicon
Val.Date
05/24/2011
Description/
Notes
ECDSA
Key Pair, SIG(gen); SIG(ver);
P: 192, 224, 256, 384, 521
K: 163, 233, 283, 409, 571
B: 163, 233, 283, 409, 571
SHS: Val# 1446
RNG: Val# 818
Freescale''s DSHA 0A10 is included in multiple QorIQ integrated communications processors, including:
P4080 Rev. 2 silicon, P4040 Rev. 2 silicon, and P1023.
Table 52. ECDSA Certificate 418
Validation No.
418
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 11200121
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
06/20/2013
Description/
Notes
FIPS186-4:
PKG: CURVES( P-192 K-163 B-163 )
SigGen: CURVES( P-192: (SHA-1, 224, 256, 384, 512) P-224:(SHA-1) P-256:(SHA-1) P-384:(SHA-1)
P-521: K-163: (SHA-1, 224, 256, 384, 512) K-233:(SHA-1) K-283:(SHA-1) K-409:(SHA-1) K-571:(SHA-1)
B-163: (SHA-1, 224, 256, 384, 512) B-233:(SHA-1) B-283:(SHA-1) B-409:(SHA-1) B-571:(SHA-1) )
SHS: Val#1446
Freescale's cryptographic boundary for DSA, ECDSA and RSA includes the following CHAs and Descriptor
Controller: DECO 1.1, MDHA 2.0, PKHA-XT0.1, RNGB 2.1. Freescale's DMPR 11200121 is included in
multiple QorIQ integrated communications processors, including: P3041, P2041, P2040, P5020, P5010,
and P1010.
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
Freescale Semiconductor
33
Certificates of validation for Freescale devices
Table 53. ECDSA Certificate 419
Validation No.
419
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 12211040
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
06/20/2013
Description/
Notes
FIPS186-4:
PKG: CURVES( P-192 K-163 B-163 )
SigGen: CURVES( P-192: (SHA-1, 224, 256, 384, 512) P-224:(SHA-1) P-256:(SHA-1) P-384:(SHA-1)
P-521: K-163: (SHA-1, 224, 256, 384, 512) K-233:(SHA-1) K-283:(SHA-1) K-409:(SHA-1) K-571:(SHA-1)
B-163: (SHA-1, 224, 256, 384, 512) B-233:(SHA-1) B-283:(SHA-1) B-409:(SHA-1) B-571:(SHA-1) )
SHS: Val#2108
DRBG: Val# 94
Freescale's cryptographic boundary for DSA, ECDSA and RSA includes the following CHAs and Descriptor
Controller: DECO 1.2, MDHA 2.1, PKHA-SD32 1.0, RNGB 4.0. Freescale's DMPR 12211040 is included
in the BSC9131 and BSC9132 QorIQ Qonverge processors.
Table 54. ECDSA Certificate 420
Validation No.
420
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 13221121
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
06/20/2013
Description/
Notes
FIPS186-4:
PKG: CURVES( P-192 K-163 B-163 )
SigGen: CURVES( P-192: (SHA-1, 224, 256, 384, 512) P-224:(SHA-1) P-256:(SHA-1) P-384:(SHA-1)
P-521: K-163: (SHA-1, 224, 256, 384, 512) K-233:(SHA-1) K-283:(SHA-1) K-409:(SHA-1) K-571:(SHA-1)
B-163: (SHA-1, 224, 256, 384, 512) B-233:(SHA-1) B-283:(SHA-1) B-409:(SHA-1) B-571:(SHA-1) )
SHS: Val#2109
Freescale's cryptographic boundary for DSA, ECDSA and RSA includes the following CHAs and Descriptor
Controller: DECO 1.3, MDHA 2.2, PKHA-SD32 1.1, RNGB 2.1. Freescale's DMPR 13221121 is included
in the P4080, Rev. 3 silicon, QorIQ integrated communications processor.
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
34
Freescale Semiconductor
Certificates of validation for Freescale devices
Table 55. ECDSA Certificate 421
Validation No.
421
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 20222141
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
06/20/2013
Description/
Notes
FIPS186-4:
PKG: CURVES( P-192 K-163 B-163 )
SigGen: CURVES( P-192: (SHA-1, 224, 256, 384, 512) P-224:(SHA-1) P-256:(SHA-1) P-384:(SHA-1)
P-521: K-163: (SHA-1, 224, 256, 384, 512) K-233:(SHA-1) K-283:(SHA-1) K-409:(SHA-1) K-571:(SHA-1)
B-163: (SHA-1, 224, 256, 384, 512) B-233:(SHA-1) B-283:(SHA-1) B-409:(SHA-1) B-571:(SHA-1) )
SHS: Val#2109
DRBG: Val# 348
Freescale's cryptographic boundary for DSA, ECDSA and RSA includes the following CHAs and Descriptor
Controller: DECO 2.0, MDHA 2.2, PKHA-SD64 2.1, RNG4 4.1. Freescale's DMPR 20222141 is included in
multiple QorIQ integrated communications processor and co-processors, including: P5040, P5021, T4240
Rev. 1 silicon, T4160 Rev. 1 silicon, and B4860.
Table 56. ECDSA Certificate 422
Validation No.
422
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 30233242
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
06/20/2013
Description/
Notes
FIPS186-4:
PKG: CURVES( P-192 K-163 B-163 )
SigGen: CURVES( P-192: (SHA-1, 224, 256, 384, 512) P-224:(SHA-1) P-256:(SHA-1) P-384:(SHA-1)
P-521: K-163: (SHA-1, 224, 256, 384, 512) K-233:(SHA-1) K-283:(SHA-1) K-409:(SHA-1) K-571:(SHA-1)
B-163: (SHA-1, 224, 256, 384, 512) B-233:(SHA-1) B-283:(SHA-1) B-409:(SHA-1) B-571:(SHA-1) )
DRBG: Val# 349
Freescale's cryptographic boundary for DSA, ECDSA and RSA includes the following CHAs plus Descriptor
Controller: DECO 3.0, MDHA 2.3, PKHA-SD128 3.2, RNG4 4.2. Freescale's DMPR 30233242 is included
in multiple QorIQ integrated communications processor and co-processors, including: C291, C292, C293,
T4240 Rev. 2 silicon, and T4160 Rev. 2 silicon.
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
Freescale Semiconductor
35
Certificates of validation for Freescale devices
Table 57. ECDSA Certificate 423
Validation No.
423
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 30231242
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
06/20/2013
Description/
Notes
FIPS186-4:
PKG: CURVES( P-192 K-163 B-163 )
SigGen: CURVES( P-192: (SHA-1, 224, 256, 384, 512) P-224:(SHA-1) P-256:(SHA-1) P-384:(SHA-1)
P-521: K-163: (SHA-1, 224, 256, 384, 512) K-233:(SHA-1) K-283:(SHA-1) K-409:(SHA-1) K-571:(SHA-1)
B-163: (SHA-1, 224, 256, 384, 512) B-233:(SHA-1) B-283:(SHA-1) B-409:(SHA-1) B-571:(SHA-1) )
SHS: Val#2110
DRBG: Val# 349
Freescale's cryptographic boundary for DSA, ECDSA and RSA includes the following CHAs and Descriptor
Controller: DECO 3.0, MDHA 2.3, PKHA-SD32 1.2, RNG4 4.2. Freescale's DMPR 30231242 is included in
the T1040 QorIQ integrated communications processor.
Table 58. ECDSA Certificate 424
Validation No.
424
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 30232242
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
06/20/2013
Description/
Notes
FIPS186-4:
PKG: CURVES( P-192 K-163 B-163 )
SigGen: CURVES( P-192: (SHA-1, 224, 256, 384, 512) P-224:(SHA-1) P-256:(SHA-1) P-384:(SHA-1)
P-521: K-163: (SHA-1, 224, 256, 384, 512) K-233:(SHA-1) K-283:(SHA-1) K-409:(SHA-1) K-571:(SHA-1)
B-163: (SHA-1, 224, 256, 384, 512) B-233:(SHA-1) B-283:(SHA-1) B-409:(SHA-1) B-571:(SHA-1) )
SHS: Val#2110
DRBG: Val# 349
SHS: Val#2110
DRBG: Val# 349
Freescale's cryptographic boundary for DSA, ECDSA and RSA includes the following CHAs and Descriptor
Controller: DECO 3.0, MDHA 2.3, PKHA-SD64 2.2, RNG4 4.2. Freescale's DMPR 30232242 is included in
the T2080 QorIQ integrated communications processor.
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
36
Freescale Semiconductor
Certificates of validation for Freescale devices
1.10
Key agreement and key derivation functions
The cryptographic boundary and definition of the certified implementation for pair-wise key establishment
schemes using discrete logarithm cryptography and application-specific key derivation functions includes
multiple “engines” within the SEC block, specifically the Descriptor Controller (DECO), PKHA, RNG,
and MDHA. A Freescale QorIQ, QorIQ Qonverge, or C29x product is only listed if it contains the tested
combination of these engines.
Freescale’s application-specific key derivation functions and pair-wise key establishment schemes using
discrete logarithm cryptography certificates are located at the following address:
csrc.nist.gov/groups/STM/cavp/documents/components/componentnewval.html
1.10.1
Pair-wise key establishment schemes using discrete logarithm
cryptography
Table 59. CVL Certificate 271, ECC
Validation No.
271
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 11200121
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
05/30/2014
Description/
Notes
SP800-56A: Recommendation for Pair-Wise Key Establishment Schemes Using Discrete Logarithm
Cryptography, Section 5.7.1.2: ECC CDH Primitive
Curves tested: P-224 P-256 P-384 P-521 K-233 K-283 K-409 K-571 B-233 B-283 B-409 B-571
Freescale's cryptographic boundary for DSA, ECDSA, RSA, KAS and ASKDF includes the following CHAs
plus Descriptor Controller: DECO 1.1, MDHA 2.0, PKHA-XT0.1, RNGB 2.1. Freescale's DMPR11200121
is included in multiple QorIQ integrated communications processors, including: P3041, P2041, P2040,
P5020, P5010, and P1010.
Table 60. CVL Certificate 273, ECC
Validation No.
273
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 12211040
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
Freescale Semiconductor
37
Certificates of validation for Freescale devices
Validation No.
273
Val.Date
05/30/2014
Description/
Notes
SP800-56A: Recommendation for Pair-Wise Key Establishment Schemes Using Discrete Logarithm
Cryptography, Section 5.7.1.2: ECC CDH Primitive
Curves tested: P-224 P-256 P-384 P-521 K-233 K-283 K-409 K-571 B-233 B-283 B-409 B-571
Freescale's cryptographic boundary for DSA, ECDSA, RSA, KAS and ASKDF includes the following CHAs
plus Descriptor Controller: DECO 1.2, MDHA 2.1, PKHA-SD32 1.0, RNGB 4.0. Freescale's DMPR
12211040 is included in the QorIQ integrated communications processors: BSC9131 and BSC9132.
Table 61. CVL Certificate 275, ECC
Validation No.
275
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 13221121
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
05/30/2014
Description/
Notes
SP800-56A: Recommendation for Pair-Wise Key Establishment Schemes Using Discrete Logarithm
Cryptography, Section 5.7.1.2: ECC CDH Primitive
Curves tested: P-224 P-256 P-384 P-521 K-233 K-283 K-409 K-571 B-233 B-283 B-409 B-571
Freescale's cryptographic boundary for DSA, ECDSA, RSA, KAS and ASKDF includes the following CHAs
plus Descriptor Controller: DECO 1.3, MDHA 2.2, PKHA-SD32 1.1, RNGB 2.1. Freescale's DMPR
13221121 is included in the P4080, Rev. 3 silicon, QorIQ integrated communications processors.
Table 62. CVL Certificate 277, ECC
Validation No.
277
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 30233242
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
38
Freescale Semiconductor
Certificates of validation for Freescale devices
Validation No.
277
Val.Date
05/30/2014
Description/
Notes
SP800-56A: Recommendation for Pair-Wise Key Establishment Schemes Using Discrete Logarithm
Cryptography, Section 5.7.1.2: ECC CDH Primitive
Curves tested: P-224 P-256 P-384 P-521 K-233 K-283 K-409 K-571 B-233 B-283 B-409 B-571
Freescale's cryptographic boundary for DSA, ECDSA and RSA includes the following CHAs plus Descriptor
Controller: DECO 3.0, MDHA 2.3, PKHA-SD128 3.2, RNG4 4.2. Freescale's DMPR 30233242 is included
in multiple QorIQ integrated communications processors and co-processors, including: C291, C292, C293,
T4240 Rev. 2 silicon, and T4160 Rev. 2 silicon.
Table 63. CVL Certificate 279, ECC
Validation No.
279
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR DMPR 30231242
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
05/30/2014
Description/
Notes
SP800-56A: Recommendation for Pair-Wise Key Establishment Schemes Using Discrete Logarithm
Cryptography, Section 5.7.1.2: ECC CDH Primitive
Curves tested: P-224 P-256 P-384 P-521 K-233 K-283 K-409 K-571 B-233 B-283 B-409 B-571
Freescale's cryptographic boundary for DSA, ECDSA, RSA, KAS and ASKDF includes the following CHAs
and Descriptor Controller: DECO 3.0, MDHA 2.3, PKHA-SD32 1.2, RNG4 4.2. Freescale's
DMPR30231242 is included in the T1040 QorIQ integrated communications processors.
Table 64. CVL Certificate 281, ECC
Validation No.
281
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 30232242
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
Freescale Semiconductor
39
Certificates of validation for Freescale devices
Validation No.
281
Val.Date
05/30/2014
Description/
Notes
SP800-56A: Recommendation for Pair-Wise Key Establishment Schemes Using Discrete Logarithm
Cryptography, Section 5.7.1.2: ECC CDH Primitive
Curves tested: P-224 P-256 P-384 P-521 K-233 K-283 K-409 K-571 B-233 B-283 B-409 B-571
Freescale's cryptographic boundary for DSA, ECDSA and RSA includes the following CHAs plus Descriptor
Controller: DECO 3.0, MDHA 2.3, PKHA-SD64 2.2, RNG4 4.2. Freescale's DMPR 30232242 is included in
the QorIQ T2080 integrated communications processors.
Table 65. CVL Certificate 283, ECC
Validation No.
283
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 20222141
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
05/30/2014
Description/
Notes
SP800-56A: Recommendation for Pair-Wise Key Establishment Schemes Using Discrete Logarithm
Cryptography, Section 5.7.1.2: ECC CDH Primitive
Curves tested: P-224 P-256 P-384 P-521 K-233 K-283 K-409 K-571 B-233 B-283 B-409 B-571
Freescale's cryptographic boundary for DSA, ECDSA and RSA includes the following CHAs plus Descriptor
Controller: DECO 2.0, MDHA 2.2, PKHA-SD64 2.1, RNG4 4.1. Freescale's DMPR 20222141 is included in
multiple QorIQ integrated communications processors and co-processors, including: P5040, P5021, T4240
Rev. 1 silicon, T4160 Rev. 1 silicon, and B4860.
1.10.2
Application-specific key derivation functions
Table 66. CVL Certificate 272, KDF-135
Validation No.
272
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 11200121
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
40
Freescale Semiconductor
Certificates of validation for Freescale devices
Validation No.
272
Val.Date
05/30/2014
Description/
Notes
SP800-135: Recommendation for Existing Application-Specific Key Derivation Functions; Section 4.2: TLS
TLS( TLS1.0/1.1 TLS1.2 (SHA 256 , 384 ) ) SHA Val#1446 HMAC Val#967
Freescale's cryptographic boundary for DSA, ECDSA, RSA, KAS and ASKDF includes the following CHAs
plus Descriptor Controller: DECO 1.1, MDHA 2.0, PKHA-XT0.1, RNGB 2.1. Freescale's DMPR11200121
is included in multiple QorIQ integrated communications processors, including: P3041, P2041, P2040,
P5020, P5010, and P1010.
Table 67. CVL Certificate 274, KDF-135
Validation No.
274
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 12211040
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
05/30/2014
Description/
Notes
SP800-135: Recommendation for Existing Application-Specific Key Derivation Functions; Section 4.2: TLS
TLS( TLS1.0/1.1 TLS1.2 (SHA 256 , 384 ) ) SHA Val#2108 HMAC Val#1532
Freescale's cryptographic boundary for DSA, ECDSA, RSA, KAS and ASKDF includes the following CHAs
plus Descriptor Controller: DECO 1.2, MDHA 2.1, PKHA-SD32 1.0, RNGB 4.0. Freescale's
DMPR12211040 is included in the QorIQ Integrated Communications Processors: BSC9131 and
BSC9132.
Table 68. CVL Certificate 276, KDF-135
Validation No.
276
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 13221121
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
05/30/2014
Description/
Notes
SP800-135: Recommendation for Existing Application-Specific Key Derivation Functions; Section 4.2: TLS
TLS( TLS1.0/1.1 TLS1.2 (SHA 256 , 384 ) ) SHA Val#2109 HMAC Val#1533
Freescale's cryptographic boundary for DSA, ECDSA, RSA, KAS and ASKDF includes the following CHAs
plus Descriptor Controller: DECO 1.3, MDHA 2.2, PKHA-SD32 1.1, RNGB 2.1. Freescale's
DMPR13221121 is included in the P4080, Rev. 3 silicon, QorIQ integrated communications processor.
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
Freescale Semiconductor
41
Certificates of validation for Freescale devices
Table 69. CVL Certificate 278, KDF-135
Validation No.
278
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 30233242
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
05/30/2014
Description/
Notes
SP800-135: Recommendation for Existing Application-Specific Key Derivation Functions; Section 4.2: TLS
and Section 4.1.2: IKEv2
TLS( TLS1.0/1.1 TLS1.2 (SHA 256 , 384 ) ) SHA Val#2110 HMAC Val#1534
IKEv2( ( 224 (SHA 1 , 256 , 384 , 512 ) ) ( 384 (SHA 1 , 256 , 384 , 512 ) ) ( 384 (SHA 1 , 256 , 384 , 512 )
) SHA Val#2110 HMAC Val#1534
Freescale's cryptographic boundary for DSA, ECDSA and RSA includes the following CHAs plus Descriptor
Controller: DECO 3.0, MDHA 2.3, PKHA-SD128 3.2, RNG4 4.2. Freescale's DMPR 30233242 is included
in multiple QorIQ integrated communications processors and co-processors, including: C291, C292, C293,
T4240 Rev. 2 silicon, and T4160 Rev. 2 silicon.
Table 70. CVL Certificate 280, KDF-135
Validation No.
280
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR DMPR 30231242
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
05/30/2014
Description/
Notes
SP800-135: Recommendation for Existing Application-Specific Key Derivation Functions; Section 4.2: TLS
and Section 4.1.2: IKEv2
TLS( TLS1.0/1.1 TLS1.2 (SHA 256 , 384 ) ) SHA Val#2110 HMAC Val#1534
IKEv2( ( 224 (SHA 1 , 256 , 384 , 512 ) ) ( 4096 (SHA 1 , 256 , 384 , 512 ) ) ( 384 (SHA 1 , 256 , 384 , 512
) ) SHA Val#2110 HMAC Val#1534
Freescale's cryptographic boundary for DSA, ECDSA, RSA, KAS and ASKDF includes the following CHAs
and Descriptor Controller: DECO 3.0, MDHA 2.3, PKHA-SD32 1.2, RNG4 4.2. Freescale's 30231242 is
included in the T1040 QorIQ integrated communications processor.
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
42
Freescale Semiconductor
Certificates of validation for Freescale devices
Table 71. CVL Certificate 282, KDF-135
Validation No.
282
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 30232242
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
05/30/2014
Description/
Notes
SP800-135: Recommendation for Existing Application-Specific Key Derivation Functions; Section 4.2: TLS
and Section 4.1.2: IKEv2
TLS( TLS1.0/1.1 TLS1.2 (SHA 256 , 384 ) ) SHA Val#2110 HMAC Val#1534
IKEv2( ( 224 (SHA 1 , 256 , 384 , 512 ) ) ( 4096 (SHA 1 , 256 , 384 , 512 ) ) ( 384 (SHA 1 , 256 , 384 , 512
) ) SHA Val#2110 HMAC Val#1534
Freescale's cryptographic boundary for DSA, ECDSA and RSA includes the following CHAs and Descriptor
Controller: DECO 3.0, MDHA 2.3, PKHA-SD64 2.2, RNG4 4.2. Freescale's DMPR 30232242 is included in
the T2080 QorIQ integrated communications processor.
Table 72. CVL Certificate 284, KDF-135
Validation No.
284
Vendor
Freescale Semiconductor ____________ Geoff Waters
7700 W.Parmer Lane _______________ TEL: 512-996-5815
Austin, TX 78729
USA
Implementation
DMPR 20222141
Operational
Environment
Chronologic VCS simulator, vcs D-2010.06-04
Val.Date
05/30/2014
Description/
Notes
SP800-135: Recommendation for Existing Application-Specific Key Derivation Functions; Section 4.2: TLS
TLS( TLS1.0/1.1 TLS1.2 (SHA 256 , 384 ) ) SHA Val#2109 HMAC Val#1533
Freescale's cryptographic boundary for DSA, ECDSA and RSA includes the following CHAs and Descriptor
Controller: DECO 2.0, MDHA 2.2, PKHA-SD64 2.1, RNG4 4.1. Freescale's DMPR 20222141 is included in
multiple QorIQ integrated communications processors and co-processors, including: P5040, P5021, T4240
Rev. 1 silicon, T4160 Rev. 1 silicon, and B4860.
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
Freescale Semiconductor
43
Revision history
2
Revision history
This table provides a revision history for this document.
Table 73. Revision history
Revision
Date
Substantive change(s)
1.7
03/2015
• Added device part numbers (P1024, P1015, P1025, P1016) to some certificates.”
• Included an expanded Contents listing.
1.6
07/2014
•
•
•
•
•
1.5
01/2014
• Reorganized RNG certifications so that they appear before asymmetric crypto
certifications.
• Added new certificates in each section.
1.4
03/2012
• Updated part numbers associated with various certificates.
• Added RNG certificate #818.
1.3
06/2011
Added new certificates in each section.
1.2
09/2010
Reformatted document for clarity.
1.1
08/2010
Updated part numbers.
1.0
04/2010
Initial public release
Added Section 1.10, “Key agreement and key derivation functions.”
Fixed minor typos throughout document. Corrected dates from 2103 to 2013.
Updated PSC9131 and PSC9132 to BSC9131 and BSC9132, respectively.
Removed Section 1 heading “CAVP-to-CMVP mapping.”
Added Table 1, “Certificates of validation for Freescale devices.”
NIST Cryptographic Algorithm Validation Program (CAVP) Certifications for Freescale Cryptographic
Accelerators, Rev. 1.7
44
Freescale Semiconductor
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© 2010-2012, 2014-2015 Freescale Semiconductor, Inc.
Document Number: FSLNISTCAVP
Rev. 1.7
03/2015