Data Sheet

Freescale Semiconductor
Data Sheet: Technical Data
Document Number: BSC9132
Rev. 1, 08/2014
BSC9132
BSC9132 QorIQ Qonverge
Multicore Baseband
Processor
The following list provides an overview of the feature set:
• Two high-performance 32-bit e500 cores built on Power
Architecture® technology:
– 36-bit physical addressing
– Double-precision floating-point support
– 32-Kbyte L1 instruction cache and 32-Kbyte L1 data
cache
– Enhanced hardware and software debug support
– 800 Mhz/1 GHz/1.2 GHz clock frequency
– 512-Kbyte L2 cache with ECC; also configurable as
SRAM and stashing memory
• Two SC3850 core subsystems; each core connects to the
following:
– 32 Kbyte 8-way level 1 data/instruction cache
(L1 Dcache/ICache)
– 512 Kbyte 8-way level 2 unified instruction/data cache
(L2 cache/M2 memory)
– Memory management unit (MMU)
– Enhanced programmable interrupt controller (EPIC)
– Debug and profiling unit (DPU)
– Two 32-bit quad timers
• 32 Kbytes of shared M3 memory
• Multi Accelerator Platform Engine for Pico Base Station
Baseband Processing (MAPLE-B2P)
– Supports variable sizes in Fourier Transforms,
Convolution, Filtering, Turbo, Viterbi, Chiprate, MIMO
– Consists of accelerators for UMTS chip rate processing,
LTE UP/DL channel processing, Matrix Inversion
operations, and CRC algorithms
• Two DDR3/DDR3L SDRAM memory controllers support
32-bit with ECC
• Integrated security engine (ULE CAAM)
– Protocol support includes DES, AES, RNG, CRC, MDE,
PKE, SHA, and MD5
• Secure boot capability
• Two enhanced three-speed Ethernet controllers (eTSECs)
© 2014 Freescale Semiconductor, Inc. All rights reserved.
FC-PBGA–780
23 mm x 23 mm
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– TCP/IP acceleration, quality of service, and
classification capabilities
– IEEE Std 1588™ support
– Supports SGMII interfaces
High-speed interfaces supporting the following
multiplexing options:
– One PCI Express interface with 5G support
– Four lanes of high-speed serial interfaces (SerDes) to be
shared between PCI Express, SGMII, and CPRI
High-speed USB controller (USB 2.0)
– Host and device support
– Enhanced host controller interface (EHCI)
– ULPI interface
Enhanced secure digital (SD/MMC) host controller
(eSDHC)
Integrated Flash controller (IFC), supporting NAND,
NOR, and general ASIC
Two TDM interfaces
Antenna interface controller (AIC), supporting four
industry standard JESD/four custom parallel RF interfaces
(three dual and one single port) and a 2-lane CPRI interface
Universal Subscriber Identity Module (USIM) interface
– Facilitates communication to SIM cards or Eurochip
pre-paid phone cards
Two enhanced serial peripheral interfaces (eSPI)
Programmable interrupt controller (PIC) compliant with
OpenPIC standard
Two DMA controllers
– 4-channel DMA on Power Architecture side
– 32 unidirectional channels, providing up to 16
memory-to-memory channels on DSP side
Two I2C interfaces
Two dual UART (DUART) interfaces
96 general-purpose I/O signals
Eight 32-bit timers
Operating temperature (Ta - Tj) range: 0–105° C
Table of Contents
1
2
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Ball Layout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2 Pinout Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
2.1 Overall DC Electrical Characteristics . . . . . . . . . . . . . .53
2.2 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.3 Power-Down Requirements . . . . . . . . . . . . . . . . . . . . .59
2.4 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.5 Power-on Ramp Rate . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.6 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.7 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.8 DDR3 and DDR3L SDRAM Controller . . . . . . . . . . . . .64
2.9 eSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
2.10 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
2.11 Ethernet: Enhanced Three-Speed Ethernet (eTSEC) .76
2.12 USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
2.13 Integrated Flash Controller (IFC) . . . . . . . . . . . . . . . . .83
2.14 Enhanced Secure Digital Host Controller (eSDHC) . . .87
2.15 Programmable Interrupt Controller (PIC) Specifications89
2.16 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
2.17 I2C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
2.18 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
2.19 TDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
2.20 High-Speed Serial Interface (HSSI) DC Electrical
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
2.21 Radio Frequency (RF) Interface . . . . . . . . . . . . . . . . .120
3
4
5
6
7
2.22 Universal Subscriber Identity Module (USIM) . . . . . . 123
2.23 Timers and Timers_32b AC Timing Specifications . . 127
Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . 128
3.1 Power Architecture System Clocking. . . . . . . . . . . . . 128
3.2 DSP System Clocking . . . . . . . . . . . . . . . . . . . . . . . . 131
3.3 Supply Power Default Setting . . . . . . . . . . . . . . . . . . 132
3.4 PLL Power Supply Design . . . . . . . . . . . . . . . . . . . . . 133
3.5 Decoupling Recommendations . . . . . . . . . . . . . . . . . 134
3.6 SerDes
Block
Power
Supply
Decoupling
Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . 135
3.7 Guidelines for High-Speed Interface Termination . . . 136
3.8 Pull-Up and Pull-Down Resistor Requirements . . . . . 136
3.9 Output Buffer DC Impedance . . . . . . . . . . . . . . . . . . 137
3.10 Configuration Pin Muxing . . . . . . . . . . . . . . . . . . . . . 137
3.11 JTAG Configuration Signals. . . . . . . . . . . . . . . . . . . . 138
3.12 Guidelines for High-Speed Interface Termination . . . 140
3.13 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
3.14 Security Fuse Processor . . . . . . . . . . . . . . . . . . . . . . 141
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
4.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 141
4.2 Mechanical Dimensions of the FC-PBGA . . . . . . . . . 142
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
5.1 Part Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
2
Freescale Semiconductor
Pin Assignments
This figure shows the major functional units.
StarCore
SC3850 DSP Core
StarCore
SC3850 DSP Core
Power Architecture Coherency Power Architecture
e500 Core
e500 Core
Module
32-Kbyte
32-Kbyte
I-Cache
32-Kbyte 32-Kbyte 512-Kbyte 32-Kbyte I-Cache
32-Kbyte
L1 D-Cache L1 I-Cache L2 Cache L1 D-Cache L1 I-Cache
BSC9132
32-Kbyte
32-Kbyte
32-Kbyte
32-Kbyte
L1 D-Cache L1 I-Cache L1 D-Cache L1 I-Cache
512-Kbyte
L2 Cache
512-Kbyte
L2 Cache
32-bit DDR3/3L
Memory
Controller
32-Kbyte
Shared
M3 Memory
32-bit DDR3/3L
Memory
Controller
1GE
1GE
MAPLE-B2P
Baseband
Accelerator
LTE/UMTS/WiMAX
RF Parallel
DMA
IEEE 1588™
CPRI
2x I2C
Security
Engine
4.4
PCI Express
2x DUART
Ethernet
DMA
USB 2.0
2x eSPI
Secure Boot
Multicore
Fabric
GPIO
SGMII SGMII
USIM
IFC
x2
x2
x4
4-lane 6-GHz SerDes
eSDHC
2x TDM
Clocks/Reset
Figure 1. BSC9132 Block Diagram
1
Pin Assignments
This section contains a top-level ball layout diagram followed by four detailed quadrant views and a pinout listing table.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
3
Pin Assignments
1.1
Ball Layout Diagrams
SEE DETAIL B
SEE DETAIL A
1
A
B
C
2
3
5
ANT3_ ANT3_ ANT3_ ANT3_
DIO008 DIO006 DIO003 DIO001
ANT3_
DIO011
VSS
ANT3_ X2VDD ANT3_
DIO007
DIO002
ANT3_
ANT3_
ANT3_ ANT3_ ANT3_
RX_
TXNRX FRAME DIO009 DIO004 DIO005
D
ANT3_
RX_CLK
E
ANT3_
ANT2_ ANT2_
TX_
DIO001 DIO000 FRAME
F
4
VSS
6
SPI2_
MISO
ANT2_
DIO004
ANT2_ ANT2_ ANT2_ ANT2_ ANT2_
DIO006 DIO008 DIO011 DIO009 DIO010
SPI2_
CS1_B
ANT3_ SPI2_
DIO000 CS0_B
X2VDD
ANT3_ ANT3_ ANT3_
SPI2_
TX_CLK DIO010 ENABLE CS3_B
VSS
7
SPI2_
CLK
VSS
VSS
VSS
SPI2_
MOSI
VSS
8
SPI2_
CS2_B
VSS
9
VSS
10
11
12
13
14
D1_
D1_
MDQ29 MDQS08
VSS
VSS
VSS
16
17
18
19
VSS
D1_
D1_
MDQS_ G1VDD MDQS_
B03
B01
D1_
D1_
D1_
D1_
MDQS_ D1_
MDQ24 MDQ27 MDQ25
B02 MDQ14
D1_
D1_
G1VDD D1_
D1_
D1_
MECC02MECC00
MDQ20 MDQ21 MDQ19
D1_
D1_
D1_
D1_
MECC03 MDM08 MECC07 MDM02
VSS
D1_
MDQ17
VSS
D1_
MDQ10
D1_
MCK_
B02
G1VDD
D1_
MCK_
B00
D1_
D1_ MDQS_
B00
MDQ15
G1VDD
VSS
VSS
NC_
BGA_
E19
D1_
MCAS_B
ANT2_
ANT2_ ANT2_
RX_
DIO100 TXNRX FRAME
VSS
VSS
VSS
G1VDD G1VDD G1VDD G1VDD G1VDD G1VDD
G1VDD G1VDD G1VDD G1VDD G1VDD
J
ANT2_ ANT2_ ANT2_ X2VDD ANT2_
ENABLE DIO109 RX_CLK
DIO003
K
VDDC
VSS
VDDC
D1_
VDDC
MVREF
VSS
IFC_
AD07
VSS
IFC_
AD08
E
D1_
MA15
SDHC_ SDHC_
DATA01 DATA02
IFC_
AD06
BVDD
IFC_
AD09
IFC_
AD10
D1_
MA14
SDHC_ BVDD
WP
IFC_
AD11
IFC_
AD12
IFC_
AD13
IFC_
AD14
VSS
IFC_
AD15
G1VDD
VSS
IFC_
CS_
B00
VDD
VSS
VDD
VSS
VDDC
VSS
VDDC
VSS
VDDC
VSS
SENSE
VDDC
ANT1_
DIO009
ANT1_ ANT1_
DIO005 DIO004
X2VDD
VSS
VDD
VSS
VDD
VSS
VDDC
VSS
VDDC
VSS
VDDC
N
ANT1_ X1VDD ANT1_ X1VDD ANT1_
REF_CLK
DIO011
DIO003
ANT1_ ANT1_
DIO006 DIO001
X1VDD
VSS
VDD
VSS
VDD
VSS
VDDC
VSS
VDDC
VSS
P
ANT1_ ANT1_ ANT1_ ANT1_ ANT1_
ENABLE RX_CLK TXNRX DIO100 TX_CLK
X1VDD
VSS
VDDC
VSS
VDDC
VSS
VDDC
VSS
VDDC
VSS
V
W
Y
AA
AB
AC
VSS
AVDD_
D2_DDR
VSS
VSS
D2_
MA02
D2_
MA08
D2_
MBA00
ANT4_
TX_
FRAME
VSS
D2_
MA04
D2_
MA10
D2_
D2_
MBA02 MBA01
G2VDD
AVDD_
CORE0
VSS
CVDD POVDD1
VSS
USB_
D03
VDDC
VSS
AVDD_
CORE1
VSS
CVDD POVDD2 USB_
DIR
VDDC
VSS
VDDC
VSS
VDDC
VSS
VDDC
VSS
VSS
ANT4_
X1VDD
DIO008
ANT4_
ANT4_ FA_VDD X1VDD
RX_
FRAME TXNRX
D2_
MA01
D2_
MCS_
B00
VSS
D2_
MA00
VSS
VSS
VSS
VDDC
VDDC
VDDC
VSS
VDDC
VDDC
VSS
VDDC
VSS
D2_
MVREF
VSS
VSS
VSS
VSS
VDDC
VDDC
VDDC
VDDC
D2_
MCS_ G2VDD G2VDD G2VDD G2VDD G2VDD G2VDD G2VDD
B01
VSS
D2_
G2VDD MDQ01
D2_
D2_
D2_
D2_
D2_
D2_
MDQ10 MDM01 MDQ18 MDQ17 MDQ30 G2VDD MDQ24
G2VDD
VSS
D2_
D2_
D2_
MCK00 MDIC00 MCK02
D2_
MCS_
B03
D2_
MCK_
B00
D2_
MDQ08
D2_
D2_
D2_ G2VDD
MDIC01 MCK01
MODT01
VSS
5
6
7
VSS
VDDC
VDDC
VSS
VDDC
VSS
AVDD_
DSP
VSS
VSS
VDDC
VDDC
VSS
VSS
VSS
D2_
D2_
MDQ15 MDQS01
VSS
D2_
D2_
D2_ G2VDD
G2VDD
MDQS00
MDQ19 MDQS02
VSS
D2_
MDM08
D2_
MDQS_
D2_
D2_
B08
MDQ16 MECC07
XCORE SD_REF
XPAD
VDD _CLK2_B
VDD
VSS
XCORE
VDD
SD_
RX03
SD_
TX03
SD_
TX_
B03
XCORE
VSS
9
SEE DETAIL C
10
11
12
13
14
15
16
17
18
19
USB_
D07
P
USB_
CLK
USB_
STP
R
T
IIC1_
SDA
OVDD
UART_
SIN00
LVDD
HRESET TRST_B
_REQ_B
VSS
TEST_
SEL_B
TEMP_
D1_
ANODE DDRCLK
VSS
CVDD_ DSP_ TEMP_
VSS
VSEL CLKIN CATHODE
EC_
MDIO
UART_
SOUT00
VSS
UART_ UART_
RTS_B01 SIN01
TSEC_ TSEC_
TSEC_
1588_
1588_ LVDD
1588_ BVDD_
CLK_OUT PULSE_OUT1
TRIG_IN1VSEL01
U
V
W
Y
DSP_
TCK
AA
SD_ XCORE
TSEC_ DSP_
UART_ UART_
XCORE BVDD_ 1588_CLK
PLL1_
TRST_BRTS_B00 CTS_B00 VSS
VSS
VSS VSEL00
TPA
_IN
AB
XPAD
VDD
VSS
EC_
MDC
SD1 SD_PLL1 SD1
AGND _TPD
AVDD
XPAD
VSS
XPAD
VDD
SD_
TX02
XPAD
VSS
XPAD SD_TX
_B02
VSS
XPAD
VDD
SD_
RX02
XCORE
VDD
20
21
XCORE
VSS
SD_IMP
_CAL_RX XPAD
VSS
XCORE
VSS
D2_
D2_
D2_
D2_
D2_
D2_
D2_
D2_
SD_
D2_
MDQS_ MDM02 MDQ22 MECC01 MDQS08 MECC06 XCORE SD_RX XCORE
MDQS_ MDQ09
RX_B02 XCORE
MDQ11
B02
VSS
_B03
VDD
VSS
B00
8
VSS
HRESET SCAN_
CVDD
_B
MODE_B
IIC1_
SCL
VSS
XCORE SD_IMP_ XPAD
CAL_TX VSS
VSS
USB_
D04
OVDD
AVDD_
MAPLE
SD_
PLL2_
TPD
USB_
D06
TDI
VSS
XPAD
VSS
N
TDO
VSS
XPAD
VDD
USB_
D00
TMS
VSS
SD2
AGND
USB_
D01
CFG_1_
JTAG_
MODE
VSS
L
USB_
D02
OVDD READY
TCK
K
M
EE0
UART_
CTS_ UART_
B01 SOUT01
J
SPI1_
CS0_B
EE1
VSS
TMP_
DETECT
H
SPI1_
CLK
VSS
OVDD
UDE_B1
G
IFC_
AVD
CFG_0_
JTAG_ OVDD
MODE
VDDC
D2_
XCORE
G2VDD MECC04 VSS
VSS
UDE_
B0
VSS
G2VDD POVDD3 XCORE
VSS
D2_
MDQ29
VSS
IFC_
IFC_
CLK00 CS_B01
F
VSS
SPI1_ SPI1_CS1SPI1_CS2 CVDD
CS3_B
_B
_B
SENSE CVDD USB_D05 USB_
VSS
NXT
VDDC
D2_
D2_
D2_
D2_ XCORE SD_REF XPAD
MDQ20 MDQS03 MECC00 MECC05 VSS
_CLK2
VSS
D2_
D2_
D2_
D2_
D2_
D2_
D2_
MCK_ MDQ14 MDQ13 MDQS_ MDQ23 MDQ21 MDQS_
B01
B03
B02
D2_
D2_
D2_
MCKE01MCK_BO1 MDQ12
VSS
D2_
D2_
D2_
D2_
D2_
D2_
D2_
D2_
D2_
SD_PLL2 SD2
MDM00 MDQ05 MDQ00 MDQ04 MDQ28 MDM03 MDQ27 MECC02 MECC03 XCORE _TPA
AVDD
VSS
D2_
D2_
D2_
D2_
D2_
D2_
MDQ03 MDQ02 G2VDD MDQ07 MDQ25 MDQ31 MDQ26
4
VSS
VSS
D2_
MCS_
B02
3
VDDC
VDDC
AE
2
SPI1_
MISO
VSS
D2_
MA06
1
AVDD_ VSS
D1_DDR
VSS
D2_
D2_
D2_
MA11 MRAS_B MA13
AH
VSS
VDDC
D2_
D2_
D2_
D2_
MA12 MCAS_B MWE_B MDQ06
NC_
D2_
D2_
BGA_
MODT00 MCKE00
AE4
IFC_
WE_B
VSS
D2_
MA14
D2_
MA03
IFC_
CLE
VDDC
D2_
MA09
D2_
MA05
IFC_
CS_B02
VSS
D2_
MA15
AG
VSS
VDDC
VSS
D2_
MA07
SPI1_
MOSI
VSS
AD
AF
VSS
VDDC
ANT4_ ANT4_ ANT4_
ANT4_
DIO010 DIO011 RX_CLK X1VDD TX_CLK X1VDD
ANT4_
ENABLE
IFC_
WP_B
VSS
ANT4_ ANT4_ ANT4_ ANT4_ ANT4_
DIO002 DIO004 DIO005 DIO003 DIO007
ANT4_
DIO009 X1VDD
IFC_
RB_B
VDDC
VSS
IFC_
IFC_
IFC_
IFC_
BVDD
IFC_
IFC_
ADDR26 ADDR25 ADDR24 ADDR23
ADDR22 ADDR21
BVDD
VSS
VDDC
IFC_
IFC_
IFC_
ADDR18 ADDR17 ADDR16
IFC_
OE_B
ANT1_
DIO106
VSS
VSS
IFC_
BCTL
ANT1_
ANT1_
DIO102 X1VDD DIO103 X1VDD
ANT4_ ANT4_ X1VDD
DIO001 DIO006
IFC_
IFC_
ADDR20 ADDR19
BVDD
VSS
ANT1_ ANT1_ ANT1_
X1VDD ANT4_
DIO109 DIO110 DIO111
DIO000
VSS
D1_
MCS_
D1_
B03 MODT01
X2VDD
U
C
SDHC_
DATA03
ANT1_
DIO000
T
IFC_
AD02
BVDD
BVDD
ANT1_ ANT1_
DIO107 DIO108 X1VDD
VSS
D1_
MA09
VSS
ANT1_
DIO105 VSS
SDHC_ SDHC_
CD
CMD
B
D1_
MA00
VDDC
ANT1_
DIO104 VSS
IFC_
AD01
D1_
MCS_
B01
VSS
R
SDHC
_CLK
D
VDDC
ANT1_
DIO002
BVDD
IFC_
AD05
VSS
VSS
D1_
MA10
IFC_
AD04
VDDC
ANT1_
ANT1_
TX_
RX_ ANT1_
ANT1_
DIO101 FRAME AGC FRAME
D1_
MA02
A
IFC_
AD03
VSS
VSS
IFC_
AD00
SDHC_
DATA00
VDD
ANT1_ ANT1_ ANT1_
DIO010 DIO008 DIO007
VSS
VSS
VSS
VSS
D1_
MA04
D1_
MA12
VDD
ANT2_ ANT2_ ANT2_ ANT2_ ANT2_
DIO111 DIO108 DIO110 DIO106 DIO103
X2VDD ANT2_
DIO105
SENSE
VDD
D1_
MA01
VSS
VSS
M
ANT2_ ANT2_ ANT2_
DIO107 DIO104 DIO101
VDD
D1_
MA13
28
D1_
D1_
MCS_
B02 MODT00
X2VDD
L
ANT2_ VSS
REF_CLK
VSS
27
D1_
D1_
MBA00 MBA02
H
VDD
26
D1_
MA11
D1_
D1_
D1_
D1_
MDQ02 MDQ01 MDQ06 MDIC01
VSS
25
D1_
MA07
D1_
D1_
D1_
D1_
D1_
D1_
MECC05MECC01 MDQ22 MDQ16 MDQ23 MDQ18
X2VDD
D1_
D1_
MRAS_B MBA01
24
D1_
MCK_
D1_
G1VDD D1_
B01 MWE_B
MA05
VSS
ANT2_ ANT2_
DIO002 DIO102
23
G1VDD
D1_
D1_
D1_
MDQ04 MDM00 MDQ03
D1_
D1_
D1_
MDQ07 MDQ00 MDQ05
22
D1_
MA08
AVDD_
PLAT
ANT2_
TX_CLK
21
VSS
VSS
VSS
D1_
MA03
D1_
D1_
D1_
D1_
D1_
D1_
MCS_
MDQ13 MDQS00 MDQ08 MCK01 MCKE01 B00
ANT2_
ANT2_ X2VDD ANT2_
ANT2_
TX_
AGC
DIO007 FRAME DIO005
G
20
D1_
D1_
D1_
D1_
D1_
D1_
D1_
D1_
D1_
D1_
D1_
D1_
MDQS_
MDQ28 MDQS03 MDM01 MDQS01 MDQ09 MDQ12 MCK02 MDIC00 MCK00 MCKE00 MA06
B08
D1_
D1_
D1_
D1_
D1_
D1_
D1_
MECC06 MDQ31 MDQ26 MDM03 MDQ30 MDQS02 MDQ11
D1_
MECC04
15
SD_
RX01
SD_RX
_B01
22
SD_
TX01
DSP_
TDO
DSP_
TDI
DSP_
TMS
XCORE XCORE LVDD_
VSS
VSS
VSEL
XPAD
VDD
SD_
TX00
XVDD1_ D2_
VSEL DDRCLK
AC
XVDD2_
VSEL
AD
OVDD
XPAD
VSS
VSS
SYSCLK
AE
XPAD
VDD
SD_TX
_B01
XPAD
VSS
SD_TX
_B00
XCORE
VSS
VSS
AF
XCORE
VSS
SD_
RX00
XCORE SD_REF XCORE
_CLK1 VSS
VDD
RTC
AG
XCORE SD_RX
VDD
_B00
23
24
XCORE SD_REF XCORE
VSS _CLK1_B VDD
25
26
27
AH
28
SEE DETAIL D
Figure 2. Ball Layout Diagram—Top-Level View
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
4
Freescale Semiconductor
Pin Assignments
Figure 3 shows detailed view A.
DETAIL A
1
A
B
C
2
3
4
5
ANT3_ ANT3_ ANT3_ ANT3_
DIO008 DIO006 DIO003 DIO001
ANT3_
DIO011
VSS
ANT3_ X2VDD ANT3_
DIO007
DIO002
ANT3_
ANT3_
ANT3_ ANT3_ ANT3_
RX_
TXNRX FRAME DIO009 DIO004 DIO005
6
SPI2_
MISO
7
SPI2_
CS1_B
ANT3_ SPI2_
DIO000 CS0_B
8
SPI2_
CS2_B
VSS
9
10
11
12
13
14
D1_
D1_
D1_
D1_
D1_
MDQS_
MDQ28 MDQS03 MDM01 MDQS01
B08
D1_
D1_
MDQS_ G1VDD MDQS_
D1_
D1_
VSS
B03
B01
MDQ29 MDQS08
VSS
X2VDD
VSS
D1_
D1_
D1_
D1_
D1_
D1_
D1_
MECC06 MDQ31 MDQ26 MDM03 MDQ30 MDQS02 MDQ11
ANT3_ ANT3_ ANT3_
SPI2_
TX_CLK DIO010 ENABLE CS3_B
VSS
D1_
MECC04
SPI2_
CLK
SPI2_
MOSI
VSS
D1_
D1_
G1VDD D1_
D1_
D1_
MECC02MECC00
MDQ20 MDQ21 MDQ19
VSS
VSS
VSS
D1_
D1_
D1_
D1_
MECC03 MDM08 MECC07 MDM02
ANT2_
ANT2_ X2VDD ANT2_
ANT2_
TX_
DIO007 FRAME DIO005
AGC
VSS
AVDD_
PLAT
VSS
D1_
D1_
D1_
D1_
D1_
D1_
MECC05MECC01 MDQ22 MDQ16 MDQ23 MDQ18
H
ANT2_
ANT2_ ANT2_
RX_
DIO100 TXNRX FRAME
VSS
VSS
VSS
G1VDD G1VDD G1VDD G1VDD G1VDD G1VDD
J
ANT2_ ANT2_ ANT2_ X2VDD ANT2_
DIO003
ENABLE DIO109 RX_CLK
ANT2_ ANT2_
DIO002 DIO102
X2VDD
VSS
VDD
VSS
VDD
SENSE
VDD
VDDC
K
ANT2_ VSS
REF_CLK
X2VDD ANT2_
DIO105
X2VDD
VSS
VDD
VSS
VDD
VSS
VDDC
ANT1_
DIO000
X2VDD
VSS
VDD
VSS
VDD
VSS
VDDC
ANT1_
DIO009
ANT1_ ANT1_
DIO005 DIO004
X2VDD
VSS
VDD
VSS
VDD
VSS
VDDC
N
ANT1_ X1VDD ANT1_ X1VDD ANT1_
REF_CLK
DIO011
DIO003
ANT1_ ANT1_
DIO006 DIO001
X1VDD
VSS
VDD
VSS
VDD
VSS
VDDC
P
ANT1_ ANT1_ ANT1_ ANT1_ ANT1_
ENABLE RX_CLK TXNRX DIO100 TX_CLK
X1VDD
VSS
VDDC
VSS
VDDC
VSS
VDDC
D
E
F
G
ANT3_
RX_CLK
VSS
ANT3_
ANT2_ ANT2_
TX_
DIO001 DIO000 FRAME
VSS
ANT2_
DIO004
ANT2_ ANT2_ ANT2_ ANT2_ ANT2_
DIO006 DIO008 DIO011 DIO009 DIO010
VSS
ANT2_
TX_CLK
ANT2_ ANT2_ ANT2_
DIO107 DIO104 DIO101
L
ANT2_ ANT2_ ANT2_ ANT2_ ANT2_
DIO111 DIO108 DIO110 DIO106 DIO103
M
ANT1_ ANT1_ ANT1_
DIO010 DIO008 DIO007
VSS
VSS
VSS
ANT1_
DIO002
VSS
D1_
D1_
D1_
D1_
MDQS_ D1_
MDQ24 MDQ27 MDQ25
B02 MDQ14
VSS
D1_
MDQ17
Figure 3. Ball Layout Diagram—Detail A
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
5
Pin Assignments
Figure 4 shows detailed view B.
DETAIL B
15
16
17
18
19
20
21
D1_
D1_
D1_
D1_
D1_
D1_
D1_
MDQ09 MDQ12 MCK02 MDIC00 MCK00 MCKE00 MA06
VSS
D1_
MDQ10
D1_
MCK_
B02
G1VDD
D1_
MCK_
B00
D1_
MA03
G1VDD
VSS
VSS
VDDC
VSS
VSS
VDDC
VSS
28
D1_
MA01
D1_
MA04
VSS
IFC_
AD00
D1_
MA02
D1_
MA10
BVDD
SDHC
_CLK
IFC_
AD01
SDHC_ SDHC_
CD
CMD
VSS
IFC_
AD02
A
D1_
MA07
D1_
MA11
D1_
D1_
MBA00 MBA02
D1_
MCK_
D1_
G1VDD D1_
B01 MWE_B
MA05
VSS
D1_
MA12
VSS
SDHC_
DATA00
IFC_
AD03
IFC_
AD04
IFC_
AD05
D1_
D1_
MCS_
B02 MODT00
D1_
MA00
D1_
MA09
BVDD
SDHC_
DATA03
IFC_
AD07
VSS
IFC_
AD08
D1_
MCS_
B01
D1_
MA15
SDHC_ SDHC_
DATA01 DATA02
IFC_
AD06
BVDD
IFC_
AD09
IFC_
AD10
D1_
MA14
SDHC_ BVDD
WP
IFC_
AD11
IFC_
AD12
IFC_
AD13
IFC_
AD14
VSS
IFC_
AD15
VSS
NC_
BGA_
E19
D1_
MCAS_B
D1_
MA13
G1VDD G1VDD G1VDD G1VDD G1VDD
VDDC
27
25
G1VDD
D1_
D1_
D1_
D1_
MDQ02 MDQ01 MDQ06 MDIC01
VSS
D1_
D1_
MRAS_B MBA01
26
24
D1_
MA08
D1_
D1_
D1_
MDQ04 MDM00 MDQ03
D1_
D1_
D1_
MDQ07 MDQ00 MDQ05
23
VSS
D1_
D1_
D1_
D1_
D1_
D1_
MCS_
MDQ13 MDQS00 MDQ08 MCK01 MCKE01 B00
D1_
MDQS_
D1_
B00
MDQ15
22
D1_
VDDC
MVREF
VSS
D1_
MCS_
D1_
B03 MODT01
G1VDD
IFC_
IFC_
ADDR20 ADDR19
VSS
BVDD
VSS
VDDC
VSS
BVDD
IFC_
CS_
B00
VSS
VDDC
VSS
SENSE
VDDC
VDDC
VSS
VDDC
VSS
VDDC
VSS
VSS
VDDC
VSS
VSS
IFC_
IFC_
IFC_
ADDR18 ADDR17 ADDR16
IFC_
IFC_
IFC_
IFC_
BVDD
IFC_
IFC_
ADDR22 ADDR21
ADDR26 ADDR25 ADDR24 ADDR23
IFC_
BCTL
IFC_
OE_B
BVDD
IFC_
RB_B
IFC_
WP_B
VSS
SPI1_
MOSI
VSS
IFC_
CS_B02
IFC_
CLE
IFC_
WE_B
VSS
AVDD_ VSS
D1_DDR
SPI1_
MISO
VDDC
VSS
AVDD_
CORE0
VSS
CVDD POVDD1
VSS
USB_
D03
VDDC
VSS
AVDD_
CORE1
VSS
CVDD POVDD2 USB_
DIR
USB_
D06
IFC_
IFC_
CLK00 CS_B01
B
C
D
E
F
G
H
J
K
L
VSS
IFC_
AVD
SPI1_
CLK
SPI1_
CS0_B
M
USB_
D02
USB_
D01
USB_
D00
N
USB_
D04
VSS
USB_
D07
P
SPI1_ SPI1_CS1SPI1_CS2 CVDD
_B
_B
CS3_B
Figure 4. Ball Layout Diagram—Detail B
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
6
Freescale Semiconductor
Pin Assignments
Figure 5 shows detailed view C.
DETAIL C
ANT1_
ANT1_
TX_
RX_ ANT1_
ANT1_
ANT1_
DIO101 FRAME AGC FRAME DIO102
X1VDD ANT1_
DIO103
X1VDD
VSS
VDDC
VSS
VDDC
VSS
VDDC
T
ANT1_
DIO104
ANT1_
DIO106
ANT1_ ANT1_
DIO107 DIO108
X1VDD
VSS
VDDC
VSS
VDDC
VSS
VDDC
U
ANT1_ ANT1_ ANT1_ X1VDD ANT4_
DIO109 DIO110 DIO111
DIO000
ANT4_ ANT4_
DIO001 DIO006
X1VDD
VSS
VDDC
VSS
VDDC
VSS
VDDC
V
ANT4_ ANT4_ ANT4_ ANT4_ ANT4_
DIO002 DIO004 DIO005 DIO003 DIO007
X1VDD
VSS
VDDC
VSS
VDDC
VSS
VDDC
ANT4_ X1VDD ANT4_ ANT4_ ANT4_ X1VDD ANT4_ X1VDD
DIO009
DIO010 DIO011 RX_CLK
TX_CLK
VSS
VDDC
VSS
VDDC
VSS
VDDC
VSS
VDDC
VSS
D2_
MVREF
VSS
VDDC
R
W
Y
VSS
VSS
ANT1_
DIO105
ANT4_
TX_
ANT4_
ENABLE FRAME
VSS
VSS
VSS
ANT4_
DIO008
ANT4_
ANT4_ FA_VDD X1VDD
RX_
FRAME TXNRX
D2_
MCS_
B00
D2_
MCS_ G2VDD G2VDD G2VDD G2VDD G2VDD G2VDD G2VDD
B01
D2_
MA00
VSS
AA
AVDD_
D2_DDR
VSS
AB
VSS
D2_
MA02
AC
D2_
MA08
D2_
MBA00
AD
VSS
D2_
MA09
D2_
D2_
D2_
MA11 MRAS_B MA13
AE
D2_
MA15
D2_
MA14
D2_
MA06
VSS
D2_
D2_
D2_
MCK00 MDIC00 MCK02
AF
D2_
MA07
G2VDD
D2_
MCS_
B02
D2_
MCS_
B03
D2_
MCK_
B00
AG
D2_
MA05
D2_
MA03
D2_
MA04
D2_
MA10
D2_
D2_
MBA02 MBA01
G2VDD
D2_
MA01
VSS
D2_
D2_
D2_
D2_
MA12 MCAS_B MWE_B MDQ06
G2VDD
D2_
MDQ08
D2_ G2VDD
D2_
D2_
MODT01
MDIC01 MCK01
D2_
MDQ01
1
2
3
4
5
6
D2_
D2_ G2VDD
D2_
D2_
D2_
D2_
MDQ03 MDQ02
MDQ07 MDQ25 MDQ31 MDQ26
D2_
D2_
D2_
D2_
D2_
G2VDD
D2_
MDQ10 MDM01 MDQ18 MDQ17 MDQ30
MDQ24
VSS
D2_
D2_
MDQ15 MDQS01
VSS
D2_
D2_
D2_
MDQ20 MDQS03 MECC00
D2_
D2_
D2_
MDQS_ D2_
MDQS_
MCK_
D2_
D2_
D2_
B01
B03
B02 MDQ14 MDQ13
MDQ23 MDQ21
VSS
NC_
BGA_
D2_
D2_
D2_
D2_
D2_
MODT00 MCKE00 AE4 MCKE01 MCK_BO1MDQ12
AH
D2_
D2_
D2_
D2_
D2_
D2_
D2_
MDM00 MDQ05 MDQ00 MDQ04 MDQ28 MDM03 MDQ27
7
VSS
D2_
G2VDD D2_
D2_ G2VDD
D2_
D2_
MDQS00
MDQ19 MDQS02
MDQ16 MECC07
D2_
D2_
MDQS_ D2_
MDQ09 MDQ11
B00
8
9
10
D2_
D2_
D2_
MDQS_ D2_
B02 MDM02 MDQ22 MECC01
11
12
13
14
Figure 5. Ball Layout Diagram—Detail C
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
7
Pin Assignments
Figure 6 shows detailed view D.
DETAIL D
USB_
CLK
USB_
STP
CVDD
VSS
EE1
EE0
CFG_0_
JTAG_ OVDD
MODE
TMS
TDO
TDI
CFG_1_
JTAG_
MODE
IIC1_
SCL
IIC1_
SDA
OVDD
VSS
VDDC
VSS
VDDC
VSS
VSS
VDDC
VSS
VDDC
VSS
VSS
VDDC
VSS
VDDC
VSS
OVDD READY
VSS
VDDC
VSS
VDDC
VSS
OVDD
OVDD
VSS
VDDC
VSS
VDDC
VSS
VSS
VSS
VSS
AVDD_
DSP
VSS
VDDC
VSS
AVDD_
MAPLE
VSS
UART_
SIN00
G2VDD POVDD3 XCORE SD2
VSS
AGND
XPAD
VDD
XPAD
VDD
VSS
EC_
MDC
D2_
D2_
XCORE SD_PLL2 SD2
MECC02 MECC03 VSS
_TPA
AVDD
G2VDD
D2_
MDQ29
D2_
XCORE
MECC04 VSS
VSS
XPAD
VSS
SD_
PLL2_
TPD
XCORE SD_IMP_ XPAD
VSS CAL_TX VSS
SENSE CVDD USB_D05 USB_
VSS
NXT
VSS
UDE_
B0
UDE_B1
TMP_
DETECT
TCK
UART_
CTS_ UART_
B01 SOUT01
LVDD
HRESET SCAN_
_B
MODE_B
R
HRESET TRST_B
_REQ_B
T
VSS
TEST_
SEL_B
TEMP_
D1_
ANODE DDRCLK
VSS
CVDD_ DSP_ TEMP_
VSS
VSEL CLKIN CATHODE
EC_
MDIO
UART_
SOUT00
VSS
UART_ UART_
RTS_B01 SIN01
TSEC_ TSEC_
TSEC_
1588_
1588_ LVDD
1588_ BVDD_
CLK_OUT PULSE_OUT1
TRIG_IN1VSEL01
U
V
W
Y
DSP_
TCK
AA
SD_
TSEC_ DSP_
UART_
PLL1_ XCORE XCORE BVDD_ 1588_CLKTRST_B UART_
VSS
CTS_B00
TPA
RTS_B00
VSS
VSS
VSEL00
_IN
AB
SD1 SD_PLL1 SD1
AGND _TPD
AVDD
DSP_
TMS
XVDD1_ D2_
VSEL DDRCLK
AC
XCORE XPAD SD_IMP XPAD XCORE XCORE LVDD_
VSS
VSS
VSEL
VSS
VSS _CAL_RX VSS
OVDD XVDD2_
VSEL
AD
XCORE DSP_
TDO
VSS
DSP_
TDI
D2_ XCORE SD_REF XPAD
MECC05 VSS
_CLK2
VSS
SD_
TX03
XPAD
VDD
SD_
TX02
XPAD
VSS
SD_
TX01
XPAD
VDD
SD_
TX00
XPAD
VSS
VSS
SYSCLK
AE
D2_ XCORE SD_REF XPAD
MDM08 VDD _CLK2_B VDD
SD_
TX_
B03
XPAD
VSS
SD_TX
_B02
XPAD
VDD
SD_TX
_B01
XPAD
VSS
SD_TX
_B00
XPAD
VDD
XCORE
VSS
VSS
AF
SD_ XCORE
RX02
VDD
SD_
RX01
XCORE
VSS
SD_
RX00
XCORE SD_REF XCORE
VDD
_CLK1
VSS
RTC
AG
D2_
MDQS_
B08
VSS
XCORE
VDD
SD_
RX03
XCORE
VSS
D2_
D2_
XCORE SD_RX XCORE
SD_ XCORE
MDQS08 MECC06 VSS
_B03
VDD
RX_B02 VSS
15
16
17
18
19
20
21
AH
SD_RX XCORE SD_RX XCORE SD_REF XCORE
_B00
VSS _CLK1_B VDD
_B01
VDD
22
23
24
25
26
27
28
Figure 6. Ball Layout Diagram—Detail D
1.2
Pinout Assignments
This table provides the pinout listing.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
8
Freescale Semiconductor
Pin Assignments
Table 1. BSC9132 Pinout Listing
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
DDR 1 (Power Architecture)
D1_MDQ00
Data
F16
I/O
G1VDD
—
D1_MDQ01
Data
G16
I/O
G1VDD
—
D1_MDQ02
Data
G15
I/O
G1VDD
—
D1_MDQ03
Data
E18
I/O
G1VDD
—
D1_MDQ04
Data
E16
I/O
G1VDD
—
D1_MDQ05
Data
F17
I/O
G1VDD
—
D1_MDQ06
Data
G17
I/O
G1VDD
—
D1_MDQ07
Data
F15
I/O
G1VDD
—
D1_MDQ08
Data
C17
I/O
G1VDD
—
D1_MDQ09
Data
A15
I/O
G1VDD
—
D1_MDQ10
Data
B16
I/O
G1VDD
—
D1_MDQ11
Data
C14
I/O
G1VDD
—
D1_MDQ12
Data
A16
I/O
G1VDD
—
D1_MDQ13
Data
C15
I/O
G1VDD
—
D1_MDQ14
Data
D14
I/O
G1VDD
—
D1_MDQ15
Data
D15
I/O
G1VDD
—
D1_MDQ16
Data
G12
I/O
G1VDD
—
D1_MDQ17
Data
F14
I/O
G1VDD
—
D1_MDQ18
Data
G14
I/O
G1VDD
—
D1_MDQ19
Data
E14
I/O
G1VDD
—
D1_MDQ20
Data
E12
I/O
G1VDD
—
D1_MDQ21
Data
E13
I/O
G1VDD
—
D1_MDQ22
Data
G11
I/O
G1VDD
—
D1_MDQ23
Data
G13
I/O
G1VDD
—
D1_MDQ24
Data
D10
I/O
G1VDD
—
D1_MDQ25
Data
D12
I/O
G1VDD
—
D1_MDQ26
Data
C10
I/O
G1VDD
—
D1_MDQ27
Data
D11
I/O
G1VDD
—
D1_MDQ28
Data
A11
I/O
G1VDD
—
D1_MDQ29
Data
B9
I/O
G1VDD
—
D1_MDQ30
Data
C12
I/O
G1VDD
—
D1_MDQ31
Data
C9
I/O
G1VDD
—
D1_MDM00
Data Mask
E17
O
G1VDD
—
D1_MDM01
Data Mask
A13
O
G1VDD
—
D1_MDM02
Data Mask
F12
O
G1VDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
9
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
D1_MDM03
Data Mask
C11
O
G1VDD
—
D1_MDQS00
Data Strobe
C16
I/O
G1VDD
—
D1_MDQS01
Data Strobe
A14
I/O
G1VDD
—
D1_MDQS02
Data Strobe
C13
I/O
G1VDD
—
D1_MDQS03
Data Strobe
A12
I/O
G1VDD
—
D1_MDQS_B00
Data Strobe
D16
I/O
G1VDD
—
D1_MDQS_B01
Data Strobe
B14
I/O
G1VDD
—
D1_MDQS_B02
Data Strobe
D13
I/O
G1VDD
—
D1_MDQS_B03
Data Strobe
B12
I/O
G1VDD
—
D1_MBA00
Bank Select
C23
O
G1VDD
—
D1_MBA01
Bank Select
A23
O
G1VDD
—
D1_MBA02
Bank Select
C24
O
G1VDD
—
D1_MA00
Address
E22
O
G1VDD
—
D1_MA01
Address
A24
O
G1VDD
—
D1_MA02
Address
B24
O
G1VDD
—
D1_MA03
Address
B20
O
G1VDD
—
D1_MA04
Address
A25
O
G1VDD
—
D1_MA05
Address
D21
O
G1VDD
—
D1_MA06
Address
A21
O
G1VDD
—
D1_MA07
Address
C21
O
G1VDD
—
D1_MA08
Address
B22
O
G1VDD
—
D1_MA09
Address
E23
O
G1VDD
—
D1_MA10
Address
B25
O
G1VDD
—
D1_MA11
Address
C22
O
G1VDD
—
D1_MA12
Address
D23
O
G1VDD
—
D1_MA13
Address
G19
O
G1VDD
—
D1_MA14
Address
G22
O
G1VDD
—
D1_MA15
Address
F22
O
G1VDD
—
D1_MWE_B
Write Enable
D19
O
G1VDD
—
D1_MRAS_B
Row Address Strobe
A22
O
G1VDD
—
D1_MCAS_B
Column Address Strobe
F19
O
G1VDD
—
D1_MCS_B00
Chip Select
C20
O
G1VDD
—
D1_MCS_B01
Chip Select
F20
O
G1VDD
—
D1_MCS_B02
Chip Select
E20
O
G1VDD
—
D1_MCS_B03
Chip Select
G20
O
G1VDD
—
D1_MCKE00
Clock Enable
A20
O
G1VDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
10
Freescale Semiconductor
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
D1_MCKE01
Clock Enable
C19
O
G1VDD
—
D1_MCK00
Clock
A19
O
G1VDD
—
D1_MCK01
Clock
C18
O
G1VDD
—
D1_MCK02
Clock
A17
O
G1VDD
—
D1_MCK_B00
Clock Complements
B19
O
G1VDD
—
D1_MCK_B01
Clock Complements
D18
O
G1VDD
—
D1_MCK_B02
Clock Complements
B17
O
G1VDD
—
D1_MODT00
On Die Termination
E21
O
G1VDD
—
D1_MODT01
On Die Termination
G21
O
G1VDD
—
D1_MDIC00
Driver Impedence Calibration
A18
I/O
VSS
14
D1_MDIC01
Driver Impedence Calibration
G18
I/O
G1VDD
14
D1_MECC00
ECC data
E10
I/O
G1VDD
—
D1_MECC01
ECC data
G10
I/O
G1VDD
—
D1_MECC02
ECC data
E9
I/O
G1VDD
—
D1_MECC03
ECC data
F9
I/O
G1VDD
—
D1_MECC04
ECC data
D8
I/O
G1VDD
—
D1_MECC05
ECC data
G9
I/O
G1VDD
—
D1_MECC06
ECC data
C8
I/O
G1VDD
—
D1_MECC07
ECC data
F11
I/O
G1VDD
—
D1_MDQS08
ECC Strobe
B10
I/O
G1VDD
—
D1_MDQS_B08
ECC Strobe
A10
I/O
G1VDD
—
D1_MDM08
ECC Data Mask
F10
O
G1VDD
—
DDR 2 (DSP)
D2_MDQ00
Data
AB10
I/O
G2VDD
—
D2_MDQ01
Data
AD7
I/O
G2VDD
—
D2_MDQ02
Data
AC9
I/O
G2VDD
—
D2_MDQ03
Data
AC8
I/O
G2VDD
—
D2_MDQ04
Data
AB11
I/O
G2VDD
—
D2_MDQ05
Data
AB9
I/O
G2VDD
—
D2_MDQ06
Data
AC7
I/O
G2VDD
—
D2_MDQ07
Data
AC11
I/O
G2VDD
—
D2_MDQ08
Data
AF6
I/O
G2VDD
—
D2_MDQ09
Data
AH9
I/O
G2VDD
—
D2_MDQ10
Data
AD8
I/O
G2VDD
—
D2_MDQ11
Data
AH10
I/O
G2VDD
—
D2_MDQ12
Data
AH7
I/O
G2VDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
11
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
D2_MDQ13
Data
AF9
I/O
G2VDD
—
D2_MDQ14
Data
AF8
I/O
G2VDD
—
D2_MDQ15
Data
AE9
I/O
G2VDD
—
D2_MDQ16
Data
AG13
I/O
G2VDD
—
D2_MDQ17
Data
AD11
I/O
G2VDD
—
D2_MDQ18
Data
AD10
I/O
G2VDD
—
D2_MDQ19
Data
AG10
I/O
G2VDD
—
D2_MDQ20
Data
AE12
I/O
G2VDD
—
D2_MDQ21
Data
AF12
I/O
G2VDD
—
D2_MDQ22
Data
AH13
I/O
G2VDD
—
D2_MDQ23
Data
AF11
I/O
G2VDD
—
D2_MDQ24
Data
AD14
I/O
G2VDD
—
D2_MDQ25
Data
AC12
I/O
G2VDD
—
D2_MDQ26
Data
AC14
I/O
G2VDD
—
D2_MDQ27
Data
AB14
I/O
G2VDD
—
D2_MDQ28
Data
AB12
I/O
G2VDD
—
D2_MDQ29
Data
AD15
I/O
G2VDD
—
D2_MDQ30
Data
AD12
I/O
G2VDD
—
D2_MDQ31
Data
AC13
I/O
G2VDD
—
D2_MDM00
Data Mask
AB8
O
G2VDD
—
D2_MDM01
Data Mask
AD9
O
G2VDD
—
D2_MDM02
Data Mask
AH12
O
G2VDD
—
D2_MDM03
Data Mask
AB13
O
G2VDD
—
D2_MDQS00
Data Strobe
AG8
I/O
G2VDD
—
D2_MDQS01
Data Strobe
AE10
I/O
G2VDD
—
D2_MDQS02
Data Strobe
AG11
I/O
G2VDD
—
D2_MDQS03
Data Strobe
AE13
I/O
G2VDD
—
D2_MDQS_B00
Data Strobe
AH8
I/O
G2VDD
—
D2_MDQS_B01
Data Strobe
AF10
I/O
G2VDD
—
D2_MDQS_B02
Data Strobe
AH11
I/O
G2VDD
—
D2_MDQS_B03
Data Strobe
AF13
I/O
G2VDD
—
D2_MBA00
Bank Select
AC2
O
G2VDD
—
D2_MBA01
Bank Select
AB4
O
G2VDD
—
D2_MBA02
Bank Select
AB3
O
G2VDD
—
D2_MA00
Address
AB6
O
G2VDD
—
D2_MA01
Address
AA5
O
G2VDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
12
Freescale Semiconductor
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
D2_MA02
Address
AB2
O
G2VDD
—
D2_MA03
Address
AG2
O
G2VDD
—
D2_MA04
Address
AA3
O
G2VDD
—
D2_MA05
Address
AG1
O
G2VDD
—
D2_MA06
Address
AE3
O
G2VDD
—
D2_MA07
Address
AF1
O
G2VDD
—
D2_MA08
Address
AC1
O
G2VDD
—
D2_MA09
Address
AD2
O
G2VDD
—
D2_MA10
Address
AA4
O
G2VDD
—
D2_MA11
Address
AD3
O
G2VDD
—
D2_MA12
Address
AC4
O
G2VDD
—
D2_MA13
Address
AD5
O
G2VDD
—
D2_MA14
Address
AE2
O
G2VDD
—
D2_MA15
Address
AE1
O
G2VDD
—
D2_MWE_B
Write Enable
AC6
O
G2VDD
—
D2_MRAS_B
Row Address Strobe
AD4
O
G2VDD
—
D2_MCAS_B
Column Address Strobe
AC5
O
G2VDD
—
D2_MCS_B00
Chip Select
AA6
O
G2VDD
—
D2_MCS_B01
Chip Select
AA7
O
G2VDD
—
D2_MCS_B02
Chip Select
AF3
O
G2VDD
—
D2_MCS_B03
Chip Select
AF4
O
G2VDD
—
D2_MCKE00
Clock Enable
AH3
O
G2VDD
—
D2_MCKE01
Clock Enable
AH5
O
G2VDD
—
D2_MCK00
Clock
AE5
O
G2VDD
—
D2_MCK01
Clock
AG6
O
G2VDD
—
D2_MCK02
Clock
AE7
O
G2VDD
—
D2_MCK_B00
Clock Complements
AF5
O
G2VDD
—
D2_MCK_B01
Clock Complements
AH6
O
G2VDD
—
D2_MCK_B02
Clock Complements
AF7
O
G2VDD
—
D2_MODT00
On Die Termination
AH2
O
G2VDD
—
D2_MODT01
On Die Termination
AG3
O
G2VDD
—
D2_MDIC00
Driver Impedence Calibration
AE6
I/O
VSS
14
D2_MDIC01
Driver Impedence Calibration
AG5
I/O
G2VDD
14
D2_MECC00
ECC data
AE14
I/O
G2VDD
—
D2_MECC01
ECC data
AH14
I/O
G2VDD
—
D2_MECC02
ECC data
AB15
I/O
G2VDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
13
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
D2_MECC03
ECC data
AB16
I/O
G2VDD
—
D2_MECC04
ECC data
AC16
I/O
G2VDD
—
D2_MECC05
ECC data
AE15
I/O
G2VDD
—
D2_MECC06
ECC data
AH16
I/O
G2VDD
—
D2_MECC07
ECC data
AG14
I/O
G2VDD
—
D2_MDQS08
ECC Strobe
AH15
I/O
G2VDD
—
D2_MDQS_B08
ECC Strobe
AG15
I/O
G2VDD
—
D2_MDM08
ECC Data Mask
AF15
O
G2VDD
—
Ethernet Management
EC_MDC
Management Data Clock
AA22
O
LVDD
2
EC_MDIO
Management Data In/Out
Y24
I/O
LVDD
2
eTSEC 1588
TSEC_1588_CLK_IN
1588 Clock In
AB24
I
LVDD
—
TSEC_1588_CLK_OUT/
CLK_OUT
1588 Clock Out
AA23
O
LVDD
—
TSEC_1588_TRIG_IN1
1588 Trigger In
AA26
I
LVDD
—
TSEC_1588_PULSE_OUT1/
PPS_OUT
1588 Pulse Out
AA24
O
LVDD
2
IFC
IFC_AD00
IFC Muxed Address,Data
A27
I/O
BVDD
18
IFC_AD01
IFC Muxed Address,Data
B28
I/O
BVDD
18
IFC_AD02
IFC Muxed Address,Data
C28
I/O
BVDD
18
IFC_AD03
IFC Muxed Address,Data
D26
I/O
BVDD
18
IFC_AD04
IFC Muxed Address,Data
D27
I/O
BVDD
18
IFC_AD05
IFC Muxed Address,Data
D28
I/O
BVDD
18
IFC_AD06
IFC Muxed Address,Data
F25
I/O
BVDD
2
IFC_AD07
IFC Muxed Address,Data
E26
I/O
BVDD
18
IFC_AD08/
GPIO34
IFC Muxed Address,Data
E28
I/O
BVDD
—
IFC_AD09/
GPIO35
IFC Muxed Address,Data
F27
I/O
BVDD
—
IFC_AD10/
GPIO36
IFC Muxed Address,Data
F28
I/O
BVDD
—
IFC_AD11/
GPIO37/
IRQ08
IFC Muxed Address,Data
G25
I/O
BVDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
14
Freescale Semiconductor
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
IFC_AD12/
GPIO38/
IRQ09
IFC Muxed Address,Data
G26
I/O
BVDD
—
IFC_AD13/
GPIO39/
IRQ07
IFC Muxed Address,Data
G27
I/O
BVDD
—
IFC_AD14/
GPIO40/
IRQ06
IFC Muxed Address,Data
G28
I/O
BVDD
—
IFC_AD15/
GPIO41/
TIMER02
IFC Muxed Address,Data
H28
I/O
BVDD
—
IFC_ADDR16/
GPO08
IFC Address
H26
O
BVDD
2
IFC_ADDR17/
GPO09
IFC Address
H25
O
BVDD
2
IFC_ADDR18/
GPO10
IFC Address
H24
O
BVDD
2
IFC_ADDR19/
GPO11
IFC Address
H22
O
BVDD
2
IFC_ADDR20/
GPO12
IFC Address
H21
O
BVDD
2
IFC_ADDR21/
GPO13
IFC Address
J28
O
BVDD
2
IFC_ADDR22/
GPO14
IFC Address
J27
O
BVDD
18
IFC_ADDR23/
GPO15
IFC Address
J25
O
BVDD
2
IFC_ADDR24/
GPO16
IFC Address
J24
O
BVDD
2
IFC_ADDR25/
GPO17
IFC Address
J23
O
BVDD
2
IFC_ADDR26/
GPO18
IFC Address
J22
O
BVDD
2
IFC_AVD/
GPO54
IFC Address Valid
L28
O
BVDD
2
IFC_CS_B00/
GPO55
IFC Chip Select
K21
O
BVDD
—
IFC_CS_B01/
GPO64
IFC Chip Select
K28
O
BVDD
—
IFC_CS_B02/
GPO65
IFC Chip Select
L24
O
BVDD
—
IFC_WE_B/
GPO52
IFC Write Enable/GPCM Write Byte Select0/
Generic ASIC i/f Start of Frame
L26
O
BVDD
2
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
15
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
IFC_CLE/
GPO48
NAND Command Latch Enable/GPCM Write
Byte Select1
L25
O
BVDD
18
IFC_OE_B/
GPO49
NOR Output Enable/NAND Read Enable/
GPCM Output Enable/Generic ASIC Interface
Read-Write Indicator
K23
O
BVDD
2
IFC_WP_B/
GPO66
IFC Write Protect
K26
O
BVDD
18
IFC_RB_B/
GPO50
IFC Read Busy/GPCM External Transreciver/
Generic ASIC i/f Ready Indicator
K25
I
BVDD
—
IFC_BCTL/
GPO67
Data Buffer Control
K22
O
BVDD
18
IFC_CLK00/
GPO68
IFC Clock
K27
O
BVDD
—
eSDHC
SDHC_CLK/
SIM_CLK/
GPO52
SDHC Clock
B27
O
BVDD
—
SDHC_CMD/
SIM_RST_B/
GPIO48
SDHC Command
C26
I/O
BVDD
15
SDHC_DATA00/
SIM_TRXD/
GPIO49
SDHC Data2 in all modes
D25
I/O
BVDD
15
SDHC_DATA01/
SIM_SVEN/
GPIO50
SDHC Data1 in 4-bit mode
F23
I/O
BVDD
15
SDHC_DATA02/
SIM_PD/
GPIO51
SDHC Data2 in 4-bit mode
F24
I/O
BVDD
15
SDHC_DATA03/
DMA_DDONE_B00/
CKSTP1_IN_B/
GPIO77
SDHC Data3 in 1-bit mode
SDHC Data3 in 4-bit mode
E25
I/O
BVDD
15,16
SDHC_WP/
DMA_DREQ_B00/
CKSTP0_IN_B/
GPIO78
SDHC Write Protect Detect
G23
I
BVDD
—
SDHC_CD/
DMA_DACK_B00/
MCP1_B/
GPIO79/
IRQ10
SDHC Card Detect
C25
I
BVDD
—
USIM
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
16
Freescale Semiconductor
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
SDHC_CLK/
SIM_CLK/
GPO52
SIM Clock
B27
O
BVDD
—
SDHC_CMD/
SIM_RST_B/
GPIO48
SIM Reset
C26
O
BVDD
17
SDHC_DATA00/
SIM_TRXD/
GPIO49
SIM TX RX Data
D25
I/O
BVDD
15
SDHC_DATA01/
SIM_SVEN/
GPIO50
SIM Enable
F23
O
BVDD
17
SDHC_DATA02/
SIM_PD/
GPIO51
SIM Card Detect
F24
I
BVDD
17
USIM over SPI1
SPI1_CLK/
SIM_CLK
SIM Clock
M27
O
CVDD
—
SPI1_MISO/
UART_CTS_B03/
SIM_RST_B/
GPIO55
SIM Reset
M22
O
CVDD
17
SPI1_CS0_B/
UART_RTS_B03/
SIM_TRXD
SIM TX RX Data
M28
I/O
CVDD
15
SPI1_MOSI/
UART_SIN03/
SIM_SVEN/
GPIO54
SIM Enable
L22
O
CVDD
17
UART_CTS_B00/
SIM_PD/
TIMER04/
GPIO42/
IRQ04
SIM Card Detect
AB27
I
OVDD
17
USB
USB_CLK/
UART_SIN02/
GPIO69/
IRQ11/
TIMER03
ULPI Clock
R24
I
CVDD
—
USB_D07/
UART_SOUT02/
GPIO70
ULPI Data
P28
I/O
CVDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
17
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
USB_D06/
UART_CTS_B02/
GPIO62
ULPI Data
P25
I/O
CVDD
—
USB_D05/
UART_RTS_B02/
GPIO63
ULPI Data
R22
I/O
CVDD
—
USB_D04/
GPIO00/
IRQ00
ULPI Data
P26
I/O
CVDD
—
USB_D03/
GPIO01/
IRQ01
ULPI Data
N25
I/O
CVDD
—
USB_D02/
IIC2_SDA/
GPIO71
ULPI Data
N26
I/O
CVDD
—
USB_D01/
IIC2_SCL/
GPIO72
ULPI Data
N27
I/O
CVDD
—
USB_D00/
IRQ02/
GPIO53
ULPI Data
N28
I/O
CVDD
—
USB_STP/
IRQ_OUT_B/
GPO73
ULPI Stop
R25
O
CVDD
—
USB_DIR/
GPIO02/
TIMER01/
MCP0_B
ULPI Data Direction
P24
I
CVDD
—
USB_NXT/
GPIO03/
IRQ03/
TRIG_IN
ULPI Next Data Throttle Control
R23
I
CVDD
—
USB over ANT2
ANT2_DIO009/
USB_CLK/
GPIO59
ULPI Clock
F4
I
X2VDD
—
ANT2_DIO007/
USB_D07/
GPIO32
ULPI Data
G3
I/O
X2VDD
—
ANT2_DIO006/
USB_D06/
GPIO31
ULPI Data
F1
I/O
X2VDD
—
ANT2_DIO005/
USB_D05/
GPIO30
ULPI Data
G5
I/O
X2VDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
18
Freescale Semiconductor
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
ANT2_DIO004/
USB_D04/
GPIO29
ULPI Data
E5
I/O
X2VDD
—
ANT2_DIO003/
USB_D03/
GPIO28
ULPI Data
J5
I/O
X2VDD
—
ANT2_DIO002/
USB_D02/
GPIO27
ULPI Data
J6
I/O
X2VDD
—
ANT2_DIO001/
USB_D01/
GPIO26
ULPI Data
E1
I/O
X2VDD
—
ANT2_DIO000/
USB_D00/
GPIO25
ULPI Data
E2
I/O
X2VDD
—
ANT2_ENABLE/
USB_STP
ULPI Stop
J1
O
X2VDD
—
ANT2_DIO008/
USB_DIR/
GPIO33
ULPI Data Direction
F2
I
X2VDD
—
ANT2_DIO010/
USB_NXT/
GPIO60
ULPI Next Data Throttle Control
F5
I
X2VDD
—
DUART
UART_SOUT00
UART0 Transmit Data
Y25
O
OVDD
2
UART_SIN00
UART0 Receive Data
Y22
I
OVDD
—
UART_CTS_B00/
SIM_PD/
TIMER04/
GPIO42/
IRQ04
UART0 Clear to Send
AB27
I
OVDD
—
UART_RTS_B00/
PPS_LED/
GPO43
UART0 Ready to Send
AB26
O
OVDD
2
UART_SOUT01/
GPO56
UART1 Transmit Data
W23
O
OVDD
2
UART_SIN01/
GPIO57
UART1 Receive Data
Y28
I
OVDD
—
UART_CTS_B01/
SYS_DMA_REQ/
SRESET_B/
GPIO44/
IRQ05
UART1 Clear to Send
W22
I
OVDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
19
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
UART_RTS_B01/
SYS_DMA_DONE/
GPO45/
ANT4_AGC
Signal Description
UART1 Ready to Send
Pin
Number
Pin
Type
Power
Supply
Note
Y27
O
OVDD
2
UART2 over USB
USB_D07/
UART_SOUT02/
GPIO70
UART2 Transmit Data
P28
O
CVDD
—
USB_CLK/
UART_SIN02/
GPIO69/
IRQ11/
TIMER03
UART2 Receive Data
R24
I
CVDD
—
USB_D06/
UART_CTS_B02/
GPIO62
UART2 Clear to Send
P25
I
CVDD
—
USB_D05/
UART_RTS_B02/
GPIO63
UART2 Ready to Send
R22
O
CVDD
—
UART3 over SPI1
SPI1_CS1_B/
UART_SOUT03/
GPO74
UART3 Transmit Data
M24
O
CVDD
—
SPI1_MOSI/
UART_SIN03/
SIM_SVEN/
GPIO54
UART3 Receive Data
L22
I
CVDD
—
SPI1_MISO/
UART_CTS_B03/
SIM_RST_B/
GPIO55
UART3 Clear to Send
M22
I
CVDD
—
SPI1_CS0_B/
UART_RTS_B03/
SIM_TRXD
UART3 Ready to Send
M28
O
CVDD
—
SPI1
SPI1_MOSI/
UART_SIN03/
SIM_SVEN/
GPIO54
SPI Master Out Slave In Data
L22
I/O
CVDD
—
SPI1_MISO/
UART_CTS_B03/
SIM_RST_B/
GPIO55
SPI Master In Slave Out Data
M22
I
CVDD
—
SPI1_CLK/
SIM_CLK
SPI Serial Clock
M27
O
CVDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
20
Freescale Semiconductor
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
SPI1_CS0_B/
UART_RTS_B03/
SIM_TRXD
SPI Slave Select
M28
O
CVDD
—
SPI1_CS1_B/
UART_SOUT03/
GPO74
SPI Slave Select
M24
O
CVDD
—
SPI1_CS2_B/
CKSTP0_OUT_B/
GPO75
SPI Slave Select
M25
O
CVDD
—
SPI1_CS3_B/
CKSTP1_OUT_B/
GPO76
SPI Slave Select
M23
O
CVDD
—
SPI2 for RF Interface Control
SPI2_CLK
SPI Serial Clock
E6
O
X2VDD
—
SPI2_MOSI
SPI Master Out Slave In Data
E7
I/O
X2VDD
2
SPI2_MISO
SPI Master In Slave Out Data
A6
I
X2VDD
—
SPI2_CS0_B
SPI Slave Select
B7
O
X2VDD
—
SPI2_CS1_B
SPI Slave Select
A7
O
X2VDD
—
SPI2_CS2_B/
GPO93
SPI Slave Select
A8
O
X2VDD
—
SPI2_CS3_B/
GPO94
SPI Slave Select
D6
O
X2VDD
—
I2C1
IIC1_SDA/
GPIO46
Serial Data
V25
I/O
OVDD
5
IIC1_SCL/
GPIO47
Serial Clock
V24
I/O
OVDD
5
I2C2
USB_D02/
IIC2_SDA/
GPIO71
Serial Data
N26
I/O
CVDD
5
USB_D01/
IIC2_SCL/
GPIO72
Serial Clock
N27
I/O
CVDD
5
TDM1 over RF2
ANT2_DIO100/
TDM1_TCK
TDM1 Clock
H1
I/O
X2VDD
—
ANT2_DIO101/
TDM1_TFS
TDM1 Transmit Frame Sync
K5
I/O
X2VDD
—
ANT2_DIO103/
TDM1_TXD
TDM1 Transmit Data
L5
I/O
X2VDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
21
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
ANT2_DIO104/
TDM1_RCK/
GPIO92
TDM1 Receive Clock
K4
I/O
X2VDD
—
ANT2_DIO105/
TDM1_RFS/
TIMER08
TDM1 Receive Frame Sync
K7
I/O
X2VDD
—
ANT2_DIO102/
TDM1_RXD
TDM1 Receive Data
J7
I/O
X2VDD
—
TDM2 over RF3
ANT3_RX_CLK/
TDM2_TCK/
GPIO04
TDM2 Clock
D1
I/O
X2VDD
—
ANT3_DIO007/
TDM2_TFS
TDM2 Transmit Frame Sync
B3
I/O
X2VDD
—
ANT3_DIO011/
TDM2_TXD
TDM2 Transmit Data
B1
I/O
X2VDD
—
ANT3_DIO008/
TDM2_RCK/
CKSTP0_OUT_B
TDM2 Receive Clock
A2
I/O
X2VDD
—
ANT3_DIO009/
TDM2_RFS/
CKSTP1_OUT_B
TDM2 Receive Frame Sync
C3
I/O
X2VDD
—
ANT3_DIO010/
TDM2_RXD
TDM2 Receive Data
D4
I/O
X2VDD
—
SerDes
SD_TX03
Tx Data out
AE19
O
XPADVDD
—
SD_TX02
Tx Data out
AE21
O
XPADVDD
—
SD_TX01
Tx Data out
AE23
O
XPADVDD
—
SD_TX00
Tx Data out
AE25
O
XPADVDD
—
SD_TX_B03
Tx Data out, inverted
AF19
O
XPADVDD
—
SD_TX_B02
Tx Data out, inverted
AF21
O
XPADVDD
—
SD_TX_B01
Tx Data out, inverted
AF23
O
XPADVDD
—
SD_TX_B00
Tx Data out, inverted
AF25
O
XPADVDD
—
SD_RX03
Rx Data in
AG18
I
XCOREVDD
—
SD_RX02
Rx Data in
AG20
I
XCOREVDD
—
SD_RX01
Rx Data in
AG22
I
XCOREVDD
—
SD_RX00
Rx Data in
AG24
I
XCOREVDD
—
SD_RX_B03
Rx Data in, Inverted
AH18
I
XCOREVDD
—
SD_RX_B02
Rx Data in, Inverted
AH20
I
XCOREVDD
—
SD_RX_B01
Rx Data in, Inverted
AH22
I
XCOREVDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
22
Freescale Semiconductor
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
SD_RX_B00
Rx Data in, Inverted
AH24
I
XCOREVDD
—
SD_REF_CLK1
Reference clock
AG26
I
XCOREVDD
—
SD_REF_CLK1_B
Reference clock, Inverted
AH26
I
XCOREVDD
—
SD_REF_CLK2
Reference clock
AE17
I
XCOREVDD
—
SD_REF_CLK2_B
Reference clock, Inverted
AF17
I
XCOREVDD
—
SD_IMP_CAL_TX
Transmitter impedance calibration
AD18
I
XPADVDD
6
SD_IMP_CAL_RX
Receiver impedance calibration
AD22
I
XCOREVDD
6
SD_PLL1_TPA
PLL test point analog
AB20
O
SD1AVDD
—
SD_PLL1_TPD
PLL test point digital
AC21
O
XPADVDD
—
SD_PLL2_TPA
PLL test point analog
AB18
O
SD2AVDD
—
SD_PLL2_TPD
PLL test point digital
AC19
O
XPADVDD
—
CPRI Signals
ANT3_DIO000/
CP_SYNC1
CPRI Sync
B6
I/O
X2VDD
—
ANT3_DIO001/
CP_SYNC2
CPRI Sync
A5
I/O
X2VDD
—
ANT3_DIO002/
CP_LOS1
CPRI LOS
B5
I
X2VDD
—
ANT3_DIO003/
CP_LOS2
CPRI LOS
A4
I
X2VDD
—
ANT3_DIO004/
CP_TX_INT_B
CPRI Transmit Interrupt
C4
O
X2VDD
—
ANT3_DIO006/
CP_RX_INT_B
CPRI Receive Interrupt
A3
O
X2VDD
—
ANT3_DIO005/
CP_RCLK
CPRI Recovered Clock
C5
O
X2VDD
—
RF Interface 1
ANT1_REF_CLK
Parallel Interface Reference Clock
N1
I
X1VDD
—
ANT1_AGC/
GPO58
AGC Control
R3
O
X1VDD
2
ANT1_TX_CLK/
TSEC_1588_ALARM_OUT2
Transmit Clock
P5
O
X1VDD
—
ANT1_RX_CLK/
TSEC_1588_TRIG_IN2/
GPIO95
Receive Clock
P2
I
X1VDD
—
ANT1_TXNRX/
TSEC_1588_PULSE_OUT2/
GPO19
TX_RX Control
P3
O
X1VDD
—
ANT1_ENABLE/
TSEC_1588_ALARM_OUT1
Antenna Enable
P1
O
X1VDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
23
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
ANT1_TX_FRAME/
GPO20
Transmit Frame
R4
O
X1VDD
4, 13
ANT1_RX_FRAME/
GPIO80
Receive Frame
R2
I
X1VDD
—
ANT1_DIO000
Data
L7
I/O
X1VDD
2
ANT1_DIO001
Data
N7
I/O
X1VDD
2, 4
ANT1_DIO002
Data
P7
I/O
X1VDD
2
ANT1_DIO003
Data
N5
I/O
X1VDD
2
ANT1_DIO004
Data
M7
I/O
X1VDD
ANT1_DIO005
Data
M6
I/O
X1VDD
ANT1_DIO006
Data
N6
I/O
X1VDD
2
ANT1_DIO007
Data
M3
I/O
X1VDD
2
ANT1_DIO008
Data
M2
I/O
X1VDD
2
ANT1_DIO009
Data
M5
I/O
X1VDD
2
ANT1_DIO010
Data
M1
I/O
X1VDD
2
ANT1_DIO011
Data
N3
I/O
X1VDD
2
ANT1_DIO100/
GPIO81
Data
P4
I
X1VDD
—
ANT1_DIO101/
GPIO82
Data
R1
I
X1VDD
—
ANT1_DIO102/
GPIO83
Data
R5
I
X1VDD
—
ANT1_DIO103/
GPIO84
Data
R7
I
X1VDD
—
ANT1_DIO104/
GPIO85
Data
T1
I
X1VDD
—
ANT1_DIO105/
GPIO86
Data
T3
I
X1VDD
—
ANT1_DIO106/
GPIO87/
IRQ10
Data
T5
I
X1VDD
—
ANT1_DIO107/
GPIO88/
IRQ11
Data
T6
I
X1VDD
—
ANT1_DIO108/
GPIO21/
IRQ08
Data
T7
I
X1VDD
—
ANT1_DIO109/
GPIO22/
IRQ09
Data
U1
I
X1VDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
24
Freescale Semiconductor
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
ANT1_DIO110/
TIMER06/
GPIO23
Data
U2
I
X1VDD
—
ANT1_DIO111/
TIMER07/
GPIO24
Data
U3
I
X1VDD
—
RF Interface 2
ANT2_REF_CLK/
ANT3_AGC
Parallel Interface Reference Clock
K1
I
X2VDD
—
ANT2_AGC/
GPO89
AGC Control
G1
O
X2VDD
2
ANT2_TX_CLK/
GPO90
Transmit Clock
H5
O
X2VDD
—
ANT2_RX_CLK/
GPIO91
Receive Clock
J3
I
X2VDD
—
ANT2_TXNRX/
DMA_DACK_B00
TX_RX Control
H2
O
X2VDD
—
ANT2_ENABLE/
USB_STP
Antenna Enable
J1
O
X2VDD
—
ANT2_TX_FRAME/
DMA_DDONE_B00
Transmit Frame
G4
O
X2VDD
4, 13
ANT2_RX_FRAME/
DMA_DREQ_B00
Receive Frame
H3
I
X2VDD
—
ANT2_DIO000/
USB_D00/
GPIO25
Data
E2
I/O
X2VDD
—
ANT2_DIO001/
USB_D01/
GPIO26
Data
E1
I/O
X2VDD
—
ANT2_DIO002/
USB_D02/
GPIO27
Data
J6
I/O
X2VDD
—
ANT2_DIO003/
USB_D03/
GPIO28
Data
J5
I/O
X2VDD
—
ANT2_DIO004/
USB_D04/
GPIO29
Data
E5
I/O
X2VDD
—
ANT2_DIO005/
USB_D05/
GPIO30
Data
G5
I/O
X2VDD
—
ANT2_DIO006/
USB_D06/
GPIO31
Data
F1
I/O
X2VDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
25
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
ANT2_DIO007/
USB_D07/
GPIO32
Data
G3
I/O
X2VDD
—
ANT2_DIO008/
USB_DIR/
GPIO33
Data
F2
I/O
X2VDD
—
ANT2_DIO009/
USB_CLK/
GPIO59
Data
F4
I/O
X2VDD
—
ANT2_DIO010/
USB_NXT/
GPIO60
Data
F5
I/O
X2VDD
—
ANT2_DIO011/
GPIO61
Data
F3
I/O
X2VDD
—
ANT2_DIO100/
TDM1_TCK
Data
H1
I
X2VDD
—
ANT2_DIO101/
TDM1_TFS
Data
K5
I
X2VDD
—
ANT2_DIO102/
TDM1_RXD
Data
J7
I
X2VDD
—
ANT2_DIO103/
TDM1_TXD
Data
L5
I
X2VDD
—
ANT2_DIO104/
TDM1_RCK/
GPIO92
Data
K4
I
X2VDD
—
ANT2_DIO105/
TDM1_RFS/
TIMER08
Data
K7
I
X2VDD
—
ANT2_DIO106/
IRQ04
Data
L4
I
X2VDD
—
ANT2_DIO107/
IRQ05
Data
K3
I
X2VDD
—
ANT2_DIO108/
IRQ06
Data
L2
I
X2VDD
—
ANT2_DIO109/
IRQ07
Data
J2
I
X2VDD
—
ANT2_DIO110
Data
L3
I
X2VDD
—
ANT2_DIO111
Data
L1
I
X2VDD
—
RF Interface 3
ANT2_REF_CLK/
ANT3_AGC
AGC
K1
O
X2VDD
—
ANT3_TX_CLK
Transmit Clock
D3
O
X2VDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
26
Freescale Semiconductor
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
ANT3_RX_CLK/
TDM2_TCK/
GPIO04
Receive Clock
D1
I
X2VDD
—
ANT3_TXNRX
TX_RX Control
C1
O
X2VDD
—
ANT3_ENABLE
Antenna Enable
D5
O
X2VDD
—
ANT3_TX_FRAME
Transmit Frame
E3
O
X2VDD
2
ANT3_RX_FRAME/
GPIO05
Receive Frame
C2
I
X2VDD
—
ANT3_DIO000/
CP_SYNC1
Data
B6
I/O
X2VDD
—
ANT3_DIO001/
CP_SYNC2
Data
A5
I/O
X2VDD
4, 13
ANT3_DIO002/
CP_LOS1
Data
B5
I/O
X2VDD
4, 13
ANT3_DIO003/
CP_LOS2
Data
A4
I/O
X2VDD
4, 13
ANT3_DIO004/
CP_TX_INT_B
Data
C4
I/O
X2VDD
4, 13
ANT3_DIO005/
CP_RCLK
Data
C5
I/O
X2VDD
4, 13
ANT3_DIO006/
CP_RX_INT_B
Data
A3
I/O
X2VDD
4, 13
ANT3_DIO007/
TDM2_TFS
Data
B3
I/O
X2VDD
—
ANT3_DIO008/
TDM2_RCK/
CKSTP0_OUT_B
Data
A2
I/O
X2VDD
—
ANT3_DIO009/
TDM2_RFS/
CKSTP1_OUT_B
Data
C3
I/O
X2VDD
4, 13
ANT3_DIO010/
TDM2_RXD
Data
D4
I/O
X2VDD
4, 13
ANT3_DIO011/
TDM2_TXD
Data
B1
I/O
X2VDD
—
RF Interface 4
UART_RTS_B01/
SYS_DMA_DONE/
GPO45/
ANT4_AGC
AGC
Y27
O
OVDD
—
ANT4_TX_CLK
Transmit Clock
W7
O
X1VDD
—
ANT4_RX_CLK/
GPIO04/
TRIG_IN
Receive Clock
W5
I
X1VDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
27
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
ANT4_TXNRX
TX_RX Control
Y6
O
X1VDD
—
ANT4_ENABLE/
SYS_DMA_DONE
Antenna Enable
Y2
O
X1VDD
—
ANT4_TX_FRAME/
GPO06
Transmit Frame
Y3
O
X1VDD
2
ANT4_RX_FRAME/
GPIO05
Receive Frame
Y5
I
X1VDD
—
ANT4_DIO000/
TIMER05
Data
U5
I/O
X1VDD
—
ANT4_DIO001/
SYS_DMA_REQ
Data
U6
I/O
X1VDD
—
ANT4_DIO002/
IRQ00
Data
V1
I/O
X1VDD
—
ANT4_DIO003/
IRQ01
Data
V4
I/O
X1VDD
—
ANT4_DIO004/
IRQ02
Data
V2
I/O
X1VDD
—
ANT4_DIO005/
IRQ03
Data
V3
I/O
X1VDD
—
ANT4_DIO006/
IRQ_OUT_B
Data
U7
I/O
X1VDD
—
ANT4_DIO007/
MCP1_B
Data
V5
I/O
X1VDD
—
ANT4_DIO008/
MCP0_B
Data
V7
I/O
X1VDD
—
ANT4_DIO009/
CKSTP0_IN_B
Data
W1
I/O
X1VDD
—
ANT4_DIO010/
CKSTP1_IN_B
Data
W3
I/O
X1VDD
—
ANT4_DIO011/
SRESET_B
Data
W4
I/O
X1VDD
—
System Control/Power Management
HRESET_REQ_B
Hard Reset Request Out
T27
O
OVDD
4
UART_CTS_B01/
SYS_DMA_REQ/
SRESET_B/
GPIO44/
IRQ05
Soft Reset over UART
W22
I
OVDD
—
ANT4_DIO011/
SRESET_B
Soft Reset over RF 4
W4
I
X1VDD
—
SPI1_CS2_B/
CKSTP0_OUT_B/
GPO75
Checkstop Out
M25
O
CVDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
28
Freescale Semiconductor
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
SPI1_CS3_B/
CKSTP1_OUT_B/
GPO76
Checkstop Out
M23
O
CVDD
—
READY/
ASLEEP/
READY_P1
Ready/Trigger Out/Asleep
U21
O
OVDD
2
UDE_B0
Unconditional Debug Event
T21
I
OVDD
—
UDE_B1
Unconditional Debug Event
T22
I
OVDD
—
EE0
DSP Debug Request
T26
I
OVDD
—
EE1
DSP Debug Acknowledge
T25
O
OVDD
2
TMP_DETECT
Tamper Detect
T23
I
OVDD
—
UART_RTS_B00/
PPS_LED/
GPO43
UART0 Ready to Send
AB26
O
OVDD
—
AE28
I
OVDD
—
Clocking
SYSCLK
System Clock
D1_DDRCLK
DDR PLL Reference Clock
V28
I
OVDD
—
D2_DDRCLK
DDR PLL Reference Clock
AC28
I
OVDD
—
RTC
Real Time Clock
AG28
I
OVDD
—
DSP_CLKIN
DSP PLL Reference Clock
W26
I
OVDD
—
TSEC_1588_PULSE_OUT1/
PPS_OUT
PPS Pulse Out
AA24
O
LVDD
2
I/O Voltage Select
BVDD_VSEL00
BVDD Voltage Selection
AB23
I
OVDD
—
BVDD_VSEL01
BVDD Voltage Selection
AA27
I
OVDD
—
CVDD_VSEL
CVDD Voltage Selection
W25
I
OVDD
—
LVDD_VSEL
LVDD Voltage Selection
AD26
I
OVDD
—
XVDD1_VSEL
XVDD 1 Voltage Selection
AC27
I
OVDD
—
XVDD2_VSEL
XVDD 2 Voltage Selection
AD28
I
OVDD
—
Test
SCAN_MODE_B
Scan Mode
R28
I
OVDD
1
CFG_0_JTAG_MODE
JTAG mode selection 0
U22
I
OVDD
10
CFG_1_JTAG_MODE
JTAG mode selection 1
V22
I
OVDD
10
TEST_SEL_B
Test Select
U28
I
OVDD
11
JTAG (Power Architecture)
TCK
Test Clock
V23
I
OVDD
TDI
Test Data In
U26
I
OVDD
3
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
29
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
TDO
Test Data Out
U25
O
OVDD
—
TMS
Test Mode Select
U24
I
OVDD
3
TRST_B
Test Reset
T28
I
OVDD
3
JTAG (DSP)
DSP_TCK
Test Clock
AA28
I
OVDD
—
DSP_TDI
Test Data In
AC25
I
OVDD
3
DSP_TDO
Test Data Out
AC24
O
OVDD
—
DSP_TMS
Test Mode Select
AC26
I
OVDD
3
DSP_TRST_B
Test Reset
AB25
I
OVDD
3
Analog
D1_MVREF
DDR Reference Voltage
J17
I
G1VDD
—
D2_MVREF
DDR Reference Voltage
Y12
I
G2VDD
—
TEMP_ANODE
Temperature Diode Anode
V27
I
—
9
TEMP_CATHODE
Temperature Diode Cathode
W27
I
—
9
SENSEVDD
VDD Sensing Pin—MAPLE
J13
I
—
—
SENSEVDDC
VDD Sensing Pin
L20
I
—
—
SENSEVSS
GND Sensing Pin
R20
I
—
—
Timers
USB_DIR/
GPIO02/
TIMER01/
MCP0_B
Timer 1
P24
I/O
CVDD
—
IFC_AD15/
GPIO41/
TIMER02
Timer 2
H28
I/O
BVDD
—
USB_CLK/
UART_SIN02/
GPIO69/
IRQ11/
TIMER03
Timer 3
R24
I/O
CVDD
—
UART_CTS_B00/
SIM_PD/
TIMER04/
GPIO42/
IRQ04
Timer 4
AB27
I/O
OVDD
—
ANT4_DIO000/
TIMER05
Timer 5
U5
I/O
X1VDD
—
ANT1_DIO110/
TIMER06/
GPIO23
Timer 6
U2
I/O
X1VDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
30
Freescale Semiconductor
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
ANT1_DIO111/
TIMER07/
GPIO24
Timer 7
U3
I/O
X1VDD
—
ANT2_DIO105/
TDM1_RFS/
TIMER08
Timer 8
K7
I/O
X2VDD
—
OCeaN DMA
SDHC_DATA03/
DMA_DDONE_B00/
CKSTP1_IN_B/
GPIO77
DMA done
E25
I/O
BVDD
ANT2_TX_FRAME/
DMA_DDONE_B00
DMA done
G4
O
X2VDD
SDHC_WP/
DMA_DREQ_B00/
CKSTP0_IN_B/
GPIO78
DMA request
G23
I
BVDD
—
ANT2_RX_FRAME/
DMA_DREQ_B00
DMA request
H3
I
X2VDD
—
SDHC_CD/
DMA_DACK_B00/
MCP1_B/
GPIO79/
IRQ10
DMA acknowledge
C25
O
BVDD
—
ANT2_TXNRX/
DMA_DACK_B00
DMA acknowledge
H2
O
X2VDD
—
System DMA
ANT4_ENABLE/
SYS_DMA_DONE
System DMA done
Y2
O
X1VDD
—
UART_RTS_B01/
SYS_DMA_DONE/
GPO45/
ANT4_AGC
System DMA done
Y27
O
OVDD
—
UART_CTS_B01/
SYS_DMA_REQ/
SRESET_B/
GPIO44/
IRQ05
System DMA request
W22
I
OVDD
—
ANT4_DIO001/
SYS_DMA_REQ
System DMA request
U6
I
X1VDD
—
P26
I
CVDD
—
Interrupts
USB_D04/
GPIO00/
IRQ00
External Interrupt
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
31
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
ANT4_DIO002/
IRQ00
External Interrupt
V1
I
X1VDD
—
USB_D03/
GPIO01/
IRQ01
External Interrupt
N25
I
CVDD
—
ANT4_DIO003/
IRQ01
External Interrupt
V4
I
X1VDD
—
USB_D00/
IRQ02/
GPIO53
External Interrupt
N28
I
CVDD
—
ANT4_DIO004/
IRQ02
External Interrupt
V2
I
X1VDD
—
USB_NXT/
GPIO03/
IRQ03/
TRIG_IN
External Interrupt
R23
I
CVDD
—
ANT4_DIO005/
IRQ03
External Interrupt
V3
I
X1VDD
—
UART_CTS_B00/
SIM_PD/
TIMER04/
GPIO42/
IRQ04
External Interrupt
AB27
I
OVDD
—
ANT2_DIO106/
IRQ04
External Interrupt
L4
I
X2VDD
—
UART_CTS_B01/
SYS_DMA_REQ/
SRESET_B/
GPIO44/
IRQ05
External Interrupt
W22
I
OVDD
—
ANT2_DIO107/
IRQ05
External Interrupt
K3
I
X2VDD
—
IFC_AD14/
GPIO40/
IRQ06
External Interrupt
G28
I
BVDD
—
ANT2_DIO108/
IRQ06
External Interrupt
L2
I
X2VDD
—
IFC_AD13/
GPIO39/
IRQ07
External Interrupt
G27
I
BVDD
—
ANT2_DIO109/
IRQ07
External Interrupt
J2
I
X2VDD
—
IFC_AD11/
GPIO37/
IRQ08
External Interrupt
G25
I
BVDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
32
Freescale Semiconductor
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
ANT1_DIO108/
GPIO21/
IRQ08
External Interrupt
T7
I
X1VDD
—
IFC_AD12/
GPIO38/
IRQ09
External Interrupt
G26
I
BVDD
—
ANT1_DIO109/
GPIO22/
IRQ09
External Interrupt
U1
I
X1VDD
—
SDHC_CD/
DMA_DACK_B00/
MCP1_B/
GPIO79/
IRQ10
External Interrupt
C25
I
BVDD
—
ANT1_DIO106/
GPIO87/
IRQ10
External Interrupt
T5
I
X1VDD
—
USB_CLK/
UART_SIN02/
GPIO69/
IRQ11/
TIMER03
External Interrupt
R24
I
CVDD
—
ANT1_DIO107/
GPIO88/
IRQ11
External Interrupt
T6
I
X1VDD
—
USB_STP/
IRQ_OUT_B/
GPO73
Interrupt Output
R25
O
CVDD
—
ANT4_DIO006/
IRQ_OUT_B
Interrupt Output
U7
O
X1VDD
—
GPIO
USB_D04/
GPIO00/
IRQ00
General Purpose I/O
P26
I/O
CVDD
—
USB_D03/
GPIO01/
IRQ01
General Purpose I/O
N25
I/O
CVDD
—
USB_DIR/
GPIO02/
TIMER01/
MCP0_B
General Purpose I/O
P24
I/O
CVDD
—
USB_NXT/
GPIO03/
IRQ03/
TRIG_IN
General Purpose I/O
R23
I/O
CVDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
33
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
ANT3_RX_CLK/
TDM2_TCK/
GPIO04
General Purpose I/O
D1
I/O
X2VDD
—
ANT4_RX_FRAME/
GPIO05
General Purpose I/O
Y5
I/O
X1VDD
—
ANT1_DIO108/
GPIO21/
IRQ08
General Purpose I/O
T7
I/O
X1VDD
—
ANT1_DIO109/
GPIO22/
IRQ09
General Purpose I/O
U1
I/O
X1VDD
—
ANT1_DIO110/
TIMER06/
GPIO23
General Purpose I/O
U2
I/O
X1VDD
—
ANT1_DIO111/
TIMER07/
GPIO24
General Purpose I/O
U3
I/O
X1VDD
—
ANT2_DIO000/
USB_D00/
GPIO25
General Purpose I/O
E2
I/O
X2VDD
—
ANT2_DIO001/
USB_D01/
GPIO26
General Purpose I/O
E1
I/O
X2VDD
—
ANT2_DIO002/
USB_D02/
GPIO27
General Purpose I/O
J6
I/O
X2VDD
—
ANT2_DIO003/
USB_D03/
GPIO28
General Purpose I/O
J5
I/O
X2VDD
—
ANT2_DIO004/
USB_D04/
GPIO29
General Purpose I/O
E5
I/O
X2VDD
—
ANT2_DIO005/
USB_D05/
GPIO30
General Purpose I/O
G5
I/O
X2VDD
—
ANT2_DIO006/
USB_D06/
GPIO31
General Purpose I/O
F1
I/O
X2VDD
—
ANT2_DIO007/
USB_D07/
GPIO32
General Purpose I/O
G3
I/O
X2VDD
—
ANT2_DIO008/
USB_DIR/
GPIO33
General Purpose I/O
F2
I/O
X2VDD
—
IFC_AD08/
GPIO34
General Purpose I/O
E28
I/O
BVDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
34
Freescale Semiconductor
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
IFC_AD09/
GPIO35
General Purpose I/O
F27
I/O
BVDD
—
IFC_AD10/
GPIO36
General Purpose I/O
F28
I/O
BVDD
—
IFC_AD11/
GPIO37/
IRQ08
General Purpose I/O
G25
I/O
BVDD
—
IFC_AD12/
GPIO38/
IRQ09
General Purpose I/O
G26
I/O
BVDD
—
IFC_AD13/
GPIO39/
IRQ07
General Purpose I/O
G27
I/O
BVDD
—
IFC_AD14/
GPIO40/
IRQ06
General Purpose I/O
G28
I/O
BVDD
—
IFC_AD15/
GPIO41/
TIMER02
General Purpose I/O
H28
I/O
BVDD
—
UART_CTS_B00/
SIM_PD/
TIMER04/
GPIO42/
IRQ04
General Purpose I/O
AB27
I/O
OVDD
—
UART_CTS_B01/
SYS_DMA_REQ/
SRESET_B/
GPIO44/
IRQ05
General Purpose I/O
W22
I/O
OVDD
—
IIC1_SDA/
GPIO46
General Purpose I/O
V25
I/O
OVDD
—
IIC1_SCL/
GPIO47
General Purpose I/O
V24
I/O
OVDD
—
SDHC_CMD/
SIM_RST_B/
GPIO48
General Purpose I/O
C26
I/O
BVDD
—
SDHC_DATA00/
SIM_TRXD/
GPIO49
General Purpose I/O
D25
I/O
BVDD
—
SDHC_DATA01/
SIM_SVEN/
GPIO50
General Purpose I/O
F23
I/O
BVDD
—
SDHC_DATA02/
SIM_PD/
GPIO51
General Purpose I/O
F24
I/O
BVDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
35
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
USB_D00/
IRQ02/
GPIO53
General Purpose I/O
N28
I/O
CVDD
—
SPI1_MOSI/
UART_SIN03/
SIM_SVEN/
GPIO54
General Purpose I/O
L22
I/O
CVDD
—
SPI1_MISO/
UART_CTS_B03/
SIM_RST_B/
GPIO55
General Purpose I/O
M22
I/O
CVDD
—
UART_SIN01/
GPIO57
General Purpose I/O
Y28
I/O
OVDD
—
ANT2_DIO009/
USB_CLK/
GPIO59
General Purpose I/O
F4
I/O
X2VDD
—
ANT2_DIO010/
USB_NXT/
GPIO60
General Purpose I/O
F5
I/O
X2VDD
—
ANT2_DIO011/
GPIO61
General Purpose I/O
F3
I/O
X2VDD
—
USB_D06/
UART_CTS_B02/
GPIO62
General Purpose I/O
P25
I/O
CVDD
—
USB_D05/
UART_RTS_B02/
GPIO63
General Purpose I/O
R22
I/O
CVDD
—
USB_CLK/
UART_SIN02/
GPIO69/
IRQ11/
TIMER03
General Purpose I/O
R24
I/O
CVDD
—
USB_D07/
UART_SOUT02/
GPIO70
General Purpose I/O
P28
I/O
CVDD
—
USB_D02/
IIC2_SDA/
GPIO71
General Purpose I/O
N26
I/O
CVDD
—
USB_D01/
IIC2_SCL/
GPIO72
General Purpose I/O
N27
I/O
CVDD
—
SDHC_DATA03/
DMA_DDONE_B00/
CKSTP1_IN_B/
GPIO77
General Purpose I/O
E25
I/O
BVDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
36
Freescale Semiconductor
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
SDHC_WP/
DMA_DREQ_B00/
CKSTP0_IN_B/
GPIO78
General Purpose I/O
G23
I/O
BVDD
—
SDHC_CD/
DMA_DACK_B00/
MCP1_B/
GPIO79/
IRQ10
General Purpose I/O
C25
I/O
BVDD
—
ANT1_RX_FRAME/
GPIO80
General Purpose I/O
R2
I/O
X1VDD
—
ANT1_DIO100/
GPIO81
General Purpose I/O
P4
I/O
X1VDD
—
ANT1_DIO101/
GPIO82
General Purpose I/O
R1
I/O
X1VDD
—
ANT1_DIO102/
GPIO83
General Purpose I/O
R5
I/O
X1VDD
—
ANT1_DIO103/
GPIO84
General Purpose I/O
R7
I/O
X1VDD
—
ANT1_DIO104/
GPIO85
General Purpose I/O
T1
I/O
X1VDD
—
ANT1_DIO105/
GPIO86
General Purpose I/O
T3
I/O
X1VDD
—
ANT1_DIO106/
GPIO87/
IRQ10
General Purpose I/O
T5
I/O
X1VDD
—
ANT1_DIO107/
GPIO88/
IRQ11
General Purpose I/O
T6
I/O
X1VDD
—
ANT2_RX_CLK/
GPIO91
General Purpose I/O
J3
I/O
X2VDD
—
ANT2_DIO104/
TDM1_RCK/
GPIO92
General Purpose I/O
K4
I/O
X2VDD
—
ANT1_RX_CLK/
TSEC_1588_TRIG_IN2/
GPIO95
General Purpose I/O
P2
I/O
X1VDD
—
GPO
ANT4_TX_FRAME/
GPO06
General Purpose Output
Y3
O
X1VDD
—
IFC_ADDR16/
GPO08
General Purpose Output
H26
O
BVDD
—
IFC_ADDR17/
GPO09
General Purpose Output
H25
O
BVDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
37
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
IFC_ADDR18/
GPO10
General Purpose Output
H24
O
BVDD
—
IFC_ADDR19/
GPO11
General Purpose Output
H22
O
BVDD
—
IFC_ADDR20/
GPO12
General Purpose Output
H21
O
BVDD
—
IFC_ADDR21/
GPO13
General Purpose Output
J28
O
BVDD
—
IFC_ADDR22/
GPO14
General Purpose Output
J27
O
BVDD
—
IFC_ADDR23/
GPO15
General Purpose Output
J25
O
BVDD
—
IFC_ADDR24/
GPO16
General Purpose Output
J24
O
BVDD
—
IFC_ADDR25/
GPO17
General Purpose Output
J23
O
BVDD
—
IFC_ADDR26/
GPO18
General Purpose Output
J22
O
BVDD
—
ANT1_TXNRX/
TSEC_1588_PULSE_OUT2/
GPO19
General Purpose Output
P3
O
X1VDD
—
ANT1_TX_FRAME/
GPO20
General Purpose Output
R4
O
X1VDD
—
UART_RTS_B00/
PPS_LED/
GPO43
General Purpose Output
AB26
O
OVDD
—
UART_RTS_B01/
SYS_DMA_DONE/
GPO45/
ANT4_AGC
General Purpose Output
Y27
O
OVDD
—
IFC_CLE/
GPO48
General Purpose Output
L25
O
BVDD
—
IFC_OE_B/
GPO49
General Purpose Output
K23
O
BVDD
—
IFC_RB_B/
GPO50
General Purpose Output
K25
O
BVDD
—
IFC_WE_B/
GPO52
General Purpose Output
L26
O
BVDD
—
IFC_AVD/
GPO54
General Purpose Output
L28
O
BVDD
—
IFC_CS_B00/
GPO55
General Purpose Output
K21
O
BVDD
—
UART_SOUT01/
GPO56
General Purpose Output
W23
O
OVDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
38
Freescale Semiconductor
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
ANT1_AGC/
GPO58
General Purpose Output
R3
O
X1VDD
—
IFC_CS_B01/
GPO64
General Purpose Output
K28
O
BVDD
—
IFC_CS_B02/
GPO65
General Purpose Output
L24
O
BVDD
—
IFC_WP_B/
GPO66
General Purpose Output
K26
O
BVDD
—
IFC_BCTL/
GPO67
General Purpose Output
K22
O
BVDD
—
IFC_CLK00/
GPO68
General Purpose Output
K27
O
BVDD
—
USB_STP/
IRQ_OUT_B/
GPO73
General Purpose Output
R25
O
CVDD
—
SPI1_CS1_B/
UART_SOUT03/
GPO74
General Purpose Output
M24
O
CVDD
—
SPI1_CS2_B/
CKSTP0_OUT_B/
GPO75
General Purpose Output
M25
O
CVDD
—
SPI1_CS3_B/
CKSTP1_OUT_B/
GPO76
General Purpose Output
M23
O
CVDD
—
ANT2_AGC/
GPO89
General Purpose Output
G1
O
X2VDD
—
ANT2_TX_CLK/
GPO90
General Purpose Output
H5
O
X2VDD
—
SPI2_CS2_B/
GPO93
General Purpose Output
A8
O
X2VDD
—
SPI2_CS3_B/
GPO94
General Purpose Output
D6
O
X2VDD
—
Power-On-Reset Configuration
cfg_dsp_pll[0]/IFC_AD00
CCB Clock PLL Ratios
A27
I
BVDD
2
cfg_dsp_pll[1]/IFC_AD01
CCB Clock PLL Ratios
B28
I
BVDD
2
cfg_dsp_pll[2]/IFC_AD02
CCB Clock PLL Ratios
C28
I
BVDD
2
cfg_core0_pll[0]/IFC_AD03
e500 Core 0 PLL Ratios
D26
I
BVDD
2
cfg_core0_pll[1]/IFC_AD04
e500 Core 0 PLL Ratios
D27
I
BVDD
2
cfg_core0_pll[2]/IFC_AD05
e500 Core 0 PLL Ratios
D28
I
BVDD
2
cfg_core1_pll[0]/IFC_CLE/
GPO48
e500 Core 1 PLL Ratios
L25
I
BVDD
2
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
39
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
cfg_core1_pll[1]/IFC_BCTL/
GPO67
e500 Core 1 PLL Ratios
K22
I
BVDD
2
cfg_core1_pll[2]/IFC_WP_B/
GPO66
e500 Core 1 PLL Ratios
K26
I
BVDD
2
cfg_d1_ddr_pll[0]/IFC_AD07
DDR Complex Clock PLL Ratios
E26
I
BVDD
2
cfg_d1_ddr_pll[1]/
IFC_ADDR22/GPO14
DDR Complex Clock PLL Ratios
J27
I
BVDD
2
cfg_core0_speed/IFC_AD06
Core 0 Speed
F25
I
BVDD
2
cfg_core1_speed/EC_MDIO
Core 1 Speed
Y24
I
LVDD
2
cfg_dsp_pll[0]/EC_MDC
DSP Subsystem PLL Configurations
AA22
I
LVDD
2
cfg_dsp_pll[1]/IFC_ADDR16/
GPO08
DSP Subsystem PLL Configurations
H26
I
BVDD
2
cfg_dsp_pll[2]/IFC_ADDR17/
GPO09
DSP Subsystem PLL Configurations
H25
I
BVDD
2
cfg_dsp_pll[3]/IFC_ADDR18/
GPO10
DSP Subsystem PLL Configurations
H24
I
BVDD
2
cfg_dsp_pll[4]/
TSEC_1588_CLK_OUT/
CLK_OUT
DSP Subsystem PLL Configurations
AA23
I
LVDD
2
H22
I
BVDD
2
AA24
I
LVDD
2
cfg_boot_seq[0]/IFC_ADDR19/ Boot Sequencer Configuration
GPO11
cfg_boot_seq[1]/
TSEC_1588_PULSE_OUT1/
PPS_OUT
Boot Sequencer Configuration
cfg_plat_speed/IFC_ADDR20/
GPO12
Platform Speed
H21
I
BVDD
2
cfg_sys_speed/IFC_ADDR21/
GPO13
System Speed
J28
I
BVDD
2
cfg_ifc_pb[0]/IFC_ADDR23/
GPO15
IFC Pages Per Block
J25
I
BVDD
2
cfg_ifc_pb[1]/IFC_ADDR25/
GPO17
IFC Pages Per Block
J23
I
BVDD
2
cfg_ifc_pb[2]/IFC_ADDR26/
GPO18
IFC Pages Per Block
J22
I
BVDD
2
cfg_d1_ddr_speed[0]/
IFC_ADDR24/GPO16
DDR Speed
J24
I
BVDD
2
cfg_d1_ddr_speed[1]/
UART_SOUT00
DDR Speed
Y25
I
OVDD
2
cfg_cpu0_boot/IFC_OE_B/
GPO49
CPU Boot Configuration
K23
I
BVDD
2
cfg_d1_dram_type/IFC_AVD/
GPO54
DDR1 DRAM Type
L28
I
BVDD
2
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
40
Freescale Semiconductor
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
R3
I
X1VDD
2
cfg_d2_dram_type/
ANT1_AGC/
GPO58
DDR2 DRAM Type
cfg_ifc_ecc[0]/
UART_RTS_B00/
PPS_LED/GPO43
IFC ECC Enable Configuration
AB26
I
OVDD
2
cfg_ifc_ecc[1]/UART_SOUT01/
GPO56
IFC ECC Enable Configuration
W23
I
OVDD
2
cfg_host_agt/UART_RTS_B01/
SYS_DMA_DONE/
GPO45/
ANT4_AGC
Host/Agent Configuration
Y27
I
OVDD
2
cfg_ifc_adm_mode/IFC_WE_B/ IFC Address Shift Mode Configuration
GPO52
L26
I
BVDD
2
cfg_ifc_flash_mode/EE1
IFC Flash Mode Configuration
T25
I
OVDD
2
cfg_srds_io_ports[0]/READY/
ASLEEP/READY_P1
SerDes I/O Port Selection
U21
I
OVDD
2
cfg_srds_io_ports[1]/
ANT1_DIO000
SerDes I/O Port Selection
L7
I
X1VDD
2
cfg_srds_io_ports[2]/
ANT1_DIO010
SerDes I/O Port Selection
M1
I
X1VDD
2
cfg_srds_io_ports[3]/
ANT1_DIO011
SerDes I/O Port Selection
N3
I
X1VDD
2
cfg_srds_io_ports[4]/
ANT3_TX_FRAME
SerDes I/O Port Selection
E3
I
X2VDD
2
cfg_srds_io_ports[5]/
ANT4_TX_FRAME/
GPO06
SerDes I/O Port Selection
Y3
I
X1VDD
2
cfg_srds_io_ports[6]/
SPI2_MOSI
SerDes I/O Port Selection
E7
I
X2VDD
2
cfg_rom_loc[0]/ANT1_DIO006
Boot ROM Location
N6
I
X1VDD
2
cfg_rom_loc[1]/ANT1_DIO007
Boot ROM Location
M3
I
X1VDD
2
cfg_rom_loc[2]/ANT1_DIO008
Boot ROM Location
M2
I
X1VDD
2
cfg_rom_loc[3]/ANT2_AGC/
GPO89
Boot ROM Location
G1
I
X2VDD
2
cfg_srds_pll_timeout_en/
ANT1_DIO001
SerDes PLL Timeout Enable
N7
I
X1VDD
2, 4
cfg_d1_ddr_half_full_mode/
ANT1_DIO002
Power Architecture DDR Mode
P7
I
X1VDD
2
cfg_d2_ddr_half_full_mode/
ANT1_DIO003
DSP DDR Mode
N5
I
X1VDD
2
cfg_srds_refclk/ANT1_DIO009
SerDes Reference Clock Configuration
M5
I
X1VDD
2
Power Supply
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
41
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
AVDD_PLAT
Platform PLL Supply
G7
—
AVDD_PLAT
—
AVDD_CORE0
Core PLL Supply
N20
—
AVDD_CORE0
—
AVDD_CORE1
Core PLL Supply
P20
—
AVDD_CORE1
—
AVDD_D1_DDR
DDR PLL Supply
M20
—
AVDD_D1_DDR
—
AVDD_D2_DDR
DDR PLL Supply
AA1
—
AVDD_D2_DDR
—
AVDD_DSP
DSP PLL Supply
Y16
—
AVDD_DSP
—
AVDD_MAPLE
MAPLE PLL Supply
Y20
—
AVDD_MAPLE
—
SD1AVDD
SerDes PLL Supply
AC22
—
SD1AVDD
—
SD2AVDD
SerDes PLL Supply
AB19
—
SD2AVDD
—
POVDD1
Secure Fuse Programming Overdrive
N23
—
POVDD1
8
POVDD2
Central Fuse Programming Overdrive—DSP
P23
—
—
8
POVDD3
Central Fuse Programming Overdrive—DSP
AA16
—
—
8
FA_VDD
POSt VDD
Y7
—
—
7
VDDC
Core/Platform Supply
J14
—
VDDC
—
VDDC
Core/Platform Supply
K14
—
VDDC
—
VDDC
Core/Platform Supply
L14
—
VDDC
—
VDDC
Core/Platform Supply
M14
—
VDDC
—
VDDC
Core/Platform Supply
N14
—
VDDC
—
VDDC
Core/Platform Supply
P10
—
VDDC
—
VDDC
Core/Platform Supply
P12
—
VDDC
—
VDDC
Core/Platform Supply
P14
—
VDDC
—
VDDC
Core/Platform Supply
R10
—
VDDC
—
VDDC
Core/Platform Supply
R12
—
VDDC
—
VDDC
Core/Platform Supply
R14
—
VDDC
—
VDDC
Core/Platform Supply
T10
—
VDDC
—
VDDC
Core/Platform Supply
T12
—
VDDC
—
VDDC
Core/Platform Supply
T14
—
VDDC
—
VDDC
Core/Platform Supply
U10
—
VDDC
—
VDDC
Core/Platform Supply
U12
—
VDDC
—
VDDC
Core/Platform Supply
U14
—
VDDC
—
VDDC
Core/Platform Supply
V10
—
VDDC
—
VDDC
Core/Platform Supply
V12
—
VDDC
—
VDDC
Core/Platform Supply
V14
—
VDDC
—
VDDC
Core/Platform Supply
W10
—
VDDC
—
VDDC
Core/Platform Supply
W12
—
VDDC
—
VDDC
Core/Platform Supply
W14
—
VDDC
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
42
Freescale Semiconductor
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
VDDC
Core/Platform Supply
Y10
—
VDDC
—
VDDC
Core/Platform Supply
Y14
—
VDDC
—
VDDC
Core/Platform Supply
J16
—
VDDC
—
VDDC
Core/Platform Supply
J18
—
VDDC
—
VDDC
Core/Platform Supply
K16
—
VDDC
—
VDDC
Core/Platform Supply
K18
—
VDDC
—
VDDC
Core/Platform Supply
L16
—
VDDC
—
VDDC
Core/Platform Supply
L18
—
VDDC
—
VDDC
Core/Platform Supply
M16
—
VDDC
—
VDDC
Core/Platform Supply
M18
—
VDDC
—
VDDC
Core/Platform Supply
N16
—
VDDC
—
VDDC
Core/Platform Supply
N18
—
VDDC
—
VDDC
Core/Platform Supply
P16
—
VDDC
—
VDDC
Core/Platform Supply
P18
—
VDDC
—
VDDC
Core/Platform Supply
R16
—
VDDC
—
VDDC
Core/Platform Supply
R18
—
VDDC
—
VDDC
Core/Platform Supply
T16
—
VDDC
—
VDDC
Core/Platform Supply
T18
—
VDDC
—
VDDC
Core/Platform Supply
U16
—
VDDC
—
VDDC
Core/Platform Supply
U18
—
VDDC
—
VDDC
Core/Platform Supply
V16
—
VDDC
—
VDDC
Core/Platform Supply
V18
—
VDDC
—
VDDC
Core/Platform Supply
W16
—
VDDC
—
VDDC
Core/Platform Supply
W18
—
VDDC
—
VDDC
Core/Platform Supply
Y18
—
VDDC
—
VDD
MAPLE Supply
J10
—
VDD
—
VDD
MAPLE Supply
J12
—
VDD
—
VDD
MAPLE Supply
K10
—
VDD
—
VDD
MAPLE Supply
K12
—
VDD
—
VDD
MAPLE Supply
L10
—
VDD
—
VDD
MAPLE Supply
L12
—
VDD
—
VDD
MAPLE Supply
M10
—
VDD
—
VDD
MAPLE Supply
M12
—
VDD
—
VDD
MAPLE Supply
N10
—
VDD
—
VDD
MAPLE Supply
N12
—
VDD
—
G1VDD
DDR Supply
B13
—
G1VDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
43
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
G1VDD
DDR Supply
E11
—
G1VDD
—
G1VDD
DDR Supply
H9
—
G1VDD
—
G1VDD
DDR Supply
H10
—
G1VDD
—
G1VDD
DDR Supply
H11
—
G1VDD
—
G1VDD
DDR Supply
H12
—
G1VDD
—
G1VDD
DDR Supply
H13
—
G1VDD
—
G1VDD
DDR Supply
H14
—
G1VDD
—
G1VDD
DDR Supply
H15
—
G1VDD
—
G1VDD
DDR Supply
H16
—
G1VDD
—
G1VDD
DDR Supply
H17
—
G1VDD
—
G1VDD
DDR Supply
H18
—
G1VDD
—
G1VDD
DDR Supply
H19
—
G1VDD
—
G1VDD
DDR Supply
H20
—
G1VDD
—
G1VDD
DDR Supply
B18
—
G1VDD
—
G1VDD
DDR Supply
B23
—
G1VDD
—
G1VDD
DDR Supply
D20
—
G1VDD
—
G1VDD
DDR Supply
E15
—
G1VDD
—
G2VDD
DDR Supply
AC3
—
G2VDD
—
G2VDD
DDR Supply
AC10
—
G2VDD
—
G2VDD
DDR Supply
AA8
—
G2VDD
—
G2VDD
DDR Supply
AA9
—
G2VDD
—
G2VDD
DDR Supply
AA10
—
G2VDD
—
G2VDD
DDR Supply
AA11
—
G2VDD
—
G2VDD
DDR Supply
AA12
—
G2VDD
—
G2VDD
DDR Supply
AA13
—
G2VDD
—
G2VDD
DDR Supply
AA14
—
G2VDD
—
G2VDD
DDR Supply
AA15
—
G2VDD
—
G2VDD
DDR Supply
AD6
—
G2VDD
—
G2VDD
DDR Supply
AD13
—
G2VDD
—
G2VDD
DDR Supply
AF2
—
G2VDD
—
G2VDD
DDR Supply
AG4
—
G2VDD
—
G2VDD
DDR Supply
AG9
—
G2VDD
—
G2VDD
DDR Supply
AG12
—
G2VDD
—
G2VDD
DDR Supply
AC15
—
G2VDD
—
LVDD
Ethernet Supply
Y23
—
LVDD
—
LVDD
Ethernet Supply
AA25
—
LVDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
44
Freescale Semiconductor
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
BVDD
IFC, eSDHC, USIM Supply
B26
—
BVDD
—
BVDD
IFC, eSDHC, USIM Supply
E24
—
BVDD
—
BVDD
IFC, eSDHC, USIM Supply
F26
—
BVDD
—
BVDD
IFC, eSDHC, USIM Supply
G24
—
BVDD
—
BVDD
IFC, eSDHC, USIM Supply
J20
—
BVDD
—
BVDD
IFC, eSDHC, USIM Supply
J26
—
BVDD
—
BVDD
IFC, eSDHC, USIM Supply
K20
—
BVDD
—
BVDD
IFC, eSDHC, USIM Supply
K24
—
BVDD
—
CVDD
USB, eSPI, DUART, I2C, USIM Supply
N22
—
CVDD
—
CVDD
USB, eSPI, DUART, I2C, USIM Supply
P22
—
CVDD
—
CVDD
USB, eSPI, DUART, I2C, USIM Supply
M26
—
CVDD
—
CVDD
USB, eSPI, DUART, I2C, USIM Supply
R21
—
CVDD
—
CVDD
USB, eSPI, DUART, I2C, USIM Supply
R26
—
CVDD
—
OVDD
DUART, System, I2C, JTAG Supply
U20
—
OVDD
—
OVDD
DUART, System, I2C, JTAG Supply
V20
—
OVDD
—
OVDD
DUART, System, I2C, JTAG Supply
V21
—
OVDD
—
OVDD
DUART, System, I2C, JTAG Supply
V26
—
OVDD
—
OVDD
DUART, System, I2C, JTAG Supply
U23
—
OVDD
—
OVDD
DUART, System, I2C, JTAG Supply
AD27
—
OVDD
—
X1VDD
RF Supply
N2
—
X1VDD
—
X1VDD
RF Supply
N4
—
X1VDD
—
X1VDD
RF Supply
N8
—
X1VDD
—
X1VDD
RF Supply
U4
—
X1VDD
—
X1VDD
RF Supply
W2
—
X1VDD
—
X1VDD
RF Supply
W6
—
X1VDD
—
X1VDD
RF Supply
P8
—
X1VDD
—
X1VDD
RF Supply
R6
—
X1VDD
—
X1VDD
RF Supply
R8
—
X1VDD
—
X1VDD
RF Supply
T8
—
X1VDD
—
X1VDD
RF Supply
U8
—
X1VDD
—
X1VDD
RF Supply
V8
—
X1VDD
—
X1VDD
RF Supply
W8
—
X1VDD
—
X1VDD
RF Supply
Y8
—
X1VDD
—
X2VDD
eSPI2, USB, TDM1, TDM2, RF Parallel
Interface
B4
—
X2VDD
—
X2VDD
eSPI2, USB, TDM1, TDM2, RF Parallel
Interface
C6
—
X2VDD
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
45
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
X2VDD
eSPI2, USB, TDM1, TDM2, RF Parallel
Interface
G2
—
X2VDD
—
X2VDD
eSPI2, USB, TDM1, TDM2, RF Parallel
Interface
J4
—
X2VDD
—
X2VDD
eSPI2, USB, TDM1, TDM2, RF Parallel
Interface
J8
—
X2VDD
—
X2VDD
eSPI2, USB, TDM1, TDM2, RF Parallel
Interface
K6
—
X2VDD
—
X2VDD
eSPI2, USB, TDM1, TDM2, RF Parallel
Interface
K8
—
X2VDD
—
X2VDD
eSPI2, USB, TDM1, TDM2, RF Parallel
Interface
L8
—
X2VDD
—
X2VDD
eSPI2, USB, TDM1, TDM2, RF Parallel
Interface
M8
—
X2VDD
—
XCOREVDD
SerDes Core Logic Supply
AH19
—
XCOREVDD
—
XCOREVDD
SerDes Core Logic Supply
AH23
—
XCOREVDD
—
XCOREVDD
SerDes Core Logic Supply
AH27
—
XCOREVDD
—
XCOREVDD
SerDes Core Logic Supply
AG25
—
XCOREVDD
—
XCOREVDD
SerDes Core Logic Supply
AF16
—
XCOREVDD
—
XCOREVDD
SerDes Core Logic Supply
AG17
—
XCOREVDD
—
XCOREVDD
SerDes Core Logic Supply
AG21
—
XCOREVDD
—
XPADVDD
SerDes Transceiver Supply
AA19
—
XPADVDD
—
XPADVDD
SerDes Transceiver Supply
AA20
—
XPADVDD
—
XPADVDD
SerDes Transceiver Supply
AF18
—
XPADVDD
—
XPADVDD
SerDes Transceiver Supply
AE20
—
XPADVDD
—
XPADVDD
SerDes Transceiver Supply
AF22
—
XPADVDD
—
XPADVDD
SerDes Transceiver Supply
AF26
—
XPADVDD
—
XPADVDD
SerDes Transceiver Supply
AE24
—
XPADVDD
—
Ground
VSS
Platform and Core Ground
A9
—
—
—
VSS
Platform and Core Ground
A26
—
—
—
VSS
Platform and Core Ground
B2
—
—
—
VSS
Platform and Core Ground
B8
—
—
—
VSS
Platform and Core Ground
B11
—
—
—
VSS
Platform and Core Ground
B15
—
—
—
VSS
Platform and Core Ground
B21
—
—
—
VSS
Platform and Core Ground
C27
—
—
—
VSS
Platform and Core Ground
D17
—
—
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
46
Freescale Semiconductor
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
VSS
Platform and Core Ground
D22
—
—
—
VSS
Platform and Core Ground
D24
—
—
—
VSS
Platform and Core Ground
E27
—
—
—
VSS
Platform and Core Ground
F18
—
—
—
VSS
Platform and Core Ground
F21
—
—
—
VSS
Platform and Core Ground
H23
—
—
—
VSS
Platform and Core Ground
H27
—
—
—
VSS
Platform and Core Ground
J15
—
—
—
VSS
Platform and Core Ground
J19
—
—
—
VSS
Platform and Core Ground
J21
—
—
—
VSS
Platform and Core Ground
K15
—
—
—
VSS
Platform and Core Ground
K17
—
—
—
VSS
Platform and Core Ground
K19
—
—
—
VSS
Platform and Core Ground
L15
—
—
—
VSS
Platform and Core Ground
L17
—
—
—
VSS
Platform and Core Ground
L19
—
—
—
VSS
Platform and Core Ground
L27
—
—
—
VSS
Platform and Core Ground
L21
—
—
—
VSS
Platform and Core Ground
L23
—
—
—
VSS
Platform and Core Ground
M15
—
—
—
VSS
Platform and Core Ground
M17
—
—
—
VSS
Platform and Core Ground
M19
—
—
—
VSS
Platform and Core Ground
M21
—
—
—
VSS
Platform and Core Ground
N15
—
—
—
VSS
Platform and Core Ground
N17
—
—
—
VSS
Platform and Core Ground
N19
—
—
—
VSS
Platform and Core Ground
N21
—
—
—
VSS
Platform and Core Ground
N24
—
—
—
VSS
Platform and Core Ground
P27
—
—
—
VSS
Platform and Core Ground
P15
—
—
—
VSS
Platform and Core Ground
P17
—
—
—
VSS
Platform and Core Ground
P19
—
—
—
VSS
Platform and Core Ground
P21
—
—
—
VSS
Platform and Core Ground
R15
—
—
—
VSS
Platform and Core Ground
R17
—
—
—
VSS
Platform and Core Ground
R19
—
—
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
47
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
VSS
Platform and Core Ground
T15
—
—
—
VSS
Platform and Core Ground
T17
—
—
—
VSS
Platform and Core Ground
T19
—
—
—
VSS
Platform and Core Ground
T20
—
—
—
VSS
Platform and Core Ground
T24
—
—
—
VSS
Platform and Core Ground
U27
—
—
—
VSS
Platform and Core Ground
U15
—
—
—
VSS
Platform and Core Ground
U17
—
—
—
VSS
Platform and Core Ground
U19
—
—
—
VSS
Platform and Core Ground
V15
—
—
—
VSS
Platform and Core Ground
V17
—
—
—
VSS
Platform and Core Ground
V19
—
—
—
VSS
Platform and Core Ground
W15
—
—
—
VSS
Platform and Core Ground
W17
—
—
—
VSS
Platform and Core Ground
W19
—
—
—
VSS
Platform and Core Ground
W20
—
—
—
VSS
Platform and Core Ground
W21
—
—
—
VSS
Platform and Core Ground
W24
—
—
—
VSS
Platform and Core Ground
W28
—
—
—
VSS
Platform and Core Ground
Y21
—
—
—
VSS
Platform and Core Ground
Y15
—
—
—
VSS
Platform and Core Ground
Y17
—
—
—
VSS
Platform and Core Ground
Y19
—
—
—
VSS
Platform and Core Ground
Y26
—
—
—
VSS
Platform and Core Ground
AB28
—
—
—
VSS
Platform and Core Ground
AA21
—
—
—
VSS
Platform and Core Ground
AD16
—
—
—
VSS
Platform and Core Ground
AE27
—
—
—
VSS
Platform and Core Ground
AF28
—
—
—
VSS
Platform and Core Ground
AG16
—
—
—
VSS
Platform and Core Ground
AD1
—
—
—
VSS
Platform and Core Ground
AE4
—
—
—
VSS
Platform and Core Ground
AE8
—
—
—
VSS
Platform and Core Ground
AE11
—
—
—
VSS
Platform and Core Ground
AF14
—
—
—
VSS
Platform and Core Ground
AG7
—
—
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
48
Freescale Semiconductor
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
VSS
Platform and Core Ground
C7
—
—
—
VSS
Platform and Core Ground
D2
—
—
—
VSS
Platform and Core Ground
D7
—
—
—
VSS
Platform and Core Ground
D9
—
—
—
VSS
Platform and Core Ground
E4
—
—
—
VSS
Platform and Core Ground
E8
—
—
—
VSS
Platform and Core Ground
F6
—
—
—
VSS
Platform and Core Ground
F7
—
—
—
VSS
Platform and Core Ground
F8
—
—
—
VSS
Platform and Core Ground
F13
—
—
—
VSS
Platform and Core Ground
G6
—
—
—
VSS
Platform and Core Ground
G8
—
—
—
VSS
Platform and Core Ground
H4
—
—
—
VSS
Platform and Core Ground
H6
—
—
—
VSS
Platform and Core Ground
H7
—
—
—
VSS
Platform and Core Ground
H8
—
—
—
VSS
Platform and Core Ground
J9
—
—
—
VSS
Platform and Core Ground
J11
—
—
—
VSS
Platform and Core Ground
K2
—
—
—
VSS
Platform and Core Ground
K9
—
—
—
VSS
Platform and Core Ground
K11
—
—
—
VSS
Platform and Core Ground
K13
—
—
—
VSS
Platform and Core Ground
L6
—
—
—
VSS
Platform and Core Ground
L9
—
—
—
VSS
Platform and Core Ground
L11
—
—
—
VSS
Platform and Core Ground
L13
—
—
—
VSS
Platform and Core Ground
M11
—
—
—
VSS
Platform and Core Ground
M13
—
—
—
VSS
Platform and Core Ground
M4
—
—
—
VSS
Platform and Core Ground
M9
—
—
—
VSS
Platform and Core Ground
N9
—
—
—
VSS
Platform and Core Ground
N11
—
—
—
VSS
Platform and Core Ground
N13
—
—
—
VSS
Platform and Core Ground
P9
—
—
—
VSS
Platform and Core Ground
P11
—
—
—
VSS
Platform and Core Ground
P13
—
—
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
49
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
VSS
Platform and Core Ground
R9
—
—
—
VSS
Platform and Core Ground
R11
—
—
—
VSS
Platform and Core Ground
R13
—
—
—
VSS
Platform and Core Ground
P6
—
—
—
VSS
Platform and Core Ground
T2
—
—
—
VSS
Platform and Core Ground
T4
—
—
—
VSS
Platform and Core Ground
T9
—
—
—
VSS
Platform and Core Ground
T11
—
—
—
VSS
Platform and Core Ground
T13
—
—
—
VSS
Platform and Core Ground
AB1
—
—
—
VSS
Platform and Core Ground
AB5
—
—
—
VSS
Platform and Core Ground
AB7
—
—
—
VSS
Platform and Core Ground
AA2
—
—
—
VSS
Platform and Core Ground
Y1
—
—
—
VSS
Platform and Core Ground
Y4
—
—
—
VSS
Platform and Core Ground
Y9
—
—
—
VSS
Platform and Core Ground
Y11
—
—
—
VSS
Platform and Core Ground
Y13
—
—
—
VSS
Platform and Core Ground
W9
—
—
—
VSS
Platform and Core Ground
W11
—
—
—
VSS
Platform and Core Ground
W13
—
—
—
VSS
Platform and Core Ground
V9
—
—
—
VSS
Platform and Core Ground
V11
—
—
—
VSS
Platform and Core Ground
V13
—
—
—
VSS
Platform and Core Ground
V6
—
—
—
VSS
Platform and Core Ground
U9
—
—
—
VSS
Platform and Core Ground
U11
—
—
—
VSS
Platform and Core Ground
U13
—
—
—
XCOREVSS
SerDes Core Logic Ground
AH17
—
—
—
XCOREVSS
SerDes Core Logic Ground
AH21
—
—
—
XCOREVSS
SerDes Core Logic Ground
AH25
—
—
—
XCOREVSS
SerDes Core Logic Ground
AG19
—
—
—
XCOREVSS
SerDes Core Logic Ground
AG23
—
—
—
XCOREVSS
SerDes Core Logic Ground
AG27
—
—
—
XCOREVSS
SerDes Core Logic Ground
AF27
—
—
—
XCOREVSS
SerDes Core Logic Ground
AD17
—
—
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
50
Freescale Semiconductor
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
XCOREVSS
SerDes Core Logic Ground
AD20
—
—
—
XCOREVSS
SerDes Core Logic Ground
AD24
—
—
—
XCOREVSS
SerDes Core Logic Ground
AD25
—
—
—
XCOREVSS
SerDes Core Logic Ground
AE16
—
—
—
XCOREVSS
SerDes Core Logic Ground
AA17
—
—
—
XCOREVSS
SerDes Core Logic Ground
AB17
—
—
—
XCOREVSS
SerDes Core Logic Ground
AC17
—
—
—
XCOREVSS
SerDes Core Logic Ground
AB21
—
—
—
XCOREVSS
SerDes Core Logic Ground
AB22
—
—
—
XCOREVSS
SerDes Core Logic Ground
AC23
—
—
—
XPADVSS
SerDes Transceiver Ground
AF20
—
—
—
XPADVSS
SerDes Transceiver Ground
AC18
—
—
—
XPADVSS
SerDes Transceiver Ground
AE18
—
—
—
XPADVSS
SerDes Transceiver Ground
AE22
—
—
—
XPADVSS
SerDes Transceiver Ground
AE26
—
—
—
XPADVSS
SerDes Transceiver Ground
AF24
—
—
—
XPADVSS
SerDes Transceiver Ground
AD19
—
—
—
XPADVSS
SerDes Transceiver Ground
AD21
—
—
—
XPADVSS
SerDes Transceiver Ground
AD23
—
—
—
SD2AGND
SerDes PLL Ground
AA18
—
—
—
SD1AGND
SerDes PLL Ground
AC20
—
—
—
No Connect
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
51
Pin Assignments
Table 1. BSC9132 Pinout Listing (continued)
Signal
Signal Description
Pin
Number
Pin
Type
Power
Supply
Note
NC
Address Parity Error
E19
—
—
—
NC
Address Parity Error
AH4
—
—
—
These are test signals for factory use only and must be pulled up (with 100 Ω–1 kΩ) to OVDD for normal operation.
This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the reset
state. This pull-up is designed such that it can be overpowered by an external 4.7-k pull-down resistor. However, if the signal is
intended to be high after reset, and if there is any device on the net which might pull down the value of the net at reset, then a pull
up or active driver is needed.
3
These pins have weak internal pull-up P-FETs that are always enabled.
4
This pin must NOT be pulled down during power-on reset.
5
This pin is an open drain signal.
6
This pin should be pulled down with 200Ω ± 1% resistor when used in autocalibration mode.
7 This pin should be pulled down to VSS with 10 kΩ.
8 This pin is used for fuse programming. Should be tied to VSS for normal operation (fuse read). See section Section 2.2, “Power
Sequencing,” for more details.
9 This pin may be connected to a temperature diode monitoring device such as the Analog Devices, ADT7461A™. If a temperature
diode monitoring device will not be connected, these pins may be connected to test point or left as a no connect.
10 Pin should be pulled high or low depending on the JTAG topology selected. Refer to Section 3.11, “JTAG Configuration Signals.”
11 This pin should be tied to GND/VSS when MAPLE is powered down; otherwise it should be tied to OVDD.
12 This pin is an open-drain signal if the IIC2 pin is selected.
13 It has a weak internal pull-up P-FET which is enabled only when the processor is in the reset state. This pull-up is designed such
that it can be overpowered by an external 4.7-k pull-down resistor. However, if the signal is intended to be high after reset, and if there
is any device on the net which might pull down the value of the net at reset, then a pull up or active driver is needed.
14 MDIC00 is grounded through an 36.5 O precision 1% resistor and MDIC01 is connected to GVDD through an 36.5 O precision 1%
resistor. These pins are used for automatic calibration of the DDR3/DDR3L IOs.
15 This pin should be pulled up to power rail with 10 kΩ.
16 Do not use this pin as CD pin.
17 This pin should be pulled down to GND with 10 kΩ.
18 This pin is a reset configuration pin without default value.
1
2
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
52
Freescale Semiconductor
Electrical Characteristics
2
Electrical Characteristics
This section provides the AC and DC electrical specifications. This device is currently targeted to these specifications. Some
of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O
buffer design specifications.
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1
Absolute Maximum Ratings
This table provides the absolute maximum ratings.
Table 2. Absolute Maximum Ratings1
Characteristic
Symbol
Max Value
Unit
Note
Platform supply voltage
VDDC
–0.3 to 1.05
V
—
MAPLE-B2P supply voltage
VDD
–0.3 to 1.05
V
—
AVDD_CORE[0–1]
AVDD_D[1–2]_DDR
AVDD_PLAT
AVDD_DSP
AVDD_MAPLE
SD[1–2]AVDD
–0.3 to 1.05
V
2
POVDD1
POVDD2
POVDD3
–0.3 to 1.65
V
—
GVDD[1–2]
–0.3 to 1.65
–0.3 to 1.45
V
—
Three-speed Ethernet, Ethernet management (eTSEC) and 1588
LVDD
–0.3 to 3.63
–0.3 to 2.75
V
—
IFC, eSDHC, USIM
BVDD
–0.3 to 3.63
–0.3 to 2.75
–0.3 to 1.98
V
3
DUART1, SYSCLK, system control and power management, I2C1,
clocking, I/O voltage select, and JTAG I/O voltage
OVDD
–0.3 to 3.63
V
—
USB, eSPI1, DUART2, I2C2, USIM
CVDD
–0.3 to 3.63
–0.3 to 1.98
V
3, 4
RF parallel interface
X1VDD
–0.3 to 3.63
–0.3 to 1.98
V
—
eSPI2, USB, TDM1, TDM2, RF parallel interface
X2VDD
–0.3 to 3.63
–0.3 to 1.98
V
—
SerDes pad voltage
XPADVDD
–0.3 to 1.65
V
—
SerDes core voltage
XCOREVDD
–0.3 to 1.05
V
—
PLL supply voltage
Fuse programming supply
DDR3/DDR3L DRAM I/O voltage
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
53
Electrical Characteristics
Table 2. Absolute Maximum Ratings1 (continued)
Characteristic
Input voltage
Symbol
Max Value
Unit
Note
MVIN
–0.3 to (GVDD + 0.3)
V
5, 10
MVREF
–0.3 to (GVDD/2 +
0.3)
V
10
Ethernet signals
LVIN
–0.3 to (LVDD + 0.3)
V
6, 10
IFC, eSDHC, USIM signals
BVIN
–0.3 to (BVDD + 0.3)
—
7, 10
DUART1, SYSCLK, system control and power
management, I2C1, clocking, I/O voltage select, and
JTAG I/O voltage
OVIN
–0.3 to (OVDD + 0.3)
V
8, 10
USB, eSPI1, DUART2, I2C2, USIM
CVIN
–0.3 to (CVDD + 0.3)
V
4, 10
RF parallel interface
X1VIN
–0.3 to (X1VDD + 0.3)
V
9, 10
eSPI2, USB, TDM1, TDM2, RF parallel interface
X2VIN
–0.3 to (X2VDD + 0.3)
V
9, 10
TSTG
–55 to 150
°C
—
DDR3/DDR3L DRAM signals
DDR3/DDR3L DRAM reference
Storage temperature range
Note:
1 Functional operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and functional
operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent
damage to the device.
2 AV
DD is measured at the input to the filter and not at the pin of the device.
3 USIM pins are multiplexed with the pins of other interfaces. Check Table 3 for which power supply is used (BV
DD or a CVDD)
for each particular USIM pin.
4 Caution: CV must not exceed CV
IN
DD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on
reset and power-down sequences.
5 Caution: MV must not exceed GV
IN
DD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on
reset and power-down sequences.
6 Caution: LV must not exceed LV
IN
DD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on
reset and power-down sequences.
7 Caution: BV must not exceed BV
IN
DD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on
reset and power-down sequences.
8 Caution: OV must not exceed OV
IN
DD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on
reset and power-down sequences.
9 Caution: X[1-2]V must not exceed X[1-2]V
IN
DD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
10
(C,X,B,G,L,O,R)VDD and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 7.
2.1.2
Recommended Operating Conditions
This table provides the recommended operating conditions for this device. Note that the values in this table are the
recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed.
Table 3. Recommended Operating Conditions
Characteristic
Symbol
Recommended Value Unit
Note
Platform supply voltage
VDDC
1 + 50 mV / – 30mV
V
1
MAPLE-B2P supply voltage
VDD
1 + 50 mV / – 30mV
V
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
54
Freescale Semiconductor
Electrical Characteristics
Table 3. Recommended Operating Conditions (continued)
Characteristic
Symbol
Recommended Value Unit
Note
PLL supply voltage
AVDD_CORE[0–1]
AVDD_D[1–2]_DDR
AVDD_PLAT
AVDD_DSP
AVDD_MAPLE
SD[1–2]AVDD
1 + 50 mV / – 30mV
V
1
Fuse supply voltage
POVDD1
1.5 V ± 75 mV
V
1
DDR3 DRAM I/O voltage
G[1–2]VDD
1.5 V ± 75 mV
—
—
DDR3L DRAM I/O voltage
G[1–2]VDD
1.35 V +100mV/
–67mV
—
—
Three-speed Ethernet, Ethernet management (eTSEC) and 1588
LVDD
3.3 V ± 165 mV
2.5 V ± 125 mV
V
—
DUART1, SYSCLK, system control and power management, I2C1,
clocking, I/O voltage select, and JTAG I/O voltage
OVDD
3.3 V ± 165 mV
V
—
IFC, eSDHC, USIM
BVDD
3.3 V ± 165 mV
2.5 V ± 125 mV
1.8 V ± 90 mV
V
2
USB, eSPI1, DUART2, I2C2, USIM
CVDD
3.3 V ± 165 mV
1.8 V ± 90 mV
V
2
RF parallel interface
X1VDD
3.3 V ± 165 mV
1.8 V ± 90 mV
V
—
eSPI2, USB, TDM1, TDM2, RF parallel interface
X2VDD
3.3 V ± 165 mV
1.8 V ± 90 mV
V
—
SerDes pad voltage
XPADVDD
1.5 V ± 75 mV
V
—
SerDes core voltage
XCOREVDD
1.0 V ± 50 mV
V
—
MVIN
GND to GVDD
V
—
MVREF
GND to GVDD/2
V
—
Ethernet, USB
LVIN
GND to LVDD
V
—
IFC, eSDHC signals
BVIN
GND to BVDD
V
—
DUART1, SYSCLK, system control and power
management, eSPI, I2C1, USIM, clocking, I/O
voltage select, and JTAG I/O voltage
OVIN
GND to OVDD
V
—
USB, eSPI, eSDHC, DUART2, I2C2, USIM
CVIN
GND to CVDD
V
—
RF parallel interface
X1VIN
GND to X1VDD
V
—
eSPI2, USB, TDM1, TDM2, RF parallel interface
X2VIN
GND to X2VDD
V
—
CINMAX
10
pF
3
Standard
TA/TJ
TA = 0 (min) to
TJ = 105 (max)
°C
—
Extended
TA/TJ
TA = –40 (min) to
TJ = 105 (max)
°C
—
Secure boot fuse programming
TA/TJ
TA = 0 (min) to
TJ = 70 (max)
°C
1
Input voltage
DDR3/DDR3L DRAM
DDR3/DDR3L DRAM reference
Maximum input capacitance
Operating
Temperature
range
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
55
Electrical Characteristics
Table 3. Recommended Operating Conditions (continued)
Characteristic
Symbol
Recommended Value Unit
Note
Note:
1
Caution: POVDD1 must be supplied 1.5 V and the device must operate in the specified fuse programming temperature range
only during secure boot fuse programming. For all other operating conditions, POVDD1 must be tied to GND, subject to the
power sequencing constraints shown in Section 2.2, “Power Sequencing.”
2
USIM pins are multiplexed with the pins of other interfaces. Check Table 3 for which power supply is used (BVDD or a CVDD)
for each particular USIM pin.
3
Unless otherwise stated in an interface’s DC specifications, the maximum allowed input capacitance in this table is a general
recommendation for signals.
This figure shows the undershoot and overshoot voltages at the interfaces.
B/G/L/O/XVVDD + 20%
B/G/L/O/XVVDD + 5%
B/G/L/O/XVVDD
VIH
GND
GND – 0.3 V
VIL
GND – 0.7 V
Not to Exceed 10%
of tCLOCK1
Note:
1. tCLOCK refers to the clock period associated with the respective interface:
For I2C and JTAG, tCLOCK references SYSCLK.
For DDR, tCLOCK references MCLK.
For eTSEC, tCLOCK references TSECn_GTX_CLK125.
For IFC, tCLOCK references IFC_CLK.
Figure 7. Overshoot/Undershoot Voltage for BVDD/GVDD/LVDD/OVDD/X1VDD/X2VDD
The core voltage must always be provided at nominal 1 V (see Table 3 for actual recommended core voltage). Voltage to the
processor interface I/Os are provided through separate sets of supply pins and must be provided at the voltages shown in Table 3.
The input voltage threshold scales with respect to the associated I/O supply voltage. OVDD and LVDD based receivers are simple
CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR3 SDRAM interface uses a differential
receiver referenced the externally supplied MVREF signal (nominally set to GVDD/2). The DDR DQS receivers cannot be
operated in single-ended fashion. The complement signal must be properly driven and cannot be grounded.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
56
Freescale Semiconductor
Electrical Characteristics
2.1.3
Output Driver Characteristics
This table provides information on the characteristics of the output driver strengths. The values are preliminary estimates.
Table 4. Output Drive Capability
Driver Type
Output Impedance (Ω)
Supply Voltage
Note
47 ± 7
BVDD = 3.3/2.5/1.8 V
—
IFC, GPIO[0:7], eSDHC
DDR3 (programmable)
16
GVDD = 1.5 V DDR3
32 (half strength mode) GVDD = 1.35 V DDR3L
eTSEC, USB
2
DUART1, system control, I C1, USIM, JTAG
2
USB, eSPI1, DUART2, I C2, USIM
RF parallel interface
eSPI2, USB, TDM1, TDM2, RF parallel interface
1
47 ± 7
LVDD = 3.3/2.5 V
—
47 ± 7
OVDD = 3.3 V
2
47 ± 7
CVDD = 3.3/1.8 V
2
LVCMOS
X1VDD = 3.3/1.8 V
—
—
X2VDD = 3.3/1.8 V
—
Note:
1 The drive strength of the DDR3 interface in half-strength mode is at T = 125°C and at GV
j
DD (min).
2 USIM pins are multiplexed with the pins of other interfaces. Check Table 3 for which power supply is used (BV
DD or a CVDD)
for each particular USIM pin.
2.2
Power Sequencing
The device requires its power rails to be applied in a specific sequence in order to ensure proper device operation. These
requirements are as follows for power up:
1.
2.
3.
VDD, VDDC, AVDD (all PLL supplies), XCOREVDD
LVDD, BVDD, CVDD, OVDD, X1VDD, X2VDD, G1VDD, G2VDD, XPADVDD
For secure boot fuse programming: After deassertion of HRESET_B, drive POVDD1 = 1.5 V after a required minimum
delay per Table 5. After fuse programming is completed, it is required to return POVDD1 = GND before the system is
power cycled (HRESET_B assertion) or powered down (VDDC ramp down) per the required timing specified in
Table 5. See Section 3.14, “Security Fuse Processor,” for additional details.
WARNING
Only 100,000 POR cycles are permitted per lifetime of a device. Only one secure boot fuse
programming event is permitted per lifetime of a device.
No activity other than that required for secure boot fuse programming is permitted while
POVDD1 driven to any voltage above GND, including the reading of the fuse block. The
reading of the fuse block may only occur while POVDD1 = GND.
POVDD2 and POVDD3 are always tied to GND.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
57
Electrical Characteristics
This figure provides the POVDD1 timing diagram.
Fuse programming 1
POVDD1
10% POVDD1
10% POVDD1
90% VDD_PL
tPOVDD_VDD
VDDC
HRESET_B
tPOVDD_PROG
90% OVDD
90% OVDD
tPOVDD_RST
tPOVDD_DELAY
NOTE: POVDD must be stable at 1.5 V prior to initiating fuse programming.
Figure 8. POVDD1 Timing Diagram
This table provides information on the power-down and power-up sequence parameters for POVDD1.
Table 5. POVDD1 Timing 5
Driver Type
Min
Max
Unit
Note
tPOVDD_DELAY
1500
—
tSYSCLK
1
tPOVDD_PROG
0
—
μs
2
tPOVDD_VDD
0
—
μs
3
tPOVDD_RST
0
—
μs
4
Note:
1. Delay required from the deassertion of HRESET_B to driving POVDD1 ramp up. Delay measured from HRESET_B deassertion
at 90% OVDD to 10% POVDD1 ramp up.
2. Delay required from fuse programming finished to POVDD1 ramp down start. Fuse programming must complete while POVDD1
is stable at 1.5 V. No activity other than that required for secure boot fuse programming is permitted while POVDD1 driven to
any voltage above GND, including the reading of the fuse block. The reading of the fuse block may only occur while
POVDD1 = GND. After fuse programming is completed, it is required to return POVDD1 = GND.
3. Delay required from POVDD1 ramp down complete to VDDC ramp down start. POVDD1 must be grounded to minimum
10% POVDD1 before VDDC is at 90% VDDC.
4. Delay required from POVDD1 ramp down complete to HRESET_B assertion. POVDD1 must be grounded to minimum 10%
POVDD1 before HRESET_B assertion reaches 90% OVDD.
5. Only one secure boot fuse programming event is permitted per lifetime of a device.
All supplies must be at their stable values within 50 ms.
Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered
sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step
reach 10% of theirs.
In order to guarantee MCKE low during power-up, the above sequencing for GVDD is required. If there is no concern about any
of the DDR signals being in an indeterminate state during power-up, the sequencing for GVDD is not required.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
58
Freescale Semiconductor
Electrical Characteristics
2.3
Power-Down Requirements
The power-down cycle must complete such that power supply values are below 0.4 V before a new power-up cycle can be
started.
2.4
RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements. Table 6 provides the
RESET initialization AC timing specifications.
Table 6. RESET Initialization Timing Specifications
Parameter
Min
Max
Unit
Note
Required assertion time of HRESET_B
600
—
μs
1, 2, 5
Minimum assertion time of TRESET_B simultaneous to HRESET_B assertion
25
—
ns
3
Minimum assertion time for SRESET_B
3
—
tSYSCLK
4
PLL input setup time with stable SYSCLK before HRESET_B negation
25
—
μs
—
Input setup time for POR configurations (other than PLL configuration) with respect to negation
of HRESET_B
4
—
tSYSCLK
4
Input hold time for all POR configurations (including PLL configuration) with respect to
negation of HRESET_B
2
—
tSYSCLK
4
Maximum valid-to-high impedance time for actively driven POR configurations with respect to
negation of HRESET_B
—
8
tSYSCLK
4
Note:
1. There may be some extra current leakage when driving signals high during this time.
2. Reset assertion timing requirements for DDR3 DRAMs may differ.
3. TRST is an asynchronous level sensitive signal. For guidance on how this requirement can be met, refer to the JTAG signal
termination guidelines in Section 3.11.1, “Termination of Unused Signals.”
4. SYSCLK is the primary clock input.
5. Reset initialization should start only after all power supplies are stable.
This table provides the PLL lock times.
Table 7. PLL Lock Times
Parameter
PLL lock times
2.5
Min
Max
Unit
Note
—
100
μs
—
Power-on Ramp Rate
This section describes the AC electrical specifications for the power-on ramp rate requirements. Controlling the maximum
power-on ramp rate is required to avoid falsely triggering the ESD circuitry. Table 8 provides the power supply ramp rate
specifications.
Table 8. Power Supply Ramp Rate
Parameter
Min
Max
Unit
Required ramp rate
—
36000
V/s
Required ramp time
—
50
ms
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
59
Electrical Characteristics
Table 8. Power Supply Ramp Rate (continued)
Parameter
Min
Max
Unit
Note:
1. Ramp rate is specified as a linear ramp from 10 to 90% of the nominal voltage of the specific voltage supply.
2. All MCKE signals must remain low during the power up sequence.
2.6
Power Characteristics
This table shows the power dissipations of the VDDC and VDD supplies for various operating DSP and core complex bus clock
(CCB_clk) frequencies versus the core and DDR clock frequencies.
Table 9. Core Power Dissipation
PA/DSP
MAPLE
PA Core DSP Core
CCB
DDR
eTVPE
Power Mode Frequency Frequency Frequency
VDDC (V)
Frequency Frequency
(MHz)
(MHz)
(MHz)
(MHz)
(MHz)
Typical
1200
1200
600
1333
800
1
VDD (V)
Junction VDDC + VDD
Temp (°C) Power (W)
1
Thermal
65
8.9
1, 2
105
11.9
1, 3, 5
14.8
1, 4, 5
65
8.7
1, 2
105
11.3
1, 3, 5
13.9
1, 4, 5
Maximum
Typical
1000
1000
500
1333
800
1
1
Thermal
Note
Maximum
Note:
1. These values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and configurations.
The values do not include power dissipation for I/O supplies.
2. Typical power is a measured value while running a typical use case using the nominal process and recommended core, platform
voltages (VDDC), and MAPLE (VDD) at 65 °C junction temperature (see Table 3).
3. Thermal power is the power measured while running a 50% (Cores) and 40% (Platform) utilization case, using the worst case process
and recommended core, platform voltages (VDDC), and MAPLE (VDD) at maximum operating junction temperature (see Table 3).
4. Maximum power is measured while running a maximum power pattern using the worst case process, and recommended core, platform
voltages (VDDC), and MAPLE (VDD) at maximum operating junction temperature (see Table 3).
5. An estimated IO power while running a USE case using the nominal process and recommended voltages is 1.5 W (see Table 3).
Table 10. I/O Power
PS#
I/O
Primary pin name
Pin
width
Voltage domain
Recommended
value
Current
max
Typical
current (A)
Max
(A)
OVDD
37
General I/O supply
3.3V
—
0.178
0.266
BVDD
46
Local Bus and GPIO I/O supply
1.8V/ 2.5V/ 3.3V
—
0.097
0.148
3
LVDD
32
TSEC I/O supply
3.3V/ 2.5V
—
0.051
0.076
3
CVDD
19
ULPI/SPI/UART/SIM I/O supply
3.3V/ 1.8V
—
0.030
0.045
3
GVDD1
—
DDR1 (PPC Side) I/O supply
1.5V/ 1.35V
—
0.710
0.950
1, 2, 3
GVDD2
—
DDR2 (DSP Side) I/O supply
1.5V/ 1.35V
—
0.710
0.950
1, 2, 3
X1VDD
—
ANT1I/O supply
3.3V/ 1.8V
—
0.098
0.140
3
X2VDD
—
ANT2, ANT3 I/O supply
3.3V/ 1.8V
—
0.098
0.140
3
Note
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
60
Freescale Semiconductor
Electrical Characteristics
Table 10. I/O Power (continued)
PS#
Primary pin name
Pin
width
Voltage domain
Recommended
value
Current
max
Typical
current (A)
Max
(A)
Note
SVDD
—
SerDes Core logic supply
1.0V
—
0.144
0.144
—
XVDD
—
SerDes I/O supply
1.5V
—
0.058
0.058
—
AVDD_CORE0
—
Core 0 PLL supply
—
—
AVDD_CORE1
—
Core 1 PLL supply
—
—
AVDD_DSP
—
DSP PLL supply
—
—
AVDD_PLAT
—
Platform PLL supply
AVDD_D1_DDR
—
DDR PLL supply
AVDD_D2_DDR
—
DDR PLL supply
—
—
SDAVDD1
—
SerDes PLL supply
—
—
SDAVDD2
—
SerDes PLL supply
—
—
SD
Analog
1.0V
—
0.005
—
0.015
—
—
Note:
1 For DDR typical, it is 40% DIMM utilization.
2 For DDR max, it is 75% DIMM utilization.
3 For I/O with different possible voltages, the currents listed above are for the higher voltage.
2.7
Input Clocks
This section provides information about the system clock specifications, spread spectrum sources, real time clock
specifications, TDM clock specifications, and other input sources.
2.7.1
System Clock and DDR Clock Specifications
This table provides the system clock (SYSCLK) and DDR clock (DDRCLK) 3.3 V DC specifications.
Table 11. SYSCLK/DDRCLK DC Electrical Characteristics
At recommended operating conditions with OVDD = 3.3 V ± 165 mV
Parameter
Symbol
Min
Typical
Max
Unit
Note
Input high voltage
VIH
2.0
—
—
V
1
Input low voltage
VIL
—
—
0.8
V
1
Input capacitance
CIN
—
7
15
pf
—
Input current (VIN= 0 V or VIN = VDDC)
IIN
—
—
±50
μA
2
Note:
1. Note that the min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.
2. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 3.
This table provides the system clock (SYSCLK) and DDR clock (DDRCLK) AC timing specifications.
Table 12. SYSCLK/DDRCLK AC Timing Specifications
At recommended operating conditions with OVDD = 3.3 V ± 165 mV
Parameter/Condition
SYSCLK frequency
Symbol
Min
Typ
Max
Unit
Note
fSYSCLK
66
—
100
MHz
1, 2
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
61
Electrical Characteristics
Table 12. SYSCLK/DDRCLK AC Timing Specifications (continued)
At recommended operating conditions with OVDD = 3.3 V ± 165 mV
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Note
SYSCLK cycle time
tSYSCLK
7.5
—
10
ns
1, 2
DDRCLK frequency
fDDRCLK
66
—
166
MHz
1
DDRCLK cycle time
tDDRCLK
6.0
—
15.15
ns
—
SYSCLK/DDRCLK duty cycle
tKHK/
tSYSCLK/DDRCLK
40
—
60
%
2
SYSCLK/DDRCLK slew rate
—
1
—
4
V/ns
3
SYSCLK/DDRCLK peak period jitter
—
—
—
± 150
ps
—
SYSCLK/DDRCLK jitter phase noise
at –56 dBc
—
—
—
500
kHz
4
AC Input Swing Limits at 3.3 V OVDD
ΔVAC
1.9
—
—
V
—
Note:
1. Caution: The relevant clock ratio settings must be chosen such that the resulting SYSCLK frequency do not exceed their
respective maximum or minimum operating frequencies.
2. Measured at the rising edge and/or the falling edge at OVDD/2.
3. Slew rate as measured from ±0.3 ΔVAC at the center of peak to peak voltage at clock input.
4. Phase noise is calculated as FFT of TIE jitter.
2.7.2
DSP Clock (DSPCLKIN) Specifications
This table provides the DSP clock (DSPCLKIN) 3.3 V DC specifications.
Table 13. DSPCLKIN DC Electrical Characteristics
At recommended operating conditions with OVDD = 3.3 V ± 165 mV
Parameter
Symbol
Min
Typical
Max
Unit
Note
Input high voltage
VIH
2.0
—
—
V
1
Input low voltage
VIL
—
—
0.8
V
1
Input capacitance
CIN
—
7
15
pf
—
Input current (VIN= 0 V or VIN = VDDC)
IIN
—
—
±50
μA
2
Note:
1. Note that the min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.
2. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 3.
This table provides the DSP clock (DSPCLKIN) AC timing specifications.
Table 14. DSPCLKIN AC Timing Specifications
At recommended operating conditions with OVDD = 3.3 V ± 165 mV
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Note
DSPCLKIN frequency
fSYSCLK
66
—
133
MHz
1, 2
DSPCLKIN cycle time
tSYSCLK
7.5
—
10
ns
1, 2
DSPCLKIN duty cycle
tKHK/ tSYSCLK
40
—
60
%
2
DSPCLKIN slew rate
—
1
—
4
V/ns
3
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
62
Freescale Semiconductor
Electrical Characteristics
Table 14. DSPCLKIN AC Timing Specifications (continued)
At recommended operating conditions with OVDD = 3.3 V ± 165 mV
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Note
DSPCLKIN peak period jitter
—
—
—
±150
ps
—
DSPCLKIN jitter phase noise at –56 dBc
—
—
—
500
kHz
4
ΔVAC
1.9
—
—
V
—
AC Input Swing Limits at 3.3 V OVDD
Note:
1. Caution: The relevant clock ratio settings must be chosen such that the resulting DSPCLKIN frequency do not exceed their
respective maximum or minimum operating frequencies.
2. Measured at the rising edge and/or the falling edge at OVDD/2.
3. Slew rate as measured from ±0.3 ΔVAC at the center of peak to peak voltage at clock input.
4. Phase noise is calculated as FFT of TIE jitter.
2.7.3
Spread Spectrum Sources
Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference emissions (EMI) by
spreading the emitted noise to a wider spectrum and reducing the peak noise magnitude in order to meet industry and
government requirements. These clock sources intentionally add long-term jitter in order to diffuse the EMI spectral content.
The jitter specification given in this table considers short-term (cycle-to-cycle) jitter only and the clock generator’s
cycle-to-cycle output jitter should meet the input cycle-to-cycle jitter requirement. Frequency modulation and spread are
separate concerns, and the device is compatible with spread spectrum sources if the recommendations listed in this table are
observed.
Table 15. Spread Spectrum Clock Source Recommendations
At recommended operating conditions. See Table 3.
Parameter
Min
Max
Unit
Note
Frequency modulation
—
60
kHz
—
Frequency spread
—
1.0
%
1, 2
Note:
1. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO frequencies, must meet the
minimum and maximum specifications given in Table 99.
2. Maximum spread spectrum frequency may not result in exceeding any maximum operating frequency of the device
CAUTION
The processor’s minimum and maximum SYSCLK, core, and VCO frequencies must not
be exceeded regardless of the type of clock source. Therefore, systems in which the
processor is operated at its maximum rated e500 core frequency should avoid violating the
stated limits by using down-spreading only.
2.7.4
Real Time Clock Specifications
The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then used as an input to the
counters of the PIC and the TimeBase unit of the e500. There is no jitter specification. The minimum pulse width of the RTC
signal should be greater than 2x the period of the CCB clock. That is, minimum clock high time is 2 × tCCB, and minimum clock
low time is 2 × tCCB. There is no minimum RTC frequency; RTC may be grounded if not needed.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
63
Electrical Characteristics
2.7.5
RF Parallel Interface Clock Specifications
The following table lists the RF parallel interface clock DC electrical characteristics.
Table 16. RF Parallel Reference Clock DC Electrical Characteristics
Parameter
Symbol
Min
Typical
Max
Unit
Note
Input high voltage
VIH
2.0
—
—
V
1
Input low voltage
VIL
—
—
0.8
V
1
Input capacitance
CIN
—
7
15
C
—
Input current (VIN= 0 V or VIN = VDDC)
IIN
—
—
±50
μA
2
Note:
1. The max VIH, and min VIL values can be found in Table 3.
2. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 3.
The following table lists the RF parallel interface clock AC electrical characteristics.
Table 17. RF Parallel Reference Clock AC Electrical Characteristics
At recommended operating conditions with OVDD = 3.3 V ± 165 mV
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Note
ANTn_REF_CLK frequency
fANT_REF_CLK
—
19.2
—
MHz
—
ANTn_REF_CLK cycle time
tANT_REF_CLK
—
52
—
ns
—
ANTn_REF_CLK duty cycle
tKHK/tANT_REF_CLK
48
50
52
%
—
ANTn_REF_CLK slew rate
—
1
—
4
V/ns
1
ANTn_REF_CLK peak period jitter
—
—
—
±100
ps
—
ΔVAC
1.9
—
—
V
—
AC Input Swing Limits at 3.3 V OVDD
Note:
1. Slew rate as measured from ±0.3 ΔVAC at the center of peak to peak voltage at clock input.
2.7.6
Other Input Clocks
A description of the overall clocking of this device is available in the BSC9132 QorIQ Qonverge Multicore Baseband Processor
Reference Manual in the form of a clock subsystem block diagram. For information about the input clock requirements of other
functional blocks such as SerDes, Ethernet Management, eSDHC, and IFC, see the specific interface section.
2.8
DDR3 and DDR3L SDRAM Controller
This section describes the DC and AC electrical specifications for the DDR3 and DDR3L SDRAM controller interface. Note
that the required GVDD(typ) voltage is 1.5 V and 1.35 V when interfacing to DDR3 or DDR3L SDRAM, respectively.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
64
Freescale Semiconductor
Electrical Characteristics
2.8.1
DDR3 and DDR3L SDRAM Interface DC Electrical Characteristics
This table provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3
SDRAM.
Table 18. DDR3 SDRAM Interface DC Electrical Characteristics
At recommended operating condition with GVDD = 1.5 V1
Parameter
Symbol
Min
Max
Unit
Note
MVREFn
0.49 × GVDD
0.51 × GVDD
V
2, 3, 4
Input high voltage
VIH
MVREFn + 0.100
GVDD
V
5
Input low voltage
VIL
GND
MVREFn – 0.100
V
5
I/O leakage current
IOZ
–50
50
μA
6
I/O reference voltage
Note:
1. GVDD is expected to be within 50 mV of the DRAM’s voltage supply at all times. The DRAM’s and memory controller’s voltage
supply may or may not be from the same source.
2. MVREFn is expected to be equal to 0.5 × GVDD and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREFn may not exceed ±1% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be
equal to MVREFn with a min value of MVREFn – 0.04 and a max value of MVREFn + 0.04. VTT should track variations in the
DC level of MVREFn.
4. The voltage regulator for MVREFn must be able to supply up to125 μA current.
5. Input capacitance load for DQ, DQS, and DQS_B are available in the IBIS models.
6. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.
This table provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3L
SDRAM.
Table 19. DDR3L SDRAM Interface DC Electrical Characteristics
At recommended operating condition with GVDD = 1.35 V1
Parameter
Symbol
Min
Max
Unit
Note
MVREFn
0.49 × GVDD
0.51 × GVDD
V
2, 3, 4
Input high voltage
VIH
MVREFn + 0.090
GVDD
V
5
Input low voltage
VIL
GND
MVREFn – 0.090
V
5
Output high current (VOUT = 0.641 V)
IOH
—
–23.3
mA
6, 7
Output low current (VOUT = 0.641 V)
IOL
23.3
—
mA
6, 7
I/O leakage current
IOZ
–50
50
μA
8
I/O reference voltage
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
65
Electrical Characteristics
Table 19. DDR3L SDRAM Interface DC Electrical Characteristics (continued)
At recommended operating condition with GVDD = 1.35 V1
Parameter
Symbol
Min
Max
Unit
Note
Note:
1. GVDD is expected to be within 50 mV of the DRAM’s voltage supply at all times. The DRAM’s and memory controller’s voltage
supply may or may not be from the same source.
2. MVREFn is expected to be equal to 0.5 × GVDD and to track GVDD DC variations as measured at the receiver.Peak-to-peak
noise on MVREFn may not exceed the MVREFn DC level by more than ±1% of GVDD (i.e. ±13.5 mV).
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be
equal to MVREFn with a min value of MVREFn – 0.04 and a max value of MVREFn + 0.04. VTT should track variations in the
DC level of MVREFn.
4. The voltage regulator for MVREFn must be able to supply up to125 μA current.
5. Input capacitance load for DQ, DQS, and DQS_B are available in the IBIS models.
6. IOH and IOL are measured at GVDD = 1.282 V
7. See the IBIS model for the complete output IV curve characteristics.
8. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.
This table provides the DDR controller interface capacitance for DDR3.
Table 20. DDR3 SDRAM Capacitance
At recommended operating conditions with GVDD of 1.5 V ± 5% for DDR3 or 1.35 V ± 5% for DDR3L.
Parameter
Symbol
Min
Max
Unit
Note
Input/output capacitance: DQ, DQS, DQS_B
CIO
6
8
pF
—
Delta input/output capacitance: DQ, DQS, DQS_B
CDIO
—
0.5
pF
—
This table provides the current draw characteristics for MVREFn.
-
Table 21. Current Draw Characteristics for MVREFn
For recommended operating conditions, seeTable 3.
Parameter
Symbol
Min
Max
Unit
Note
Current draw for DDR3 SDRAM for MVREFn
IMVREFn
—
700
μA
—
Current draw for DDR3L SDRAM for MVREFn
IMVREFn
—
700
μA
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
66
Freescale Semiconductor
Electrical Characteristics
2.8.2
DDR3 and DDR3L SDRAM Interface AC Timing Specifications
This section provides the AC timing specifications for the DDR SDRAM controller interface. The DDR controller supports
DDR3 and DDR3L memories. Note that the required GVDD(typ) voltage is 1.5 V when interfacing to DDR3 SDRAM, and the
required GVDD(typ) voltage is 1.35 V when interfacing to DDR3L SDRAM.
2.8.2.1
DDR3 and DDR3L SDRAM Interface Input AC Timing Specifications
This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3 SDRAM.
Table 22. DDR3 SDRAM Interface Input AC Timing Specifications
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
VILAC
—
AC input low voltage
> 1200 MHz data rate
≤ 1200 MHz data rate
Max
Unit
Note
V
—
V
—
MVREFn – 0.150
MVREFn – 0.175
AC input high voltage
—
VIHAC
> 1200 MHz data rate
≤ 1200 MHz data rate
MVREFn + 0.150
MVREFn + 0.175
This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3L SDRAM.
Table 23. DDR3L SDRAM Interface Input AC Timing Specifications
For recommended operating conditions, see Table 3.
Parameter
AC input low voltage
> 1067 MHz data rate
≤ 1067 MHz data rate
AC input high voltage
> 1067 MHz data rate
≤ 1067 MHz data rate
Symbol
Min
VILAC
—
Max
Unit
Note
V
—
V
—
MVREFn – 0.135
MVREFn – 0.160
VIHAC
—
MVREFn + 0.135
MVREFn + 0.160
This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3/3L SDRAM.
Table 24. DDR3 and DDR3L SDRAM Interface Input AC Timing Specifications
At recommended operating conditions with GVDD of 1.5 V ± 5% for DDR3 or 1.35 V ± 5% for DDR3L.
Parameter
Symbol
Min
Max
Unit
Note
tCISKEW
—
—
ps
1
1333 MHz data rate
–125
125
1200 MHz data rate
–147.5
147.5
1066 MHz data rate
–170
170
800 MHz data rate
–200
200
667 MHz data rate
–240
240
Controller Skew for MDQS—MDQ/MECC
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
67
Electrical Characteristics
Table 24. DDR3 and DDR3L SDRAM Interface Input AC Timing Specifications (continued)
At recommended operating conditions with GVDD of 1.5 V ± 5% for DDR3 or 1.35 V ± 5% for DDR3L.
Parameter
Symbol
Min
Max
Unit
Note
tDISKEW
—
—
ps
2
1333 MHz data rate
–250
250
1200 MHz data rate
–275
275
1066 MHz data rate
–300
300
800 MHz data rate
–425
425
667 MHz data rate
–510
510
Tolerated Skew for MDQS—MDQ/MECC
Note:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
is captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be
determined by the following equation: tDISKEW = ±(T ÷ 4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the
absolute value of tCISKEW.
This figure shows the DDR3 and DDR3L SDRAM interface input timing diagram.
MCK[n]_B
MCK[n]
tMCK
MDQS[n]
tDISKEW
MDQ[x]
D0
D1
tDISKEW
tDISKEW
Figure 9. DDR3 and DDR3L SDRAM Interface Input Timing Diagram
2.8.2.2
DDR3 and DDR3L SDRAM Interface Output AC Timing Specifications
This table contains the output AC timing targets for the DDR3 and DDR3L SDRAM interface.
Table 25. DDR3 and DDR3L SDRAM Interface Output AC Timing Specifications
At recommended operating conditions with GVDD of 1.5 V ± 5% for DDR3 or 1.35 V ± 5% for DDR3L.
Parameter
MCK[n] cycle time
Symbol1
Min
Max
Unit
Note
tMCK
1.5
3
ns
2
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
68
Freescale Semiconductor
Electrical Characteristics
Table 25. DDR3 and DDR3L SDRAM Interface Output AC Timing Specifications (continued)
At recommended operating conditions with GVDD of 1.5 V ± 5% for DDR3 or 1.35 V ± 5% for DDR3L.
Parameter
Symbol1
ADDR/CMD output setup with respect to MCK
tDDKHAS
Min
Max
1333 MHz data rate
0.606
—
1200 MHz data rate
0.675
—
1066 MHz data rate
0.744
—
800 MHz data rate
0.917
—
667 MHz data rate
1.10
—
ADDR/CMD output hold with respect to MCK
tDDKHAX
1333 MHz data rate
0.606
—
1200 MHz data rate
0.675
—
1066 MHz data rate
0.744
—
800 MHz data rate
0.917
—
667 MHz data rate
1.10
—
MCS[n]_B output setup with respect to MCK
tDDKHCS
1333 MHz data rate
0.606
—
1200 MHz data rate
0.675
—
1066 MHz data rate
0.744
—
800 MHz data rate
0.917
—
667 MHz data rate
1.10
—
MCS[n]_B output hold with respect to MCK
tDDKHCX
1333 MHz data rate
0.606
—
1200 MHz data rate
0.675
—
1066 MHz data rate
0.744
—
800 MHz data rate
0.917
—
667 MHz data rate
1.10
—
MCK to MDQS Skew
tDDKHMH
> 1066 MHz data rate
–0.245
0.245
800 MHz data rate
–0.375
0.375
667 MHz data rate
–0.6
0.6
Unit
Note
ns
3
ns
3
ns
3
ns
3
ns
4
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
69
Electrical Characteristics
Table 25. DDR3 and DDR3L SDRAM Interface Output AC Timing Specifications (continued)
At recommended operating conditions with GVDD of 1.5 V ± 5% for DDR3 or 1.35 V ± 5% for DDR3L.
Parameter
MDQ/MECC/MDM output setup with respect
to MDQS
Symbol1
Min
Max
tDDKHDS,
tDDKLDS
1333 MHz data rate
250
—
1200 MHz data rate
275
—
1066 MHz data rate
300
—
800 MHz data rate
375
—
667 MHz data rate
450
—
MDQ/MECC/MDM output hold with respect to
MDQS
tDDKHDX,
tDDKLDX
1333 MHz data rate
250
—
1200 MHz data rate
275
—
1066 MHz data rate
300
—
800 MHz data rate
375
—
667 MHz data rate
450
—
Unit
Note
ps
5
ps
5
MDQS preamble
tDDKHMP
0.9 × tMCK
—
ns
—
MDQS postamble
tDDKHME
0.4 × tMCK
0.6 × tMCK
ns
—
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK_B and MDQS/MDQS_B referenced measurements are made from the crossing of the two signals.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK_B, MCS_B, and MDQ/MECC/MDM/MDQS.
4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD)
from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control
of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This is typically set to the same delay
as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these two parameters
have been set to the same adjustment value. See the BSC9132 QorIQ Qonverge Multicore Baseband Processor Reference
Manual for a description and explanation of the timing modifications enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
NOTE
For the ADDR/CMD setup and hold specifications in Table 25, it is assumed that the clock
control register is set to adjust the memory clocks by ½ applied cycle.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
70
Freescale Semiconductor
Electrical Characteristics
This figure shows the DDR3 and DDR3L SDRAM interface output timing for the MCK to MDQS skew measurement
(tDDKHMH).
MCK_B[n]
MCK[n]
tMCK
tDDKHMH(max) = 0.6 ns or 0.375 ns
MDQS
tDDKHMH(min) = –0.6 ns or –0.375 ns
MDQS
Figure 10. tDDKHMH Timing Diagram
This figure shows the DDR3 and DDR3L SDRAM output timing diagram.
MCK_B
MCK
tMCK
tDDKHAS, tDDKHCS
tDDKHAX, tDDKHCX
ADDR/CMD
Write A0
NOOP
tDDKHMP
tDDKHMH
MDQS[n]
tDDKHME
tDDKHDS
tDDKLDS
MDQ[x]
D0
D1
tDDKLDX
tDDKHDX
Figure 11. DDR3 and DDR3L Output Timing Diagram
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
71
Electrical Characteristics
This figure provides the AC test load for the DDR3 and DDR3Lcontroller bus.
Output
Z0 = 50 Ω
RL = 50 Ω
GVDD/2
Figure 12. DDR3 and DDR3L Controller Bus AC Test Load
2.8.2.3
DDR3 and DDR3L SDRAM Differential Timing Specifications
This section describes the DC and AC differential timing specifications for the DDR3 SDRAM controller interface. Figure 13
shows the differential timing specification.
GVDD
VTR
GVDD/2
VOX or VIX
VCP
GND
Figure 13. DDR3, and DDR3L SDRAM Differential Timing Specifications
NOTE
VTR specifies the true input signal (such as MCK or MDQS) and VCP is the
complementary input signal (such as MCK_B or MDQS_B).
This table provides the DDR3 differential specifications for the differential signals MDQS/MDQS_B and MCK/MCK_B.
Table 26. DDR3 SDRAM Differential Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
Note
Input AC Differential Cross-Point Voltage
VIXAC
0.5 × GVDD – 0.150 0.5 × GVDD + 0.150
V
1
Output AC Differential Cross-Point Voltage
VOXAC
0.5 × GVDD – 0.115 0.5 × GVDD + 0.115
V
1
Note:
1. I/O drivers are calibrated before making measurements.
This table provides the DDR3 differential specifications for the differential signals MDQS/MDQS_B and MCK/MCK_B.
Table 27. DDR3L SDRAM Differential Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
Note
Input AC Differential Cross-Point Voltage
VIXAC
0.5 × GVDD – 0.135 0.5 × GVDD + 0.135
V
1
Output AC Differential Cross-Point Voltage
VOXAC
0.5 × GVDD – 0.105 0.5 × GVDD + 0.105
V
1
Note:
1. I/O drivers are calibrated before making measurements.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
72
Freescale Semiconductor
Electrical Characteristics
2.9
eSPI
This section describes the DC and AC electrical specifications for the SPI.
2.9.1
eSPI1 DC Electrical Characteristics
This table provides the DC electrical characteristics for the eSPI1 on the device operating on a 3.3 V power supply.
Table 28. eSPI1 DC Electrical Characteristics (CVDD = 3.3 V)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
VIH
2.0
—
V
1
Input low voltage
VIL
—
0.8
V
1
Input current (0 V ≤ VIN ≤ CVDD)
IIN
—
±10
μA
2
Output high voltage (IOH = –6.0 mA)
VOH
2.4
—
V
—
Output low voltage (IOL = 6.0 mA)
VOL
—
0.5
V
—
Output low voltage (IOL = 3.2 mA)
VOL
—
0.4
V
—
Note:
1 The min V and max V values are based on the respective min and max OV values found in Table 3.
IL
IH
IN
2 The symbol V , in this case, represents the OV symbol referenced in Section 2.1.2, “Recommended Operating Conditions.”
IN
IN
This table provides the DC electrical characteristics for the eSPI1 and eSPI2 on the device operating on a 1.8 V power supply.
Table 29. eSPI DC Electrical Characteristics (CVDD, X2VDD = 1.8 V)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
VIH
1.25
—
V
1
Input low voltage
VIL
—
0.6
V
1
Input current (0 V ≤ VIN ≤ CVDD/X2VDD)
IIN
—
±40
μA
2, 3
Output high voltage (IOH = –6.0 mA)
VOH
1.35
—
V
—
Output low voltage (IOL = 6.0 mA)
VOL
—
0.4
V
—
Note:
1 The min V and max V values are based on the respective min and max OV values found in Table 3.
IL
IH
IN
2 The symbol V , in this case, represents the OV symbol referenced in Section 2.1.2, “Recommended Operating Conditions.”
IN
IN
3 eSPI1 is powered on CV , SPI2 is on X2V
DD
DD (see Table 3).
2.9.2
eSPI1 AC Timing Specifications
This table provides the eSPI1 input and output AC timing specifications.
Table 30. eSPI1 AC Timing Specifications
For recommended operating conditions, see Table 3.
Characteristic
eSPI outputs—Master data (internal clock) hold time
Symbol1
Min
Max
tNIKHOX
0.5 +
(tPLATFORM_CLK/2)
—
Unit Note
ns
2
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
73
Electrical Characteristics
Table 30. eSPI1 AC Timing Specifications (continued)
For recommended operating conditions, see Table 3.
Symbol1
Min
Max
eSPI outputs—Master data (internal clock) delay
tNIKHOV
—
6.0 +
(tPLATFORM_CLK/2)
ns
2
SPI_CS outputs—Master data (internal clock) hold time
tNIKHOX2
0
—
ns
2
SPI_CS outputs—Master data (internal clock) delay
tNIKHOV2
—
6.0
ns
2
eSPI inputs—Master data (internal clock) input setup time
tNIIVKH
5
—
ns
—
eSPI inputs—Master data (internal clock) input hold time
tNIIXKH
0
—
ns
—
Characteristic
Unit Note
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI outputs
internal timing (NI) for the time tSPI memory clock reference (K) goes from the high state (H) until outputs (O) are valid (V).
2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are
measured at the pin.
This figure provides the AC test load for eSPI1.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 14. eSPI1 AC Test Load
This figure represents the AC timing from Table 30 in master mode (internal clock). Note that although the specifications are
generally refer to the rising edge of the clock, Figure 14 also apply when the falling edge is the active edge. Also, note that the
clock edge is selectable on eSPI1.
SPICLK (output)
tNIIVKH
Input Signals:
SPIMISO1
tNIIXKH
tNIKHOX
tNIKHOV
Output Signals:
SPIMOSI1
tNIKHOV2
Output Signals:
SPI_CS[0:3]1
tNIKHOX2
Figure 15. eSPI1 AC Timing in Master Mode (Internal Clock) Diagram
2.10
DUART
This section describes the DC and AC electrical specifications for the DUART interfaces.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
74
Freescale Semiconductor
Electrical Characteristics
2.10.1
DUART DC Electrical Characteristics
Table 31 and Table 33 provide the DC electrical characteristics for the two DUARTs on the device, which correspond to four
UART interfaces. DUART1 is powered by OVDD, while DUART2 is powered by the CVDD.
This table provides the DC timing parameters for the DUART interface operating from a 3.3 V power supply.
Table 31. DUART DC Electrical Characteristics (OVDD, CVDD = 3.3 V)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
VIH
2
—
V
1
Input low voltage
VIL
—
0.8
V
1
Input current (OVIN/CVIN = 0 V or OVIN/CVIN = OVDD/CVDD)
IIN
—
±40
μA
2
Output high voltage (OVDD/CVDD = mn, IOH = –2 mA)
VOH
2.4
—
V
—
Output low voltage (OVDD/CVDD = min, IOL = 2 mA)
VOL
—
0.4
V
—
Note:
1. Note that the min VILand max VIH values are based on the respective min and max OVIN/CVIN values found in Figure 3.
2. Note that the symbol OVIN/CVIN represents the input voltage of the supply. It is referenced in Figure 3.
This table provides the DC timing parameters for the DUART interface operating from a 1.8 V power supply.
Table 32. DUART DC Electrical Characteristics (CVDD = 1.8 V)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
VIH
1.25
—
V
1
Input low voltage
VIL
—
0.6
V
1
Input current (CVIN = 0 V or CVIN = CVDD)
IIN
—
±40
μA
2
Output high voltage (CVDD = mn, IOH = –2 mA)
VOH
1.35
—
V
—
Output low voltage (CVDD = min, IOL = 2 mA)
VOL
—
0.4
V
—
Note:
1. Note that the min VILand max VIH values are based on the respective min and max CVIN values found in Figure 3.
2. Note that the symbol CVIN represents the input voltage of the supply. It is referenced in Figure 3.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
75
Electrical Characteristics
2.10.2
DUART AC Electrical Specifications
This table provides the AC timing parameters for the DUART interface.
Table 33. DUART AC Timing Specifications
Parameter
Value
Unit
Note
Minimum baud rate
CCB clock/1,048,576
baud
1
Maximum baud rate
CCB clock/16
baud
2
16
—
3
Oversample rate
Note:
1. CCB clock refers to the platform clock.
2. Actual attainable baud rate is limited by the latency of interrupt processing.
3. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are
sampled each 16th sample.
2.11
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
This section provides the AC and DC electrical characteristics for enhanced three-speed Ethernet10/100/1000 controller and
MII management.
2.11.1
SGMII Interface Electrical Characteristics
For SGMII interface electrical characteristics, see Section 2.20, “High-Speed Serial Interface (HSSI) DC Electrical
Characteristics.”
2.11.2
2.11.2.1
MII Management
MII Management DC Electrical Characteristics
The MDC and MDIO are defined to operate at a supply voltage of 3.3 V and 2.5 V. The DC electrical characteristics for MDIO
and MDC are provided in Table 34 and Table 35.
Table 34. MII Management DC Electrical Characteristics
At recommended operating conditions with LVDD = 3.3 V.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
VIH
2.0
—
V
—
Input low voltage
VIL
—
0.90
V
—
Input high current (LVDD = Max, VIN = 2.1 V)
IIH
—
40
μA
1
Input low current (LVDD = Max, VIN = 0.5 V)
IIL
–600
—
μA
1
Output high voltage (LVDD = Min, IOH = –1.0 mA)
VOH
2.4
LVDD + 0.3
V
—
Output low voltage (LVDD = Min, IOL = 1.0 mA)
VOL
GND
0.4
V
—
Note:
1. Note that the symbol VIN, in this case, represents the LVIN symbol referenced in Table 2 and Table 3.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
76
Freescale Semiconductor
Electrical Characteristics
Table 35. MII Management DC Electrical Characteristics
At recommended operating conditions with LVDD = 2.5 V.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
VIH
1.70
LVDD + 0.3
V
—
Input low voltage
VIL
–0.3
0.70
V
—
Input high current (VIN = LVDD,)
IIH
—
10
μA
1, 2
Input low current (VIN = GND)
IIL
–15
—
μA
—
Output high voltage
(LVDD = Min, IOH = –1.0 mA)
VOH
2.00
LVDD + 0.3
V
—
Output low voltage
(LVDD = Min, IOL = 1.0 mA)
VOL
GND – 0.3
0.40
V
—
Note:
1. EC1_MDC and EC1_MDIO operate on LVDD.
2. Note that the symbol VIN, in this case, represents the LVIN and TVIN symbols referenced in Table 3.
2.11.2.2
MII Management AC Electrical Specifications
This table provides the MII management AC timing specifications.
Table 36. MII Management AC Timing Specifications
Symbol1
Min
Typ
Max
Unit
Note
MDC frequency
fMDC
—
2.5
—
MHz
2
MDC period
tMDC
—
400
—
ns
—
MDC clock pulse width high
tMDCH
32
—
—
ns
—
MDC to MDIO delay
tMDKHDX
(16*tplb_clk) – 3
—
(16*tplb_clk) + 3
ns
3, 4
MDIO to MDC setup time
tMDDVKH
5
—
—
ns
—
MDIO to MDC hold time
tMDDXKH
0
—
—
ns
—
Parameter
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management
data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.
Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state
(V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention
is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the platform clock frequency (MIIMCFG [MgmtClk] field determines the clock frequency of
the MgmtClk Clock EC_MDC).
3. This parameter is dependent on the platform clock frequency. The delay is equal to 16 platform clock periods ±3 ns. For
example, with a platform clock of 333 MHz, the min/max delay is 48 ns ± 3 ns. Similarly, if the platform clock is 400 MHz, the
min/max delay is 40 ns ± 3 ns.
4. tplb_clk is the platform (CCB) clock.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
77
Electrical Characteristics
This figure shows the MII management interface timing diagram.
tMDCR
tMDC
MDC
tMDCF
tMDCH
MDIO
(Input)
tMDDVKH
tMDDXKH
MDIO
(Output)
tMDKHDX
Figure 16. MII Management Interface Timing Diagram
2.11.3
2.11.3.1
eTSEC IEEE Std 1588 Electrical Specifications
eTSEC IEEE Std 1588 DC Specifications
This table shows IEEE Std 1588 DC electrical characteristics when operating at LVDD = 3.3 V supply.
Table 37. eTSEC IEEE 1588 DC Electrical Characteristics (LVDD = 3.3 V)
For recommended operating conditions with LVDD = 3.3 V.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage
VIH
2.0
—
V
2
Input low voltage
VIL
—
0.9
V
2
Input high current (LVDD = Max, VIN = 2.1 V)
IIH
—
40
μA
1
Input low current (LVDD = Max, VIN = 0.5 V)
IIL
–600
—
μA
1
Output high voltage (LVDD = Min, IOH = –1.0 mA)
VOH
2.4
—
V
—
Output low voltage (LVDD = Min, IOL = 1.0 mA)
VOL
—
0.4
V
—
Note:
1. The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3.
2. The symbol VIN, in this case, represents the LVIN symbols referenced in Table 2 and Table 3.
This table shows the IEEE 1588 DC electrical characteristics when operating at LVDD = 2.5 V supply.
Table 38. eTSEC IEEE 1588 DC Electrical Characteristics (LVDD = 2.5 V)
For recommended operating conditions with LVDD = 2.5 V
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage
VIH
1.70
—
V
—
Input low voltage
VIL
—
0.70
V
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
78
Freescale Semiconductor
Electrical Characteristics
Table 38. eTSEC IEEE 1588 DC Electrical Characteristics (LVDD = 2.5 V) (continued)
For recommended operating conditions with LVDD = 2.5 V
Parameter
Symbol
Min
Max
Unit
Notes
IIH
—
±40
μA
2
Output high voltage (LVDD = min, IOH = –1.0 mA)
VOH
2.00
—
V
—
Output low voltage (LVDD = min, IOL = 1.0 mA)
VOL
—
0.40
V
—
Input current (LVIN = 0 V or LVIN = LVDD)
Note:
1. The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3.
2. The symbol VIN, in this case, represents the LVIN symbols referenced in Table 2 and Table 3.
2.11.3.2
eTSEC IEEE Std 1588 AC Specifications
This table provides the IEEE Std 1588 AC timing specifications.
Table 39. eTSEC IEEE 1588 AC Timing Specifications
For recommended operating conditions, see Table 3
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Note
TSEC_1588_CLK clock period
tT1588CLK
5
—
TRX_CLK*7
ns
1, 3
TSEC_1588_CLK duty cycle
tT1588CLKH
/tT1588CLK
40
50
60
%
—
TSEC_1588_CLK peak-to-peak jitter
tT1588CLKINJ
—
—
250
ps
—
Rise time eTSEC_1588_CLK (20%–80%)
tT1588CLKINR
1.0
—
2.0
ns
—
Fall time eTSEC_1588_CLK (80%–20%)
tT1588CLKINF
1.0
—
2.0
ns
—
TSEC_1588_CLK_OUT clock period
tT1588CLKOUT
2 x tT1588CLK
—
—
ns
—
TSEC_1588_CLK_OUT duty cycle
tT1588CLKOTH
/tT1588CLKOUT
30
50
70
%
—
tT1588OV
0.5
—
3.0
ns
—
tT1588TRIGH
2*tT1588CLK_MAX
—
—
ns
2
TSEC_1588_PULSE_OUT
TSEC_1588_TRIG_IN pulse width
Note:
1.TRX_CLK is the max clock period of eTSEC receiving clock selected by TMR_CTRL[CKSEL]. See the BSC9132 QorIQ
Qonverge Multicore Baseband Processor Reference Manual for a description of TMR_CTRL registers.
2. It needs to be at least two times the clock period of the clock selected by TMR_CTRL[CKSEL]. See the BSC9132 QorIQ
Qonverge Multicore Baseband Processor Reference Manualfor a description of TMR_CTRL registers.
3. The maximum value of tT1588CLK is not only defined by the value of TRX_CLK, but also defined by the recovered clock. For
example, for 10/100/1000 Mbps modes, the maximum value of tT1588CLK is 2800, 280, and 56 ns respectively.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
79
Electrical Characteristics
Figure 17 shows the data and command output AC timing diagram.
tT1588CLKOUT
tT1588CLKOUTH
TSEC_1588_CLK_OUT
tT1588OV
TSEC_1588_PULSE_OUT
TSEC_1588_TRIG_OUT
1
eTSEC IEEE 1588 Output AC timing: The output delay is counted starting at the rising edge if tT1588CLKOUT is non-inverting.
Otherwise, it is counted starting at the falling edge.
Figure 17. eTSEC IEEE 1588 Output AC Timing
This figure shows the data and command input AC timing diagram.
tT1588CLK
tT1588CLKH
TSEC_1588_CLK
TSEC_1588_TRIG_IN
tT1588TRIGH
Figure 18. eTSEC IEEE 1588 Input AC Timing
2.12
USB
This section provides the AC and DC electrical specifications for the USB interface.
2.12.1
USB DC Electrical Characteristics
This table provides the DC electrical characteristics for the ULPI interface when operating at 3.3 V.
Table 40. USB DC Electrical Characteristics (CVDD/X2VDD = 3.3 V)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
VIH
2
—
V
1
Input low voltage
VIL
—
0.8
V
1
Input current
(CVIN/X2VIN = 0 V or CVIN/X2VIN = CVDD/X2VDD)
IIN
—
±40
μA
2
VOH
2.8
—
V
—
Output high voltage
(CVDD/X2VDD = min, IOH = –2 mA)
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
80
Freescale Semiconductor
Electrical Characteristics
Table 40. USB DC Electrical Characteristics (CVDD/X2VDD = 3.3 V) (continued)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
VOL
—
0.3
V
—
Output low voltage
(CVDD/X2VDD = min, IOL = 2 mA)
Note:
1. Note that the min VILand max VIH values are based on the respective min and max CVIN/X2VIN values found in Table 3.
2. Note that the symbol CVIN and X2VIN represent the input voltage of the power supplies. See Table 3.
This table provides the DC electrical characteristics for the ULPI interface when operating at 1.8 V.
Table 41. USB DC Electrical Characteristics (CVDD/X2VDD = 1.8 V)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
VIH
1.25
—
V
1
Input low voltage
VIL
—
0.6
V
1
Input current (CVIN/X2VIN = 0 V or CVIN/X2VIN = CVDD/X2VDD)
IIN
—
±40
μA
2
Output high voltage (CVDD/X2VDD = min, IOH = –2 mA)
VOH
1.35
—
V
—
Output low voltage (CVDD/X2VDD = min, IOL = 2 mA)
VOL
—
0.4
V
—
Note:
1. Note that the min VILand max VIH values are based on the respective min and max CVIN/X2VIN values found in Table 3.
2. Note that the symbol CVIN/X2VIN represents the input voltage of the supply. See Table 3.
2.12.2
USB AC Electrical Specifications
This table describes the general timing parameters of the USB interface of the device.
Table 42. USB General Timing Parameters (ULPI Mode)
For recommended operating conditions, see Table 3.
Symbol1
Min
Max
Unit
Note
tUSCK
15
—
ns
2, 3, 4, 5
Input setup to USB clock—all inputs
tUSIVKH
4
—
ns
2, 3, 4, 5
input hold to USB clock—all inputs
tUSIXKH
1
—
ns
2, 3, 4, 5
USB clock to output valid—all outputs
tUSKHOV
—
7
ns
2, 3, 4, 5
Output hold from USB clock—all outputs
tUSKHOX
2
—
ns
2, 3, 4, 5
Parameter
USB clock cycle time
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
81
Electrical Characteristics
Table 42. USB General Timing Parameters (ULPI Mode) (continued)
For recommended operating conditions, see Table 3.
Parameter
Symbol1
Min
Max
Unit
Note
Note:
1. The symbols for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs
and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes USB timing (US) for
the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, tUSKHOX symbolizes
USB timing (US) for the USB clock reference (K) to go high (H) with respect to the output (O) going invalid (X) or output hold
time.
2. All timings are in reference to USB clock.
3. All signals are measured from BVDD/2 of the rising edge of the USB clock to 0.4 × OVDD of the signal in question for 3.3 V
signaling levels.
4. Input timings are measured at the pin.
5. For active/float timing measurements, the high impedance or off state is defined to be when the total current delivered through
the component pin is less than or equal to that of the leakage current specification.
Figure 19 and Figure 20 provide the USB AC test load and signals, respectively.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 19. USB AC Test Load
USB0_CLK/USB1_CLK/DR_CLK
tUSIVKH
tUSIXKH
Input Signals
tUSKHOV
tUSKHOX
Output Signals:
Figure 20. USB Signals
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
82
Freescale Semiconductor
Electrical Characteristics
This table provides the USB clock input (USB_CLK_IN) AC timing specifications.
Table 43. USB_CLK_IN AC Timing Specifications
Parameter/Condition
Conditions
Frequency range
Steady state
Clock frequency tolerance
—
Reference clock duty cycle
Measured at 1.6 V
Symbol
Min
Typ
Max
Unit
fUSB_CLK_IN
59.97
60
60.03
MHz
tCLK_TOL
–0.05
0
0.05
%
tCLK_DUTY
40
50
60
%
tCLK_PJ
—
—
200
ps
Total input jitter/time interval Peak-to-peak value measured with a second
error
order high-pass filter of 500 kHz bandwidth
2.13
Integrated Flash Controller (IFC)
This section describes the DC and AC electrical specifications for the integrated flash controller.
2.13.1
IFC DC Electrical Characteristics
This table provides the DC electrical characteristics for the integrated flash controller when operating at BVDD = 3.3 V.
Table 44. Integrated Flash Controller DC Electrical Characteristics (3.3 V)
For recommended operating conditions, see Table 3
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
VIH
2
—
V
1
Input low voltage
VIL
—
0.8
V
1
Input current
(VIN = 0 V or VIN = BVDD)
IIN
—
±40
μA
2
Output high voltage
(BVDD = min, IOH = –2 mA)
VOH
2.8
—
V
—
Output low voltage
(BVDD = min, IOH = 2 mA)
VOL
—
0.4
V
—
Note:
1. The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3.
2. The symbol VIN, in this case, represents the BVIN symbol referenced in Section 2.1.2, “Recommended Operating
Conditions.”
This table provides the DC electrical characteristics for the integrated flash controller when operating at BVDD = 2.5 V.
Table 45. Integrated Flash Controller DC Electrical Characteristics (2.5 V)
For recommended operating conditions, see Table 3
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
VIH
1.7
—
V
1
Input low voltage
VIL
—
0.7
V
1
Input current
(VIN = 0 V or VIN = BVDD)
IIN
—
±40
μA
2
VOH
2.0
—
V
—
Output high voltage
(BVDD = min, IOH = –1 mA)
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
83
Electrical Characteristics
Table 45. Integrated Flash Controller DC Electrical Characteristics (2.5 V)
For recommended operating conditions, see Table 3
Parameter
Symbol
Min
Max
Unit
Note
VOL
—
0.4
V
—
Output low voltage
(BVDD = min, IOL = 1 mA)
Note:
1. The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3.
2. The symbol VIN, in this case, represents the BVIN symbol referenced in Section 2.1.2, “Recommended Operating Conditions.”
This table provides the DC electrical characteristics for the integrated flash controller when operating at BVDD = 1.8 V.
Table 46. Integrated Flash Controller DC Electrical Characteristics (1.8 V)
For recommended operating conditions, see Table 3
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
VIH
1.25
—
V
1
Input low voltage
VIL
—
0.6
V
1
Input current
(VIN = 0 V or VIN = BVDD)
IIN
—
±40
μA
2
Output high voltage
(BVDD = min, IOH = –0.5 mA)
VOH
1.35
—
V
—
Output low voltage
(BVDD = min, IOL = 0.5 mA)
VOL
—
0.4
V
—
Note:
1. The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3.
2. The symbol VIN, in this case, represents the BVIN symbol referenced in Section 2.1.2, “Recommended Operating Conditions.”
2.13.2
IFC AC Timing Specifications
This section describes the AC timing specifications for the integrated flash controller.
2.13.2.1
Test Condition
This figure provides the AC test load for the integrated flash controller.
Output
Z0 = 50 Ω
RL = 50 Ω
BVDD/2
Figure 21. Integrated Flash Controller AC Test Load
2.13.2.2
IFC AC Timing Specifications
All output signal timings are relative to the falling edge of any IFC_CLK. The external circuit must use the rising edge of the
IFC_CLKs to latch the data.
All input timings are relative to the rising edge of IFC_CLKs.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
84
Freescale Semiconductor
Electrical Characteristics
This table describes the timing specifications of the integrated flash controller interface.
Table 47. IFC Timing Specifications (BVDD = 3.3 V, 2.5 V, and 1.8 V)
For recommended operating conditions, see Table 3
Symbol1
Min
Max
Unit
Note
IFC_CLK cycle time
tIBK
10
—
ns
—
IFC_CLK duty cycle
tIBKH/tIBK
45
55
%
—
Input setup
tIBIVKH
4
—
ns
—
Input hold
tIBIXKH
1
—
ns
—
Output delay
tIBKLOV
—
1.5
ns
—
Output hold
tIBKLOX
–2
—
ns
5, 6
Parameter
Note:
1. All signals are measured from BVDD/2 of rising/falling edge of IFC_CLK to BVDD/2 of the signal in question.
2. Skew measured between different IFC_CLK signals at BVDD/2.
3. For purposes of active/float timing measurements, the high impedance or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
4. tIBONOT is a measurement of the maximum time between the negation of ALE and any change in AD when
FTIM0_CSn[TEAHC] = 0.
5. Here the negative sign means output transit happens earlier than the falling edge of IFC_CLK.
6. Here a convention has been followed in which the more negative/less-positive the number, the smaller the number would be.
For example –2 is smaller then –1 and –1 is smaller then 0. So if the min value of this parameter is shown as –2 ns than the
for any part parameter’s measure will never go to –3ns though it can go to –1 ns.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
85
Electrical Characteristics
This figure shows the AC timing diagram.
IFC_CLK[m]
tIBIVKH
tIBIXKH
Input Signals
tIBKLOV
tIBKLOX
Output Signals
AD
(address phase)
ALE
tIBKLOX
AD
(data phase)
Figure 22. Integrated Flash Controller Signals
Figure 22 applies to all the controllers that IFC supports.
For input signals, the AC timing data is used directly for all controllers. For output signals, each type of controller provides its
own unique method to control the signal timing. The final signal delay value for output signals is the programmed delay plus
the AC timing delay.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
86
Freescale Semiconductor
Electrical Characteristics
This figure shows how the AC timing diagram applies to GPCM. The same principle also applies to other controllers of IFC.
IFC_CLK
AD[0:31]
address
read data
write data
address
teahc + tIBKLOV
teadc + tIBKLOV
ALE
tacse + tIBKLOV
CE_B
taco + tIBKLOV
trad + tIBKHOV
OE_B
tch + tIBKLOV
tcs+ tIBKLOV
WE_B
twp + tIBKLOV
BCTL
read
write
1
taco, trad, teahc, teadc, tacse, tcs, tch, twp are programmable. See the BSC9132 QorIQ Qonverge Multicore Baseband Processor
Reference Manual.
2 For output signals, each type of controller provides its own unique method to control the signal timing. The final signal delay
value for output signals is the programmed delay plus the AC timing delay.
Figure 23. GPCM Output Timing Diagram
2.14
Enhanced Secure Digital Host Controller (eSDHC)
This section describes the DC and AC electrical specifications for the eSDHC interface.
2.14.1
eSDHC DC Electrical Characteristics
This table provides the DC electrical characteristics for the eSDHC interface.
Table 48. eSDHC Interface DC Electrical Characteristics
At recommended operating conditions with BVDD = 3.3 V or 1.8 V.
Characteristic
Symbol
Condition
Min
Max
Unit
Note
Input high voltage
VIH
—
0.625 × BVDD
—
V
1
Input low voltage
VIL
—
—
0.25 × BVDD
V
1
Output high voltage
VOH
IOH = –100 uA at BVDD min
0.75 × BVDD
—
V
—
Output low voltage
VOL
IOL = 100uA at BVDD min
—
0.125 × BVDD
V
—
Output high voltage
VOH
IOH = –100 uA
BVDD - 0.2
—
V
2
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
87
Electrical Characteristics
Table 48. eSDHC Interface DC Electrical Characteristics (continued)
At recommended operating conditions with BVDD = 3.3 V or 1.8 V.
Characteristic
Output low voltage
Input/output leakage current
Symbol
Condition
Min
Max
Unit
Note
VOL
IOL = 2 mA
—
0.3
V
2
IIN/IOZ
—
–10
10
uA
—
Note:
1. Note that the min VILand max VIH values are based on the respective min and max BVIN values found in Figure 3.
2. Open drain mode for MMC cards only.
2.14.2
eSDHC AC Timing Specifications
This table provides the eSDHC AC timing specifications as defined in Figure 25.
Table 49. eSDHC AC Timing Specifications
At recommended operating conditions with BVDD = 3.3 or 1.8 V
Parameter
Symbol1
SD_CLK clock frequency:
SD/SDIO Full-speed/High-speed mode
MMC Full-speed/High-speed mode
fSFSCK
SD_CLK clock low time—Full-speed/High-speed mode
Min
Max
Unit
Note
0
0
25/50
20/52
MHz
2, 4
tSFSCKL
10/7
—
ns
4
SD_CLK clock high time—Full-speed/High-speed mode
tSFSCKH
10/7
—
ns
4
SD_CLK clock rise and fall times
tSFSCKR/
tSFSCKF
—
3
ns
4
Input setup times: SD_CMD, SD_DATx
tSFSIVKH
2.5
—
ns
3, 4
Input hold times: SD_CMD, SD_DATx
tSFSIXKH
2.5
—
ns
3, 4
Output delay time: SD_CLK to SD_CMD, SD_DATx valid
tSFSKHOV
—
3
ns
4
Output delay time: SD_CLK to SD_CMD, SD_DATx hold time
tSFSKHOX
–3
—
ns
4
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFHSKHOV
symbolizes eSDHC high speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the
output (O) reaching the invalid state (X) or output hold time. Note that, in general, the clock reference symbol representation
is based on five letters representing the clock of a particular functional. For rise and fall times, the latter convention is used
with the appropriate letter: R (rise) or F (fall).
2. In full speed mode, clock frequency value can be 0–25 MHz for a SD/SDIO card and 0–20 MHz for a MMC card. In high
speed mode, clock frequency value can be 0–50 MHz for a SD/SDIO card and 0–52 MHz for a MMC card.
3. To satisfy setup timing, one way board routing delay between Host and Card, on SD_CLK, SD_CMD and SD_DATx should
not exceed 1 ns for any high speed MMC card. For any high speed or default speed mode SD card, the one way board routing
delay between Host and Card, on SD_CLK, SD_CMD and SD_DATx should not exceed 1.5 ns.
4. CCARD ≤10 pF, (1 card), and CL = CBUS + CHOST + CCARD ≤ 40 pF
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
88
Freescale Semiconductor
Electrical Characteristics
This figure provides the eSDHC clock input timing diagram.
eSDHC
External Clock
operational mode
VM
VM
VM
tSFSCKL
tSFSCKH
tSFSCK
tSFSCKF
tSFSCKR
VM = Midpoint Voltage (BVDD/2)
Figure 24. eSDHC Clock Input Timing Diagram
This figure provides the data and command input/output timing diagram.
VM
SD_CK
External Clock
VM
VM
VM
tSFSIXKH
tSFSIVKH
SD_DAT/CMD
Inputs
SD_DAT/CMD
Outputs
tSFSKHOX
tSFSKHOV
VM = Midpoint Voltage (BVDD/2)
Figure 25. eSDHC Data and Command Input/Output Timing Diagram Referenced to Clock
2.15
Programmable Interrupt Controller (PIC) Specifications
This section describes the DC and AC electrical specifications for the PIC.
2.15.1
PIC DC Electrical Characteristics
This table provides the DC electrical characteristics for the PIC interface when operating at
CVDD/OVDD/BVDD/X1VDD/X2VDD = 3.3 V.
Table 50. PIC DC Electrical Characteristics (3.3 V)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
VIH
2
—
V
1
Input low voltage
VIL
—
0.8
V
1
Input current (CVIN/OVIN/BVIN/X1VIN/X2VIN = 0V or
CVIN/OVIN/BVIN/X1VIN/X2VIN = CVDD/OVDD/BVDD/X1VDD/X2VDD)
IIN
—
±40
μA
2
VOH
2.4
—
V
—
Output high voltage (CVDD/OVDD/BVDD/X1VDD/X2VDD = min,
IOH = –2 mA)
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
89
Electrical Characteristics
Table 50. PIC DC Electrical Characteristics (3.3 V) (continued)
For recommended operating conditions, see Table 3.
Parameter
Output low voltage (CVDD/OVDD/BVDD/X1VDD/X2VDD = min,
IOL = 2 mA)
Symbol
Min
Max
Unit
Note
VOL
—
0.4
V
—
Note:
1. Note that the min VILand max VIH values are based on the respective min and max CVIN/OVIN/BVIN/X1VIN/X2VIN values
found in Table 3.
2. Note that the symbol CVIN/OVIN/BVIN/X1VIN/X2VIN represents the input voltage of the supply. See Table 3.
This table provides the DC electrical characteristics for the PIC interface when operating at LVDD/OVDD/BVDD/CVDD = 2.5 V.
Table 51. PIC DC Electrical Characteristics (2.5 V)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
VIH
1.7
—
V
1
Input low voltage
VIL
—
0.7
V
1
Input current (CVIN/OVIN/BVIN/X1VIN/X2VIN = 0V or
CVIN/OVIN/BVIN/X1VIN/X2VIN =
CVDD/OVDD/BVDD/X1VDD/X2VDD)
IIN
—
±40
μA
2
Output high voltage (CVDD/OVDD/BVDD/X1VDD/X2VDD = min,
IOH = –2 mA)
VOH
2.0
—
V
—
Output low voltage (CVDD/OVDD/BVDD/X1VDD/X2VDD = min,
IOL = 2 mA)
VOL
—
0.4
V
—
Note:
1. Note that the min VILand max VIH values are based on the respective min and max CVIN/OVIN/BVIN/X1VIN/X2VIN values
found in Table 3.
2. Note that the symbol CVIN/OVIN/BVIN/X1VIN/X2VIN represents the input voltage of the supply. See Table 3.
This table provides the DC electrical characteristics for the PIC interface when operating at LVDD/OVDD/BVDD/CVDD = 1.8 V.
Table 52. PIC DC Electrical Characteristics (1.8 V)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
VIH
1.25
—
V
1
Input low voltage
VIL
—
0.6
V
1
Input current (CVIN/OVIN/BVIN/X1VIN/X2VIN = 0V or
CVIN/OVIN/BVIN/X1VIN/X2VIN =
CVDD/OVDD/BVDD/X1VDD/X2VDD)
IIN
—
±40
μA
2
VOH
1.35
—
V
—
Output high voltage (CVDD/OVDD/BVDD/X1VDD/X2VDD = min,
IOH = –2 mA)
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
90
Freescale Semiconductor
Electrical Characteristics
Table 52. PIC DC Electrical Characteristics (1.8 V) (continued)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
VOL
—
0.4
V
—
Output low voltage (CVDD/OVDD/BVDD/X1VDD/X2VDD = min,
IOL = 2 mA)
Note:
1. Note that the min VILand max VIH values are based on the respective min and max CVIN/OVIN/BVIN/X1VIN/X2VIN values
found in Table 3.
2. Note that the symbol CVIN/OVIN/BVIN/X1VIN/X2VIN represents the input voltage of the supply. See Table 3.
2.15.2
PIC AC Timing Specifications
This table provides the PIC input and output AC timing specifications.
Table 53. PIC Input AC Timing Specifications
For recommended operating conditions, see Table 3
Parameter
PIC inputs—minimum pulse width
Symbol
Min
Max
Unit
Note
tPIWID
3
—
SYSCLK
1
Note:
1. PIC inputs and outputs are asynchronous to any visible clock. PIC outputs should be synchronized before use by any external
synchronous logic. PIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when working in
edge-triggered mode.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
91
Electrical Characteristics
2.16
JTAG
This section describes the AC electrical specifications for the IEEE Std 1149.1™ (JTAG) interface. This section applies to both
the Power Architecture and DSP JTAG ports. The BSC9132 has multiple JTAG topology; see Section 3.11, “JTAG
Configuration Signals,” for details.
2.16.1
JTAG DC Electrical Characteristics
This table provides the JTAG DC electrical characteristics.
Table 54. JTAG DC Electrical Characteristics
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
VIH
2.1
—
V
1
Input low voltage
VIL
—
0.8
V
1
Input current (OVIN = 0V or OVIN = OVDD)
IIN
—
±40
μA
2
Output high voltage (OVDD = min, IOH = –2 mA)
VOH
2.4
—
V
—
Output low voltage (OVDD = min, IOL = 2 mA)
VOL
—
0.4
V
—
Note:
1. Note that the min VILand max VIH values are based on the respective min and max OVIN values found in Table 3
2. Note that the symbol OVIN represents the input voltage of the supply. It is referenced in Table 3.
2.16.2
JTAG AC Timing Specifications
This table provides the JTAG AC timing specifications as defined in Figure 26 through Figure 29.
Table 55. JTAG AC Timing Specifications
For recommended operating conditions see Table 3.
Symbol1
Min
Max
Unit
Note
JTAG external clock frequency of operation
fJTG
0
33.3
MHz
—
JTAG external clock cycle time
tJTG
30
—
ns
—
tJTKHKL
15
—
ns
—
tJTGR and tJTGF
0
2
ns
—
tTRST
25
—
ns
2
Input setup times
tJTDVKH
4
—
ns
—
Input hold times
tJTDXKH
10
—
ns
—
Output valid times
tJTKLDV
4
10
ns
3
Output hold times
tJTKLDX
30
—
ns
3
Parameter
JTAG external clock pulse width measured at 1.4 V
JTAG external clock rise and fall times
TRST_B assert time
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
92
Freescale Semiconductor
Electrical Characteristics
Table 55. JTAG AC Timing Specifications (continued)
For recommended operating conditions see Table 3.
Parameter
JTAG external clock to output high impedance
Symbol1
Min
Max
Unit
Note
tJTKLDZ
4
10
ns
—
Note:
1. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing
(JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to
the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D)
reaching the invalid state (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that in general, the clock
reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays
must be added for trace lengths, vias, and connectors in the system.
This figure provides the AC test load for TDO and the boundary-scan outputs.
Z0 = 50 Ω
Output
RL = 50 Ω
OVDD/2
Figure 26. AC Test Load for the JTAG Interface
This figure provides the JTAG clock input timing diagram.
JTAG
External Clock
VM
VM
VM
tJTGR
tJTKHKL
tJTGF
tJTG
VM = Midpoint Voltage (OVDD/2)
Figure 27. JTAG Clock Input Timing Diagram
This figure provides the TRST_B timing diagram.
TRST_B
VM
VM
tTRST
VM = Midpoint Voltage (OVDD/2)
Figure 28. TRST_B Timing Diagram
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
93
Electrical Characteristics
This figure provides the boundary-scan timing diagram.
JTAG
External Clock
VM
VM
tJTDVKH
tJTDXKH
Boundary
Data Inputs
Input
Data Valid
tJTKLDV
tJTKLDX
Boundary
Data Outputs
Output Data Valid
tJTKLDZ
Boundary
Data Outputs
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Figure 29. Boundary-Scan Timing Diagram
2.17
I2C
This section describes the DC and AC electrical characteristics for the two I2C interfaces. The input voltage for I2C1 is provided
by a OVDD (3.3 V) power supply, while the input voltage for I2C2 is provided by a CVDD (3.3 V/1.8 V) power supply.
2.17.1
I2C DC Electrical Characteristics
This table provides the DC electrical characteristics for the I2C interfaces operating from a 3.3 power supply.
Table 56. I2C DC Electrical Characteristics (CVDD = 3.3 V)
For recommended operating conditions, see Table 3
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
VIH
2
—
V
1
Input low voltage
VIL
—
0.8
V
1
Output low voltage
VOL
0
0.4
V
2
Pulse width of spikes which must be suppressed by the input filter
tI2KHKL
0
50
ns
3
Input current each I/O pin (input voltage is between 0.1 × OVDD and
0.9 × OVDD(max)
II
–10
10
μA
4
Capacitance for each I/O pin
CI
—
10
pF
—
Note:
1. Note that the min VILand max VIH values are based on the respective min and max CVIN values found in Table 3.
2. Output voltage (open drain or open collector) condition = 3 mA sink current.
3. See the BSC9132 QorIQ Qonverge Multicore Baseband Processor Reference Manual for information on the digital filter used.
4. I/O pins obstruct the SDA and SCL lines if OVDD is switched off.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
94
Freescale Semiconductor
Electrical Characteristics
This table provides the DC timing parameters for the I2C interface operating from a 1.8 V power supply.
Table 57. I2C DC Electrical Characteristics (CVDD = 1.8 V)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
VIH
1.25
—
V
1
Input low voltage
VIL
—
0.6
V
1
Input current (CVIN = 0 V or CVIN = CVDD)
IIN
—
±40
μA
2
Output high voltage (CVDD = mn, IOH = –2 mA)
VOH
1.35
—
V
—
Output low voltage (CVDD = min, IOL = 2 mA)
VOL
—
0.4
V
—
Note:
1. Note that the min VILand max VIH values are based on the respective min and max CVIN values found in Figure 3.
2. Note that the symbol CVIN represents the input voltage of the supply. It is referenced in Figure 3.
2.17.2
I2C AC Electrical Specifications
This table provides the AC timing parameters for the I2C interfaces.
Table 58. I2C AC Electrical Specifications
For recommended operating conditions see Table 3. All values refer to VIH (min) and VIL (max) levels (see Table 56)
Symbol1
Min
Max
Unit
Note
SCL clock frequency
fI2C
0
400
kHz
2
Low period of the SCL clock
tI2CL
1.3
—
μs
—
High period of the SCL clock
tI2CH
0.6
—
μs
—
Setup time for a repeated START condition
tI2SVKH
0.6
—
μs
—
Hold time (repeated) START condition (after this period, the first
clock pulse is generated)
tI2SXKL
0.6
—
μs
—
Data setup time
tI2DVKH
100
—
ns
—
μs
3
—
0
—
—
Parameter
Data hold time:
tI2DXKL
CBUS compatible masters
I2C bus devices
Data output delay time
tI2OVKL
—
0.9
μs
4
Set-up time for STOP condition
tI2PVKH
0.6
—
μs
—
Bus free time between a STOP and START condition
tI2KHDX
1.3
—
μs
—
Noise margin at the LOW level for each connected device
(including hysteresis)
VNL
0.1 × OVDD
—
V
—
Noise margin at the HIGH level for each connected device
(including hysteresis)
VNH
0.2 × OVDD
—
V
—
Capacitive load for each bus line
Cb
—
400
pF
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
95
Electrical Characteristics
Table 58. I2C AC Electrical Specifications (continued)
For recommended operating conditions see Table 3. All values refer to VIH (min) and VIL (max) levels (see Table 56)
Symbol1
Parameter
Min
Max
Unit
Note
Note:
1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2)
with respect to the time data input signals (D) reaching the valid state (V) relative to the tI2C clock reference (K) going to the
high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the START
condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH
symbolizes I2C timing (I2) for the time that the data with respect to the STOP condition (P) reaches the valid state (V) relative
to the tI2C clock reference (K) going to the high (H) state or setup time.
2. The requirements for I2C frequency calculation must be followed. See Freescale application note AN2919, “Determining the
I2C Frequency Divider Ratio for SCL.”
3. As a transmitter, the device provides a delay time of at least 300 ns for the SDA signal (referred to as the VIHmin of the SCL
signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of a START or STOP
condition. When the device acts as the I2C bus master while transmitting, it drives both SCL and SDA. As long as the load on
SCL and SDA are balanced, the device does not generate an unintended START or STOP condition. Therefore, the 300 ns
SDA output delay time is not a concern. If under some rare condition, the 300 ns SDA output delay time is required for the
device as transmitter, application note AN2919 referred to in note 4 below is recommended.
4. The maximum tI2OVKL has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.
This figure provides the AC test load for the I2C.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 30. I2C AC Test Load
This figure shows the AC timing diagram for the I2C bus.
SDA
tI2CF
tI2DVKH
tI2CL
tI2KHKL
tI2SXKL
tI2CF
tI2CR
SCL
tI2SXKL
S
tI2CH
tI2DXKL, tI2OVKL
tI2SVKH
tI2PVKH
Sr
P
S
Figure 31. I2C Bus AC Timing Diagram
2.18
GPIO
This section describes the DC and AC electrical specifications for the GPIO interface.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
96
Freescale Semiconductor
Electrical Characteristics
2.18.1
GPIO DC Electrical Characteristics
This table provides the DC electrical characteristics for the GPIO interface when operating from 3.3-V supply.
Table 59. GPIO DC Electrical Characteristics (3.3 V)
For recommended operating conditions, see Table 3
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
VIH
2
—
V
1
Input low voltage
VIL
—
0.8
V
1
Input current
(BVIN = 0 V or BVIN = BVDD)
IIN
—
±40
μA
2
Output high voltage
(BVDD = min, IOH = –2 mA)
VOH
2.4
—
V
—
Low-level output voltage
(BVDD = min, IOL = 2 mA)
VOL
—
0.4
V
—
Note:
1. Note that the min VILand max VIH values are based on the min and max BVIN respective values found in Table 3.
2. Note that the symbol BVIN represents the input voltage of the supply. It is referenced in Table 3.
This table provides the DC electrical characteristics for the GPIO interface when operating from 2.5-V supply.
Table 60. GPIO DC Electrical Characteristics (2.5 V)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
VIH
1.7
—
V
1
Input low voltage
VIL
—
0.7
V
1
Input current
(BVIN = 0 V or BVIN = BVDD)
IIN
—
±40
μA
2
Output high voltage
(BVDD = min, IOH = 2 mA)
VOH
1.7
—
V
—
Low-level output voltage
(BVDD = min, IOL = 2 mA)
VOL
—
0.7
V
—
Note:
1. Note that the min VILand max VIH values are based on the min and max BVIN respective values found in Table 3.
2. Note that the symbol BVIN represents the input voltage of the supply. It is referenced in Table 3.
This table provides the DC electrical characteristics for the GPIO interface when operating from 1.8-V supply.
Table 61. GPIO DC Electrical Characteristics (1.8 V)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
VIH
1.2
—
V
1
Input low voltage
VIL
—
0.6
V
1
Input current (BVIN = 0 V or BVIN = BVDD)
IIN
—
±40
μA
2
Output high voltage (BVDD = min, IOH = –0.5 mA)
VOH
1.35
—
V
—
Low-level output voltage (BVDD = min, IOL = 0.5 mA)
VOL
—
0.4
V
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
97
Electrical Characteristics
Table 61. GPIO DC Electrical Characteristics (1.8 V) (continued)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Note:
1. Note that the min VILand max VIH values are based on the min and max BVIN respective values found in Table 3.
2. Note that the symbol BVIN represents the input voltage of the supply. It is referenced in Table 3.
2.18.2
GPIO AC Timing Specifications
This table provides the GPIO input and output AC timing specifications.
Table 62. GPIO Input AC Timing Specifications
For recommended operating conditions, see Table 3
Parameter
Symbol
Min
Unit
Note
tPIWID
20
ns
1
GPIO inputs—minimum pulse width
Note:
1. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any
external synchronous logic. GPIO inputs are required to be valid for at least tPIWID to ensure proper operation.
This figure provides the AC test load for the GPIO.
Output
Z0 = 50 Ω
R L = 50 Ω
OVDD/2
Figure 32. GPIO AC Test Load
2.19
TDM
This section describes the DC and AC electrical specifications for the TDM.
2.19.1
TDM DC Electrical Characteristics
This table provides the DC electrical characteristics for the TDM interface when operating at 3.3 V.
Table 63. TDM DC Electrical Characteristics (X2VDD = 3.3 V)
For recommended operating conditions, see Table 3.
Characteristic
Symbol
Min
Max
Unit
Note
Input high voltage
VIH
2.0
—
V
1
Input low voltage
VIL
–0.3
0.8
V
1
Input current (X2VIN = 0 V or
X2VIN = X2VDD)
IIN
—
±40
μA
2
Output high voltage (X2VDD = min,
IOH = –2 mA)
VOH
2.4
—
V
—
Output low voltage (X2VDD = min, IOL = 2 mA)
VOL
—
0.4
V
—
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
98
Freescale Semiconductor
Electrical Characteristics
Table 63. TDM DC Electrical Characteristics (X2VDD = 3.3 V) (continued)
For recommended operating conditions, see Table 3.
Characteristic
Symbol
Min
Max
Unit
Note
Note:
1. Note that the min VILand max VIH values are based on the min and max X2VIN respective values found in Table 3
2. Note that the symbol X2VIN represents the input voltage of the supply. It is referenced in Table 3
This table provides the DC electrical characteristics for the TDM interface when operating at 1.8 V.
Table 64. TDM DC Electrical Characteristics (X2VDD = 1.8 V)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
VIH
1.25
—
V
1
Input low voltage
VIL
—
0.6
V
1
Input current (X2VIN = 0 V or
X2VIN = X2VDD)
IIN
—
±40
μA
2
Output high voltage (X2VDD = min,
IOH = –2 mA)
VOH
1.35
—
V
—
Output low voltage (X2VDD = min, IOL = 2 mA)
VOL
—
0.4
V
—
Note:
1. Note that the min VILand max VIH values are based on the min and max X2VIN respective values found in Table 3
2. Note that the symbol X2VIN represents the input voltage of the supply. It is referenced in Table 3
2.19.2
TDM AC Electrical Characteristics
This table provides the input and output AC timing specifications for the TDM interface.
Table 65. TDM AC Timing Specifications for 62.5 MHz1
Symbol2
Min
Max
Unit
Note
tDM
16.0
—
ns
3
TDMxRCK/TDMxTCK high pulse width
tDM_HIGH
7.0
—
ns
3
TDMxRCK/TDMxTCK low pulse width
tDM_LOW
7.0
—
ns
3
TDM all input setup time
tDMIVKH
3.6
—
ns
4, 5
TDMxRD input hold time
tDMRDIXKH
1.9
—
ns
4, 8
TDMxTFS/TDMxRFS input hold time
tDMFSIXKH
1.9
—
ns
5
TDMxTCK high to TDMxTD output active
tDM_OUTAC
2.5
—
ns
7
TDMxTCK high to TDMxTD output valid
tDMTKHOV
—
9.8
ns
7, 9
TDMxTD hold time
tDMTKHOX
2.5
—
ns
7
TDMxTCK high to TDMxTD output high impedance
tDM_OUTHI
—
9.8
ns
7
TDMxTFS/TDMxRFS output valid
tDMFSKHOV
—
9.25
ns
6
TDMxTFS/TDMxRFS output hold time
tDMFSKHOX
2.0
—
ns
6
Parameter
TDMxRCK/TDMxTCK
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
99
Electrical Characteristics
Table 65. TDM AC Timing Specifications for 62.5 MHz1 (continued)
Symbol2
Parameter
Min
Max
Unit
Note
Note: Output values are based on 30 pF capacitive load.
Note: Inputs are referenced to the sampling that the TDM is programmed to use. Outputs are referenced to the programming
edge they are programmed to use. Use of the rising edge or falling edge as a reference is programmable. tDMxTCK and
tDMxRCK are shown using the rising edge.
1. All values are based on a maximum TDM interface frequency of 62.5 MHz.
2. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the output internal
timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).
3. Relevant for all pins that function as TDM RX/TX clock—pins may be TDM_RCK and TDM_TCK, pending TDM port
configuration.
4. Relevant for all pins that function as TDM receive data—pins may be TDM_RCK, TDM_RSN, TDM_RDT, TDM_TDT, pending
TDM port configuration.
5. Relevant for all pins that function as TDM input frame sync (TX/RX)—pins may be TDM_TSN, TDM_RSN, pending TDM port
configuration.
6. Relevant for all pins that function as TDM output frame sync (TX/RX)—pins may be TDM_TSN, TDM_RSN, pending TDM port
configuration.
7. Relevant for all pins that function as TDM transmit data—pins may be TDM_RCK, TDM_RSN, TDM_RDT, TDM_TDT, pending
TDM port configuration.
8. Applies to any TDM pin that functions as Rx data (including TDMxTD and others).
9. Represents the time from the positive clock edge to the valid data on the Tx data like; it applies to any TDM pin that functions
as Tx data (including TDMxRD and others).
This figure shows the TDM receive signal timing.
tDM
tDM_HIGH
tDM_LOW
TDMxRCK
tDMIVKH
tDMRDIXKH
TDMxRD
tDMIVKH
tDMFSIXKH
TDMxRFS
tDMFSKHOV
~
~
TDMxRFS (output)
tDMFSKHOX
Figure 33. TDM Receive Signals
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
100
Freescale Semiconductor
Electrical Characteristics
This figure shows the TDM transmit signal timing.
tDM
tDM_HIGH
tDM_OUTHI
tDMTKHOV
tDM_OUTAC
TDMxTD
TDMxRCK
tDMFSKHOV
TDMxTFS (output)
tDMFSIXKH
tDMIVKH
~
~ ~
~
TDMxTCK
tDM_LOW
tDMTKHOX
tDMFSKHOX
TDMxTFS (input)
Figure 34. TDM Transmit Signals
This figure provides the AC test load for the TDM.
Output
Z0 = 50 Ω
RL = 50 Ω
VDDIO/2
Figure 35. TDM AC Test Load
2.20
High-Speed Serial Interface (HSSI) DC Electrical Characteristics
The device features an HSSI that includes one 4-channel SerDes port (lanes 0 through 3) used for high-speed serial interface
applications (PCI Express, CPRI, and SGMII). This section and its subsections describe the common portion of the SerDes DC,
including the DC requirements for the SerDes reference clocks and the SerDes data lane transmitter (Tx) and receiver (Rx)
reference circuits. The data lane circuit specifications are specific for each supported interface, and they have individual
subsections by protocol. The selection of individual data channel functionality is done via the reset configuration word. Specific
AC electrical characteristics are defined in Section 2.20.3, “HSSI AC Timing Specifications.”
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
101
Electrical Characteristics
2.20.1
SerDes
2.20.1.1
SerDes Signal Term Definitions
The SerDes interface uses differential signaling to transfer data across the serial link. This section defines terms used in the
description and specification of differential signals. Figure 36 shows how the signals are defined. Figure 36 shows the
waveform for either a transmitter output (SD_TX[0:3] and SD_TX_B[0:3]) or a receiver input (SD_RX[0:3] and
SD_RX_B[0:3]). Each signal swings between X volts and Y volts where X > Y.
SD_TX[0:3] or
SD_RX[0:3]
X Volts
Vcm = (X + Y)/2
SD_TX_B[0:3] or
SD_RX_B[0:3]
Y Volts
Differential Swing, VID or VOD = X – Y
Differential Peak Voltage, VDIFFp = |X – Y|
Differential Peak-Peak Voltage, VDIFFpp = 2 × VDIFFp (not shown)
Figure 36. Differential Voltage Definitions for Transmitter/Receiver
This table lists the definitions based on this waveform. To simplify the illustration, the definitions assume that the SerDes
transmitter and receiver operate in a fully symmetrical differential signaling environment.
Table 66. Differential Signal Definitions
Term
Definition
Single-Ended Swing
The transmitter output signals and the receiver input signals SD_TX[0:3], SD_TX_B[0:3],
SD_RX[0:3] and SD_RX_B[0:3] each have a peak-to-peak swing of X – Y volts. This is also
referred to as each signal wire’s single-ended swing.
Differential Output Voltage, VOD
(or Differential Output Swing):
The differential output voltage (or swing) of the transmitter, VOD, is defined as the difference
of the two complimentary output voltages: VSD_TX[0:3] – VSD_TX_B[0:3]. The VOD value can
be either positive or negative.
Differential Input Voltage, VID (or
Differential Input Swing)
The differential input voltage (or swing) of the receiver, VID, is defined as the difference of
the two complimentary input voltages: VSD_RX[0:3] – VSD_RX_B[0:3]. The VID value can be
either positive or negative.
Differential Peak Voltage, VDIFFp
The peak value of the differential transmitter output signal or the differential receiver input
signal is defined as the differential peak voltage, VDIFFp = |X– Y| volts.
Differential Peak-to-Peak, VDIFFp-p Since the differential output signal of the transmitter and the differential input signal of the
receiver each range from A – B to –(A – B) volts, the peak-to-peak value of the differential
transmitter output signal or the differential receiver input signal is defined as differential
peak-to-peak voltage, VDIFFp-p = 2 × VDIFFp = 2 × |(A – B)| volts, which is twice the
differential swing in amplitude, or twice of the differential peak. For example, the output
differential peak-peak voltage can also be calculated as VTX-DIFFp-p = 2 × |VOD|.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
102
Freescale Semiconductor
Electrical Characteristics
Table 66. Differential Signal Definitions (continued)
Term
Definition
Differential Waveform
The differential waveform is constructed by subtracting the inverting signal (SD_TX_B[0:3],
for example) from the non-inverting signal (SD_TX_B[0:3], for example) within a differential
pair. There is only one signal trace curve in a differential waveform. The voltage
represented in the differential waveform is not referenced to ground. Refer to Figure 36 as
an example for differential waveform.
Common Mode Voltage, Vcm
The common mode voltage is equal to half of the sum of the voltages between each
conductor of a balanced interchange circuit and ground. In this example, for SerDes output,
Vcm_out = (VSD_TX[0:3] + VSD_TX_B[0:3]) ÷ 2 = (A + B) ÷ 2, which is the arithmetic mean of
the two complimentary output voltages within a differential pair. In a system, the common
mode voltage may often differ from one component’s output to the other’s input. It may be
different between the receiver input and driver output circuits within the same component.
It is also referred to as the DC offset on some occasions.
To illustrate these definitions using real values, consider the example of a current mode logic (CML) transmitter that has a
common mode voltage of 2.25 V and outputs, TD and TD_B. If these outputs have a swing from 2.0 V to 2.5 V, the peak-to-peak
voltage swing of each signal (TD or TD_B) is 500 mV p-p, which is referred to as the single-ended swing for each signal.
Because the differential signaling environment is fully symmetrical in this example, the transmitter output differential swing
(VOD) has the same amplitude as each signal single-ended swing. The differential output signal ranges between 500 mV and
–500 mV. In other words, VOD is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage (VDIFFp)
is 500 mV. The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p.
2.20.1.2
SerDes Reference Clock Receiver Characteristics
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding
SerDes lanes. The SerDes reference clock inputs are SD_REF_CLK1/SD_REF_CLK1_B or
SD_REF_CLK2/SD_REF_CLK2_B. Figure 37 shows a receiver reference diagram of the SerDes reference clocks.
SD_REF_CLK[1–2]
50 Ω
REF_CLK
Amp
To PLL
50 Ω
SXCVSS
SD_REF_CLK[1–2]_B
Figure 37. Receiver of SerDes Reference Clocks
The characteristics of the clock signals are:
•
•
The supply voltage requirements for XCOREVDD are as specified in Table 3.
The SerDes reference clock receiver reference circuit structure is as follows:
— The SD_REF_CLK[1–2] and SD_REF_CLK[1–2]_B are internally AC-coupled differential inputs as shown in
Figure 37. Each differential clock input (SD_REF_CLK[1–2] or SD_REF_CLK[1–2]_B has on-chip 50-Ω
termination to XCOREVSS followed by on-chip AC-coupling.
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. Refer to the differential mode and
single-ended mode descriptions below for detailed requirements.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
103
Electrical Characteristics
•
•
The maximum average current requirement also determines the common mode voltage range.
— When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the
maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage
is not critical as long as it is within the range allowed by the maximum average current of 8 mA because the input
is AC-coupled on-chip.
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V / 50 = 8 mA)
while the minimum common mode input level is 0.1 V above GNDSXC. For example, a clock with a 50/50 duty
cycle can be produced by a clock driver with output driven by its current source from 0 mA to 16 mA (0–0.8 V),
such that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the common mode
voltage at 400 mV.
— If the device driving the SD_REF_CLK[1–2] and SD_REF_CLK[1–2]_B inputs cannot drive 50 Ω to GNDSXC
DC or the drive strength of the clock driver chip exceeds the maximum input current limitations, it must be
AC-coupled externally.
The input amplitude requirement is described in detail in Section 2.20.2.1, “DC-Level Requirements for SerDes
Reference Clocks.”
2.20.1.3
SerDes Transmitter and Receiver Reference Circuits
This figure shows the reference circuits for SerDes data lane transmitter and receiver.
50 Ω SD_TX[0:3]
SD_RX[0:3]
50 Ω
Transmitter
Receiver
50 Ω
SD_TX_B[0:3]
SD_RX_B[0:3]
50 Ω
Note: The [0:3] indicates the specific SerDes lane. Actual signals are assigned by the RCW assignments at reset.
Figure 38. SerDes Transmitter and Receiver Reference Circuits
2.20.1.4
SerDes Equalization
With the use of high-speed serial links, the interconnect media causes degradation of the signal at the receiver and produces
effects such as inter-symbol interference (ISI) or data-dependent jitter. This loss can be large enough to degrade the eye opening
at the receiver beyond that allowed by the specification. To offset a portion of these effects, equalization can be used. The
following is a list of the most commonly used equalization techniques:
•
•
•
Pre-emphasis on the transmitter.
A passive high-pass filter network placed at the receiver, often referred to as passive equalization.
The use of active circuits in the receiver, often referred to as adaptive equalization.
2.20.2
HSSI DC Timing Specifications
The following subsections define the DC-level requirements for the SerDes reference clocks, the PCI Express data lines, the
CPRI data lines, and the SGMII data lines.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
104
Freescale Semiconductor
Electrical Characteristics
2.20.2.1
DC-Level Requirements for SerDes Reference Clocks
The DC-level requirement for the SerDes reference clock inputs is different depending on the signaling mode used to connect
the clock driver chip and SerDes reference clock inputs, as described below:
•
Differential Mode
— The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-peak (or
between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have
a single-ended swing of less than 800 mV and greater than 200 mV. This requirement is the same for both external
DC-coupled or AC-coupled connection.
— For an external DC-coupled connection, the maximum average current requirements sets the requirement for
average voltage (common mode voltage) as between 100 mV and 400 mV. Figure 39 shows the SerDes reference
clock input requirement for DC-coupled connection scheme.
SD_REF_CLK[1–2]
200 mV < Input Amplitude or Differential Peak < 800 mV
Vmax < 800 mV
100 mV < Vcm < 400 mV
Vmin > 0 V
SD_REF_CLK[1–2]_B
Figure 39. Differential Reference Clock Input DC Requirements (External DC-Coupled)
— For an external AC-coupled connection, there is no common mode voltage requirement for the clock driver.
Because the external AC-coupling capacitor blocks the DC-level, the clock driver and the SerDes reference clock
receiver operate in different command mode voltages. The SerDes reference clock receiver in this connection
scheme has its common mode voltage set to GNDSXC. Each signal wire of the differential inputs is allowed to
swing below and above the command mode voltage GNDSXC. Figure 40 shows the SerDes reference clock input
requirement for AC-coupled connection scheme.
200 mV < Input Amplitude or Differential Peak < 800 mV
SD_REF_CLK[1–2]
Vmax < Vcm + 400 mV
Vcm
SD_REF_CLK[1–2]_B
Vmin > Vcm – 400 mV
Figure 40. Differential Reference Clock Input DC Requirements (External AC-Coupled)
•
Single-Ended Mode
— The reference clock can also be single-ended. The SD_REF_CLK[1–2] input amplitude (single-ended swing)
must be between 400 mV and 800 mV peak-peak (from VMIN to VMAX) with SD_REF_CLK[1–2]_B either left
unconnected or tied to ground.
— The SD_REF_CLK[1–2] input average voltage must be between 200 and 400 mV. Figure 41 shows the SerDes
reference clock input requirement for single-ended signaling mode.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
105
Electrical Characteristics
— To meet the input amplitude requirement, the reference clock inputs may need to be DC- or AC-coupled
externally. For the best noise performance, the reference of the clock could be DC- or AC-coupled into the unused
phase (SD_REF_CLK[1–2]_B) through the same source impedance as the clock input (SD_REF_CLK[1–2]) in
use.
400 mV < SD_REF_CLK[1–2] Input Amplitude < 800 mV
SD_REF_CLK[1–2]
0V
SD_REF_CLK[1–2]_B
Figure 41. Single-Ended Reference Clock Input DC Requirements
2.20.2.2
DC-Level Requirements for PCI Express Configurations
The DC-level requirements for PCI Express implementations have separate requirements for the Tx and Rx lines. The BSC9132
supports a 2.5 Gbps and a 5 Gbps PCI Express interface defined by the PCI Express Base Specification, Revision 2.0. The
transmitter specifications for 2.5 Gbps are defined in Table 67 and the receiver specifications are defined in Table 68. For 5
Gbps, the transmitter specifications are defined in Table 69 and the receiver specifications are defined in Table 1.
Note that specifications are valid at the recommended operating conditions listed in Table 3.
Table 67. PCI Express (2.5 Gbps) Differential Transmitter (Tx) Output DC Specifications
Parameter
Symbol
Min
Nom
Max
Unit
Condition
Differential peak-to-peak output
voltage swing
VTX-DIFFp-p
800
1000
1200
mV
VTX-DIFFp-p = 2 × |VTX-D+ – VTX-D–|,
Measured at the package pins with a
test load of 50 Ω to GND on each pin.
De-emphasized differential
output voltage (ratio)
VTX-DE-RATI
3.0
3.5
4.0
dB
Ratio of the VTX-DIFFp-p of the second
and following bits after a transition
divided by the VTX-DIFFp-p of the first
bit after a transition.
Measured at the package pins with a
test load of 50 Ω to GND on each pin.
DC differential Tx impedance
ZTX-DIFF-DC
80
100
120
Ω
Tx DC differential mode low
Impedance
ZTX-DC
40
50
60
Ω
Required Tx D+ as well as D– DC
Impedance during all states
O
DC single-ended TX impedance
Table 68. PCI Express (2.5 Gbps) Differential Receiver (Rx) Input DC Specifications
Parameter
Symbol
Min
Nom
Max
Unit
Note
Differential input peak-to-peak voltage
VRX-DIFFp-p
120
1000
1200
mV
1
DC differential Input Impedance
ZRX-DIFF-DC
80
100
120
Ω
2
ZRX-DC
40
50
60
Ω
3
ZRX-HIGH-IMP-DC
50
—
—
KΩ
4
VRX-IDLE-DET-DIFFp-p
65
—
175
mV
5
DC input impedance
Powered down DC input impedance
Electrical idle detect threshold
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
106
Freescale Semiconductor
Electrical Characteristics
Table 68. PCI Express (2.5 Gbps) Differential Receiver (Rx) Input DC Specifications (continued)
Parameter
Symbol
Min
Nom
Max
Unit
Note
Note:
1. VRX-DIFFp-p = 2 × |VRX-D+ – VRX-D-| Measured at the package pins with a test load of 50 Ω to GND on each pin.
2. Rx DC differential mode impedance. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect
(the initial state of the LTSSM), there is a 5 ms transition time before the receiver termination values must be met on all
unconfigured lanes of a port.
3. Required Rx D+ as well as D– DC Impedance (50 ±20% tolerance). Measured at the package pins with a test load of 50 Ω to GND
on each pin. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the
LTSSM), there is a 5 ms transition time before the receiver termination values must be met on all unconfigured lanes of a port.
4. Required Rx D+ as well as D– DC Impedance when the receiver terminations do not have power. The Rx DC common mode
impedance that exists when no power is present or fundamental reset is asserted. This helps ensure that the receiver detect circuit
does not falsely assume a receiver is powered on when it is not. This term must be measured at 300 mV above the Rx ground.
5. VRX-IDLE-DET-DIFFp-p = 2 × |VRX-D+ – VRX-D–|. Measured at the package pins of the receiver.
Table 69. PCI Express (5 Gbps) Differential Transmitter (Tx) Output DC Specifications
Parameter
Symbol
Min
Nom
Max
Unit
VTX-DIFFp-p
800
1000
1200
mV
VTX-DIFFp-p = 2 × |VTX-D+ – VTX-D–|,
Measured at the package pins with a
test load of 50 Ω to GND on each pin.
Low power differential
peak-to-peak output voltage
swing
VTX-DIFFp-p_low
400
500
1200
mV
VTX-DIFFp-p = 2 × |VTX-D+ – VTX-D–|,
Measured at the package pins with a
test load of 50 Ω to GND on each pin.
De-emphasized differential
output voltage (ratio)
VTX-DE-RATIO-3.5d
3.0
3.5
4.0
dB
Ratio of the VTX-DIFFp-p of the second
and following bits after a transition
divided by the VTX-DIFFp-p of the first bit
after a transition.
Measured at the package pins with a
test load of 50 Ω to GND on each pin.
De-emphasized differential
output voltage (ratio)
VTX-DE-RATIO-6.0d
5.5
6.0
6.5
dB
Ratio of the VTX-DIFFp-p of the second
and following bits after a transition
divided by the VTX-DIFFp-p of the first bit
after a transition.
Measured at the package pins with a
test load of 50 Ω to GND on each pin.
ZTX-DIFF-DC
80
100
120
Ω
Tx DC differential mode low impedance
ZTX-DC
40
50
60
Ω
Required Tx D+ as well as D– DC
impedance during all states
Differential peak-to-peak
output voltage swing
B
B
DC differential Tx impedance
Transmitter DC impedance
Condition
Table 1. PCI Express (5 Gbps) Differential Receiver (Rx) Input DC Specifications
Parameter
Symbol
Min
Nom
Max
Unit
Note
Differential input peak-to-peak voltage
VRX-DIFFp-p
120
1000
1200
mV
1
DC differential Input Impedance
ZRX-DIFF-DC
80
100
120
Ω
2
ZRX-DC
40
50
60
Ω
3
ZRX-HIGH-IMP-DC
50
—
—
ΚΩ
4
VRX-IDLE-DET-DIFFp-p
65
—
175
mV
5
DC input impedance
Powered down DC input impedance
Electrical idle detect threshold
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
107
Electrical Characteristics
Table 1. PCI Express (5 Gbps) Differential Receiver (Rx) Input DC Specifications (continued)
Parameter
Symbol
Min
Nom
Max
Unit
Note
Note:
1. VRX-DIFFp-p = 2 × |VRX-D+ – VRX-D-| Measured at the package pins with a test load of 50 Ω to GND on each pin.
2. Rx DC differential mode impedance. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect
(the initial state of the LTSSM), there is a 5 ms transition time before the receiver termination values must be met on all
unconfigured lanes of a port.
3. Required Rx D+ as well as D– DC Impedance (50 ±20% tolerance). Measured at the package pins with a test load of 50 Ω to GND
on each pin. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the
LTSSM), there is a 5 ms transition time before the receiver termination values must be met on all unconfigured lanes of a port.
4. Required Rx D+ as well as D– DC Impedance when the receiver terminations do not have power. The Rx DC common mode
impedance that exists when no power is present or fundamental reset is asserted. This helps ensure that the receiver detect circuit
does not falsely assume a receiver is powered on when it is not. This term must be measured at 300 mV above the Rx ground.
5. VRX-IDLE-DET-DIFFp-p = 2 × |VRX-D+ – VRX-D–|. Measured at the package pins of the receiver.
2.20.2.3
DC-Level Requirements for CPRI Configurations
This section provide various DC-level requirements for CPRI Configurations. Specifications are valid at the recommended
operating conditions listed in Table 3.
Table 70. CPRI Transmitter DC Specifications (LV: 1.2288, 2.4576 and 3.072 Gbps)
Parameter
Symbol
Min
Nom
Max
Unit
Condition
VO
–0.40
—
2.30
V
Voltage relative to COMMON of either signal
comprising a differential pair.
VDIFFPP
800
—
1600
mVp-p
T_Rd
80
100
120
Ω
Output voltage
Differential output voltage
Differential resistance
L[0:3]TECR0[AMP_RED] = 0b000000.
—
Note: LV is XAUI-based.
Table 71. CPRI Transmitter DC Specifications (LV-II: 1.2288, 2.4576, 3.072, 4.9152, and 6.144 Gbps)
Parameter
Output differential voltage (into
floating load Rload = 100 Ω)
Differential resistance
Symbo
l
Min
Nom
Max
Unit
T_Vdiff
800
—
1200
mV
T_Rd
80
100
120
Ω
Condition
L[0:3]TECR0[AMP_RED] = 0x000000
—
Note: LV-II is CEI-6G-LR-based.
Table 72. CPRI Receiver DC Specifications (LV: 1.2288, 2.4576 and 3.072 Gbps)
Parameter
Differential input voltage
Difference resistance
Symbol
Min
Nom
Max
Unit
VIN
200
—
1600
mVp-p
R_Rdin
80
—
120
Ω
Condition
Measured at receiver.
—
Note: LV is XAUI-based.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
108
Freescale Semiconductor
Electrical Characteristics
Table 73. CPRI Receiver DC Specifications (LV-II: 1.2288, 2.4576, 3.072, 4.9152, and 6.144 Gbps)
Parameter
Symbol
Min
Nom
Max
Unit
Condition
Input differential voltage
R_Vdiff
N/A
—
1200
mV
It is assumed that for the R_Vdiff min
specification, that the eye can be
closed at the receiver after passing the
signal through a CEI/CPRI Level II LR
compliant channel.
Differential resistance
R_Rdin
80
—
120
Ω
—
Note: LV-II is CEI-6G-LR-based.
2.20.2.4
DC-Level Requirements for SGMII Configurations
Table 74 describes the SGMII SerDes transmitter AC-coupled DC electrical characteristics. Specifications are valid at the
recommended operating conditions listed in Table 3.
Table 74. SGMII DC Transmitter Electrical Characteristics
Symbo
l
Min
Nom
Max
Unit
Conditions
Output
differential
voltage
|VOD|
0.64 × Nom
500
1.45 × Nom
mV
• The |VOD| value shown in the Typ column is based
on the condition of XVDD_SRDS2-Typ = 1.0 V, no
common mode offset variation (VOS = 500mV),
SerDes transmitter is terminated with 100-Ω
differential load between SD_TXn and SD_TX_Bn.
• Amplitude setting:
L[0:3]TECR0[AMD_RED] = 0b000000
Output
differential
voltage
|VOD|
0.64 × Nom
459
1.45 × Nom
mV
• The |VOD| value shown in the Typ column is based
on the condition of XVDD_SRDS2-Typ = 1.0V, no
common mode offset variation (VOS = 500mV),
SerDes transmitter is terminated with 100-Ω
differential load between SD_TXn and SD_TX_Bn.
• Amplitude setting:
L[0:3]TECR0[AMD_RED] = 0b000010
Output
differential
voltage
|VOD|
0.64 × Nom
417
1.45 × Nom
mV
• The |VOD| value shown in the Typ column is based
on the condition of XVDD_SRDS2-Typ = 1.0V, no
common mode offset variation (VOS = 500mV),
SerDes transmitter is terminated with 100-Ω
differential load between SD_TXn and SD_TX_Bn.
• Amplitude setting:
L[0:3]TECR0[AMD_RED] = 0b000101
Output
differential
voltage
|VOD|
0.64 × Nom
376
1.45 × Nom
mV
• The |VOD| value shown in the Typ column is based
on the condition of XVDD_SRDS2-Typ = 1.0V, no
common mode offset variation (VOS = 500mV),
SerDes transmitter is terminated with 100-Ω
differential load between SD_TXn and SD_TX_Bn.
• Amplitude setting:
L[0:3]TECR0[AMD_RED] = 0b001000
Parameter
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
109
Electrical Characteristics
Table 74. SGMII DC Transmitter Electrical Characteristics (continued)
Symbo
l
Min
Nom
Max
Unit
Conditions
Output
differential
voltage
|VOD|
0.64 × Nom
333
1.45 × Nom
mV
• The |VOD| value shown in the Typ column is based
on the condition of XVDD_SRDS2-Typ = 1.0V, no
common mode offset variation (VOS = 500mV),
SerDes transmitter is terminated with 100-Ω
differential load between SD_TXn and SD_TX_Bn.
• Amplitude setting:
L[0:3]TECR0[AMD_RED] = 0b001100
Output
differential
voltage
|VOD|
0.64 × Nom
292
1.45 × Nom
mV
• The |VOD| value shown in the Typ column is based
on the condition of XVDD_SRDS2-Typ=1.0V, no
common mode offset variation (VOS =500mV),
SerDes transmitter is terminated with 100-Ω
differential load between SD_TXn and SD_TX_Bn.
• Amplitude setting:
L[0:3]TECR0[AMD_RED] = 0b001111
Output
differential
voltage
|VOD|
0.64 × Nom
250
1.45 × Nom
mV
• The |VOD| value shown in the Typ column is based
on the condition of XVDD_SRDS2-Typ=1.0V, no
common mode offset variation (VOS =500mV),
SerDes transmitter is terminated with 100-Ω
differential load between SD_TXn and SD_TX_Bn.
• Amplitude setting:
L[0:3]TECR0[AMD_RED] = 0b010011
Output
impedance
(single-ended)
RO
40
50
60
Ω
—
Output high
voltage
VOH
—
—
1.5 × |VOD,
max|
mV
—
Output low
voltage
VOL
|VOD|, min/2
—
—
mV
—
Parameter
Table 75 describes the SGMII SerDes receiver AC-coupled DC electrical characteristics.
Table 75. SGMII DC Receiver Electrical Characteristics1,2
Parameter
Input differential
Loss of signal
voltage3
threshold4
Receiver differential input
impedance
Symbol
Min
Nom
Max
Unit
VRX_DIFFp-p
100
—
1200
mV
L[0:3]GCR1[RECTL_SIGD] = 0b001
175
—
1200
mV
L[0:3]GCR1[RECTL_SIGD] = 0b100
30
—
100
mV
L[0:3]GCR1[RECTL_SIGD] = 0b001
65
—
175
mV
L[0:3]GCR1[RECTL_SIGD] = 0b100
80
—
120
Ω
VLOS
ZRX_DIFF
Condition
—
Note:
1. The supply voltage is 1.0 V.
2. Input must be externally AC-coupled.
3. VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage.
4. The concept of this parameter is equivalent to the Electrical Idle Detect Threshold parameter in the PCI Express interface.
Refer to the PCI Express Differential Receiver (RX) Input Specifications section of the PCI Express Specification document.
for details.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
110
Freescale Semiconductor
Electrical Characteristics
2.20.3
HSSI AC Timing Specifications
The following subsections define the AC timing requirements for the SerDes reference clocks, the PCI Express data lines, and
the SGMII data lines.
2.20.3.1
AC-Level Requirements for SerDes Reference Clock
Table 76 lists AC requirements for the SerDes reference clocks.
Table 76. SD_REF_CLK[1–2] and SD_REF_CLK[1–2]_B Input Clock Requirements
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Nom
Max
Unit
Note
SD_REF_CLK[1–2]/SD_REF_CLK[1–2]_B
frequency range
tCLK_REF
—
100/125
CPRI: 122.88
—
MHz
1
SD_REF_CLK[1–2]/SD_REF_CLK[1–2]_B
clock frequency tolerance
CPRI, SGMII
PCI Express interface
tCLK_TOL
SD_REF_CLK[1–2]/SD_REF_CLK[1–2]_B
reference clock duty cycle
—
–100
–300
—
—
100
300
ppm
ppm
tCLK_DUTY
40
50
60
%
4
SD_REF_CLK[1–2]/SD_REF_CLK[1–2]_B max
deterministic peak-peak jitter at 10-6 BER
tCLK_DJ
—
—
42
ps
—
SD_REF_CLK[1–2]/SD_REF_CLK[1–2]_B total
reference clock jitter at 10-6 BER (peak-to-peak
jitter at ref_clk input)
tCLK_TJ
—
—
86
ps
2
tCLKRR/tCLKFR
1
—
4
V/ns
3
Differential input high voltage
VIH
200
—
—
mV
4
Differential input low voltage
VIL
—
—
–200
mV
4
Rise-Fall
—
—
20
%
5, 6
SD_REF_CLK/SD_REF_CLK_B rising/falling
edge rate
Rising edge rate (SD_REF_CLKn to falling edge
rate)
Note:
1 Only 100, 122.88, and 125 MHz have been tested. CPRI uses 122.88 MHz. The other interfaces use 100 or 125 MHz. Other
values will not work correctly with the rest of the system.
2 Limits are from PCI Express CEM Rev 2.0.
3
Measured from –200 mV to +200 mV on the differential waveform (derived from SD_REF_CLKn minus SD_REF_CLKn_B).
The signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is
centered on the differential zero crossing. See Figure 42.
4 Measurement taken from differential waveform.
5
Measurement taken from single-ended waveform.
6 Matching applies to rising edge for SD_REF_CLKn and falling edge rate for SD_REF_CLKn_B. It is measured using a 200
mV window centered on the median cross point where SD_REF_CLKn rising meets SD_REF_CLKn_B falling. The median
cross point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The rising
edge rate of SD_RF_CLKn should be compared to the falling edge rate of SD_REF_CLKn_B; the maximum allowed
difference should not exceed 20% of the slowest edge rate. See Figure 43.
7 REF_CLK jitter must be less than 0.05 UI when measured against a Golden PLL reference. The Golden PLL must have a
maximum baud rate bandwidth greater than 1667, with a maximum 20 dB/dec rolloff down to a baud rate of 16.67 with no
peaking around the corner frequency.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
111
Electrical Characteristics
Rise Edge Rate
Fall Edge Rate
VIH = +200 mV
0.0 V
VIL = –200 mV
SD_REF_CLKn –
SD_REF_CLKn_B
Figure 42. Differential Measurement Points for Rise and Fall Time
Figure 43. Single-Ended Measurement Points for Rise and Fall Time Matching
2.20.3.2
Spread Spectrum Clock
SD_REF_CLK[1–2] and SD_REF_CLK[1–2]_B were designed to work with a spread spectrum clock (+0 to 0.5% spreading
at 30–33 KHz rate is allowed), assuming both ends have the same reference clock and the industry protocol supports it. For
better results, use a source without significant unintended modulation.
2.20.3.3
PCI Express AC Physical Layer Specifications
The AC requirements for PCI Express implementations have separate requirements for the Tx and Rx lines. The BSC9132
supports a 2.5 Gbps or a 5.0 Gbps PCI Express interface defined by the PCI Express Base Specification, Revision 2.0. The 2.5
Gbps transmitter specifications are defined in Table 77 and the receiver specifications are defined in Table 78. The 5.0 Gbps
transmitter specifications are defined in Table 79 and the receiver specifications are defined in Table 80. The parameters are
specified at the component pins. the AC timing specifications do not include REF_CLK jitter.
Table 77. PCI Express 2.0 (2.5 Gbps) Differential Transmitter (Tx) Output AC Specifications
For recommended operating conditions, see Table 3.
Parameter
Unit interval
Symbol
UI
Min
Nom
Max
399.88 400.00 400.12
Unit
Comments
ps
Each UI is 400 ps ± 300 ppm. UI does not
account for spread spectrum clock dictated
variations. See note 1.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
112
Freescale Semiconductor
Electrical Characteristics
Table 77. PCI Express 2.0 (2.5 Gbps) Differential Transmitter (Tx) Output AC Specifications (continued)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Nom
Max
Unit
TTX-EYE
0.75
—
—
UI
The maximum transmitter jitter can be
derived as TTX-MAX-JITTER = 1 – TTX-EYE =
0.25 UI. This does not include spread
spectrum or REF_CLK jitter. It includes
device random jitter at 10–12. See notes 2
and 3.
Time between the jitter
median and maximum
deviation from the
median.
TTX-EYE-MEDIAN-
—
—
0.125
UI
Jitter is defined as the measurement
variation of the crossing points (VTX-DIFFp-p
= 0 V) in relation to a recovered Tx UI. A
recovered Tx UI is calculated over 3500
consecutive unit intervals of sample data.
Jitter is measured using all edges of the 250
consecutive UI in the center of the 3500 UI
used for calculating the Tx UI. See notes 2
and 3.
AC coupling capacitor
CTX
75
—
200
nF
All transmitters must be AC coupled. The AC
coupling is required either within the media
or within the transmitting component itself.
See note 4.
Tx eye width
to-MAX-JITTER
Comments
Note:
1 No test load is necessarily associated with this value.
2 Specified at the measurement point into a timing and voltage test load as shown in Figure 47 and measured over any 250
consecutive Tx UIs.
3 AT
TX-EYE = 0.75 UI provides for a total sum of deterministic and random jitter budget of TTX-NAX-JITTER = 0.25 UI for the
transmitter collected over any 250 consecutive Tx UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total
Tx jitter budget collected over any 250 consecutive Tx UIs. It should be noted that the median is not the same as the mean.
The jitter median describes the point in time where the number of jitter points on either side is approximately equal as
opposed to the averaged time value.
4 The DSP device SerDes transmitter does not have a built-in C . An external AC coupling capacitor is required.
TX
Table 78. PCI Express 2.0 (2.5 Gbps) Differential Receiver (Rx) Input AC Specifications
Parameter
Symbol
Unit Interval
UI
Minimum receiver eye
width
Maximum time between
the jitter median and
maximum deviation from
the median.
Min
Nom
Max
399.88 400.00 400.12
Unit
Comments
ps
Each UI is 400 ps ± 300 ppm. UI does not account
for spread spectrum clock dictated variations. See
note 1.
TRX-EYE
0.4
—
—
UI
The maximum interconnect media and Transmitter
jitter that can be tolerated by the Receiver can be
derived as TRX-MAX-JITTER = 1 – TRX-EYE= 0.6 UI.
See notes 2 and 3.
TRX-EYE-MEDIAN-
—
—
0.3
UI
Jitter is defined as the measurement variation of
the crossing points (VRX-DIFFp-p = 0 V) in relation to
a recovered Tx UI. A recovered Tx UI is calculated
over 3500 consecutive unit intervals of sample
data. Jitter is measured using all edges of the 250
consecutive UI in the center of the 3500 UI used for
calculating the Tx UI.
See notes 2, 3, and 4.
to-MAX-JITTER
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
113
Electrical Characteristics
Table 78. PCI Express 2.0 (2.5 Gbps) Differential Receiver (Rx) Input AC Specifications (continued)
Parameter
Symbol
Min
Nom
Max
Unit
Comments
Note:
1
No test load is necessarily associated with this value.
2
Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 47 should be used as the
Rx device when taking measurements. If the clocks to the Rx and Tx are not derived from the same reference clock, the Tx UI
recovered from 3500 consecutive UI must be used as a reference for the eye diagram.
3
A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the Transmitter and interconnect
collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the
median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any 250 consecutive
Tx UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the
number of jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the Rx and Tx
are not derived from the same reference clock, the Tx UI recovered from 3500 consecutive UI must be used as the reference for
the eye diagram.
4
It is recommended that the recovered Tx UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm using
a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated data.
Table 79. PCI Express 2.0 (5.0 Gbps) Differential Transmitter (Tx) Output AC Specifications
Parameter
Unit Interval
Symbol
UI
Min
Nom
Max
199.94 200.00 200.06
Unit
Comments
ps
Each UI is 400 ps ± 300 ppm. UI does not
account for spread spectrum clock dictated
variations. See note 1.
Minimum Tx eye width
TTX-EYE
0.75
—
—
UI
The maximum Transmitter jitter can be
derived as:
TTX-MAX-JITTER = 1 – TTX-EYE = 0.25 UI.
See notes 2 and 3.
Tx RMS deterministic
jitter > 1.5 MHz
TTX-HF-DJ-DD
—
—
0.15
ps
—
Tx RMS deterministic
jitter < 1.5 MHz
TTX-LF-RMS
—
3.0
—
ps
Reference input clock RMS jitter
(< 1.5 MHz) at pin < 1 ps
AC coupling capacitor
CTX
75
—
200
nF
All transmitters must be AC coupled. The AC
coupling is required either within the media
or within the transmitting component itself.
See note 4.
Note:
1 No test load is necessarily associated with this value.
2 Specified at the measurement point into a timing and voltage test load as shown in Figure 47 and measured over any 250
consecutive Tx UIs.
3 AT
TX-EYE = 0.75 UI provides for a total sum of deterministic and random jitter budget of TTX-MAX-JITTER = 0.25 UI for the
Transmitter collected over any 250 consecutive Tx UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total
Tx jitter budget collected over any 250 consecutive Tx UIs. It should be noted that the median is not the same as the mean.
The jitter median describes the point in time where the number of jitter points on either side is approximately equal as
opposed to the averaged time value.
4
The DSP device SerDes transmitter does not have a built-in CTX. An external AC coupling capacitor is required.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
114
Freescale Semiconductor
Electrical Characteristics
Table 80. PCI Express 2.0 (5.0 Gbps) Differential Receiver (Rx) Input AC Specifications
Parameter
Symbol
Unit Interval
Min
UI
Nom
Max
199.40 200.00 200.06
Unit
Conditions
ps
Each UI is 400 ps ±300 ppm. UI does not
account for spread spectrum clock dictated
variations. See Note 1.
Max Rx inherent timing
error
TRX-TJ-CC
—
—
0.4
UI
The maximum inherent total timing error for
common REF_CLK Rx architecture
Maximum time between
the jitter median and
maximum deviation from
the median
TRX-TJ-DC
—
—
0.34
UI
Max Rx inherent total timing error
Max Rx inherent
deterministic timing error
TRX-DJ-DD-CC
—
—
0.30
UI
The maximum inherent deterministic timing
error for common REF_CLK Rx architecture
Max Rx inherent
deterministic timing error
TRX-DJ-DD-DC
—
—
0.24
UI
The maximum inherent deterministic timing
error for common REF_CLK Rx architecture
Note: No test load is necessarily accosted with this value.
2.20.3.4
CPRI AC Timing Specifications
Table 81 defines the transmitter AC specifications for the CPRI LV lanes. The AC timing specifications do not include
REF_CLK jitter.
Table 81. CPRI Transmitter AC Timing Specifications (LV-I: 1.2288, 2.4576, and 3.072 Gbps)
For recommended operating conditions, see Table 3.
Characteristic
Symbol
Min
Nom
Max
Unit
Deterministic Jitter
JD
—
—
0.17
UI p-p
Total Jitter
JT
—
—
0.35
UI p-p
Unit Interval: 1.2288 GBaud
UI
1/1228.8 –
100ppm
1/1228.8
1/1228.8 + 100ppm
µs
Unit Interval: 2.4576 GBaud
UI
1/2457.6 –
100ppm
1/2457.6
1/2457.6 + 100ppm
µs
Unit Interval: 3.072 GBaud
UI
1/3072.0 –
100ppm
1/3072.0
1/3072.0 + 100ppm
µs
Table 82 defines the transmitter AC specifications for the CPRI LV-II lanes. The AC timing specifications do not include
REF_CLK jitter.
Table 82. CPRI Transmitter AC Timing Specifications (LV-II: 1.2288, 2.4576, 3.072, 4.9152, and 6.144 Gbps)
For recommended operating conditions, see Table 3.
Characteristic
Symbol
Min
Nom
Max
Unit
Uncorrelated High Probability Jitter
T_UHPJ
—
—
0.15
UI p-p
T_TJ
—
—
0.30
UI p-p
Unit Interval: 1.2288 GBaud
UI
1/1228.8 –
100ppm
1/1228.8
1/1228.8 + 100ppm
µs
Unit Interval: 2.4576 GBaud
UI
1/2457.6 – 100ppm
1/2457.6
1/2457.6 + 100ppm
µs
Unit Interval: 3.072 GBaud
UI
1/3072.0 – 100ppm
1/3072.0
1/3072.0 + 100ppm
µs
Total Jitter
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
115
Electrical Characteristics
Table 82. CPRI Transmitter AC Timing Specifications (LV-II: 1.2288, 2.4576, 3.072, 4.9152, and 6.144 Gbps)
For recommended operating conditions, see Table 3.
Characteristic
Symbol
Min
Nom
Max
Unit
Unit Interval: 4.9152 GBaud
UI
1/4915.2 – 100ppm
1/4915.2.8
1/4915.2 + 100ppm
µs
Unit Interval: 6.144 GBaud
UI
1/6144.0 – 100ppm
1/6144.0
1/6144.0 + 100ppm
µs
Table 83 defines the Receiver AC specifications for CPRI LV. The AC timing specifications do not include REF_CLK jitter.
Table 83. CPRI Receiver AC Timing Specifications (LV-I: 1.2288, 2.4576, and 3.072 Gbps)
For recommended operating conditions, see Table 3.
Characteristic
Symbol
Min
Nom
Max
Unit
Deterministic jitter tolerance
JD
—
—
0.37
UI p-p
Combined deterministic and
random jitter tolerance
JDR
—
—
0.55
UI p-p
Total Jitter tolerance
JT
—
—
0.65
UI p-p
Unit Interval: 1.2288 GBaud
UI
1/1228.8 – 100ppm
1/1228.8
1/1228.8 + 100ppm
ps
Unit Interval: 2.4576 GBaud
UI
1/2457.6 – 100ppm
1/2457.6
1/2457.6 + 100ppm
ps
Unit Interval: 3.072 GBaud
UI
1/3072.0 – 100ppm
1/3072.0
1/3072.0 + 100ppm
ps
—
10–12
—
Bit error ratio
BER
—
Table 84 defines the Receiver AC specifications for CPRI LV-II. The AC timing specifications do not include REF_CLK jitter.
Table 84. CPRI Receiver AC Timing Specifications (LV-II: 1.2288, 2.4576, 3.072, 4.9152, and 6.144 Gbps)
For recommended operating conditions, see Table 3.
Characteristic
Symbol
Min
Nom
Max
Unit
R_GJ
—
—
0.275
UI p-p
Uncorrelated bounded high
probability jitter
R_UBHPJ
—
—
0.150
UI p-p
Correlated bounded high
probability jitter
R_CBHPJ
—
—
0.525
UI p-p
R_BHPJ
—
—
0.675
UI p-p
R_SJ-max
—
—
5.000
UI p-p
R_SJ-hf
—
—
0.050
UI p-p
Total Jitter (does not include
sinusoidal jitter).
R_TJ
—
—
0.950
UI p-p
Unit Interval: 1.2288 GBaud
UI
1/1228.8 – 100ppm
1/1228.8
1/1228.8 + 100ppm
µs
Unit Interval: 2.4576 GBaud
UI
1/2457.6 – 100ppm
1/2457.6
1/2457.6 + 100ppm
µs
Unit Interval: 3.072 GBaud
UI
1/3072.0 – 100ppm
1/3072.0
1/3072.0 + 100ppm
µs
Unit Interval: 4.9152 GBaud
UI
1/4915.2 – 100ppm
1/4915.2.8
1/4915.2 + 100ppm
µs
Unit Interval: 6.144 GBaud
UI
1/6144.0 – 100ppm
1/6144.0
1/6144.0 + 100ppm
µs
Gaussian
Bounded high probability jitter
Sinusoidal jitter, maximum
Sinusoidal jitter, high frequency
Note: The AC specifications do not include REF_CLK jitter. The sinusoidal jitter in the total jitter tolerance may have any
amplitude and frequency in the unshaded region of Figure 46. The ISl jitter (R_CBHPJ) and amplitude have to be
correlated, for example, by a PC trace.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
116
Freescale Semiconductor
Electrical Characteristics
NOTE
The intended application is a point-to-point interface up to two connectors. The maximum
allowed total loss (channel + interconnects + other loss) is 20.4 dB @ 6.144 Gbps.
2.20.3.5
SGMII AC Timing Specifications
Table 85 provides the SGMII transmit AC timing specifications. The AC timing specifications do not include REF_CLK jitter.
Table 85. SGMII Transmit AC Timing Specifications
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Nom
Max
Unit
Unit interval
UI
800 – 100ppm
800
800 + 100ppm
pS
Deterministic jitter
JD
—
—
0.17
UI p-p —
Total jitter
JT
—
—
0.35
UI p-p —
CTX
75
—
200
AC coupling capacitor
Note:
Condition
± 100ppm
nF
All transmitters must be
AC-coupled
The AC specifications do not include REF_CLK jitter.
Table 86 provides the SGMII receiver AC timing specifications. The AC timing specifications do not include REF_CLK jitter.
Table 86. SGMII Receive AC Timing Specifications
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Nom
Max
Unit
Unit interval
UI
800 – 100ppm
800
800 + 100ppm
pS
Deterministic jitter tolerance
JD
—
—
0.37
UI p-p Measured at receiver.
Combined deterministic and
random jitter tolerance
JDR
—
—
0.55
UI p-p Measured at receiver
JT
—
—
0.65
UI p-p Measured at receiver
—
10–12
Total jitter tolerance
Bit error ratio
BER
—
—
Condition
± 100ppm
—
Note: The AC specifications do not include REF_CLK jitter. The sinusoidal jitter in the total jitter tolerance may have any
amplitude and frequency in the unshaded region shown in Figure 44 or Figure 45.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
117
Electrical Characteristics
8.5 UIp-p
Sinusoidal
Jitter
Amplitude
20 dB/dec
0.10 UIp-p
baud/14200
Frequency
baud/1667
20 MHz
Figure 44. Single Frequency Sinusoidal Jitter Limits for Baud Rate <3.125 Gbps
8.5 UIp-p
Sinusoidal
Jitter
Amplitude
0.10 UIp-p
22.1 kHz
Frequency
1.875 MHz
20 MHz
Figure 45. Single Frequency Sinusoidal Jitter Limits for Baud Rate 3.125 Gbps
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
118
Freescale Semiconductor
Electrical Characteristics
5 UI p-p
Sinusoidal
Jitter
Amplitude
0.05 UI p-p
22.1 kHz
Frequency
2.999 MHz
20 MHz
Figure 46. Single Frequency Sinusoidal Jitter Limits for Baud Rate 5.0 Gbps
2.20.3.6
Compliance Test and Measurement Load
Transmitter and receiver AC characteristics are measured at the transmitter outputs (SD_TXn and SD_TX_Bn) or at the receiver
inputs (SD_RXn and SD_RXn_B). The AC timing and voltage parameters must be verified at the measurement point, as
specified within 0.2 inches of the package pins, into a test/measurement load shown in Figure 47.
NOTE
The allowance of the measurement point to be within 0.2 inches of the package pins is
meant to acknowledge that package/board routing may benefit from D+ and D– not being
exactly matched in length at the package pin boundary. If the vendor does not explicitly
state where the measurement point is located, the measurement point is assumed to be the
D+ and D– package pins.
D+ Package
Pin
C = CTX
TX
Silicon
+ Package
D– Package
Pin
C = CTX
R = 50Ω
R = 50Ω
Figure 47. Compliance Test/Measurement Load
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
119
Electrical Characteristics
2.21
Radio Frequency (RF) Interface
2.21.1
RF Parallel Interface
The BSC9132 has an RF parallel interface.
2.21.1.1
RF Parallel Interface DC Electrical Characteristics (eSPI2)
2.21.1.1.1
RF Parallel Interface DC Data Path
Table 87 provides the DC electrical characteristics for the RF parallel interface when operating at 3.3 V.
Table 87. RF Parallel Interface DC Electrical Characteristics (X1VDD, X2VDD = 3.3 V)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
VIH
2
—
V
1
Input low voltage
VIL
—
0.8
V
1
Input current
(X1VIN/X2VIN = 0 V or X1VIN/X2VIN = X1VDD/X2VDD)
IIN
—
±40
μA
2
Output high voltage
(X1VDD/X2VDD = min, IOH = –2 mA)
VOH
2.8
—
V
—
Output low voltage
(X1VDD/X2VDD = min, IOL = 2 mA)
VOL
—
0.3
V
—
Note:
1. Note that the min VILand max VIH values are based on the respective min and max X1VIN/X2VIN values found in Table 3.
2. Note that the symbol X1VIN/X2VIN represent the input voltage of the power supplies. It is referenced in Table 3.
Table 88 provides the DC electrical characteristics for the RF interface when operating at 1.8 V.
Table 88. RF Parallel Interface DC Electrical Characteristics (X1VDD, X2VDD = 1.8 V)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
VIH
1.25
—
V
1
Input low voltage
VIL
—
0.6
V
1
Input current (X1VIN/X2VIN = 0 V or X1VIN/X2VIN = X1VDD/X2VDD)
IIN
—
±40
μA
2
Output high voltage (X1VDD/X2VDD = min, IOH = –2 mA)
VOH
1.35
—
V
—
Output low voltage (X1VDD/X2VDD = min, IOL = 2 mA)
VOL
—
0.4
V
—
Note:
1. Note that the min VILand max VIH values are based on the respective min and max X1VIN/X2VIN values found in Table 3.
2. Note that the symbol X1VIN/X2VIN represents the input voltage of the supply. It is referenced in Table 3.
2.21.1.1.2
RF Parallel Interface DC Control Plane
See Table 29 in Section 2.9.1, “eSPI1 DC Electrical Characteristics,” for the DC specs for eSPI2, powered by X2VDD = 1.8 V.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
120
Freescale Semiconductor
Electrical Characteristics
2.21.1.2
2.21.1.2.1
RF Parallel Interface AC Electrical Characteristics (eSPI2)
RF Parallel AC Data Interface
Table 89 provides the timing specifications for the RF parallel interface.
Table 89. RF Parallel Interface Timing Specification (3.3 V, 1.8 V)1,2
Parameter
Symbol
Min
Max
Unit
Note
Data_clk (MCLK) clock period
tPDCP
16.276
(61.44)
—
ns
(MHz)
—
Data_clk (MCLK) and fb_clk (FCLK) pulse width
tPDMP
45% of tPDCP
—
—
—
Delay between MCLK and FCLK at the external RFIC including
trace delay
tPDCD
—
7.32
ns
—
tPDMFD
—
6.32
ns
—
Control/Data output valid time wrt FCLK during Tx from the
BSC9132 BBIC
tPDOV
—
6.0
ns
—
Control/Data hold from FCLK during Tx from the BSC9132 BBIC
tPDOX
1.37
—
ns
3
Control/Data setup wrt MCLK
tPDIV
2.5
—
ns
—
Control/Data hold wrt MCLK
tPDIX
0.4
—
ns
—
MCLK input to FCLK output delay at the BSC9132 BBIC
Note:
1 The max trace delay of MCLK from the external RFIC to the BSC9132 BBIC and FCK/TXNRX/ENABLE from BBIC to RFIC =
1 ns each.
2 The max allowable trace skew between MCLK/FCLK and the respective data/control is 70 ps.
3 1.37 ns includes 70 ps trace skew.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
121
Electrical Characteristics
Launch edge at BBIC
during Tx (both pos
and neg edge of clock)
Capture edge wrt
the shown launch
edge (opp. of the
launch edge)
Launch edge at RFIC
during Rx (both pos
and neg edge of clock)
MCLK
(data_clk)
at BBIC
FB_CLK
at BBIC
tPDCP
BBIC Tx
Data/Control
RX_DATA/
RX_FRAME
tPDOX
tPDOV
MCLK input to FCLK output delay at BBIC end
tPDIV
tPDIX
Figure 48. RF Parallel Interface AC Timing Diagram
2.21.1.2.2
RF Parallel Interface AC Control Plane
Table 90. RF Parallel Control Plane Interface AC Timing Specification
Parameter
Symbol
Min
Max
Unit
Control plane clock period
tPCCP
33.3 (30)
—
ns (MHz)
Clock min pulse width
tPCMP
16.6
—
ns
PCB trace delay between the BSC9132 BBIC master and the
external RFIC slave
tPCBD
—
1
ns
Setup time from CPCSB assertion to first rising edge of SPICLK
tPCSC
6.1
—
ns
Hold time from last SPICLK falling edge to CPCSB deassertion
tPCHC
9.9
—
ns
MOSI data output setup time against SPICLK
tPCOV
—
15.4
ns
MOSI data ouptut hold time against SPICLK
tPCOX
–16.4
—
ns
MISO data input setup time against SPICLK
tPCIV
7.9
—
ns
MISO data input hold time against SPICLK
tPCIX
21.9
—
ns
Note: RF parallel control plane is SPI2.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
122
Freescale Semiconductor
Electrical Characteristics
ci=0; cp=1
CPCSB
Launch edge at BBIC
(always rise-edge)
Capture edge at BBIC
(always fall-edge)
SPICLK (BBIC)
MOSI
tPCSC
tPCOX
tPCOV
Capture edge at RFIC
SPICLK (RFIC)
MISO
tBD
tBD + tCQ
tBD: Board delay from the BSC9132 BBIC to the external RFIC or
back
tCQ: Delay in RFIC from input of SPICLK to output valid data
Max permissible board skew: 100 ps
Proposed frequency of SPICLK: 30 MHz
tPCIV
tPCIX
Data timing at RF parallel interface:
Input data setup requirement: 1 ns
Input data hold requirement: 0 ns
tCQ: 4.5 ns–6.5 ns (6.5 ns is critical, which defines
the max frequency)
Figure 49. RF Parallel Control Plane Interface AC Timing Diagram
2.22
Universal Subscriber Identity Module (USIM)
The USIM module interface consist of a total of five pins. Only “Internal One Wire” interface mode is supported. In this mode,
the Rx input of the USIM IP is connected to the TX output of the USIM, which is internal to the device. Only one bidirectional
signal (Rx/Tx) is routed to the device pin, which is connected to the external SIM card.
The interface is meant to be used with synchronous SIM cards. This means that the SIM module provides a clock for the SIM
card to use. The frequency of this clock is normally 372 times the data rate on the Rx/Tx pins; however, the SIM module can
work with CLK equal to 16 times the data rate on Rx/Tx pins.
There is no timing relationship between the clock and the data. The clock that the SIM module provides to the SIM card will
be used by the SIM card to recover the clock from the data much like a standard UART. All five pins of SIM module are
asynchronous to each other.
There are no required timing relationships between the pads in normal mode, The SIM card is initiated by the interface device,
whereupon the SIM card will send a response with an Answer to Reset. Although the SIM interface has no specific requirement,
the ISO-7816 specifies reset and power down sequences. For detailed information, see ISO-7816.
The USIM interface pins are available at two locations. At one location, it is multiplexed with eSDHC and TDM functionality
and is powered by the BVDD power supply (3.3V/2.5V/1.8V). At the other location, it is multiplexed with eSPI and UART
functionality and is powered by CVDD power supply (3.3V/1.8V).
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
123
Electrical Characteristics
2.22.1
USIM DC Electrical Characteristics
This table provides the DC electrical characteristics for the USIM interface.
Table 91. USIM Interface DC Electrical Characteristics
At recommended operating conditions with BVDD = 3.3 V/2.5 V/1.8 V.
Characteristic
Symbol
Condition
Min
Max
Unit
Note
Input high voltage
VIH
—
0.625 × BVDD
—
V
1
Input low voltage
VIL
—
—
0.25 × BVDD
V
1
Output high voltage
VOH
IOH = –100 uA at BVDDmin
0.75 × BVDD
—
V
—
Output low voltage
VOL
IOL = 100uA at CVDDmin
—
0.125 × BVDD
V
—
Output high voltage
VOH
IOH = –100 uA
BVDD - 0.2
—
V
2
Output low voltage
VOL
IOL = 2 mA
—
0.3
V
2
IIN/IOZ
—
–10
10
uA
—
Input/output leakage current
Note:
1. Note that the min VILand max VIH values are based on the respective min and max BVIN values found in Figure 3.
2. Open drain mode for SIM cards only.
2.22.2
USIM General Timing Requirements
The timing requirements for the USIM are found in Table 92.
Table 92. USIM Timing Specification, High Drive Strength
Parameter
Symbol
Min
Max
Unit
Note
USIM clock frequency (SIM_CLK)
Sfreq
0.01
25
MHz
1
USIM clock rise time (SIM_CLK)
Srise
—
0.09 × (1/Sfreq)
ns
2
USIM clock fall time (SIM_CLK)
Sfall
—
0.09* × 1/Sfreq)
ns
2
USIM input transition time (SIM_TRXD, SIM_PD)
Strans
10
25
ns
—
USIM I/O rise time / fall time (SIM_TRXD)
Tr/Tf
—
1
μs
3
USIM RST rise time / fall time (SIM_RST)
Tr/Tf
—
1
μs
4
Note:
1 50% duty cycle clock
2
With C = 50 pF
3 With CIN = 30 pF, COUT = 30 pF
4 With C = 30 pF
IN
1/SI1
SIM_CLK
SI3
SI2
Figure 50. USIM Clock Timing Diagram
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
124
Freescale Semiconductor
Electrical Characteristics
2.22.3
USIM External Pull Up/Pull Down Resistor Requirements
External off-chip pull up resistor of 20 KΩ is required on the SIM_TRXD pin.
External off-chip pull down resistors are required on the SIM_PD, SIM_SVEN, SIM_RST pins.
2.22.4
2.22.4.1
USIM Reset Sequence
SIM Cards With Internal Reset
The sequence of reset for this kind of SIM cards is as follows (see Figure 51):
•
•
•
After power up, the clock signal is enabled on SIM_CLK (time T0).
After 200 clock cycles, Rx must be high.
The card must send a response on Rx acknowledging the reset between 400 and 40000 clock cycles after T0.
SIM_SVEN
SIM_CLK
RESPONSE
SIM_TRXD
SI7
SI8
T0
Figure 51. Internal-Reset Card Reset Sequence
Table 93. Parameters of Reset Sequence For Card With Internal Reset
ID
Parameter
Symbol
Min
Max
Unit
SI7
SIM clock to SIM TX data H
Sclk2dat
—
200
SIM_CLK clock cycle
SI8
SIM clock to SIM get ATR data
Sclk2atr
400
40000
SIM_CLK clock cycle
2.22.4.2
SIM Cards With Active-Low Reset
The sequence of reset for this kind of card is as follows (see Figure 52):
•
•
•
•
•
After powering up, the clock signal is enabled on SIM_CLK (time T0).
After 200 clock cycles, SIM_TRXD must be high.
SIM_RST must remain Low for at least 40000 clock cycles after T0 (no response is to be received on Rx during those
40000 clock cycles).
SIM_RST is set High (time T1).
SIM_RST must remain High for at least 40000 clock cycles after T1 and a response must be received on SIM_TRXD
between 400 and 40000 clock cycles after T1.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
125
Electrical Characteristics
SIM_SVEN
SIM_RST
SIM_CLK
RESPONSE
SIM_TRXD
SI9
SI10
SI11
SI11
T0
T1
Figure 52. Active-Low Reset Card Reset Sequence
Table 94. Parameters of Reset Sequence For Active-Low Reset Card
ID
Parameter
Symbol
Min
Max
Unit
SI9
SIM clock to SIM TX data H
Sclk2dat
—
200
SIM_CLK clock cycle
SI10
SIM reset rising to SIM TX data low
Sclk2atr
400
40000
SIM_CLK clock cycle
SI11
SIM clock to SIM reset signals
Sclk2rst
40000
—
SIM_CLK clock cycle
2.22.4.3
USIM Power Down Sequence
Power down sequence for SIM interface is as follows:
•
•
•
•
•
SIM_PD port detects the removal of the SIM card
SIM_RST goes low
SIM_CLK goes low
SIM_TRXD goes low
SIM_SVEN goes low
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
126
Freescale Semiconductor
Electrical Characteristics
Each of these steps is done in one CKIL period (typically 32 KHz). Power down is initiated by detection of a SIM card removal
or is launched by the processor. See Figure 53 and Table 95 for the timing requirements for this sequence, with FCKIL = CKIL
frequency value.
SIM_PD
SIM_RST
SI12
SIM_CLK
SI13
SIM_TRXD
SI14
SIM_SVEN
Figure 53. SmartCard Interface Power Down AC Timing
Table 95. Timing Requirements for Power Down Sequence
ID
Parameter
Symbol
Min
Max
Unit
SI12
USIM reset to USIM clock stop
Srst2clk
0.9 × 1/Fckil
1.1 × 1/FCKIL
ns
SI13
USIM reset to USIM Tx data low
Srst2dat
1.8 × 1/Fckil
2.2 × 1/FCKIL
ns
SI14
USIM reset to USIM voltage enable low
Srst2ven
2.7 × 1/Fckil
3.3 × 1/FCKIL
ns
SI15
USIM presence detect to USIM reset low
Spd2rst
0.9 × 1/Fckil
1.1 × 1/FCKIL
ns
2.23
Timers and Timers_32b AC Timing Specifications
This table lists the timer input AC timing specifications.
Table 96. Timers Input AC Timing Specifications
For recommended operating conditions, see Table 3.
Parameter
Timers inputs—minimum pulse width
Symbol
Minimum
Unit
Note
TTIWID
8
ns
1, 2
Note:
1. The maximum allowed frequency of timer outputs is 125 MHz. Configure the timer modules appropriately.
2. Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by any
external synchronous logic. Timer inputs are required to be valid for at least tTIWID ns to ensure proper operation.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
127
Hardware Design Considerations
This figure shows the AC test load for the timers.
Output
Z0 = 50 Ω
VDDIO/2
RL = 50 Ω
Figure 54. Timer AC Test Load
3
Hardware Design Considerations
This section discusses the hardware design considerations.
3.1
Power Architecture System Clocking
This section describes the PLL configuration for the Power Architecture side of the device. Note that the platform clock is
identical to the internal core complex bus (CCB) clock.
This device includes 6 PLLs, as follows:
•
•
•
•
3.1.1
The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency ratio
between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in
Section 3.1.2, “Power Architecture Platform to SYSCLK PLL Ratio.”
The e500 core PLL generates the core clock from the platform clock. The frequency ratio between the e500 core clock
and the platform clock is selected using the e500 PLL ratio configuration bits as described in Section 3.1.3, “e500 Core
to Platform Clock PLL Ratios.” This device has two e500 core PLLs.
The DDR PLL generates the clocking for the DDR SDRAM controller. The frequency ratio between DDR clock and
platform clock is selected using the DDR PLL ratio configuration bits as described in section Section 3.1.4, “Power
Architecture DDR/DDRCLK PLL Ratio.”
The SerDes block has two PLLs.
Power Architecture Clock Ranges
Table 97 provides the clocking specifications for the processor core and platform.
Table 97. Power Architecture Processor Clocking Specifications
Characteristic
Maximum Processor Core
Frequency
Unit
Note
Min
Max
e500 core processor frequency
400
1200
MHz
1, 2, 3
Platform CCB bus clock frequency
267
600
MHz
1, 4, 5
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
128
Freescale Semiconductor
Hardware Design Considerations
Table 97. Power Architecture Processor Clocking Specifications (continued)
Maximum Processor Core
Frequency
Characteristic
Min
Unit
Note
Max
Note:
1. Caution: The Power Architecture platform clock to SYSCLK ratio and e500 core to platform clock ratio settings must be
chosen such that the resulting SYSCLK frequency, e500 (core) frequency, and platform clock frequency do not exceed their
respective maximum or minimum operating frequencies. See Section 3.1.2, “Power Architecture Platform to SYSCLK PLL
Ratio,” and Section 3.1.3, “e500 Core to Platform Clock PLL Ratios” and Section 3.1.4, “Power Architecture DDR/DDRCLK
PLL Ratio,” for ratio settings.
2. The minimum e500 core frequency is based on the minimum platform clock frequency of 267 MHz.
3. The reset config signal cfg_core_speed must be pulled low if the core frequency is 1001 MHz or below.
4. These values are preliminary and subject to change.
5. The reset config signal cfg_plat_speed must be pulled low if the CCB bus frequency is lower than 320 MHz.
The DDR memory controller can run in asynchronous mode.
Table 98 provides the clocking specifications for the memory bus.
Table 98. Power Architecture Memory Bus Clocking Specifications
Characteristic
Memory bus clock frequency
Min
Max
Unit
Note
266
400
MHz
1, 2, 3
Note:
1. Caution: The platform clock to SYSCLK ratio and e500 core to platform clock ratio settings must be chosen such that the
resulting SYSCLK frequency, e500 (core) frequency, and platform frequency do not exceed their respective maximum or
minimum operating frequencies. See Section 3.1.2, “Power Architecture Platform to SYSCLK PLL Ratio,” and Section 3.1.3,
“e500 Core to Platform Clock PLL Ratios,” and Section 3.1.4, “Power Architecture DDR/DDRCLK PLL Ratio,” for ratio settings.
2. The memory bus clock refers to the memory controllers’ Dn_MCK[0:5] and Dn_MCK[0:5]_B output clocks, running at half of
the DDR data rate.
3. In asynchronous mode, the memory bus clock speed is dictated by its own PLL. See Section 3.1.4, “Power Architecture
DDR/DDRCLK PLL Ratio.” The memory bus clock speed must be less than or equal to the platform clock rate, which in turn
must be less than the DDR data rate.
As a general guideline, the following procedures can be used for selecting the DDR data rate or platform frequency:
1.
2.
3.
4.
5.
3.1.2
Start with the processor core frequency selection.
Once the processor core frequency is determined, select the platform frequency from the options listed in Table 100
and Table 105.
Check the platform to SYSCLK ratio to verify a valid ratio can be chosen from Table 103.
Please note that the DDR data rate must be greater than the platform frequency. In other words, running DDR data rate
lower than the platform frequency is not supported.
Verify all clock ratios to ensure that there is no violation to any clock and/or ratio specification.
Power Architecture Platform to SYSCLK PLL Ratio
The clock that drives the internal CCB bus is called the platform clock. The frequency of the platform clock is set using the
following reset signals, as shown in Table 99:
•
SYSCLK input signal
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
129
Hardware Design Considerations
•
Binary value on IFC_AD[0:2] at power up
These signals must be pulled to the desired values.
In asynchronous mode, the memory bus clock frequency is decoupled from the platform bus frequency.
Table 99. Power Architecture Platform/SYSCLK Clock Ratios
3.1.3
Binary Value of IFC_AD[0:2] Signals
Platform: SYSCLK Ratio
000
4:1
001
5:1
010
6:1
All Others
Reserved
e500 Core to Platform Clock PLL Ratios
The clock ratio between the e500 core0 and the platform clock is determined by the binary value of IFC_AD[3:5] signals at
power up. Table 100 describes the supported ratios. There are no default values for these PLL ratios; these signals must be pulled
to the desired values. Note that IFC_AD[6] must be pulled low if the core frequency is 1001 MHz or below.
Table 100. e500 Core0 to Platform Clock Ratios
Binary Value of
IFC_AD[3:5]Signals
e500 Core0: Platform
Ratio
010
1:1
011
1.5:1
100
2:1
101
2.5:1
110
3:1
All Others
Reserved
The clock ratio between the e500 core1 and the platform clock is determined by the binary value of the IFC_CLE, IFC_OE_B,
IFC_WP_B signals at power up. Table 101 describes the supported ratios. There are no default values for these PLL ratios; these
signals must be pulled to the desired values. Note that IFC_AD[12] must be pulled low if the core frequency is 1001 MHz or
below.
Table 101. e500 Core1 to Platform Clock Ratios
Binary Value of
IFC_CLE, IFC_OE_B, IFC_WP_B Signals
e500 Core1: Platform Ratio
010
1:1
011
1.5:1
100
2:1
101
2.5:1
110
3:1
All Others
Reserved
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
130
Freescale Semiconductor
Hardware Design Considerations
3.1.4
Power Architecture DDR/DDRCLK PLL Ratio
Table 102 describes the clock ratio between the dual DDR memory controller complexes and the DDR PLL reference clock,
DDRCLK, which is not the memory bus clock. The DDR memory controller complexes clock frequency is equal to the DDR
data rate.
The DDR PLL rate to DDRCLK ratios listed in Table 102 reflects the DDR data rate to DDRCLK ratio, since the DDR PLL
rate in asynchronous mode means the DDR data rate resulting from DDR PLL output. This ratio is determined by the binary
value of the IFC_AD[7].
Table 102. Power Architecture DDR Clock Ratio
3.1.5
Binary Value of {IFC_AD[7],
IFC_ADDR[22]} Signal
DDR:DDRCLK Ratio
00
8:1
01
10:1
10
12:1
11
Reserved
Power Architecture SYSCLK and Platform Frequency Options
Table 103 shows the expected frequency options for SYSCLK and platform frequencies.
Table 103. Power Architecture SYSCLK and Platform Frequency Options
SYSCLK (MHz)
Platform:
SYSCLK Ratio
66.66
80
100
133
Platform Frequency (MHz)1
1)
4:1
267
320
400
533
5:1
333
400
500
—
6:1
400
480
600
—
8:1
533
—
—
—
Platform frequency values are shown rounded down to the nearest whole number (decimal place accuracy removed).
3.2
DSP System Clocking
This section describes the PLL configuration for the DSP side of the device. Note that the platform clock is identical to the
internal core complex bus (CCB) clock.
This device has the following PLLs:
•
•
•
One SC3850 core PLL
One MAPLE-eTVPE PLL
One DSP DDR PLL
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
131
Hardware Design Considerations
3.2.1
DSP Clock Ranges
Table 104 provides the clocking specifications for the SC3850 processor core, MAPLE, and DSP memory.
Table 104. DSP Processor Clocking Specifications
DSP Core
Minimum Frequency
Maximum Frequency
Unit
SC3850 cores
800
1200
MHz
MAPLE eVTPE
800
800
MHz
DSP DDR Controller
800
1333
MHz
3.2.2
DSPCLKIN and SC3850 Core Frequency Options
Table 105 shows the expected frequency options for DSPCLKIN and SC3850 core frequencies.
Table 105. Options for SC3850 Core0 and Core1 Clocking
DSPCLKIN Frequency (MHz)
PLL_T2 MF
66.66
80
100
133
SC3850 Core Frequency (MHz)
3.3
1
66.66
80
100
133
6
400
480
600
800
7.5
500
600
750
1000
8
533
640
800
1066
9
600
720
900
1200
10
667
800
1000
—
12
800
960
1200
—
15
1000
1200
—
—
Supply Power Default Setting
This device is capable of supporting multiple power supply levels on its I/O supply. Table 106 through Table 110 shows the
encoding used to select the voltage level for each I/O supply. When setting the VSEL signals, "1" is selected through a pull-up
resistor to OVDD (as seen in Table 1).
Table 106. Default Voltage Level for BVDD
BVDD_VSEL[0:1]
I/O Voltage Level
00
3.3 V
01
2.5 V
10
1.8 V
11
Reserved
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
132
Freescale Semiconductor
Hardware Design Considerations
Table 107. Default Voltage Level for CVDD
CVDD_VSEL
I/O Voltage Level
0
3.3 V
1
1.8 V
Table 108. Default Voltage Level for X1VDD
X1VDD_VSEL
I/O Voltage Level
0
3.3 V
1
1.8 V
Table 109. Default Voltage Level for X2VDD
XVDD2_VSEL
I/O Voltage Level
0
3.3 V
1
1.8 V
Table 110. Default Voltage Level for LVDD
3.4
LVDD_VSEL
I/O Voltage Level
0
3.3 V
1
2.5 V
PLL Power Supply Design
Each of the PLLs listed above is provided with power through independent power supply pins (AVDD_PLAT, AVDD_CORE0,
AVDD_CORE1, AVDD_D1_DDR, AVDD_D2_DDR, AVDD_DSP, and AVDD_MAPLE respectively). The AVDD level
should always be equivalent to VDDC, and these voltages must be derived directly from VDDC through a low frequency filter
scheme.
The recommended solution for PLL filtering is to provide independent filter circuits per PLL power supply, as illustrated in
Figure 55, one for each of the AVDD pins. By providing independent filters to each PLL the opportunity to cause noise injection
from one PLL to the other is reduced.
This circuit is intended to filter noise in the PLL’s resonant frequency range from a 500-kHz to 10-MHz range. It should be built
with surface mount capacitors with minimum Effective Series Inductance (ESL). Consistent with the recommendations of
Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small
capacitors of equal value are recommended over a single large value capacitor.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from
nearby circuits. It should be possible to route directly from the capacitors to the AVDD pin, which is on the periphery of 780 ball
FCPBGA the footprint, without the inductance of vias.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
133
Hardware Design Considerations
Figure 55 shows the core PLL (AVDD_CORE) power supply filter circuit.
VDDC
R
C1
C2
GND
AVDD_PLAT/AVDD_CORE0/AVDD_CORE1/
AVDD_D[1-2]_DDR/AVDD_DSP/AVDD_MAPL
E
Low ESL Surface Mount Capacitors
Notes:
R = 5Ω ± 5%
C1 = 10µF ± 10%, 603, X5R with ESL ≤ 0.5 nH
C2 = 1.0µF ± 10%, 402 X5R with ESL ≤ 0.5 nH
This circuit applies for system PLL, core PLL, DDR PPLL, and DSP PLL.
Figure 55. PLL Power Supply Filter Circuit
The AVDD_SRDSn signals provides power for the analog portions of the SerDes PLL. Use separate islands (that is, very wide
traces) for each PLL bank’s SDnAGND and SDnAVDD connections. The ground islands/wide traces of different PLL banks
are to be joined to a single ground plane either with an inductor or through a 0 Ω resistance. While it is possible to connect these
islands together to a single supply (possibly via a resistor or ferrite bead), it would be best for this connection to be formed by
multiple single-point connections which are as close to the source (and as far away from the chip) as possible. The multiple
single-point connections can be optimized as thick multiple wide connections to provide a good return path. The user should
simulate the return path impedance and then take appropriate PCB layout tradeoff decisions. Additionally, one should maintain
low noise and good stability of the SDnAVDD. The user should not place any digital or other bank traces near the PLL power
and ground planes.
For maximum effectiveness, the filter circuit should be placed as closely as possible to the SDAVDD ball to ensure it filters out
as much noise as possible. The ground connection should be near the SDAVDD ball. To provide effective bypass capacitance
at high frequencies, these two islands/wide traces should be directly over each other and on the nearest layer (that is,
layers 3 and 4 of a 6-layer PC board).
The capacitors are connected from SDAVDD to the ground plane. Only the surface mount technology (SMT) capacitors should
be used to minimize inductance. Connections from all capacitors to power and ground should be done with multiple vias to
further reduce inductance. The 2.2 nF capacitor is the closest to the package pin, followed by the two 2.2 µF capacitors, and
finally the 1 Ω resistor to the board supply plane. The goal is to have a 2.2 nF decoupling capacitor within approximately 0.5 cm
of each power pin.
3.5
Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high
frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching
other components in the system, and the device itself requires a clean, tightly regulated source of power. Therefore, it is
recommended that the system designer place at least one decoupling capacitor at each VDD, BVDD, CVDD, OVDD, G1VDD,
G2VDD, LVDD, RVDD, X1VDD, and X2VDD pin of the device. These decoupling capacitors should receive their power from
separate VDD, BVDD, OVDD, G1VDD, G2VDD, LVDD, RVDD, X1VDD, X2VDD, and GND power planes in the PCB,
utilizing short traces to minimize inductance. Capacitors may be placed directly under the device using a standard escape
pattern. Others may surround the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology) capacitors should be
used to minimize lead inductance, preferably 0402 or 0201 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, BVDD,
OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have
a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to
the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS
tantalum or Sanyo OSCON).
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
134
Freescale Semiconductor
Hardware Design Considerations
3.6
SerDes Block Power Supply Decoupling Recommendations
The SerDes block requires a clean, tightly regulated source of power (XCOREVDD and XPADVDD) to ensure low jitter on
transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below.
•
•
•
The board should have at least 10 × 10-nF SMT ceramic chip capacitors as close as possible to the supply balls of the
device. Where the board has blind vias, these capacitors should be placed directly below the chip supply and ground
connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the device
as close to the supply and ground connections as possible.
There should be a 1-µF ceramic chip capacitor on each side of the device. This should be done for all SerDes supplies.
Between the device and any SerDes voltage regulator there should be a 10-µF, low ESR SMT tantalum chip capacitor
and a 100-µF, low ESR SMT tantalum chip capacitor. This should be done for all SerDes supplies.
Only SMT capacitors should be used to minimize inductance. Connections from all capacitors to power and ground should be
done with multiple vias to further reduce inductance.
Figure 56 shows the SerDes PLL power supply filter circuit.
(0603-sized) default resistance with
1Ω provision to change to an inductor
SDnAVDD
XCOREVDD
2.2µF
2.2µF
0.022µF
SDnAGND
GND
0Ω (0603-sized) default resistance with
provision to change to an inductor
Figure 56. SerDes PLL Power Supply Filter Circuit
The power supplied to the XCOREVDD and XPADVDD are filtered using a circuit similar to Figure 57.
Figure 57. XCOREVDD and XPADVDD Power Supply Filter Circuit
The XCOREVSS and XPADVSS of different banks can be joined to a low noise, solid reference ground plane. Perform the noise
coupling simulation on actual PCB design implementation. The user should quantify the noise and then and then take
appropriate PCB layout tradeoff decisions, followed by validating the simulated noise against the measured noise for the
designed PCB.
In case of a board noise coupling issue, the user may use separate islands/thick wide traces for XCOREVSS, XPADVSS,
XCOREVDD and XPADVDD. Connect these “islands" together to a single supply plane; it would be best for this connection to
be a single point or multiple single-point connections as close to the source (and as far away from the chip) as possible.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
135
Hardware Design Considerations
Component values will need to be optimized/finalized based on board level filter measurements to provide best possible
attenuation up to 10 GHz, while preserving lowest loss at DC (IR drop).
3.7
Guidelines for High-Speed Interface Termination
This section provides guidelines for when the SerDes interface is entirely unused and when it is partially unused.
3.7.1
SerDes Interface Entirely Unused
If the high-speed SerDes interface is not used at all, the unused pin should be terminated as described in this section.
The following pins must be left unconnected:
•
•
•
SD_TX[3:0], SD_TX_B[3:0]
SD_RX[3:0], SD_RX_B[3:0]
SD_IMP_CAL_TX, SD_IMP_CAL_RX
The following pins must be connected to XCOREVSS:
•
•
SD_REF_CLK1, SD_REF_CLK1_B (if entire SerDes bank 1 is unused)
SD_REF_CLK2, SD_REF_CLK2_B (if entire SerDes bank 2 is unused)
Unused SD_REF_CLK1 and SD_REF_CLK2 must be connected to SGND.
Power should still be applied to the SerDes external pins:
•
•
•
3.7.2
XCOREVDD/VSS(SGND)
AVDD/VSS
XPADVDD/VSS
SerDes Interface Partly Unused
If only part of the high speed SerDes interface pins are used, the remaining high-speed serial I/O pins should be terminated as
described in this section.
The following unused pins must be left unconnected:
•
•
SD_TX[n]
SD_TX_B[n]
The following unused pins must be connected to SGND:
•
•
•
SD_RX[n], SD_RX_B[n]
SD_REF_CLK1, SD_REF_CLK1_B (If entire SerDes bank 1 is unused)
SD_REF_CLK2, SD_REF_CLK2_B (If entire SerDes bank 2 is unused)
In the RCW configuration field for each bank SRDS_LPD_Bn with unused lanes, the respective bit for each unused lane must
be set to power down the lane.
3.8
Pull-Up and Pull-Down Resistor Requirements
The device requires weak pull-up resistors on open drain type pins including I2C pins (1 kΩ is recommended) and MPIC
interrupt pins (2–10 kΩ is recommended).
Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 59.
Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions,
because most have asynchronous behavior, and spurious assertion gives unpredictable results.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
136
Freescale Semiconductor
Hardware Design Considerations
3.9
Output Buffer DC Impedance
The drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended driver
type (open drain for I2C).
To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD or GND. Then, the
value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 58). The output impedance is the average of two
components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and
RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN
are designed to be close to each other in value. Then, Z0 = (RP + RN) ÷ 2.
OVDD
RN
SW2
Pad
Data
SW1
RP
OGND
Figure 58. Driver Impedance Measurement
Table 111 summarizes the signal impedance targets. The driver impedances are targeted at minimum VDDC, nominal OVDD,
90°C.
Table 111. Impedance Characteristics
Impedance
IFC, Ethernet, DUART, Control, Configuration, Power
Management
DDR DRAM
Symbol
Unit
RN
43 Target
20 Target
Z0
W
RP
43 Target
20 Target
Z0
W
Note: Nominal supply voltages. See Table 2.
3.10
Configuration Pin Muxing
The device provides the user with power-on configuration options which can be set through the use of external pull-up or
pull-down resistors of 4.7 kΩ on certain output pins (see customer visible configuration pins). These pins are generally used as
output only pins in normal operation.
While HRESET_B is asserted however, these pins are treated as inputs. The value presented on these pins while HRESET_B
is asserted, is latched when HRESET_B deasserts, at which time the input receiver is disabled and the I/O circuit takes on its
normal function. Most of these sampled configuration pins are equipped with an on-chip gated resistor of approximately 20 kΩ.
This value should permit the 4.7-kΩ resistor to pull the configuration pin to a valid logic low level. The pull-up resistor is
enabled only during HRESET_B (and for platform/system clocks after HRESET_B deassertion to ensure capture of the reset
value). When the input receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
137
Hardware Design Considerations
minimal signal quality or delay disruption. The default value for all configuration bits treated this way has been encoded such
that a high voltage level puts the device into the default state and external resistors are needed only when non-default settings
are required by the user.
Careful board layout with stubless connections to these pull-down resistors coupled with the large value of the pull-down
resistor should minimize the disruption of signal quality or speed for output pins thus configured.
The platform PLL ratio and e500 PLL ratio configuration pins are not equipped with these default pull-up devices.
3.11
JTAG Configuration Signals
There are two JTAG ports:
•
•
Power Architecture JTAG (TDI, TDO, TMS, TCK, and TRST_B)
DSP JTAG (DSP_TDI, DSP_ TDO, DSP_TMS, DSP_TCK, and DSP_TRST_B)
Note that the DSP JTAG is available as dedicated I/O pins.
The Power Architecture JTAG is the primary JTAG interface of the chip. DSP JTAG is defined as optional debug interface. As
seen in Table 112, the JTAG topology is selectable by static value driven on two pins—CFG_0_JTAG_MODE and
CFG_1_JTAG_MODE.
Table 112. JTAG Topology
{CFG_0_JTAG_MODE,
CFG_1_JTAG_MODE}
Uses Power
Architecture
Debug Header
Uses DSP
Debug Header
00
Yes
No
Access Power Architecture domain and DSP domain using
Power Architecture JTAG port
01
Yes
No
Access DSP domain using Power Architecture JTAG port
10
Yes
No
Access Power Architecture domain using Power
Architecture JTAG port
11
Yes
Yes
Access Power Architecture domain using Power
Architecture JTAG and DSP domain using DSP JTAG
JTAG Topology
Note: For boundary SCAN, set {CFG_0_JTAG_MODE, CFG_1_JTAG_MODE} = 10.
The TRST/DSP_TRST signal is optional in the IEEE 1149.1 specification, but is provided on the device. The device requires
TRST/DSP_TRST to be asserted during reset conditions to ensure the JTAG boundary logic does not interfere with normal chip
operation. While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, generally
systems assert TRST/DSP_TRST during the power-on reset flow. Simply tying TRST/DSP_TRST to HRESET_B is not
practical because the JTAG interface is also used for accessing the common on-chip processor (COP) function.
The COP function of the processor allow a remote computer system (typically, a PC with dedicated hardware and debugging
software) to access and control the internal operations of the processor. The arrangement shown in Figure 59 and Figure 60
allows the COP/ONCE port to independently assert HRESET_B or TRST, while ensuring that the target can drive HRESET_B
as well.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
138
Freescale Semiconductor
Hardware Design Considerations
The COP interface has a standard header for connection to the target system. The 16-pin PA COP connector is shown in
Figure 59.
COP_TDO
1
2
NC
COP_TDI
3
4
COP_TRST_B
NC
5
6
COP_VDD_SENSE
COP_TCK
7
8
COP_CHKSTP_IN_B
COP_TMS
9
10
NC
COP_SRESET_B
11
12
NC
COP_HRESET_B
13
COP_CHKSTP_OUT_B
15
KEY
No pin
16
GND
Figure 59. COP Connector Physical Pinout
The ONCE interface also has a standard header for connection to the target system. The 14-pin DSP ONCE connector is shown
in Figure 60.
ONCE_TDI
1
2
GND
ONCE_TDO
3
4
GND
ONCE_TCK
5
6
GND
NC
7
8
ONCE_KEY
ONCE_HRST_B
9
10
ONCE_TMS
ONCE_VDD_SNS
11
12
NC
NC
13
14
ONCE_TRST_B
Figure 60. ONCE Connector Physical Pinout
3.11.1
Termination of Unused Signals
If the Power Architecture JTAG or DSP JTAG interface and COP/ONCE header is not used, Freescale recommends the
following connections:
•
TRST_B should be tied to HRESET_B through a 0 kΩ isolation resistor so that it is asserted when the system reset
signal (HRESET_B) is asserted, ensuring that the JTAG scan chain is initialized during the power-on reset flow.
Freescale recommends that the COP header be designed into the system as shown in Figure 59. If this is not possible,
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
139
Hardware Design Considerations
•
•
the isolation resistor allows future access to TRST_B in case a JTAG interface may need to be wired onto the system
in future debug situations.
TCK should be pulled down to GND through a 1 kΩ resistor. This prevents TCK from changing state and reading
incorrect data into the device.
No connection is required for TDI, TDO, or TMS.
NOTE
In the case where the DSP JTAG is also used (as described in Table 112), DSP_TRST and
DSP_TCK need to be handled in the same way as TRST and TCK are, as mentioned above.
3.12
Guidelines for High-Speed Interface Termination
If the high-speed SerDes interface is not used at all, the unused pin should be terminated as described in this section. However,
the SerDes must always have power applied to its supply pins.
The following pins must be left unconnected (float):
•
•
SD_TX[3:0]
SD_TX_B[3:0]
The following pins must be connected to GND:
•
•
SD_RX[3:0], SD_RX_B[3:0]
SD_REF_CLK, SD_REF_CLK_B
3.13
Thermal
This section describes the thermal specifications.
3.13.1
Thermal Characteristics
Table 113 provides the package thermal characteristics.
Table 113. Package Thermal Resistance Characteristics
Characteristic
JEDEC Board
Symbol
Lid
Unit
Junction-to-Ambient Natural Convection
Single layer board (1s)
RθJA
21
°C/W
Junction-to-Ambient Natural Convection
Four layer board (2s2p)
RθJA
14
°C/W
Junction-to-Ambient (at 200 ft/min)
Single layer board (1s)
RθJMA
15
°C/W
Junction-to-Ambient (at 200 ft/min)
Four layer board (2s2p)
RθJMA
11
°C/W
Junction-to-Board
—
RθJB
4.0
°C/W
Junction-to-Case Top
—
RθJCtop
0.7
°C/W
Note:
1. Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package.
2. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification
for the specified package.
3. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
140
Freescale Semiconductor
Package Information
3.13.2
Temperature Diode
The chip has a temperature diode on the microprocessor that can be used in conjunction with other system temperature
monitoring devices (such as Analog Devices, ADT7461A™). These devices use the negative temperature coefficient of a diode
operated at a constant current to determine the temperature of the microprocessor and its environment.
The following are the specifications of the chip’s on-board temperature diode:
Operating range: 10 – 230μA
Ideality factor over 13.5 – 220 μA: n = 1.007 ± 0.008
3.14
Security Fuse Processor
This device implements the QorIQ platform’s Trust Architecture, supporting capabilities such as secure boot. Use of the Trust
Architecture features is dependent on programming fuses in the Security Fuse Processor (SFP). The details of the Trust
Architecture and SFP can be found in the BSC9132 QorIQ Qonverge Multicore Baseband Processor Reference Manual.
In order to program SFP fuses, the user is required to supply 1.5 V to the POVDD1 pin per Section 2.2, “Power Sequencing.”
POVDD1 should only be powered for the duration of the fuse programming cycle, with a per device limit of one fuse
programming cycle. All other times POVDD1 should be connected to GND. The sequencing requirements for raising and
lowering POVDD1 are shown in Figure 8. To ensure device reliability, fuse programming must be performed within the
recommended fuse programming temperature range per Table 3.
Users not implementing the QorIQ platform’s Trust Architecture features are not required to program fuses and should connect
POVDD1 to GND.
4
Package Information
The following section describes the detailed content and mechanical description of the package.
4.1
Package Parameters
The package parameters are provided in the following list. The package type is plastic ball grid array (FC-PBGA).
Package outline
Interconnects
Pitch
Ball diameter (typical)
23 mm × 23 mm
780
0.8 mm
0.4 mm
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
141
Package Information
4.2
Mechanical Dimensions of the FC-PBGA
Figure 61 shows the package and bottom surface nomenclature.
Notes:
1. All dimentions are in milimeters.
2. Dimensions and tolerancing per ASME Y14.5-1994.
3. Maximum ball diameter measured parallel to Datum A.
4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
5. Parallelism measurement shall exclude any effect of mark on top surface of package.
6. All dimensions are symmetric across the package center lines, unless dimensioned otherwise.
7. Pin 1 through hole should be centered within foot area.
Figure 61. BSC9132 Mechanical Dimensions and Package Diagram
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
142
Freescale Semiconductor
Ordering Information
5
Ordering Information
The table below provides the Freescale part numbering nomenclature for the BSC9132. Note that the individual part numbers
correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office. Each
part number also contains a revision code which refers to the die mask revision number.
Table 114. Part numbering nomenclature
Product Code
BSC
n
x
t
Part
Identifier
Qual
Status
Temp
Range
Encryp- Package
tion
Type
N=
Industrial
Tier
S, L = Std
temp
(0–105°C)
E = SEC 7 =
Present FC-PBGA
Pb-free
N = No Bumps
SEC
and
Present Package
9132
X, J = Ext
temp
(-40–105°C)
5.1
e
n
c
d
f
r
CPU
Freq
DDR
Speed
DSP
Freq
Die
Revision
K=
N=
K=
B=
1000 MHz 1333 MHz 1000 MHz Rev 1.1
M=
M=
1200 MHz
1200 MHz
P=
1400 MHz
Part Marking
Parts are marked as the example shown in this figure.
BSC9132C
SE1HHHB
ATWLYYWW
MMMMM
CCCCC
YWWLAZ
FCPBGA
Notes:
ATWLYYWW is the traceability code.
CCCCC is the country code.
MMMMM is the mask number.
YWWLAZ is the assembly traceability code.
BSC9132CSE1HHHB is the orderable part number. See Table 114 for
details.
Figure 62. Part Marking for FCPBGA Device
6
Product Documentation
The following documents are required for a complete description of the device and are needed to design properly with the part.
Some documents may require a non-disclosure agreement. Contact your local FAE for assistance.
•
BSC9132 QorIQ Qonverge Multicore Baseband Processor Reference Manual (BSC9132RM)
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
Freescale Semiconductor
143
Revision History
•
7
e500 PowerPC Core Reference Manual (E500CORERM)
Revision History
Table 115. Document Revision History
Rev
Date
Substantive Change(s)
1
08/2014
Updated Table 1, “BSC9132 Pinout Listing.”
0
03/2014
Initial public release.
BSC9132 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 1
144
Freescale Semiconductor
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implementers to use Freescale products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits based on the
information in this document.
Freescale reserves the right to make changes without further notice to any products
herein. Freescale makes no warranty, representation, or guarantee regarding the
suitability of its products for any particular purpose, nor does Freescale assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters that may be provided in Freescale data sheets and/or
specifications can and do vary in different applications, and actual performance may
vary over time. All operating parameters, including “typicals,” must be validated for each
customer application by customer’s technical experts. Freescale does not convey any
license under its patent rights nor the rights of others. Freescale sells products pursuant
to standard terms and conditions of sale, which can be found at the following address:
freescale.com/SalesTermsandConditions.
Freescale, the Freescale logo, QorIQ, and StarCore are trademarks of
Freescale Semiconductor, Inc. Reg., U.S. Pat. & Tm. Off. QorIQ Qonverge is
a trademark of Freescale Semiconductor, Inc. All other product or service
names are the property of their respective owners. The Power Architecture
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© 2014 Freescale Semiconductor, Inc.
Document Number: BSC9132
Rev. 1
08/2014
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