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CPM Interrupt Controller
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What is the CPIC?
Definition
The CPIC is the focal point for all interrupts associated with the CPM. It accepts and
prioritizes all the internal and external interrupts from all functional blocks associated
with the CPM.
Example
CPM
Port C[4:15]
CPIC
Timer1
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Timer2
Timer3
Timer4
SCC1
SCC2
SCC3
SCC4
SMC1
To SIU Interrupt Controller
SMC2
SPI
I2C
PIP
IDMA1
IDMA2
SDMA
V
N
To EPPC
RISC Timers
Bolded names are sub-block maskable interrupt sources.
CPIC Features
Important functions of the CPIC are:
• Asserts an interrupt to the SIU interrupt controller at a user programmable level.
• Generates a unique vector number for each interrupt source.
• Prioritizes the interrupts for which it is responsible.
- Highest priority interrupt source is programmable by the user.
- Programmable priority between SCCs.
- Two priority schemes for the SCCs.
CPM Interrupt Controller
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What is a Sub-Block Maskable Interrupt?
Definition
SMCEx
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Example,
SMCx
If an interrupt source is maskable within the particular sub-block of which it is a part, it
is referred to as sub-block maskable.
3
BRK
4
-
5
6
BSY TX
7
RX
SMCMx
3
BRK
4
-
5
6
BSY TX
7
RX
SMCx Interrupt to CPIC
CPM Interrupt Controller
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Programming Model
CICR - CPM Interrupt Configuration Register
0
1
2
3
4
5
6
7
8
9
10
17
18
19
20
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IRL0_IRL2
21
22
PC15 SCC1 SCC2 SCC3 SCC4 PC14
17
PC11 PC10
18
-
21
24
25
26
Timer
1
19
20
22
Timer
3
PC9 PC8 PC7
7
8
PC13 PC12
23
-
13
SCbP
27
IEN
HP0_HP4
CIPR - CPM Interrupt Pending Register
0
1
2
3
4
5
6
16
23
12
SCcP
SCdP
16
11
P. 814
14 15
28
29
SCaP
30
-
9
SDMA
10
11
IDMA IDMA
1
2
26
27
SPS
12
-
28
13
P. 816
14 15
Timer
R_TT
2
I2C
29
31
24
25
30
Timer
4
PC6 SPI SMC1 SMC2
/PIP PC5 PC4
CIMR - CPM Interrupt Mask Register
0
1
2
3
4
5
PC15 SCC1 SCC2 SCC3 SCC4 PC14
16
17
PC11 PC10
18
-
21
1
2
6
Timer
1
19
20
Timer
3
PC9 PC8 PC7
3
4
5
PC15 SCC1 SCC2 SCC3 SCC4 PC14
16
17
PC11 PC10
18
-
19
Timer
3
20
21
22
7
8
PC13 PC12
23
-
9
10
11
IDMA IDMA
SDMA
1
2
26
27
12
-
28
13
14
1
2
VN
3
I2C
29
31
24
25
30
Timer
4
PC6 SPI SMC1 /PIP PC5 PC4
SMC2
5
-
P. 816
6
Timer
1
22
PC9 PC8 PC7
4
15
Timer
R_TT
2
7
8
PC13 PC12
23
-
24
Timer
4
9
SDMA
25
10
11
IDMA IDMA
1
2
26
PC6 SPI
27
12
-
28
SMC2
SMC1 /PIP
13
14
6
15
Timer
R_TT
2
I2C
29
31
30
PC5 PC4
CIVR - CPM Interrupt Vector Register
0
-
P. 816
CISR - CPM In-Service Register
0
31
-
P. 814
7
8
9
10
11
0
CPM Interrupt Controller
12
13
14
15
IACK
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How to Prioritize the SCCs (1 of 2)
Introduction
The SCCs must be prioritized relative to each other. The user controls the order of
priority in the CICR, fields SCdP, SCcP, SCbP, and SCaP.
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Priority
Matrix
Lowest
SCC
Code
SCC1
00
SCC2
01
SCC3
10
SCC4
11
SCdP
Highest Priority
SCcP
SCbP
SCaP
CICR
Example
Problem: Set the priority so that SCC1 is highest, SCC3 is second hightest, SCC2 second
lowest, and SCC4 the lowest.
Lowest
SCC
Code
SCC1
00
SCC2
01
SCC3
10
SCC4
11
SCdP
SCbP
SCaP
CICR
01
10
11
=
=
=
=
0;
2;
1;
3;
Set the priority so that SCC2 is the highest priority, SCC3 is second highest, SCC4 is the
second lowest, and SCC1 is the lowest.
pdpr->CICR.SCaP
pdpr->CICR.SCbP
pdpr->CICR.SCcP
pdpr->CICR.SCdP
Comment
SCcP
00
pdpr->CICR.SCaP
pdpr->CICR.SCbP
pdpr->CICR.SCcP
pdpr->CICR.SCdP
Exercise
Highest Priority
=
=
=
=
_;
_;
_;
_;
SCaP, SCbP, SCcP, and SCdP should all have different numbers.
CPM Interrupt Controller
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How to Prioritize the SCCs (2 of 2)
Introduction
In addition to being prioritized relative to each other, the SCCs can be grouped together
in the priority list or spread out.
Grouped
Priority
Priority Interrupt Source
Highest
PC15
SCCa
pdpr->CICR.SPS = 0;
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SCCb
SCCc
SCCd
Spread
Priority
Priority Interrupt Source
Highest
PC15
SCCa
pdpr->CICR.SPS = 1;
SCCb
SCCc
SCCd
CPM Interrupt Controller
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How to Specify the Highest Priority Interrupt Source
Introduction
Example
The user must specify which interrupt source is to be given top priority. This is done by
writing the 5-bit interrupt vector number to CICR.HP0_HP4. A priority list is on p. 810.
Problem: make the SDMA interrupt the highest priority.
pdpr->CICR.HP0_HP4 = 0x16;
Make PC15 the highest priority interrupt..
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Exercise
pdpr->CICR.HP0_HP4 = ____;
CPM Interrupt Controller
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How the CPIC Processes an Interrupt Input
Introduction
The CPIC receives an interrupt from one of its 29 sources, processes it, and, assuming
no masking, asserts its programmed interrupt level to the SIU interrupt controller.
Flow Diagram
of How the
CPIC Processes
an Interrupt
Start
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CPM interrupt
occurs
Sub-block
maskable
?
Y
Event
masked
?
N
Y
End
N
Set bit in
CIPR
Bit set
in CIMR
?
N
End
Y
>= priority
bit set in CISR
?
Y
N
To the SIU
interrupt controller
CPM Interrupt Controller
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How the SIU Processes an Interrupt Input
Introduction
The SIU receives an interrupt from one of 8 external sources or 1 of 8 internal sources
and, assuming no masking, assertes the IREQ input to the MPC8xx.
Flow Diagram
of How the
SIU Processes
an Interrupt
Start
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SIU interrupt
occurs
Set bit in
SIPEND
Bit set in
SIMASK
?
N
End
Y
To IREQ of
the MPC8xx
MPC8xx
Action
Following the assertion of IREQ, the MPC8xx completes the present instruction and
program control goes to offset 0x500 in the exception vector table.
CPM Interrupt Controller
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How to Initialize a CPM for Interrupts
Introduction
Here we describe the steps in initializing the CPM on the MPC860 for interrupts.
Assumptions
- IMMR has been initialized previously. If not, the user must initialize it.
- Except for the above, reset conditions exist.
Action
Here are the steps in initialization :
Step
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1
Action
Example
Initialize CPM Intrpt Config Reg, CICR
SCdP: lowest priority SCC
SCcP: 2nd lowest priority SCC
SCbP: 2nd highest priority SCC
SCaP: highest priority SCC
IRL0_IRL2: CPM intrpt level
HP0_HP4: highest priority intrpt source
SPS: spread priority
(814)
2
Initialize Interrupt Mask Reg, CIMR
SCC1-4
PC4-15
TIMER1-4
IDMA1-2
SMC1-2
SDMA
R-TT
SPI
I2C
3
4
5
pdpr->SIEL.WM5 = 1;
/*WAKEUP 860 FOR LEVEL
5 INTERRUPT*/
(191)
Initialize SI Mask Reg, SIMASK
IRMx:enable external interrupt input
LVMx:enable internal interrupt input
where x is 0 to 7
Enable CPM Interrupts
Initialize Enable Interrupts, EIE
pdpr->SIMASK.ASTRUCT.IRM6 = 1;
/*ENABLE IRQ6 INTERRUPTS */
(191)
(814)
6
pdpr->CIMR.SCC2 = 1;
/* ENABLE SCC2 INTRPTS */
(817)
Initialize SI Edge/Level Reg, SIEL
EDx:edge or level interrupt input
WMx:exit low power mode
where x is 0 to 7
pdpr->CICR.HP0_HP4 = 0x16;
/* SDMA HIGHEST PRIORITY
INTERRUPT */
pdpr->CICR.IEN = 1;
/* ENABLE CPM INTERRUPTS */
asm (“ mtspr 80,0”);;
/* ENABLE INTERRUPTS */
CPM Interrupt Controller
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How to Handle a CPIC Interrupt (1 of 2)
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First Steps in
Servicing CPM
Interrupts
• The first steps in servicing a CPM interrupt:
1
Read the interrupt code in the SI vector
register, SIVEC, and go to service routine
for that code.
(192)
if (pdpr->SIVEC.IC == 0x38)
irq7esr();
/* IF IRQ7, GO TO IRQ7ESR */
2
Clear the service bit in the SI Pending
Register, SIPEND
(191)
pdpr->SIPEND = 1<<(31-6);
/* CLEAR IRQ3 PENDING BIT*/
3
Required only if service routine is to be
recoverable and lower priority interrupts
are to be masked.
Save the SI mask reg, SIMASK
Mask lower interrupt levels
(191)
sptr++ = pdpr->SIMASK.ASINT;
/* STACK SIMASK REG */
pdpr->SIMASK.ASINT &=
0xF0000000;
/* MASK INTRPTS 2-7 */
4
Required only if service routine is to be
recoverable.
Save SRR0 & SRR1 on the stack
Enable interrupts
asm (“ mfspr r9,26”);
asm (“ stwu r9,-8(r1)”);
asm (“ mfspr r9,27”);
asm (“ stw r9,4(r1)”);
asm (“ mtspr 80,0”);
5
Request the vector number via the CPM pdpr->CIVR.IACK = 1;
Interrupt Vector Reg, CIVR
(819) /* REQUEST VECTOR NUMBER*/
6
Read the interrupt vector in the CPM
if (pdpr->CIVR.VN == 0x10
interrupt vector reg, CIVR, and go to
i2cesr();
service routine for that vector number.
/* I2C VEC NUM, GO TO I2CESR*/
(819)
7
If this is a submodule maskable event
source, read the event register.
er = pdpr->SCCE2;
/* GET EVENT REGISTER */
8
If this is a submodule maskable event
source, clear the known events.
pdpr->SCCE2 = er;
/* CLEAR EVENT REGISTER */
CPM Interrupt Controller
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How to Handle a CPIC Interrupt (2 of 2)
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Last Steps in
Servicing CPM
Interrupts
• The last steps in servicing a CPM interrupt:
1
Clear the bit in the in-service reg, CISR
2
Required only if service routine was made
recoverable.
Disable interrupts
Restore SRR0 & SRR1 on the stack
asm (“ mtspr 82,0”);
asm (“ lwz r9,4(r1)”);
asm (“ mtspr 27,r9”);
asm (“ lwz r9,0(r1)”);
asm (“ addi r1,r1,8;”)
asm (“ mtspr 26,r9”);
3
Required only if service routine was made
recoverable and lower priority interrupts
were masked.
Restore the SI mask reg, SIMASK
pdpr->SIMASK.ASINT = --sptr;
/* RESTORE SIMASK REG */
pdpr->CISR = 1<<(31-6);
(818) /* CLEAR TIMER 1 BIT */
CPM Interrupt Controller
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FREESCALE
Freescale Technical Training - MPC860 Course
Phoenix, Arizona
Title: pc8.c
Handling an 860 CPM Interrupt
Creation Date: Jan. 10, 1996
From:
MC68360 Course
Author: Bob Bratt
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Description:
The results of this routine are:
1. Initializes the exception vector area with a service routine.
2. The service routine jumps to a function based on the interrupt
code.
3. The function increments a counter each time an external interrupt
level 1 occurs.
Assumptions:
1. IMMR has been previously initialized.
2. Except for 1, reset conditions exist.
Objective:
If the program executes properly, the LED counter is equal to the
number of times that the black button on the UDLP1 has been pressed.
Equipment:
MPC860ADS board and UDLP1
UDLP1 Switch Settings: N/A
Connections:
MPC860ADS board and a UDLP1 are connected through P13.
Updates:
CPM Interrupt Controller
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pc8.c (1 of 2)
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/* Equipment : 860ADS Evaluation Board and
/*
UDLP1 Universal Development Lab Board
/*
Pins 2 and 3 of JP2 must be jumpered
/* Connected: P10-C15 of ADS to J4-11 of UDLP1
/* (PC8.C)
*/
*/
*/
*/
*/
#include "mpc860.h"
struct dprbase *pdpr;
static int buffer[10];
static int sp = 0;
/*
/*
/*
/*
DUAL PORT RAM EQUATES */
PNTR TO DUAL PORT RAM */
STACK BUFER FOR SIMASK*/
STACK BUFFER POINTER */
main()
{
void intbrn();
int *ptrs,*ptrd;
char intlvl = 4;
/* EXCEPTION SERVICE RTN */
/* SOURCE & DEST POINTERS*/
/* INTERRUPT LEVEL
*/
pdpr = (struct dprbase *) (getimmr() & 0xFFFF0000);
/* INIT PNTR TO DPRBASE */
ptrs = (int *) intbrn;
/* INIT SOURCE POINTER
*/
ptrd = (int *)(getevt() + 0x500); /* INIT DEST POINTER
*/
do
/* MOVE ESR TO EVT
*/
*ptrd++ = *ptrs;
/* MOVE UNTIL
*/
while (*ptrs++ != 0x4c000064);
/* RFI INTRUCTION
*/
pdpr->CICR.IRL0_IRL2 = (unsigned) (intlvl);
/* CPM INTERRUPTS LEVEL 4*/
pdpr->CICR.HP0_HP4 = 0x1F;
/* NO INT PRIORITY CHANGE*/
pdpr->PDDAT = 0;
/* CLEAR PORT D DATA REG */
pdpr->PDDIR = 0xff;
/* MAKE PORT D8-15 OUTPUT*/
pdpr->PCINT |= 0x80;
/* CONFIG PC8 INTRPT EDGE*/
pdpr->CIMR.PC8 = 1;
/* ENABLE PORT C,8 INTRPT*/
pdpr->SIMASK.ASTRUCT.LVM4 = 1;
/* ENABLE IRQ4 INTERRUPTS*/
pdpr->CICR.IEN = 1;
/* ENABLE CPM INTERRUPTS */
asm(" mtspr 80,0");
/* ENABLE INTERRUPTS
*/
while (1==1);
}
#pragma interrupt intbrn
void intbrn()
{
void cpmesr();
asm (" stwu r9,-4(r1)");
/* PUSH GPR9 ONTO STACK */
switch (pdpr->SIVEC.IC)
/* PROCESS INTERRUPT CODE*/
{
case 0x24: asm (" mfspr r9,8"); /* PUSH LR ONTO STACK */
asm (" stwu r9,-4(r1)");
asm (" bla cpmesr"); /* PROCESS IRQ1 CODE
*/
asm (" lwz r9,0(r1)"); /* PULL LR FROM STACK */
asm (" addi r1,r1,4"); /* RESTORE STACK POINTR*/
asm (" mtspr 8,r9");
break;
default:;
}
CPM Interrupt Controller
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pc8.c (2 of 2)
asm (" lwz r9,0(r1)");
asm (" addi r1,r1,4");
/* PULL GPR9 FROM STACK */
/* RESTORE STACK POINTER */
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}
void cpmesr()
{
unsigned v1;
/* TEMPORARY STORAGE
*/
pdpr->CIVR.IACK = 1;
/* REQUEST VECTOR NUMBER */
v1 = pdpr->CIVR.VN;
/* COPY VECTOR NUMBER
*/
buffer[sp++] = pdpr->SIMASK.ASINT;
/* STACK SIMASK */
pdpr->SIMASK.ASINT &= 0xFFC<<(31-9);
/* MASK INTS 5-7*/
asm (" mfspr r9,26");
/* PUSH SRR0 ONTO STACK */
asm (" stwu r9,-8(r1)");
asm (" mfspr r9,27");
/* PUSH SRR1 ONTO STACK */
asm (" stw r9,4(r1)");
asm (" mtspr 80,0");
/* ENABLE INTERRUPTS
*/
switch (v1)
/* PROCESS VECTOR NUMBER */
{
case 0xA:
/* PC8 VECTOR NUMBER
*/
pdpr->PDDAT += 1;
/* INCREMENT DISPLAY
*/
pdpr->CISR = 1<<(31-21);
/* CLEAR IN-SRVCE BIT*/
break;
default:;
}
asm (" mtspr 82,0");
/* MAKE NON-RECOVERABLE
*/
asm (" lwz r9,4(r1)");
/* PULL SRR1 FROM STACK
*/
asm (" mtspr 27,r9");
asm (" lwz r9,0(r1)");
/* PULL SRR0 FROM STACK
*/
asm (" addi r1,r1,8");
asm (" mtspr 26,r9");
pdpr->SIMASK.ASINT = buffer[--sp]; /* RESTORE SIU MASK REG */
}
getimmr()
{
asm(" mfspr 3,638");
}
getevt()
{
if ((getmsr() & 0x40) == 0)
return (0);
else
return (0xFFF00000);
}
getmsr()
{
asm(" mfmsr 3");
}
/* GET EVT LOCATION
/*
/*
/*
/*
*/
IF MSR.IP IS 0
*/
THEN EVT IS IN LOW MEM*/
ELSE
*/
EVT IS IN HIGH MEM
*/
/* GET MACHINE STATE REG VALUE
*/
/* LOAD MACHINE STATE REG TO r3 */
CPM Interrupt Controller
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