Integrated Communications Processors MPC866 PowerQUICC™ Family Overview MPC866 Family Block Diagram Freescale Semiconductor’s PowerQUICC™ MPC866 family is designed to deliver a 4 or 16 KB I-Cache versatile, single-chip integrated processor and peripheral combination that can be used in a Instruction Bus variety of controller applications—excelling Real-Time Clock Load/Store Bus and MPC859DSL) is engineered to deliver port-to-port switching. Freescale’s leading PowerQUICC architecture integrates two processing subsystems. One is built around the 8xx core, which is instruction set System Functions 4 or 8 KB D-Cache MPC866 family (including the MPC859T Multi-PHY, UTOPIA Slave, AAL2, VBR and Bus Interface Unit Unified Bus networking products. Like the MPC862, the ATM (UTOPIA) operation, UTOPIA II Memory Controller I-MMU Embedded 8xx Core particularly in communications and simultaneous Fast Ethernet (MII) and Parallel System Interface Unit D-MMU PCMCIA Interface Fast Ethernet Controller DMAs Parallel I/O FIFOs Four Timers Baud Rate Generators 10/100 Base-T Media Access Control Parallel Port Pins Interrupt Control Dual-Port RAM Virtual IDMA and 16 Serial DMA 32-bit Controller and Program ROM Timer MII compatible with other processors built on Power Architecture™ technology. The second SCC1 is the communications processor module SCC2 (CPM). The CPM is a dedicated RISC-based SCC3 SCC4 SMC1 Time-Slot Assigner SMC2 SPI I2 C Serial Interface communications engine designed to support four serial communications controllers (SCCs), providing a total of eight serial channels: four SCCs, two serial management controllers (SMCs), one serial peripheral interface Key Features • Enhanced ATM functionality (SPI) and one inter-integrated circuit (I2C) • Power Architecture technology • Two SMCs, one SPI and one I2C interface. This dual-processor architecture Embedded 8xx core • Many other features—timers, baud rate is designed to provide superior performance • 4 KB instruction cache over traditional architectures because the • 4 KB data cache • 8K dual-port RAM • 16 KB instruction cache in MPC866P • Available in a 357-pin RoHS compliant BGA CPM offloads communications intensive processing from the embedded 8xx core. This partitioning frees up the 8xx core to perform other system functions. generators, etc. • 8 KB data cache available in MPC866P package; MPC866 and MPC859T available • Powerful memory controller and at 100 and 133 MHz; MPC859DSL available system functions at 50 and 66 MHz • Efficient architecture that involves a • Strong third-party tools support through separate RISC processor CPM for Freescale’s Design Alliance Program handling communications • Up to four SCCs • Support for Ethernet, Fast Ethernet, HDLC, asynchronous transfer mode (ATM) and more • 0.18µ technology • 1.8V core, 3.3V I/O Typical Applications MPC 866 T VR Temp. Range None 0ºC Ta to +95ºC C -40ºC to +95ºC 800 Series Device Number (850, 860, 862, etc.) Product Code KMPC Sample Pack (2 units) MPC Fully Qualified C 100 • DSLAMs D • SOHO and enterprise routers Frequency MHz • Remote access servers Die Mask Revision Package Part/Module Modifier 357 PBGA DSL 4 KB I/D Cache ZP Non-RoHS compliant T 4 KB I/D Cache P 16 KB I-Cache/8 KB D-Cache • Wireless base stations • ISDN equipment • xDSL equipment • ATM switches • Telecom switching and transmission devices 859DSL 859T 866T 866P Serial Communications Controllers (SCCs) 1 1 4 4 • Cable modems I-Cache (KB) 4 4 4 16 • DSL modems D-Cache (KB) 4 4 4 8 • T1/E1 termination equipment Ethernet (10T) 1 1 Up to 4 Up to 4 • LAN switches Ethernet (10/100) Yes Yes Yes Yes • Wireless LAN ATM Yes Yes Yes Yes - Up to 32 Up to 64 Up to 64 Multi-Channel HDLC ·· Ethernet IEEE® 802.3 and MII Technical Specifications 32-bit scaler RISC controller • Embedded 8xx microprocessor core Two serial management controllers providing 176 MIPS (using Dhrystone 2.1) 16 serial DMA (SDMA) channels at 133 MHz One I2C port Single-issue, 32-bit version of the One serial peripheral interface embedded 8xx core with 32- x 32-bit Four general-purpose timers fixed point registers Time-slot assigner 4 KB instruction cache and 4 KB data Four baud rate generators data cache available in 866P) Enhanced ATM Functionality Memory management units with 32-entry TLBs and fully associative instruction and data TLBs • Advanced on-chip emulation debug mode • Data bus dynamic bus sizing for 8-, 16- and 32-bit buses • Communications processor module ·· HDLC ·· Asynchronous HDLC ·· Channelized HDLC ·· Multi-channel HDLC ·· UART ·· IrDA ·· Basic Rate ISDN (BRI) ·· Primary Rate ISDN (PRI) ·· Simultaneous Fast Ethernet (MII) and parallel ATM operation ·· UTOPIA II Multi-PHY and UTOPIA Slave ·· Totally transparent mode with/without CRC • System integration unit Memory controller ·· AAL2 and VBR microcode in ROM Real-time clock ·· ATM port-to-port switching PCMCIA interface Protocols supported System functions Learn More: Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. © Freescale Semiconductor, Inc. 2007 Document Number: MPC866FACT REV 4 ·· ATM ·· AppleTalk® Interrupts cache (16 KB instruction cache and 8 KB • Integrated access devices For current information about Freescale products and documentation, please visit www.freescale.com.