PIC18F97J60 FAMILY Flash Microcontroller Programming Specification 1.0 DEVICE OVERVIEW 2.0 This document includes the programming specifications for the following devices: • PIC18F66J60 • PIC18F66J65 • PIC18F67J60 • PIC18F86J60 • PIC18F86J65 • PIC18F87J60 • PIC18F96J60 • PIC18F96J65 • PIC18F97J60 PROGRAMMING OVERVIEW OF THE PIC18F97J60 FAMILY The PIC18F97J60 family devices are programmed using In-Circuit Serial Programming™ (ICSP™). This programming specification applies to devices of the PIC18F97J60 family in all package types. 2.1 Pin Diagrams The pin diagrams for the PIC18F97J60 family are shown in Figure 2-1 through Figure 2-3. The pins that are required for programming are listed in Table 2-1 and shown in darker lettering in the figures. TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18F97J60 FAMILY During Programming Pin Name MCLR VDD and AVDD(1) VSS and AVSS(1) Pin Name Pin Type Pin Description MCLR P Programming Enable VDD P Power Supply VSS P Ground ENVREG ENVREG P Internal Voltage Regulator Enable VDDCORE/VCAP VDDCORE P Regulated Power Supply for Microcontroller Core VCAP I Filter Capacitor for On-Chip Voltage Regulator RB6 PGC I Serial Clock RB7 PGD I/O Serial Data Legend: I = Input, O = Output, P = Power Note 1: All power supply and ground pins must be connected, including analog and Ethernet supplies (AVDD, VDDPLL, VDDRX, VDDTX) and grounds (AVSS, VSSPLL, VSSRX, VSSTX). © 2009 Microchip Technology Inc. DS39688D-page 1 PIC18F97J60 FAMILY FIGURE 2-1: PIC18F97J60 FAMILY PIN DIAGRAMS VDDTX TPOUT- TPOUT+ VssTX RBIAS VSSPLL VDDPLL VSS VDD RD2 RD1 RD0 RE5 RE4 RE3 RE2 64-Pin TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RE1 RE0 RB0 RB1 RF7 RF6 RF5 RF4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 RF3 RF2 15 16 RB2 RB3 MCLR RG4 VSS VDDCORE/VCAP 48 47 46 45 VDDRX 44 RB4 RB5 RB6/PGC VSS OSC2 OSC1 VDD 43 42 41 40 PIC18F66J60 PIC18F66J65 PIC18F67J60 39 38 37 36 35 34 33 TPIN+ TPINVSSRX RB7/PGD RC5 RC4 RC3 RC2 Note: DS39688D-page 2 RC7 RC6 RC0 RA4 RC1 RA5 VDD VSS RA0 RA1 RA2 AVSS RA3 AVDD ENVREG RF1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Bold-faced names indicate the pins that are required for programming. For more information, see Table 2-1. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY FIGURE 2-2: PIC18F97J60 FAMILY PIN DIAGRAMS (CONTINUED) VDDTX TPOUT- TPOUT+ RBIAS VssTX VDDPLL VSSPLL RD2 RD1 VSS VDD RD0 RE7 RE6 RE5 RE4 RE3 RE2 RH0 RH1 80-Pin TQFP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RH2 RH3 1 2 RE1 RE0 RB0 RB1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RB2 RB3 MCLR RG4 VSS VDDCORE/VCAP RF7 RF6 RF5 RF4 RF3 RF2 RH7 RH6 60 VDDRX 59 58 57 56 55 TPIN+ TPINVSSRX 54 53 52 51 50 PIC18F86J60 PIC18F86J65 PIC18F87J60 49 48 47 46 45 44 43 42 17 18 19 20 41 RG0 RG1 RB4 RB5 RB6/PGC VSS OSC2 OSC1 VDD RB7/PGD RC5 RC4 RC3 RC2 RG2 RG3 Note: RJ5 RJ4 RC7 RC6 RC0 RA4 RC1 RA5 VDD VSS RA0 RA1 RA2 AVSS RA3 AVDD ENVREG RF1 RH4 RH5 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Bold-faced names indicate the pins that are required for programming. For more information, see Table 2-1. © 2009 Microchip Technology Inc. DS39688D-page 3 PIC18F97J60 FAMILY FIGURE 2-3: PIC18F97J60 FAMILY PIN DIAGRAMS (CONTINUED) VDDPLL RBIAS VSSTX TPOUT+ TPOUTVDDTX 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 RH1 RH0 RE2 RE3 RE4 RE5 RE6 RE7 RD0 RD1 RD2 RD3 RD4 RD5 VDD VSS RD6 RD7 VSSPLL 100-Pin TQFP RH2 1 75 VDDRX RH3 2 74 TPIN+ RE1 3 73 TPIN- RE0 4 72 VSSRX RB0 5 71 RG0 RB1 6 70 RG1 RB2 7 69 RB4 RB3 8 68 RB5 NC 9 67 RB6/PGC RG6 10 66 RJ2 RG5 11 RF0 12 MCLR 13 RG4 14 65 VSS 64 OSC2 PIC18F96J65 63 OSC1 PIC18F97J60 62 VDD RJ3 PIC18F96J60 DS39688D-page 4 48 49 50 RJ1 VSS VDD RA1 RA0 RA3 RA2 AVSS ENVREG AVDD RF1 RH5 RH4 Note: RJ0 RG3 47 51 RJ5 25 46 RG2 RH6 RJ4 52 RC7 24 45 RC2 RH7 44 53 RC6 23 43 RC3 RF2 RC0 54 42 22 RC1 RC4 RF3 41 55 RA4 21 40 RC5 RF4 RA5 56 39 20 38 RB7/PGD RF5 RJ7 VSS 57 37 19 RG7 RJ6 RF6 36 58 35 18 34 VDD RF7 33 59 32 17 31 VSS VDD 30 60 29 16 28 VDDCORE/VCAP 26 15 61 27 VSS Bold-faced names indicate the pins that are required for programming. For more information, see Table 2-1. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 2.1.1 ON-CHIP VOLTAGE REGULATOR The microcontroller core of PIC18F97J60 family devices can be powered either from an external source, or from an on-chip regulator, which derives power from VDD. Both sources use the common VDDCORE/VCAP pin. The regulator is enabled by connecting VDD to the ENVREG pin. In this case, a low-ESR capacitor must be connected to the VDDCORE/VCAP pin for proper device operation. If the regulator is disabled, power to the core must be supplied on VDDCORE/VCAP. Where VDD exceeds VDDCOREMAX, power to the core must be supplied separately on VDDCORE/VCAP. Examples are shown in Figure 2-4. Whether or not the regulator is used, it is always good design practice to have sufficient capacitance on all supply pins. The specifications for core voltage and capacitance are listed in Section 6.0 “AC/DC Characteristics and Timing Requirements”. FIGURE 2-4: CONNECTIONS FOR THE ON-CHIP REGULATOR For purposes of code protection, the program memory for every device is treated as a single block. Enabling code protection thus protects the entire code memory and not individual segments. The Configuration Words for these devices are located at addresses 300000h through 300005h. These are implemented as three pairs of volatile memory registers. Each register is automatically loaded from a copy stored at the end of program memory. For this reason, the last four words of the code space (also called the Flash Configuration Words) should be written with configuration data and not executable code. The addresses of the Flash Configuration Words are also listed in Table 2-2. Refer to Section 5.0 “Configuration Word” for more information. Locations 3FFFFEh and 3FFFFFh are reserved for the device ID bits. These bits may be used by the programmer to identify what device type is being programmed and are described in Section 5.1 “Device ID Word”. These device ID bits read out normally, even after code protection. TABLE 2-2: Regulator Enabled (ENVREG Tied to VDD): 3.3V PIC18FXXJ60/65 CF VDD ENVREG VDDCORE/VCAP VSS Device Regulator Disabled (ENVREG Tied to Ground): 2.5V PIC18FXXJ60/65 VDD ENVREG VDDCORE/VCAP VSS (VDD > VDDCORE) PIC18FXXJ60/65 VDD ENVREG VDDCORE/VCAP VSS 2.2 Memory Maps PIC18F97J60 family devices are available in three program memory sizes: 64 Kbytes, 96 Kbytes and 128 Kbytes. The overall memory maps for all devices are shown in Figure 2-5. © 2009 Microchip Technology Inc. Location of Flash Configuration Words 64 FFF8h:FFFFh 96 17FF8h:17FFFh 128 1FFF8h:1FFFFh PIC18F96J60 PIC18F66J65 PIC18F86J65 PIC18F96J65 PIC18F67J60 PIC18F87J60 PIC18F97J60 2.2.1 2.5V 3.3V Program Memory (Kbytes) PIC18F66J60 PIC18F86J60 (VDD = VDDCORE) PROGRAM MEMORY SIZES FOR PIC18F97J60 FAMILY DEVICES MEMORY ADDRESS POINTER Memory in the device address space (000000h to 3FFFFFh) is addressed via the Table Pointer register, which in turn is comprised of three registers: • TBLPTRU at RAM address 0FF8h • TBLPTRH at RAM address 0FF7h • TBLPTRL at RAM address 0FF6h TBLPTRU TBLPTRH TBLPTRL Addr[21:16] Addr[15:8] Addr[7:0] The 4-bit command, ‘0000’ (core instruction), is used to load the Table Pointer prior to using many read or write operations. DS39688D-page 5 PIC18F97J60 FAMILY FIGURE 2-5: MEMORY MAPS FOR PIC18F97J60 FAMILY DEVICES PIC18FX6J60 (64 Kbytes) PIC18FX6J65 (96 Kbytes) PIC18FX7J60 (128 Kbytes) Code Memory Code Memory Code Memory 000000h Flash Configuration Words 00FFFFh Flash Configuration Words Unimplemented Read as ‘0’ 017FFFh Flash Configuration Words Unimplemented Read as ‘0’ 01FFFFh Unimplemented Read as ‘0’ 1FFFFFh 200000h Configuration Space Configuration Space Configuration Space Configuration Words Configuration Words Configuration Words Configuration Space Configuration Space Configuration Space Device IDs Device IDs Device IDs 2FFFFFh 300000h 300005h 3FFFFEh 3FFFFFh Memory spaces are unimplemented or unavailable in normal execution mode and read as ‘0’. Memory spaces are read-only (Device IDs) or cannot be directly programmed by ICSP™ (Configuration Words). Note: Sizes of memory areas are not to scale. Sizes of accessible memory areas are enhanced to show detail. DS39688D-page 6 © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 2.3 Overview of the Programming Process 2.4 Figure 2-6 shows the high-level overview of the programming process. First, a Bulk Erase is performed. Next, the code memory is programmed. Since the only nonvolatile Configuration Words are within the code memory space, they too are programmed as if they were code. Code memory (including the Configuration Words) is then verified to ensure that programming was successful. FIGURE 2-6: Entering and Exiting ICSP Program/Verify Mode Entry into ICSP modes for PIC18F97J60 family devices is somewhat different than previous PIC18 devices. As shown in Figure 2-7, entering ICSP Program/Verify mode requires three steps: 1. 2. 3. Voltage is briefly applied to the MCLR pin. A 32-bit key sequence is presented on PGD. Voltage is reapplied to MCLR and held. The programming voltage applied to MCLR is VIH, or usually, VDD. There is no minimum time requirement for holding at VIH. After VIH is removed, an interval of at least P19 must elapse before presenting the key sequence on PGD. HIGH-LEVEL PROGRAMMING FLOW Start The key sequence is a specific 32-bit pattern, ‘0100 1101 0100 0011 0100 1000 0101 0000’ (more easily remembered as 4D434850h in hexadecimal). The device will enter Program/Verify mode only if the sequence is valid. The Most Significant bit of the most significant nibble must be shifted in first. Enter ICSP™ Perform Bulk Erase Once the key sequence is complete, VIH must be applied to MCLR and held at that level for as long as Program/Verify mode is to be maintained. An interval of at least time P20 and P12 must elapse before presenting data on PGD. Signals appearing on PGD before P12 has elapsed may not be interpreted as valid. Program Memory Verify Program On successful entry, the program memory can be accessed and programmed in serial fashion. While in the Program/Verify mode, all unused I/Os are placed in the high-impedance state. Exit ICSP Exiting Program/Verify mode is done by removing VIH from MCLR, as shown in Figure 2-8. The only requirement for exit is that an interval, P16, should elapse between the last clock and program signals on PGC and PGD before removing VIH. Done When VIH is reapplied to MCLR, the device will enter the ordinary operational mode and begin executing the application instructions. FIGURE 2-7: ENTERING PROGRAM/VERIFY MODE P13 P20 MCLR VDD P12 VIH VIH Program/Verify Entry Code = 4D434850h 0 b31 PGD 1 b30 0 b29 0 b28 1 b27 ... 0 b3 0 b2 0 b1 0 b0 PGC P19 © 2009 Microchip Technology Inc. P2B P2A DS39688D-page 7 PIC18F97J60 FAMILY FIGURE 2-8: EXITING PROGRAM/ VERIFY MODE Throughout this specification, commands and data are presented as illustrated in Table 2-4. The 4-bit command is shown Most Significant bit (MSb) first. The command operand, or “Data Payload”, is shown <MSB><LSB>. Figure 2-9 demonstrates how to serially present a 20-bit command/operand to the device. P16 VIH MCLR VDD 2.5.2 VIH PGD CORE INSTRUCTION The core instruction passes a 16-bit instruction to the CPU core for execution. This is needed to set up registers as appropriate for use with other commands. PGC TABLE 2-3: COMMANDS FOR PROGRAMMING PGD = Input 4-Bit Command Description 2.5 Serial Program/Verify Operation The PGC pin is used as a clock input pin and the PGD pin is used for entering command bits and data input/ output during serial operation. Commands and data are transmitted on the rising edge of PGC, latched on the falling edge of PGC and are Least Significant bit (LSb) first. 2.5.1 4-BIT COMMANDS Core Instruction (Shift in 16-bit instruction) 0000 Shift Out TABLAT Register 0010 Table Read 1000 Table Read, Post-Increment 1001 Table Read, Post-Decrement 1010 Table Read, Pre-Increment 1011 Table Write 1100 All instructions are 20 bits, consisting of a leading 4-bit command, followed by a 16-bit operand, which depends on the type of command being executed. To input a command, PGC is cycled four times. The commands needed for programming and verification are shown in Table 2-3. Table Write, Post-Increment by 2 1101 Table Write, Start Programming, Post-Increment by 2 1110 Table Write, Start Programming 1111 Depending on the 4-bit command, the 16-bit operand represents 16 bits of input data or 8 bits of input data and 8 bits of output data. TABLE 2-4: FIGURE 2-9: SAMPLE COMMAND SEQUENCE 4-Bit Command Data Payload 1101 3C 40 Core Instruction Table Write, post-increment by 2 TABLE WRITE, POST-INCREMENT TIMING (1101) P2 P2A P2B 1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2 1 3 4 PGC P5A P5 P4 P3 PGD 1 0 1 1 0 0 0 0 4-Bit Command 0 0 0 1 0 0 0 1 4 C 16-Bit Data Payload 1 1 1 0 0 n n n n 3 Fetch Next 4-Bit Command PGD = Input DS39688D-page 8 © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 3.0 DEVICE PROGRAMMING TABLE 3-1: Programming includes the ability to erase or write the memory within the device. 4-Bit Command The EECON1 register is used to control write or row erase operations. The WREN bit must be set to enable writes; this must be done prior to initiating a write sequence. It is strongly recommended that the WREN bit only be set immediately prior to a program or erase operation. The FREE bit must be set in order to erase the program space being pointed to by the Table Pointer. The erase or write sequence is initiated by setting the WR bit. 3.1 ICSP Erase 3.1.1 ICSP BULK ERASE Devices of the PIC18F97J60 family may be Bulk Erased by writing 0180h to the table address 3C0005h:3C0004h. The basic sequence is shown in Figure 3-1 and demonstrated in Table 3-1. Since the code-protect Configuration bit is stored in the program code within code memory, a Bulk Erase operation will also clear any code-protect settings for the device. BULK ERASE COMMAND SEQUENCE Data Payload 0000 0000 0000 0000 0000 0000 1100 0000 0000 0000 0000 0000 0000 1100 0E 6E 0E 6E 0E 6E 01 0E 6E 0E 6E 0E 6E 80 0000 0000 00 00 00 00 3C F8 00 F7 05 F6 01 3C F8 00 F7 04 F6 80 MOVLW 3Ch MOVWF TBLPTRU MOVLW 00h MOVWF TBLPTRH MOVLW 05h MOVWF TBLPTRL Write 01h to 3C0005h MOVLW 3Ch MOVWF TBLPTRU MOVLW 00h MOVWF TBLPTRH MOVLW 04h MOVWF TBLPTRL Write 80h TO 3C0004h to erase entire device. NOP Hold PGD low until erase completes. FIGURE 3-1: BULK ERASE FLOW Start The actual Bulk Erase function is a self-timed operation. Once the erase has started (falling edge of the 4th PGC after the NOP command), serial execution will cease until the erase completes (parameter P11). During this time, PGC may continue to toggle but PGD must be held low. Note: Core Instruction Write 0101h to 3C0005h Write 8080h to 3C0004h to Erase Entire Device A Bulk Erase is the only way to reprogram the code-protect Configuration bit from an ON state to an OFF state. Delay P11 Time Done FIGURE 3-2: BULK ERASE TIMING P5 1 2 3 4 1 2 15 16 1 2 3 4 1 2 15 16 1 2 3 4 1 2 n n PGC P5A P5 PGD 0 0 1 1 4-Bit Command 1 1 0 16-Bit Data Payload 0 P5A P5 0 0 0 0 4-Bit Command 0 0 0 16-Bit Data Payload 0 P11 0 0 0 0 4-Bit Command Erase Time 16-Bit Data Payload PGD = Input © 2009 Microchip Technology Inc. DS39688D-page 9 PIC18F97J60 FAMILY 3.1.2 ICSP ROW ERASE FIGURE 3-3: ROW ERASE CODE MEMORY FLOW It is possible to erase a single row (1024 bytes of data), provided the block is not code-protected. Rows are located at static boundaries beginning at program memory address 000000h, extending to the internal program memory limit (see Section 2.2 “Memory Maps”). Start Addr = 0 Configure Device for Row Erase The Row Erase duration is internally timed. After the WR bit in EECON1 is set, a NOP is issued, where the 4th PGC is held high for the duration of the Row Erase time, P10. Addr = Addr + 1024 The code sequence to Row Erase a PIC18F97J60 family device is shown in Table 3-2. The flowchart shown in Figure 3-3 depicts the logic necessary to completely erase a PIC18F97J60 family device. The timing diagram that details the “Row Erase” operation and parameter P10 is shown in Figure 3-4. Note: Start Erase Sequence and Hold PGC High for Time P10 All Rows Done? No Yes Done The TBLPTR register can point at any byte within the row intended for erase. TABLE 3-2: ERASE CODE MEMORY CODE SEQUENCE 4-Bit Command Data Payload Core Instruction Step 1: Enable memory writes. 0000 84 A6 BSF EECON1, WREN CLRF CLRF CLRF TBLPTRU TBLPTRH TBLPTRL Step 2: Point to first row in code memory. 0000 0000 0000 6A F8 6A F7 6A F6 Step 3: Enable erase and erase single row. 0000 0000 0000 88 A6 82 A6 00 00 BSF EECON1, FREE BSF EECON1, WR NOP – hold PGC high for time P10. Step 4: Repeat step 3, with Address Pointer incremented by 1024 until all rows are erased. FIGURE 3-4: SET WR AND START ROW-ERASE TIMING P5 1 2 3 4 1 3 2 4 5 6 15 16 1 2 3 4 PGC 2 3 P5A P5 PGD 1 P10 0 0 0 0 4-Bit Command 0 1 1 0 0 1 0 1 16-Bit Data Payload 0 0 0 0 4-Bit Command 0 Row-Erase Time 0 0 16-Bit Data Payload PGD = Input DS39688D-page 10 © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 3.2 Code Memory Programming Programming code memory is accomplished by first loading data into the write buffer and then initiating a programming sequence. The write buffer for all devices in the PIC18F97J60 family is 64 bytes; it can be mapped to any integral boundary of 64 bytes, beginning at 000000h. The actual memory write sequence takes the contents of this buffer and programs the 64 bytes of code memory that contains the Table Pointer. Write buffer locations are not cleared following a write operation; the buffer retains its data after the write is complete. This means that the buffer must be written with 64 bytes on each operation. If there are locations in the code memory that are to remain empty, the corresponding locations in the buffer must be filled with FFFFh. This avoids rewriting old data from the previous cycle. The code sequence to program a PIC18F97J60 family device is shown in Table 3-3. The flowchart shown in Figure 3-5 depicts the logic necessary to completely write a PIC18F97J60 family device. The timing diagram that details the Start Programming command and parameter P9 is shown in Figure 3-6. Note 1: To maintain the endurance specification of the Flash program memory cells, each 64-byte block of program memory should never be programmed more than once between erase operations. If any byte within a 64-byte block of program memory is written, that entire block must not be written to again until a Bulk Erase on the part, or a Row Erase on the row containing the modified 64-byte block, has been performed. The programming duration is internally timed. After a Start Programming command is issued (4-bit command, ‘1111’), a NOP is issued, where the 4th PGC is held high for the duration of the programming time, P9. TABLE 3-3: 2: The TBLPTR register must point to the same region when initiating the programming sequence as it did when the write buffers were loaded. WRITE CODE MEMORY CODE SEQUENCE 4-Bit Command Data Payload Core Instruction Step 1: Enable writes. 0000 84 A6 BSF EECON1, WREN MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF <Addr[21:16]> TBLPTRU <Addr[15:8]> TBLPTRH <Addr[7:0]> TBLPTRL Step 2: Load write buffer. 0000 0000 0000 0000 0000 0000 0E 6E 0E 6E 0E 6E <Addr[21:16]> F8 <Addr[15:8]> F7 <Addr[7:0]> F6 Step 3: Repeat for all but the last two bytes. Any unused locations should be filled with FFFFh. 1101 <MSB><LSB> Write 2 bytes and post-increment address by 2. Step 4: Load write buffer for last two bytes. 1111 0000 <MSB><LSB> 00 00 Write 2 bytes and start programming. NOP - hold PGC high for time P9. To continue writing data, repeat steps 2 through 4, where the Address Pointer is incremented by 2 at each iteration of the loop. © 2009 Microchip Technology Inc. DS39688D-page 11 PIC18F97J60 FAMILY FIGURE 3-5: PROGRAM CODE MEMORY FLOW Start N=1 LoopCount = 0 Configure Device for Writes Load 2 Bytes to Write Buffer at <Addr> N=N+1 All Bytes Written? No N=1 LoopCount = LoopCount + 1 Yes Start Write Sequence and Hold PGC High Until Done and Wait P9 All Locations Done? No Yes Done FIGURE 3-6: TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111) P5 1 2 3 4 1 3 2 4 5 6 15 16 1 2 3 4 PGC 2 3 P5A P5 PGD 1 P9 1 1 1 1 4-Bit Command n n n n n n n n 16-Bit Data Payload 0 0 0 0 4-Bit Command 0 Programming Time 0 0 16-Bit Data Payload PGD = Input DS39688D-page 12 © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 3.2.1 MODIFYING CODE MEMORY 3.2.2 The previous programming example assumed that the device had been Bulk Erased prior to programming. It may be the case, however, that the user wishes to modify only a section of an already programmed device. The appropriate number of bytes required for the erase buffer (1,024 bytes) must be read out of code memory (as described in Section 4.2 “Verify Code Memory and Configuration Word”) and buffered. Modifications can be made on this buffer. Then, the row of code memory that was read out must be erased and rewritten with the modified data. The code sequence is shown in Table 3-4. CONFIGURATION WORD PROGRAMMING Since the Flash Configuration Words are stored in program memory, they are programmed as if they were program data. Refer to Section 3.2 “Code Memory Programming” and Section 3.2.1 “Modifying Code Memory” for methods and examples on programming or modifying program memory. See also Section 5.0 “Configuration Word” for additional information on the Configuration Words. The WREN bit must be set if the WR bit in EECON1 is used to initiate a write sequence. TABLE 3-4: MODIFYING CODE MEMORY 4-Bit Command Data Payload Core Instruction Step 1: Set the Table Pointer for the block to be erased. 0000 0000 0000 0000 0000 0000 0E 6E 0E 6E 0E 6E <Addr[21:16]> F8 <Addr[8:15]> F7 <Addr[7:0]> F6 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF <Addr[21:16]> TBLPTRU <Addr[8:15]> TBLPTRH <Addr[7:0]> TBLPTRL Step 2: Enable memory writes and set up an erase. 0000 0000 84 A6 88 A6 BSF BSF EECON1, WREN EECON1, FREE Step 3: Initiate erase. 0000 0000 82 A6 00 00 BSF EECON1, WR NOP - hold PGC high for time P10. Step 4: Load write buffer. The correct bytes will be selected based on the Table Pointer. 0000 0000 0000 0000 0000 0000 1101 . . . 1111 0000 0E <Addr[21:16]> 6E F8 0E <Addr[8:15]> 6E F7 0E <Addr[7:0]> 6E F6 <MSB><LSB> . . . <MSB><LSB> 00 00 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF Write 2 <Addr[21:16]> TBLPTRU <Addr[8:15]> TBLPTRH <Addr[7:0]> TBLPTRL bytes and post-increment address by 2. Repeat write operation 30 more times to fill the write buffer Write 2 bytes and start programming. NOP - hold PGC high for time P9. Step 5: Repeat Step 4, for a total of 16 times, to completely rewrite the 1024 bytes of the erase buffer. Step 6: To continue modifying data, repeat Steps 1 through 4, where the Address Pointer is incremented by 1024 bytes at each iteration of the loop. Step 7: Disable writes. 0000 94 A6 © 2009 Microchip Technology Inc. BCF EECON1, WREN DS39688D-page 13 PIC18F97J60 FAMILY 4.0 READING THE DEVICE 4.1 Read Code Memory P6 must be introduced after the falling edge of the 8th PGC of the operand to allow PGD to transition from an input to an output. During this time, PGC must be held low (see Figure 4-1). This operation also increments the Table Pointer by one, pointing to the next byte in code memory for the next read. Code memory is accessed one byte at a time via the 4-bit command, ‘1001’ (table read, post-increment). The contents of memory pointed to by the Table Pointer (TBLPTRU:TBLPTRH:TBLPTRL) are serially output on PGD. This technique will work to read any memory in the 000000h to 3FFFFFh address space, so it also applies to the reading of the Configuration registers. The 4-bit command is shifted in LSb first. The read is executed during the next 8 clocks, then shifted out on PGD during the last 8 clocks, LSb to MSb. A delay of TABLE 4-1: READ CODE MEMORY SEQUENCE 4-Bit Command Data Payload Core Instruction Step 1: Set Table Pointer. 0000 0000 0000 0000 0000 0000 0E 6E 0E 6E 0E 6E <Addr[21:16]> F8 <Addr[15:8]> F7 <Addr[7:0]> F6 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF Addr[21:16] TBLPTRU <Addr[15:8]> TBLPTRH <Addr[7:0]> TBLPTRL Step 2: Read memory and then shift out on PGD, LSb to MSb. 1001 00 00 FIGURE 4-1: 1 TBLRD *+ TABLE READ, POST-INCREMENT INSTRUCTION TIMING (1001) 2 3 4 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15 1 16 2 3 4 PGC P5 P5A P6 P14 PGD 1 0 0 LSb 1 1 2 3 4 5 Shift Data Out PGD = Input DS39688D-page 14 PGD = Output 6 MSb n n n n Fetch Next 4-Bit Command PGD = Input © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 4.2 Verify Code Memory and Configuration Word 4.3 The verify step involves reading back the code memory space and comparing it against the copy held in the programmer’s buffer. Because the Flash Configuration Words are stored at the end of program memory, it is verified with the rest of the code at this time. The verify process is shown in the flowchart in Figure 4-2. Memory reads occur a single byte at a time, so two bytes must be read to compare against the word in the programmer’s buffer. Refer to Section 4.1 “Read Code Memory” for implementation details of reading code memory. Note: Because the Flash Configuration Word contains the device code protection bit, code memory should be verified immediately after writing if code protection is enabled. This is because the device will not be readable or verifiable if a device Reset occurs after the Flash Configuration Words (and the CP0 bit) have been cleared. FIGURE 4-2: VERIFY CODE MEMORY FLOW Start Blank Check The term “Blank Check” means to verify that the device has no programmed memory cells. All memories must be verified: code memory and Configuration bits. The Device ID registers (3FFFFEh:3FFFFFh) should be ignored. A “blank” or “erased” memory cell will read as a ‘1’. So, Blank Checking a device merely means to verify that all bytes read as FFh. The overall process flow is shown in Figure 4-3. Note: Following a device Bulk Erase, the Configuration Words will read as shown in Table 5-2. Given that Blank Checking is merely code verification with FFh expect data, refer to Section 4.2 “Verify Code Memory and Configuration Word” for implementation details. FIGURE 4-3: BLANK CHECK FLOW Start Blank Check Device Is Device Blank? Set TBLPTR = 0 Yes Continue No Abort Read Low Byte with Post-Increment Read High Byte with Post-Increment Does Word = Expect Data? No Failure, Report Error Yes No All Code Memory Verified? Yes Done © 2009 Microchip Technology Inc. DS39688D-page 15 PIC18F97J60 FAMILY 5.0 CONFIGURATION WORD TABLE 5-1: The Configuration Words of the PIC18F97J60 family devices are implemented as volatile memory registers, as opposed to the programmable nonvolatile memory used in other PIC18 devices. All of the Configuration registers (CONFIG1L, CONFIG1H, CONFIG2L, CONFIG2H, CONFIG3L and CONFIG3H) are automatically loaded following each device Reset. The data for these registers is taken from the four Flash Configuration Words located at the end of program memory. Configuration data is stored in order, starting with CONFIG1L in the lowest Flash address and ending with CONFIG4H in the last address. The mapping to specific Configuration Words is shown in Table 5-1. While four words are reserved in program memory, only three words (CONFIG1L through CONFIG3H) are used for device configuration. Users should always reserve these locations for Configuration Word data and write their application code accordingly. Configuration Byte MAPPING OF THE FLASH CONFIGURATION WORDS TO THE CONFIGURATION REGISTERS Code Space Address(1) Configuration Register Address CONFIG1L XXXF8h 300000h CONFIG1H XXXF9h 300001h CONFIG2L XXXFAh 300002h CONFIG2H XXXFBh 300003h CONFIG3L XXXFCh 300004h CONFIG3H XXXFDh 300005h CONFIG4L(2) XXXFEh 300006h CONFIG4H(2) XXXFFh 300007h Note 1: The upper four bits of each Configuration Word should always be stored in program memory as ‘1111’. This is done so these program memory addresses will always be ‘1111 xxxx xxxx xxxx’ and interpreted as a NOP instruction if they were ever to be executed. Because the corresponding bits in the Configuration Words are unimplemented, they will not change the device’s configuration. 2: See Table 2-2 for the complete addresses within code space for specific devices and memory sizes. Unimplemented in PIC18F97J60 family devices. The Configuration and Device ID registers are summarized in Table 5-2. A listing of the individual Configuration bits and their options is provided in Table 5-3. TABLE 5-2: CONFIGURATION BITS AND DEVICE IDS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/ Unprogrammed Value 300000h CONFIG1L DEBUG XINST STVREN — — — — WDTEN 111- ---1 300001h CONFIG1H —(1) —(1) —(1) —(1) —(2) CP0 — — ---- 01-- 300002h CONFIG2L IESO FCMEN — — — FOSC2 FOSC1 FOSC0 11-- -111 300003h CONFIG2H —(1) —(1) —(1) —(1) WDTPS3 WDTPS2 WDTPS1 WDTPS0 ---- 1111 300004h CONFIG3L WAIT(3) BW(3) EMB1(3) — — — 300005h CONFIG3H (1) — (1) — (1) — EMB0(3) EASHFT(3) —(1) — ETHLED ECCPMX(4) CCP2MX(4) 1111 1------ -111 3FFFFEh DEVID1(5) DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 See Table 5-4 3FFFFFh DEVID2(5) DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 See Table 5-4 Legend: Note 1: 2: 3: 4: 5: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’. The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOP if it is accidentally executed. This bit should always be maintained as ‘0’. Implemented in 100-pin devices only. Implemented in 80-pin and 100-pin devices only. This bit should always be maintained as ‘1’ for 64-pin devices. DEVID registers are read-only and cannot be programmed by the user. DS39688D-page 16 © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 5-3: Bit Name PIC18F97J60 FAMILY BIT DESCRIPTIONS Configuration Words Description DEBUG CONFIG1L Background Debugger Enable bit 1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled, RB6 and RB7 are dedicated to in-circuit debug XINST CONFIG1L Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode enabled 0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode) STVREN CONFIG1L Stack Overflow/Underflow Reset Enable bit 1 = Reset on stack overflow/underflow enabled 0 = Reset on stack overflow/underflow disabled WDTEN CONFIG1L Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on SWDTEN bit) CP0 CONFIG1H Code Protection bit 1 = Program memory is not code-protected 0 = Program memory is code-protected IESO CONFIG2L Internal/External Oscillator Switchover bit 1 = Oscillator Switchover mode enabled 0 = Oscillator Switchover mode disabled FCMEN CONFIG2L Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled FOSC2 CONFIG2L Primary Oscillator Select bit 1 = Default primary oscillator on start-up is EC or HS, depending on settings of FOSC1:FOSC0; INTRC selected when OSCCON<1:0> = 11 0 = Default primary oscillator on start-up is INTRC; INTRC also selected when OSCCON<1:0> = 11 or 00 FOSC1:FOSC0 CONFIG2L Oscillator Selection bits 11 = EC oscillator, PLL enabled and under software control, CLKO function on OSC2 10 = EC oscillator, CLKO function on OSC2 01 = HS oscillator, PLL enabled and under software control 00 = HS oscillator © 2009 Microchip Technology Inc. DS39688D-page 17 PIC18F97J60 FAMILY TABLE 5-3: PIC18F97J60 FAMILY BIT DESCRIPTIONS (CONTINUED) Bit Name Configuration Words WDTPS3:WDTPS0 CONFIG2H Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 WAIT CONFIG3L External Bus Wait Enable bit 1 = Wait states for operations on external memory bus disabled 0 = Wait states for operations on external memory bus enabled BW CONFIG3L Data Bus Width Select bit 1 = 16-Bit External Bus mode 0 = 8-Bit External Bus mode EMB1:EMB0 CONFIG3L External Memory Bus Configuration bits 11 = Microcontroller mode – external bus disabled 10 = Extended Microcontroller mode,12-Bit Address mode 01 = Extended Microcontroller mode,16-Bit Address mode 00 = Extended Microcontroller mode, 20-Bit Address mode EASHFT CONFIG3L External Address Bus Shift Enable bit 1 = Address shifting enabled; address on external bus is offset to start at 000000h 0 = Address shifting disabled; address on external bus reflects the PC value ETHLED CONFIG3H Ethernet LED Enable bit 1 = RA0/RA1 are multiplexed with LEDA/LEDB when Ethernet module is enabled and function as I/O when Ethernet is disabled 0 = RA0/RA1 function as I/O regardless of Ethernet module status ECCPMX CONFIG3H ECCP MUX bit 1 = ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3 0 = ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4 CCP2MX CONFIG3H CCP2 MUX bit 1 = ECCP2/P2A is multiplexed with RC1 0 = ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode (100-pin devices only) DS39688D-page 18 Description © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 5.1 FIGURE 5-1: Device ID Word The device ID word for the PIC18F97J60 family devices is located at 3FFFFEh:3FFFFFh. These readonly bits may be used by the programmer to identify what device type is being programmed and read out normally, even after Code Protection has been enabled. The process for reading the device IDs is shown in Figure 5-1. A complete list of device ID values for the PIC18F97J60 family is presented in Table 5-4. READ DEVICE ID WORD FLOW Start Set TBLPTR = 3FFFFE Read Low Byte with Post-Increment Read High Byte with Post-Increment Done TABLE 5-4: DEVICE ID VALUES Device ID Value Device DEVID2 DEVID1 PIC18F66J60 18h 000x xxxx PIC18F66J65 1Fh 000x xxxx PIC18F67J60 1Fh 001x xxxx PIC18F86J60 18h 001x xxxx PIC18F86J65 1Fh 010x xxxx PIC18F87J60 1Fh 011x xxxx PIC18F96J60 18h 010x xxxx PIC18F96J65 1Fh 100x xxxx PIC18F97J60 1Fh 101x xxxx Legend: The ‘x’s in DEVID1 are reserved for the device revision code. © 2009 Microchip Technology Inc. DS39688D-page 19 PIC18F97J60 FAMILY 5.2 Checksum Computation The checksum is calculated by summing the contents of all code memory locations and the device Configuration Words, appropriately masked. The Least Significant 16 bits of this sum are the checksum. The checksum calculation differs depending on whether or not code protection is enabled. Since the code memory locations read out differently depending on the code-protect setting, the table describes how to manipulate the actual code memory values to simulate TABLE 5-5: Device PIC18F66J60 PIC18F66J65 PIC18F67J60 PIC18F86J60 PIC18F86J65 PIC18F87J60 PIC18F96J60 PIC18F96J65 PIC18F97J60 the values that would be read from a protected device. When calculating a checksum by reading a device, the entire code memory can simply be read and summed. The Configuration Words can always be read. Table 5-5 describes how to calculate the checksum for each device. CHECKSUM COMPUTATION Code Protection Checksum Off SUM[000000:00FFF7] + ([00FFF8] & E1h) + ([00FFF9] & 0Ch) + ([00FFFA] & C7h) + ([00FFFB] & 0Fh) + ([00FFFD] & 04h) On 0000h Off SUM[000000:017FF7] + ([00FFF8] & E1h) + ([00FFF9] & 0Ch) + ([00FFFA] & C7h) + ([00FFFB] & 0Fh) + ([00FFFD] & 04h) On 0000h Off SUM[000000:01FFF7] + ([00FFF8] & E1h) + ([00FFF9] & 0Ch) + ([00FFFA] & C7h) + ([00FFFB] & 0Fh) + ([00FFFD] & 04h) On 0000h Off SUM[000000:00FFF7] + ([017FF8] & E1h) + ([017FF9] & 0Ch) + ([017FFA] & C7h) + ([017FFB] & 0Fh) + ([017FFD] & 07h) On 0000h Off SUM[000000:017FF7] + ([017FF8] & E1h) + ([017FF9] & 0Ch) + ([017FFA] & C7h) + ([017FFB] & 0Fh) + ([017FFD] & 07h) On 0000h Off SUM[000000:01FFF7] + ([017FF8] & E1h) + ([017FF9] & 0Ch) + ([017FFA] & C7h) + ([017FFB] & 0Fh) + ([017FFD] & 07h) On 0000h Off SUM[000000:00FFF7] + ([01FFF8] & E1h) + ([01FFF9] & 0Ch) + ([01FFFA] & C7h) + ([01FFFB] & 0Fh) + ([01FFFC] & F8h) + ([01FFFD] & 07h) On 0000h Off SUM[000000:017FF7] + ([01FFF8] & E1h) + ([01FFF9] & 0Ch) + ([01FFFA] & C7h) + ([01FFFB] & 0Fh) + ([01FFFC] & F8h) + ([01FFFD] & 07h) On 0000h Off SUM[000000:01FFF7] + ([01FFF8] & E1h) + ([01FFF9] & 0Ch) + ([01FFFA] & C7h) + ([01FFFB] & 0Fh) + ([01FFFC] & F8h) + ([01FFFD] & 07h) On 0000h Legend: [a] = Value at address a; SUM[a:b] = Sum of locations a to b inclusive; + = Addition; & = Bitwise AND. All addresses are hexadecimal. DS39688D-page 20 © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 6.0 AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS TABLE 6-1: TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE Standard Operating Conditions Operating Temperature: 25°C is recommended Param No. Sym Characteristic VDDCORE External Supply Voltage for Microcontroller Core D111 VDD Supply Voltage During Programming Min Max Units 2.35 2.70 V (Note 1) V Normal programming (Note 2) ENVREG = VSS VDDCORE 3.60 ENVREG = VDD 2.65 3.60 Conditions D112 IPP Programming Current on MCLR — 5 μA D113 IDDP Supply Current During Programming — 10 mA D031 VIL Input Low Voltage VSS 0.2 VDD V D041 VIH Input High Voltage 0.8 VDD VDD V D080 VOL Output Low Voltage — 0.4 V D090 VOH Output High Voltage 2.4 — V IOH = -8 mA @ 3.3V D012 CIO Capacitive Loading on I/O pin (PGD) — 50 pF To meet AC specifications CF Filter Capacitor Value on VCAP 1 — μF Required for controller core operation when voltage regulator is enabled Note 1: 2: IOL = 8 mA @ 3.3V VDDCORE must be supplied to the VDDCORE/VCAP pin if the on-chip voltage regulator is disabled. See Section 2.1.1 “On-Chip Voltage Regulator” for more information. VDD must also be supplied to the AVDD pins during programming and to the ENVREG if the on-chip voltage regulator is used. AVDD and AVSS should always be within ±0.3V of VDD and VSS, respectively. © 2009 Microchip Technology Inc. DS39688D-page 21 PIC18F97J60 FAMILY TABLE 6-1: TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE (CONTINUED) Standard Operating Conditions Operating Temperature: 25°C is recommended Param No. Sym Characteristic Min Max Units ns P2 TPGC Serial Clock (PGC) Period 100 — P2A TPGCL Serial Clock (PGC) Low Time 40 — ns P2B TPGCH Serial Clock (PGC) High Time 40 — ns P3 TSET1 Input Data Setup Time to Serial Clock ↓ 15 — ns P4 THLD1 Input Data Hold Time from PGC ↓ 15 — ns P5 TDLY1 Delay between 4-bit Command and Command Operand 40 — ns P5A TDLY1A Delay between 4-bit Command Operand and Next 4-bit Command 40 — ns P6 TDLY2 Delay between Last PGC ↓ of Command Byte to First PGC ↑ of Read of Data Word 20 — ns P9 TDLY5 Delay to allow Block Programming to Occur 3.4 — ms P10 TDLY6 Delay to allow Row Erase to Occur 49 — ms P11 TDLY7 Delay to allow Bulk Erase to Occur 475 — ms P12 THLD2 Input Data Hold Time from MCLR ↑ 400 — μs P13 TSET2 VDD ↑ Setup Time to MCLR ↑ 100 — ns P14 TVALID Data Out Valid from PGC ↑ 10 — ns P16 TDLY8 Delay between Last PGC ↓ and MCLR ↓ 20 — ns P19 TKEY1 Delay from First MCLR ↓ to First PGC ↑ for Key Sequence on PGD 1 — ms P20 TKEY2 Delay from Last PGC ↓ for Key Sequence on PGD to Second MCLR ↑ 40 — ns Note 1: 2: Conditions VDDCORE must be supplied to the VDDCORE/VCAP pin if the on-chip voltage regulator is disabled. See Section 2.1.1 “On-Chip Voltage Regulator” for more information. VDD must also be supplied to the AVDD pins during programming and to the ENVREG if the on-chip voltage regulator is used. AVDD and AVSS should always be within ±0.3V of VDD and VSS, respectively. DS39688D-page 22 © 2009 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2009 Microchip Technology Inc. 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