MX25L12845G MX25L12845G 3V, 128M-BIT [x 1/x 2/x 4] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY MX25L12845G Contents 1. FEATURES............................................................................................................................................................... 4 2. GENERAL DESCRIPTION...................................................................................................................................... 6 Table 1. Read performance Comparison.....................................................................................................6 3. PIN CONFIGURATIONS .......................................................................................................................................... 7 4. PIN DESCRIPTION................................................................................................................................................... 7 5. BLOCK DIAGRAM.................................................................................................................................................... 8 6. DATA PROTECTION................................................................................................................................................. 9 Table 2. Protected Area Sizes....................................................................................................................10 Table 3. 4K-bit Secured OTP Definition..................................................................................................... 11 7. Memory Organization............................................................................................................................................ 12 Table 4. Memory Organization...................................................................................................................12 8. DEVICE OPERATION............................................................................................................................................. 13 8-1. Quad Peripheral Interface (QPI) Read Mode........................................................................................... 15 9. COMMAND DESCRIPTION.................................................................................................................................... 16 9-1. 9-2. 9-3. 9-4. 9-5. 9-6. 9-7. 9-8. 9-9. 9-10. 9-11. 9-12. 9-13. 9-14. 9-15. 9-16. 9-17. 9-18. 9-19. 9-20. 9-21. 9-22. 9-23. 9-24. P/N: PM2145 Table 5. Command Set...............................................................................................................................16 Write Enable (WREN)............................................................................................................................... 20 Write Disable (WRDI)................................................................................................................................ 21 Factory Mode Enable (FMEN).................................................................................................................. 22 Read Identification (RDID)........................................................................................................................ 23 Release from Deep Power-down (RDP), Read Electronic Signature (RES)............................................ 24 Read Electronic Manufacturer ID & Device ID (REMS)............................................................................ 26 QPI ID Read (QPIID)................................................................................................................................ 27 Table 6. ID Definitions ...............................................................................................................................27 Read Status Register (RDSR).................................................................................................................. 28 Read Configuration Register (RDCR)....................................................................................................... 29 Table 7. Configuration Register..................................................................................................................33 Write Status Register (WRSR).................................................................................................................. 35 Table 8. Protection Modes..........................................................................................................................36 Read Data Bytes (READ)......................................................................................................................... 39 Read Data Bytes at Higher Speed (FAST_READ)................................................................................... 40 Dual Output Read Mode (DREAD)........................................................................................................... 42 2 x I/O Read Mode (2READ).................................................................................................................... 43 Quad Read Mode (QREAD)..................................................................................................................... 44 4 x I/O Read Mode (4READ).................................................................................................................... 45 4 x I/O Double Transfer Rate Read Mode (4DTRD)................................................................................. 47 Preamble Bit ............................................................................................................................................ 49 Burst Read................................................................................................................................................ 53 Performance Enhance Mode.................................................................................................................... 54 Performance Enhance Mode Reset.......................................................................................................... 57 Sector Erase (SE)..................................................................................................................................... 58 Block Erase (BE32K)................................................................................................................................ 59 Block Erase (BE)...................................................................................................................................... 60 2 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-25. 9-26. 9-27. 9-28. 9-29. 9-30. 9-31. 9-32. Chip Erase (CE)........................................................................................................................................ 61 Page Program (PP).................................................................................................................................. 62 4 x I/O Page Program (4PP)..................................................................................................................... 64 Deep Power-down (DP)............................................................................................................................ 65 Enter Secured OTP (ENSO)..................................................................................................................... 66 Exit Secured OTP (EXSO)........................................................................................................................ 66 Read Security Register (RDSCUR).......................................................................................................... 66 Write Security Register (WRSCUR).......................................................................................................... 66 Table 9. Security Register Definition..........................................................................................................67 9-33. Write Protection Selection (WPSEL)......................................................................................................... 68 9-34. Advanced Sector Protection..................................................................................................................... 70 9-35. Program/Erase Suspend/Resume............................................................................................................ 76 9-36. Erase Suspend......................................................................................................................................... 76 9-37. Program Suspend..................................................................................................................................... 76 9-38.Write-Resume........................................................................................................................................... 78 9-39. No Operation (NOP)................................................................................................................................. 78 9-40. Software Reset (Reset-Enable (RSTEN) and Reset (RST)).................................................................... 78 9-41. Read SFDP Mode (RDSFDP)................................................................................................................... 80 Table 10. Signature and Parameter Identification Data Values .................................................................81 Table 11. Parameter Table (0): JEDEC Flash Parameter Tables...............................................................83 Table 12. Parameter Table (1): 4-Byte Instruction Tables..........................................................................90 Table 13. Parameter Table (2): Macronix Flash Parameter Tables............................................................92 10. RESET.................................................................................................................................................................. 94 Table 14. Reset Timing-(Power On)...........................................................................................................94 Table 15. Reset Timing-(Other Operation).................................................................................................94 11. POWER-ON STATE.............................................................................................................................................. 95 12. ELECTRICAL SPECIFICATIONS......................................................................................................................... 96 Table 16. ABSOLUTE MAXIMUM RATINGS.............................................................................................96 Table 17. CAPACITANCE TA = 25°C, f = 1.0 MHz.....................................................................................96 Table 18. DC CHARACTERISTICS (Temperature = -40°C to 85°C, VCC = 2.7V - 3.6V) .........................98 Table 19. AC CHARACTERISTICS (Temperature = -40°C to 85°C, VCC = 2.7V - 3.6V) ........................99 13. OPERATING CONDITIONS................................................................................................................................ 101 Table 20. Power-Up/Down Voltage and Timing .......................................................................................103 13-1. INITIAL DELIVERY STATE..................................................................................................................... 103 14. ERASE AND PROGRAMMING PERFORMANCE............................................................................................. 104 15. ERASE AND PROGRAMMING PERFORMANCE (Factory Mode) ................................................................. 104 16. DATA RETENTION............................................................................................................................................. 105 17. LATCH-UP CHARACTERISTICS....................................................................................................................... 105 18. ORDERING INFORMATION............................................................................................................................... 106 19. PART NAME DESCRIPTION.............................................................................................................................. 107 20. PACKAGE INFORMATION................................................................................................................................. 108 20-1. 16-PIN SOP (300mil).............................................................................................................................. 108 20-2. 8-pins SOP (200mil)................................................................................................................................ 109 20-3. 8-land WSON (6x5mm)...........................................................................................................................110 21. REVISION HISTORY .......................................................................................................................................... 111 P/N: PM2145 3 REV. 1.1, FEB. 18, 2016 MX25L12845G 3V 128M-BIT [x 1/x 2/x 4] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY 1. FEATURES GENERAL • Supports Serial Peripheral Interface -- Mode 0 and Mode 3 • Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations • 128Mb: 134,217,728 x 1 bit structure or 67,108,864 x 2 bits (two I/O mode) structure or 33,554,432 x 4 bits (four I/O mode) structure • Protocol Support - Single I/O, Dual I/O and Quad I/O • Latch-up protected to 100mA from -1V to Vcc +1V • Low Vcc write inhibit is from 1.5V to 2.5V • Fast read for SPI mode - Support clock frequency up to 133MHz for all protocols - Support Fast Read, 2READ, DREAD, 4READ, QREAD instructions - Support DTR (Double Transfer Rate) Mode - Configurable dummy cycle number for fast read operation • Quad Peripheral Interface (QPI) available • Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each - Any Block can be erased individually • Programming: - 256byte page buffer - Quad Input/Output page program(4PP) to enhance program performance • Typical 100,000 erase/program cycles • 20 years data retention SOFTWARE FEATURES • Input Data Format - 1-byte Command code • Advanced Security Features - Block lock protection The BP0-BP3 and T/B status bits define the size of the area to be protected against program and erase instructions - Individual sector protection function (Solid Protect) • Additional 4K bit security OTP - Features unique identifier - Factory locked identifiable, and customer lockable • Command Reset • Program/Erase Suspend and Resume operation • Electronic Identification - JEDEC 1-byte manufacturer ID and 2-byte device ID - RES command for 1-byte Device ID - REMS command for 1-byte manufacturer ID and 1-byte device ID • Support Serial Flash Discoverable Parameters (SFDP) mode P/N: PM2145 4 REV. 1.1, FEB. 18, 2016 MX25L12845G HARDWARE FEATURES • SCLK Input - Serial clock input • SI/SIO0 - Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode • SO/SIO1 - Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode • WP#/SIO2 - Hardware write protection or serial data Input/Output for 4 x I/O read mode • RESET#/SIO3 - Hardware Reset pin or Serial input & Output for 4 x I/O read mode • PACKAGE - 16-pin SOP (300mil) - 8-pins SOP (200mil) - 8-land WSON (6x5mm) - All devices are RoHS Compliant and Halogen-free P/N: PM2145 5 REV. 1.1, FEB. 18, 2016 MX25L12845G 2. GENERAL DESCRIPTION MX25L12845G is 128Mb bits Serial Flash memory, which is configured as 16,777,216 x 8 internally. When it is in two or four I/O mode, the structure becomes 67,108,864 bits x 2 or 33,554,432 bits x 4. MX25L12845G feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# and RESET# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output. The MX25L12845G MXSMIO® (Serial Multi I/O) provides sequential read operation on the whole chip. After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis. Erase command is executed on 4K-byte sector, 32K-byte block, or 64K-byte block, or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. Advanced security features enhance the protection and security functions, please see security features section for more details. When the device is not in operation and CS# is high, it is put in standby mode. The MX25L12845G utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. Table 1. Read performance Comparison Numbers of Dummy Cycles Fast Read (MHz) Dual Output Fast Read (MHz) Quad Output Fast Read (MHz) Dual IO Fast Read (MHz) Quad IO Fast Read (MHz) Quad I/O DT Read 4 - - - 80* 54 - 6 - - - - 80* 54* 8 120*/133R 120*/133R 120*/133R 120/133R 84/104R 70/80R 10 - - - - 120/133R 84/100R (MHz) Notes: 1. * mean default status. 2. R mean VCC range = 3.0V-3.6V. P/N: PM2145 6 REV. 1.1, FEB. 18, 2016 MX25L12845G 4. PIN DESCRIPTION 3. PIN CONFIGURATIONS 8-PIN SOP (200mil) CS# SO/SIO1 WP#/SIO2 GND 1 2 3 4 SYMBOL CS# DESCRIPTION Chip Select Serial Data Input (for 1 x I/O)/ Serial SI/SIO0 Data Input & Output (for 2xI/O or 4xI/ O read mode) Serial Data Output (for 1 x I/O)/ Serial SO/SIO1 Data Input & Output (for 2xI/O or 4xI/ O read mode) SCLK Clock Input Write Protection Active Low or Serial WP#/SIO2 Data Input & Output (for 4xI/O read mode) Hardware Reset Pin Active low or RESET#/SIO3 Serial Data Input & Output (for 4xI/O read mode) NC or Serial Data Input & NC/SIO3 Output (for 4xI/O read mode) RESET#* Hardware Reset Pin Active low VCC + 3V Power Supply GND Ground NC No Connection VCC RESET#/SIO3 SCLK SI/SIO0 8 7 6 5 16-PIN SOP (300mil) NC/SIO3 VCC RESET# NC NC NC CS# SO/SIO1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SCLK SI/SIO0 NC NC NC NC GND WP#/SIO2 Notes: 1. RESET# pin has internal pull up. 8-WSON (6x5mm) CS# SO/SIO1 WP#/SIO2 GND P/N: PM2145 1 2 3 4 8 7 6 5 VCC RESET#/SIO3 SCLK SI/SIO0 7 REV. 1.1, FEB. 18, 2016 MX25L12845G 5. BLOCK DIAGRAM X-Decoder Address Generator SI/SIO0 SO/SIO1 SIO2 * SIO3 * Y-Decoder Data Register WP# * HOLD# * RESET# * CS# SCLK Memory Array Sense Amplifier SRAM Buffer Mode Logic State Machine HV Generator Clock Generator Output Buffer * Depends on part number options. P/N: PM2145 8 REV. 1.1, FEB. 18, 2016 MX25L12845G 6. DATA PROTECTION During power transition, there may be some false system level signals which result in inadvertent erasure or programming. The device is designed to protect itself from these accidental write cycles. The state machine will be reset as standby mode automatically during power up. In addition, the control register architecture of the device constrains that the memory contents can only be changed after specific command sequences have completed successfully. In the following, there are several features to protect the system from the accidental write cycles during VCC powerup and power-down or from system noise. • Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. • Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. • Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command (RES), and softreset command. • Advanced Security Features: there are some protection and security features which protect content from inadvertent write and hostile access. P/N: PM2145 9 REV. 1.1, FEB. 18, 2016 MX25L12845G I. Block lock protection - The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0 and T/B) bits to allow part of memory to be protected as read only. The protected area definition is shown as "Table 2. Protected Area Sizes", the protected areas are more flexible which may protect various area by setting value of BP0-BP3 bits. - The Hardware Proteced Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and Status Register Write Protect bit. - In four I/O and QPI mode, the feature of HPM will be disabled. Table 2. Protected Area Sizes Protected Area Sizes (T/B bit = 0) Status bit BP3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BP2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BP1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Protect Level BP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128Mb 0 (none) 1 (1 block, protected block 255th) 2 (2 blocks, block 254th-255th) 3 (4 blocks, block 252nd-255th) 4 (8 blocks, block 248th-255th) 5 (16 blocks, block 240th-255th) 6 (32 blocks, block 224th-255th) 7 (64 blocks, block 192nd-255th) 8 (128 blocks, block 128th-255th) 9 (256 blocks, protected all) 10 (256 blocks, protected all) 11 (256 blocks, protected all) 12 (256 blocks, protected all) 13 (256 blocks, protected all) 14 (256 blocks, protected all) 15 (256 blocks, protected all) Protected Area Sizes (T/B bit = 1) Status bit BP3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 P/N: PM2145 BP2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BP1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Protect Level 128Mb 0 (none) 1 (1 block, protected block 0th) 2 (2 blocks, protected block 0th~1th) 3 (4 blocks, protected block 0th~3rd) 4 (8 blocks, protected block 0th~7th) 5 (16 blocks, protected block 0th~15th) 6 (32 blocks, protected block 0th~31st) 7 (64 blocks, protected block 0th~63rd) 8 (128 blocks, protected block 0th~127th) 9 (256 blocks, protected all) 10 (256 blocks, protected all) 11 (256 blocks, protected all) 12 (256 blocks, protected all) 13 (256 blocks, protected all) 14 (256 blocks, protected all) 15 (256 blocks, protected all) 10 REV. 1.1, FEB. 18, 2016 MX25L12845G II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit one-time program area for setting device unique serial number - Which may be set by factory or system customer. - Security register bit 0 indicates whether the chip is locked by factory or not. - To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with Enter Security OTP command), and going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing Exit Security OTP command. - Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) command to set customer lock-down bit1 as "1". Please refer to "Table 9. Security Register Definition" for security register bit definition and "Table 3. 4K-bit Secured OTP Definition" for address range definition. - Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit secured OTP mode, array access is not allowed. Table 3. 4K-bit Secured OTP Definition Address range Size Standard Factory Lock xxx000~xxx00F 128-bit ESN (electrical serial number) xxx010~xxx1FF 3968-bit N/A P/N: PM2145 11 Customer Lock Determined by customer REV. 1.1, FEB. 18, 2016 MX25L12845G 7. Memory Organization Table 4. Memory Organization Block(64K-byte) Block(32K-byte) Sector 254 508 individual block lock/unlock unit:64K-byte 507 253 506 FF8FFFh 4087 FF7000h FF7FFFh … individual 16 sectors lock/unlock unit:4K-byte 4080 FF0000h FF0FFFh 4079 FEF000h FEFFFFh … 509 FF8000h 4072 FE8000h FE8FFFh 4071 FE7000h FE7FFFh … 510 4088 4064 FE0000h FE0FFFh 4063 FDF000h FDFFFFh … 255 FFFFFFh 4056 FD8000h FD8FFFh 4055 FD7000h FD7FFFh 4048 FD0000h FD0FFFh 47 02F000h 02FFFFh … 511 Address Range FFF000h … 4095 3 1 2 1 028FFFh 027000h 027FFFh … 028000h 39 32 020000h 020FFFh 31 01F000h 01FFFFh … 4 individual block lock/unlock unit:64K-byte 40 24 018000h 018FFFh 23 017000h 017FFFh 16 010000h 010FFFh 15 00F000h 00FFFFh … 2 … 5 … individual block lock/unlock unit:64K-byte 0 8 008000h 008FFFh 7 007000h 007FFFh 000000h 000FFFh 0 P/N: PM2145 individual 16 sectors lock/unlock unit:4K-byte … 0 12 REV. 1.1, FEB. 18, 2016 MX25L12845G 8. DEVICE OPERATION 1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. When incorrect command is inputted to this device, it enters standby mode and remains in standby mode until next CS# falling edge. In standby mode, SO pin of this device should be High-Z. 3. When correct command is inputted to this device, it enters active mode and remains in active mode until next CS# rising edge. 4. Input data is latched on the rising edge of Serial Clock (SCLK) and data is shifted out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as "Figure 1. Serial Modes Supported". 5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, 2READ, DREAD, 4READ, QREAD, RDSFDP, RES, REMS, QPIID, RDDPB, RDSPB, RDLR, RDCR, the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE32K, BE, CE, PP, 4PP, DP, ENSO, EXSO, WRSCUR, WPSEL, GBLK, GBULK, SUSPEND, RESUME, NOP, RSTEN, RST, EQIO, RSTQIO the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6.While a Write Status Register, Program or Erase operation is in progress, access to the memory array is neglected and will not affect the current operation of Write Status Register, Program, Erase. Figure 1. Serial Modes Supported CPOL CPHA shift in (Serial mode 0) 0 0 SCLK (Serial mode 3) 1 1 SCLK SI shift out MSB SO MSB Note: CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported. P/N: PM2145 13 REV. 1.1, FEB. 18, 2016 MX25L12845G Figure 2. Serial Input Timing tSHSL CS# tCHSL tSLCH tCHSH tSHCH SCLK tDVCH tCHCL tCHDX tCLCH LSB MSB SI High-Z SO Figure 3. Output Timing (STR mode) CS# tCH SCLK tCLQV tCLQX tCL tCLQV tSHQZ tCLQX LSB SO SI ADDR.LSB IN Figure 4. Output Timing (DTR mode) CS# tCH SCLK tCLQV tCLQV tCLQX tCL tSHQZ tCLQX SIO0 SIO1 SIO2 SIO3 tQVD P/N: PM2145 14 REV. 1.1, FEB. 18, 2016 MX25L12845G 8-1. Quad Peripheral Interface (QPI) Read Mode QPI protocol enables user to take full advantage of Quad I/O Serial Flash by providing the Quad I/O interface in command cycles, address cycles and as well as data output cycles. Enable QPI mode By issuing EQIO(35h) command, the QPI mode is enabled. After QPI mode is enabled, the device enters quad mode (4-4-4) without QE bit status changed. Figure 5. Enable QPI Sequence CS# MODE 3 SCLK 0 1 2 3 4 5 6 7 MODE 0 SIO0 35h SIO[3:1] Reset QPI (RSTQIO) To reset the QPI mode, the RSTQIO (F5h) command is required. After the RSTQIO command is issued, the device returns from QPI mode (4 I/O interface in command cycles) to SPI mode (1 I/O interface in command cycles). Note: For EQIO and RSTQIO commands, CS# high width has to follow "write spec" tSHSL (as defined by "Table 19. AC CHARACTERISTICS (Temperature = -40°C to 85°C, VCC = 2.7V - 3.6V)") for next instruction. Figure 6. Reset QPI Mode CS# SCLK SIO[3:0] P/N: PM2145 F5h 15 REV. 1.1, FEB. 18, 2016 MX25L12845G 9. COMMAND DESCRIPTION Table 5. Command Set Read/Write Array Commands Command (byte) Mode READ FAST READ (normal read) (fast read data) 2READ (2 x I/O read command) DREAD (1I 2O read) 4READ QREAD (1I 4O read) 4DTRD (Quad I/O DT Read) 1st byte SPI 3 03 (hex) SPI 3 0B (hex) SPI 3 BB (hex) SPI 3 3B (hex) SPI/QPI 3 EB (hex) SPI 3 6B (hex) SPI/QPI 3 ED (hex) 2nd byte ADD1 ADD1 ADD1 ADD1 ADD1 ADD1 ADD1 3rd byte ADD2 ADD2 ADD2 ADD2 ADD2 ADD2 ADD2 4th byte ADD3 ADD3 ADD3 ADD3 ADD3 ADD3 ADD3 Dummy* Dummy* Dummy* Dummy* Dummy* Dummy* Address Bytes 5th byte Data Cycles Action n bytes read out until CS# goes high Command (byte) PP (page program) Mode SPI/QPI n bytes read n bytes read n bytes read Quad I/O read n bytes read n bytes read out until CS# out by 2 x I/O out by Dual for bottom out by Quad out (Double goes high until CS# goes output until 128Mb with 6 output until Transfer Rate) high CS# goes high dummy cycles CS# goes high by 4xI/O until CS# goes high 4PP (quad page program) SPI SE (sector erase) SPI/QPI BE 32K (block erase 32KB) SPI/QPI BE (block erase 64KB) SPI/QPI CE (chip erase) SPI/QPI Address Bytes 3 3 3 3 3 0 1st byte 02 (hex) 38 (hex) 20 (hex) 52 (hex) D8 (hex) 60 or C7 (hex) 2nd byte ADD1 ADD1 ADD1 ADD1 3rd byte ADD2 ADD2 ADD2 ADD2 4th byte ADD3 ADD3 ADD3 ADD3 5th byte Data Cycles Action 1-256 1-256 to program the quad input to to erase the to erase the selected page program the selected sector selected 32K selected page block to erase the to erase whole selected block chip * Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in configuration register. P/N: PM2145 16 REV. 1.1, FEB. 18, 2016 MX25L12845G Register/Setting Commands Mode SPI/QPI SPI/QPI SPI/QPI SPI/QPI RDCR (read configuration register) SPI/QPI 1st byte 06 (hex) 04 (hex) 41 (hex) 05 (hex) 15 (hex) Command (byte) FMEN WREN WRDI (factory mode (write enable) (write disable) enable) RDSR (read status register) WRSR (write status/ configuration register) SPI/QPI 01 (hex) 2nd byte Values 3rd byte Values WPSEL (Write Protect Selection) SPI/QPI 68 (hex) 4th byte 5th byte Data Cycles Action sets the (WEL) resets the enable factory to read out the to read out the write enable (WEL) write mode values of the values of the latch bit enable latch bit status register configuration register Command (byte) EQIO (Enable QPI) RSTQIO (Reset QPI) Mode 1st byte SPI 35 (hex) QPI F5 (hex) Entering the QPI mode Exiting the QPI mode PGM/ERS Suspend (Suspends Program/ Erase) SPI/QPI B0 (hex) PGM/ERS Resume (Resumes Program/ Erase) SPI/QPI 30 (hex) 1-2 to write new to enter and values of the enable individal block protect status/ mode configuration register DP (Deep power down) RDP (Release from deep power down) SBL (Set Burst Length) SPI/QPI B9 (hex) SPI/QPI AB (hex) SPI/QPI C0 (hex) enters deep power down mode release from deep power down mode to set Burst length 2nd byte 3rd byte 4th byte 5th byte Data Cycles Action P/N: PM2145 17 REV. 1.1, FEB. 18, 2016 MX25L12845G ID/Security Commands REMS RDID RES (read electronic QPIID (read identific(read manufacturer (QPI ID Read) ation) electronic ID) & device ID) Mode SPI SPI/QPI SPI QPI Address Bytes 0 0 0 0 1st byte 9F (hex) AB (hex) 90 (hex) AF (hex) Command (byte) 2nd byte x 3rd byte x 4th byte RDSFDP ENSO (enter secured OTP) EXSO (exit secured OTP) SPI/QPI 3 5A (hex) SPI/QPI 0 B1 (hex) SPI/QPI 0 C1 (hex) x ADD1 x ADD2 ADD1(Note 1) ADD3 Dummy (8)(Note 5) 5th byte Data Cycles Action RDSCUR WRSCUR (read security (write security register) register) Mode SPI/QPI SPI/QPI Address Bytes 0 0 Command (byte) 1st byte ID in QPI interface outputs JEDEC to read out output the ID: 1-byte 1-byte Device Manufacturer Manufacturer ID ID & Device ID & 2-byte ID(Note 2) Device ID 2B (hex) 2F (hex) 2nd byte Read SFDP mode to enter the to exit the 4K-bit secured 4K-bit secured OTP mode OTP mode WRSPB (SPB bit program) SPI 4 ESSPB (all SPB bit erase) SPI 0 RDSPB (read SPB status) SPI 4 WRDPB (write DPB register) SPI 4 RDDPB (read DPB register) SPI 4 E3 (hex) E4 (hex) E2 (hex) E1 (hex) E0 (hex) ADD1 ADD1 ADD1 ADD1 3rd byte ADD2 ADD2 ADD2 ADD2 4th byte ADD3 ADD3 ADD3 ADD3 5th byte ADD4 ADD4 ADD4 ADD4 1 1 1 Data Cycles Action to read value to set the lockof security down bit as register "1" (once lockdown, cannot be updated) Mode Address Bytes GBLK (gang block lock) SPI/QPI 0 GBULK (gang block unlock) SPI/QPI 0 WRLR (write lock register) SPI 0 RDLR (read lock register) SPI 0 1st byte 7E (hex) 98 (hex) 2C (hex) 2D (hex) 2 2 whole chip write protect whole chip unprotect Command (byte) 2nd byte 3rd byte 4th byte 5th byte Data Cycles Action P/N: PM2145 18 REV. 1.1, FEB. 18, 2016 MX25L12845G Reset Commands Command (byte) NOP RSTEN (No Operation) (Reset Enable) RST (Reset Memory) Mode SPI/QPI SPI/QPI SPI/QPI 1st byte 00 (hex) 66 (hex)(Note 4) 99 (hex) 2nd byte 3rd byte 4th byte 5th byte Action Note 1: The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O. And the MSB is on SO/SIO1 which is different from 1 x I/O condition. Note 2: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first. Note 3: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode. Note 4: The RSTEN command must be executed before executing the RST command. If any other command is issued in-between RSTEN and RST, the RST command will be ignored. Note 5: The number in parentheses after "Dummy" stands for how many clock cycles it has. P/N: PM2145 19 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-1. Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP, SE, BE32K, BE, CE, and WRSR, which are intended to change the device content WEL bit should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CS# goes low→sending WREN instruction code→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in SPI mode. Figure 7. Write Enable (WREN) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 SCLK Mode 0 Command SI 06h High-Z SO Figure 8. Write Enable (WREN) Sequence (QPI Mode) CS# 0 Mode 3 1 SCLK Mode 0 Command 06h SIO[3:0] P/N: PM2145 20 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-2. Write Disable (WRDI) The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in SPI mode. The WEL bit is reset by following situations: - Power-up - Reset# pin driven low - WRDI command completion - WRSR command completion - PP command completion - 4PP command completion - SE command completion - BE32K command completion - BE command completion - CE command completion - PGM/ERS Suspend command completion - Softreset command completion - WRSCUR command completion - WPSEL command completion - GBLK command completion - GBULK command completion - WRLR command completion - WRSPB command completion - WRDPB command completion - ESSPB command completion Figure 9. Write Disable (WRDI) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 SCLK Mode 0 SI SO P/N: PM2145 Command 04h High-Z 21 REV. 1.1, FEB. 18, 2016 MX25L12845G Figure 10. Write Disable (WRDI) Sequence (QPI Mode) CS# 0 Mode 3 1 SCLK Mode 0 Command 04h SIO[3:0] 9-3. Factory Mode Enable (FMEN) The Factory Mode Enable (FMEN) instruction is for enhance Program and Erase performance for increase factory production throughput. The FMEN instruction need to combine with the instructions which are intended to change the device content, like PP/PP4B, 4PP/4PP4B, SE/SE4B, BE32K/BE32K4B, BE/BE4B, and CE. The sequence of issuing FMEN instruction is: CS# goes low→sending FMEN instruction code→ CS# goes high. A valid factory mode operation need to included three sequences: WREN instruction → FMEN instruction→ Program or Erase instruction. Suspend command is not acceptable under factory mode. The FMEN is reset by following situations - Power-up - Reset# pin driven low - PP/PP4B command completion - 4PP/4PP4B command completion - SE/SE4B command completion - BE32K/BE32K4B command completion - BE/BE4B command completion - CE command completion - Softreset command completion Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in SPI mode. Figure 11. Factory Mode Enable (FMEN) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 SCLK Mode 0 Command SI SO P/N: PM2145 41h High-Z 22 REV. 1.1, FEB. 18, 2016 MX25L12845G Figure 12. Factory Mode Enable (FMEN) Sequence (QPI Mode) CS# 0 Mode 3 1 SCLK Mode 0 Command 41h SIO[3:0] 9-4. Read Identification (RDID) The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix Manufacturer ID and Device ID are listed as "Table 6. ID Definitions". The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out on SO→ to end RDID operation can drive CS# to high at any time during data out. While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. Figure 13. Read Identification (RDID) Sequence (SPI mode only) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 28 29 30 31 SCLK Mode 0 Command SI 9Fh Manufacturer Identification SO High-Z 7 6 5 2 MSB P/N: PM2145 1 Device Identification 0 15 14 13 3 2 1 0 MSB 23 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-5. Release from Deep Power-down (RDP), Read Electronic Signature (RES) The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max), as specified in "Table 19. AC CHARACTERISTICS (Temperature = -40°C to 85°C, VCC = 2.7V - 3.6V)". Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. The RDP instruction is only for releasing from Deep Power Down Mode. Reset# pin goes low will release the Flash from deep power down mode. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as "Table 6. ID Definitions". This is not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. Figure 14. Read Electronic Signature (RES) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 SCLK Mode 0 Command SI ABh tRES2 3 Dummy Bytes 23 22 21 3 2 1 0 MSB SO Electronic Signature Out High-Z 7 6 5 4 3 2 1 0 MSB Deep Power-down Mode P/N: PM2145 24 Stand-by Mode REV. 1.1, FEB. 18, 2016 MX25L12845G Figure 15. Read Electronic Signature (RES) Sequence (QPI Mode) CS# MODE 3 0 1 2 3 4 5 6 7 SCLK MODE 0 3 Dummy Bytes Command SIO[3:0] X ABh X X X X X H0 L0 MSB LSB Data In Data Out Stand-by Mode Deep Power-down Mode Figure 16. Release from Deep Power-down (RDP) Sequence (SPI Mode) CS# 0 Mode 3 1 2 3 4 5 6 tRES1 7 SCLK Mode 0 Command SI ABh High-Z SO Deep Power-down Mode Stand-by Mode Figure 17. Release from Deep Power-down (RDP) Sequence (QPI Mode) CS# Mode 3 tRES1 0 1 SCLK Mode 0 Command SIO[3:0] ABh Deep Power-down Mode P/N: PM2145 25 Stand-by Mode REV. 1.1, FEB. 18, 2016 MX25L12845G 9-6. Read Electronic Manufacturer ID & Device ID (REMS) The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initiated by driving the CS# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for Macronix (C2h) and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first. The Device ID values are listed in "Table 6. ID Definitions". If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. Figure 18. Read Electronic Manufacturer & Device ID (REMS) Sequence (SPI Mode only) CS# SCLK Mode 3 0 1 2 Mode 0 3 4 5 6 7 8 Command SI 9 10 2 Dummy Bytes 15 14 13 90h 3 2 1 0 High-Z SO CS# 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK ADD (1) SI 7 6 5 4 3 2 1 0 Manufacturer ID SO 7 6 5 4 3 2 1 Device ID 0 7 MSB MSB 6 5 4 3 2 1 0 7 MSB Notes: (1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first. P/N: PM2145 26 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-7. QPI ID Read (QPIID) User can execute this QPIID Read instruction to identify the Device ID and Manufacturer ID. The sequence of issue QPIID instruction is CS# goes low→sending QPI ID instruction→Data out on SO→CS# goes high. Most significant bit (MSB) first. After the command cycle, the device will immediately output data on the falling edge of SCLK. The manufacturer ID, memory type, and device ID data byte will be output continuously, until the CS# goes high. Table 6. ID Definitions Command Type RDID 9Fh RES ABh REMS 90h QPIID AFh P/N: PM2145 MX25L12845G Manufacturer ID C2 Manufacturer ID C2 Manufacturer ID C2 Memory type 20 Electronic ID 17 Device ID 17 Memory type 20 27 Memory density 18 Memory density 18 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-8. Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data out on SO. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. Figure 19. Read Status Register (RDSR) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK Mode 0 command 05h SI SO Status Register Out High-Z 7 6 5 4 3 2 1 Status Register Out 0 7 6 5 4 3 2 1 0 7 MSB MSB Figure 20. Read Status Register (RDSR) Sequence (QPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 N SCLK Mode 0 SIO[3:0] 05h H0 L0 H0 L0 H0 L0 H0 L0 MSB LSB Status Byte Status Byte Status Byte P/N: PM2145 28 Status Byte REV. 1.1, FEB. 18, 2016 MX25L12845G 9-9. Read Configuration Register (RDCR) The RDCR instruction is for reading Configuration Register Bits. The Read Configuration Register can be read at any time (even in program/erase/write configuration register condition). It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write configuration register operation is in progress. The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→ Configuration Register data out on SO. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. Figure 21. Read Configuration Register (RDCR) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK Mode 0 command 15h SI SO Configuration register Out High-Z 7 6 5 4 3 2 1 0 Configuration register Out 7 6 5 4 3 2 1 0 7 MSB MSB Figure 22. Read Configuration Register (RDCR) Sequence (QPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 N SCLK Mode 0 SIO[3:0] 15h H0 L0 H0 L0 H0 L0 H0 L0 MSB LSB Config. Byte Config. Byte Config. Byte P/N: PM2145 29 Config. Byte REV. 1.1, FEB. 18, 2016 MX25L12845G For user to check if Program/Erase operation is finished or not, RDSR instruction flow are shown as follows: Figure 23. Program/Erase flow with read array data start WREN command RDSR command* WEL=1? No Yes Program/erase command Write program data/address (Write erase address) RDSR command WIP=0? No Yes RDSR command Read WEL=0, BP[3:0], QE, and SRWD data Read array data (same address of PGM/ERS) No Verify OK? Yes Program/erase successfully Program/erase another block? No Program/erase fail Yes * Issue RDSR to check BP[3:0]. * If WPSEL = 1, issue RDSPB to check the block status. Program/erase completed P/N: PM2145 30 REV. 1.1, FEB. 18, 2016 MX25L12845G Figure 24. Program/Erase flow without read array data (read P_FAIL/E_FAIL flag) start WREN command RDSR command* WEL=1? No Yes Program/erase command Write program data/address (Write erase address) RDSR command WIP=0? No Yes RDSR command Read WEL=0, BP[3:0], QE, and SRWD data RDSCUR command Yes P_FAIL/E_FAIL =1 ? No Program/erase fail Program/erase successfully Program/erase another block? No Yes * Issue RDSR to check BP[3:0]. * If WPSEL = 1, issue RDSPB to check the block status. Program/erase completed P/N: PM2145 31 REV. 1.1, FEB. 18, 2016 MX25L12845G Status Register The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. The program/erase command will be ignored if it is applied to a protected memory area. To ensure both WIP bit & WEL bit are both set to 0 and available for next program/erase/operations, WIP bit needs to be confirm to be 0 before polling WEL bit. After WIP bit confirmed, WEL bit needs to be confirm to be 0. BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as defined in "Table 2. Protected Area Sizes") of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase 32KB (BE32K), Block Erase (BE) and Chip Erase (CE) instructions (only if Block Protect bits (BP3:BP0) set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default. Which is unprotected. QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP#, RESET# are enable. While QE is "1", it performs Quad I/O mode and WP#, RESET# are disabled. In the other word, if the system goes into four I/O mode (QE=1), the feature of HPM and RESET will be disabled. SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. The SRWD bit defaults to be "0". Status Register bit7 SRWD (status register write protect) bit6 QE (Quad Enable) 1=status register write 1=Quad disabled Enable 0=status 0=not Quad register write Enable enabled Non-volatile Non-volatile bit bit bit5 BP3 (level of protected block) bit4 BP2 (level of protected block) bit3 BP1 (level of protected block) bit2 BP0 (level of protected block) (note 1) (note 1) (note 1) (note 1) Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit bit1 bit0 WEL WIP (write enable (write in latch) progress bit) 1=write 1=write enable operation 0=not write 0=not in write enable operation volatile bit volatile bit Note 1: Please refer to "Table 2. Protected Area Sizes". P/N: PM2145 32 REV. 1.1, FEB. 18, 2016 MX25L12845G Configuration Register The Configuration Register is able to change the default status of Flash memory. Flash memory will be configured after the CR bit is set. ODS bit The output driver strength (ODS1, ODS0) bits are volatile bits, which indicate the output driver level (as defined in "Output Driver Strength Table") of the device. The Output Driver Strength is defaulted as 30 Ohms when delivered from factory. To write the ODS bits requires the Write Status Register (WRSR) instruction to be executed. TB bit The Top/Bottom (TB) bit is a non-volatile OTP bit. The Top/Bottom (TB) bit is used to configure the Block Protect area by BP bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as “0”, which means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory device. To write the TB bits requires the Write Status Register (WRSR) instruction to be executed. PBE bit The Preamble Bit Enable (PBE) bit is a volatile bit. It is used to enable or disable the preamble bit data pattern output on dummy cycles. The PBE bit is defaulted as “0”, which means preamble bit is disabled. When it is set as “1”, the preamble bit will be enabled, and inputted into dummy cycles. To write the PBE bits requires the Write Status Register (WRSR) instruction to be executed. 4BYTE Indicator bit By writing EN4B instruction, the 4BYTE bit may be set as "1" to access the address length of 32-bit for memory area of higher density (large than 128Mb). The default state is "0" as the 24-bit address mode. The 4BYTE bit may be cleared by power-off or writing EX4B instruction to reset the state to be "0". Table 7. Configuration Register bit7 DC1 (Dummy cycle 1) bit6 DC0 (Dummy cycle 0) bit5 (Note 2) (Note 2) x volatile bit volatile bit x Reserved bit4 bit3 PBE TB (Preamble bit (top/bottom Enable) selected) 0=Top area 0=Disable protect 1=Bottom 1=Enable area protect (Default=0) volatile bit OTP bit2 Reserved bit1 bit0 ODS 1 ODS 0 (output driver (output driver strength) strength) x (Note 1) (Note 1) x volatile bit volatile bit Note 1: see "Output Driver Strength Table" Note 2: see "Dummy Cycle and Frequency Table (MHz)" P/N: PM2145 33 REV. 1.1, FEB. 18, 2016 MX25L12845G Output Driver Strength Table ODS1 0 0 1 1 ODS0 0 1 0 1 Description tCLQV=8ns (Default) tCLQV=10ns tCLQV=16ns tCLQV=6ns Note loading: 30pF Dummy Cycle and Frequency Table (MHz) (STR Mode) DC[1:0] 00 (default) 01 10 11 DC[1:0] 00 (default) 01 10 11 DC[1:0] 00 (default) 01 10 11 Numbers of Dummy clock cycles 8 8 8 8 Numbers of Dummy clock cycles 4 8 4 8 Fast Read 120/133R 120/133R 120/133R 120/133R Dual Output Fast Read 120/133R 120/133R 120/133R 120/133R Quad Output Fast Read 120/133R 120/133R 120/133R 120/133R Dual IO Fast Read 80 120/133R 80 120/133R Numbers of Dummy Quad IO Fast Read clock cycles 6 80 4 54 8 84/104R 10 120/133R (DTR Mode) DC[1:0] 00 (default) 01 10 11 Numbers of Dummy Quad IO DTR Read clock cycles 6 54 6 54 8 70/80R 10 84/100R Note: "R" mean VCC range= 3.0V-3.6V. P/N: PM2145 34 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-10.Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits and Configuration Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as shown in "Table 2. Protected Area Sizes"). The WRSR also can set or reset the Quad enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered. The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register data on SI→CS# goes high. The CS# must go high exactly at the 8 bits or 16 bits data boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset. Figure 25. Write Status Register (WRSR) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCLK Mode 0 SI SO command 01h Status Register In 7 6 4 5 Configuration Register In 2 3 0 15 14 13 12 11 10 9 1 8 MSB High-Z Note: The CS# must go high exactly at 8 bits or 16 bits data boundary to completed the write register command. Figure 26. Write Status Register (WRSR) Sequence (QPI Mode) CS# Mode 3 0 1 2 3 4 5 Mode 3 SCLK Mode 0 Mode 0 SR in Command SIO[3:0] P/N: PM2145 01h H0 35 L0 CR in H1 L1 REV. 1.1, FEB. 18, 2016 MX25L12845G Software Protected Mode (SPM): - When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0 and T/B bit, is at software protected mode (SPM). - When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0 and T/B bit, is at software protected mode (SPM) Note: If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status Register and not be executed. Hardware Protected Mode (HPM): - When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2, BP1, BP0 and T/B bit and hardware protected mode by the WP#/SIO2 to against data modification. Note: To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered. If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP3, BP2, BP1, BP0 and T/B bit. If the system enter QPI or set QE=1, the feature of HPM will be disabled. Table 8. Protection Modes Mode Software protection mode (SPM) Hardware protection mode (HPM) Status register condition WP# and SRWD bit status Memory Status register can be written in (WEL bit is set to "1") and the SRWD, BP0-BP3 bits can be changed WP#=1 and SRWD bit=0, or WP#=0 and SRWD bit=0, or WP#=1 and SRWD=1 The protected area cannot be program or erase. The SRWD, BP0-BP3 of status register bits cannot be changed WP#=0, SRWD bit=1 The protected area cannot be program or erase. Note: 1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in "Table 2. Protected Area Sizes". P/N: PM2145 36 REV. 1.1, FEB. 18, 2016 MX25L12845G Figure 27. WRSR flow start WREN command RDSR command WEL=1? No Yes WRSR command Write status register data RDSR command WIP=0? No Yes RDSR command Read WEL=0, BP[3:0], QE, and SRWD data Verify OK? No Yes WRSR successfully P/N: PM2145 WRSR fail 37 REV. 1.1, FEB. 18, 2016 MX25L12845G Figure 28. WP# Setup Timing and Hold Timing during WRSR when SRWD=1 WP# tSHWL tWHSL CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK 01h SI SO High-Z Note: WP# must be kept high until the embedded operation finish. P/N: PM2145 38 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-11.Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing READ instruction is: CS# goes low→sending READ instruction code→ 3-byte address on SI→ data out on SO→to end READ operation can use CS# to high at any time during data out. Figure 29. Read Data Bytes (READ) Sequence (SPI Mode only) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Mode 0 SI command 03h 24-Bit Address 23 22 21 3 2 1 0 MSB SO Data Out 1 High-Z 7 6 5 4 3 2 Data Out 2 1 0 7 MSB P/N: PM2145 39 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-12.Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. Read on SPI Mode The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→ 3-byte address on SI→ 8 dummy cycles (default)→ data out on SO→ to end FAST_READ operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. P/N: PM2145 40 REV. 1.1, FEB. 18, 2016 MX25L12845G Figure 30. Read at Higher Speed (FAST_READ) Sequence (SPI Mode) CS# SCLK Mode 3 0 1 2 Mode 0 3 5 6 7 8 9 10 Command SI SO 4 28 29 30 31 24-Bit Address 23 22 21 0Bh 3 2 1 0 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Configurable Dummy Cycle SI 7 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 SO 7 6 5 4 2 1 0 7 MSB MSB P/N: PM2145 3 41 6 5 4 3 2 1 0 7 MSB REV. 1.1, FEB. 18, 2016 MX25L12845G 9-13.Dual Output Read Mode (DREAD) The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing DREAD instruction is: CS# goes low→ sending DREAD instruction→3-byte address on SIO0→ 8 dummy cycles (default) on SIO0→ data out interleave on SIO1 & SIO0→ to end DREAD operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. Figure 31. Dual Read Mode Sequence CS# 0 1 2 3 4 5 6 7 8 … Command SI/SIO0 SO/SIO1 P/N: PM2145 30 31 32 9 SCLK 3B … 24 ADD Cycle A23 A22 … 39 40 41 42 43 44 45 A1 A0 High Impedance Configurable Dummy Cycle Data Out 1 Data Out 2 D6 D4 D2 D0 D6 D4 D7 D5 D3 D1 D7 D5 42 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-14.2 x I/O Read Mode (2READ) The 2READ instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 3-byte address interleave on SIO1 & SIO0→ 4 dummy cycles (default) on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to end 2READ operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. Figure 32. 2 x I/O Read Mode Sequence (SPI Mode only) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Mode 3 SCLK Mode 0 Command SI/SIO0 SO/SIO1 P/N: PM2145 BBh 12 ADD Cycles Configurable Dummy Cycle Data Out 1 Data Out 2 A22 A20 A18 A4 A2 A0 D6 D4 D2 D0 D6 D4 D2 D0 A23 A21 A19 A5 A3 A1 D7 D5 D3 D1 D7 D5 D3 D1 43 Mode 0 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-15.Quad Read Mode (QREAD) The QREAD instruction enable quad throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single QREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD instruction, the following data out will perform as 4-bit instead of previous 1-bit. The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction → 3-byte address on SI → 8 dummy cycle (Default) → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QREAD operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. Figure 33. Quad Read Mode Sequence CS# 0 1 2 3 4 5 6 7 8 … Command SIO0 SIO1 SIO2 SIO3 P/N: PM2145 29 30 31 32 33 9 SCLK 6B … 24 ADD Cycles A23 A22 … High Impedance 38 39 40 41 42 A2 A1 A0 Configurable dummy cycles Data Data Data Out 1 Out 2 Out 3 D4 D0 D4 D0 D4 D5 D1 D5 D1 D5 High Impedance D6 D2 D6 D2 D6 High Impedance D7 D3 D7 D3 D7 44 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-16.4 x I/O Read Mode (4READ) The 4READ instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. 4 x I/O Read on SPI Mode (4READ) The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 3-byte address interleave on SIO3, SIO2, SIO1 & SIO0→ 6 dummy cycles (Default) →data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS# to high at any time during data out. 4 x I/O Read on QPI Mode (4READ) The 4READ instruction also support on QPI command mode. The sequence of issuing 4READ instruction QPI mode is: CS# goes low→ sending 4READ instruction→ 3-byte address interleave on SIO3, SIO2, SIO1 & SIO0→ 6 dummy cycles (Default) →data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. P/N: PM2145 45 REV. 1.1, FEB. 18, 2016 MX25L12845G Figure 34. 4 x I/O Read Mode Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 Mode 3 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCLK Mode 0 Command 6 ADD Cycles Data Out 1 Performance enhance indicator (Note 1 & 2) Data Out 2 Mode 0 Data Out 3 Configurable Dummy Cycle (Note 3) EA/EBh A20 A16 A12 A8 A4 A0 P4 P0 D4 D0 D4 D0 D4 D0 SIO1 A21 A17 A13 A9 A5 A1 P5 P1 D5 D1 D5 D1 D5 D1 SIO2 A22 A18 A14 A10 A6 A2 P6 P2 D6 D2 D6 D2 D6 D2 SIO3 A23 A19 A15 A11 A7 A3 P7 P3 D7 D3 D7 D3 D7 D3 SIO0 Notes: 1. Hi-impedance is inhibited for the two clock cycles. 2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited. 3. Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in configuration register. Figure 35. 4 x I/O Read Mode Sequence (QPI Mode) CS# MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MODE 3 SCLK MODE 0 SIO[3:0] P/N: PM2145 MODE 0 EA/EB A5 A4 A3 A2 A1 A0 Data In 24-bit Address X X X X Configurable Dummy Cycle 46 X X H0 L0 H1 L1 H2 L2 H3 L3 MSB Data Out REV. 1.1, FEB. 18, 2016 MX25L12845G 9-17.4 x I/O Double Transfer Rate Read Mode (4DTRD) The 4DTRD instruction enables Double Transfer Rate throughput on quad I/O of Serial Flash in read mode. A Quad Enable (QE) bit of status Register must be set to "1" before sending the 4DTRD instruction. The address (interleave on 4 I/O pins) is latched on both rising and falling edge of SCLK, and data (interleave on 4 I/O pins) shift out on both rising and falling edge of SCLK. The 8-bit address can be latched-in at one clock, and 8-bit data can be read out at one clock, which means four bits at rising edge of clock, the other four bits at falling edge of clock. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4DTRD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4DTRD instruction, the following address/ dummy/data out will perform as 8-bit instead of previous 1-bit. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. While Program/Erase/Write Status Register cycle is in progress, 4DTRD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. P/N: PM2145 47 REV. 1.1, FEB. 18, 2016 MX25L12845G Figure 36. Fast Quad I/O DT Read (4DTRD) Sequence (SPI Mode) CS# Mode 3 0 7 SCLK 8 9 10 11 16 … Mode 0 17 18 … Command Performance Enhance Indicator 3 ADD Cycles Configurable Dummy Cycle A20 A16 … A4 A0 P4 P0 D4 D0 D4 D0 D4 SIO1 A21 A17 … A5 A1 P5 P1 D5 D1 D5 D1 D5 SIO2 A22 A18 … A6 A2 P6 P2 D6 D2 D6 D2 D6 SIO3 A23 A19 … A7 A3 P7 P3 D7 D3 D7 D3 D7 SIO0 EDh Notes: 1. Hi-impedance is inhibited for this clock cycle. 2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) will result in entering the performance enhance mode. 3. Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in configuration register. Figure 37. Fast Quad I/O DT Read (4DTRD) Sequence (QPI Mode) CS# Mode 3 0 1 2 3 4 5 11 10 SCLK 12 … Mode 0 Command 3 ADD Cycles Performance Enhance Indicator Configurable Dummy Cycle SIO[3:0] EDh A20 | A23 A16 | A19 A12 | A15 A8 | A11 A4 | A7 A0 | A3 P1 P0 H0 L0 H1 L1 H2 Note: 1.Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in configuration register. P/N: PM2145 48 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-18.Preamble Bit The Preamble Bit data pattern supports system/memory controller to determine valid window of data output more easily and improve data capture reliability while the flash memory is running in high frequency. Preamble Bit data pattern can be enabled or disabled by setting the bit4 of Configuration register (Preamble bit Enable bit). Once the CR<4> is set, the preamble bit is inputted into dummy cycles. Enabling preamble bit will not affect the function of enhance mode bit. In Dummy cycles, performance enhance mode bit still operates with the same function. Preamble bit will output after performance enhance mode bit. The preamble bit is a fixed 8-bit data pattern (00110100). While dummy cycle number reaches 10, the complete 8 bits will start to output right after the performance enhance mode bit. While dummy cycle is not sufficient of 10 cycles, the rest of the preamble bits will be cut. For example, 8 dummy cycles will cause 6 preamble bits to output, and 6 dummy cycles will cause 4 preamble bits to output. Figure 38. SDR 1I/O (10DC) CS# SCK … … Dummy cycle Command cycle SI CMD Address cycle An … Preamble bits A0 SO 7 6 5 4 3 2 1 0 D7 D6 D7 D6 … Figure 39. SDR 1I/O (8DC) CS# SCK … … Dummy cycle Command cycle SI SO P/N: PM2145 CMD Address cycle An … Preamble bits A0 7 49 6 5 4 3 2 D5 D4 … REV. 1.1, FEB. 18, 2016 MX25L12845G Figure 40. SDR 2I/O (10DC) CS# SCK … … Dummy cycle Command cycle SIO0 CMD SIO1 Address cycle Toggle bits Preamble bits A(n-1) … A0 7 6 5 4 3 2 1 0 D6 D4 D2 D0 An … A1 7 6 5 4 3 2 1 0 D7 D5 D3 D1 … … Figure 41. SDR 2I/O (8DC) CS# SCK … … Dummy cycle Command cycle SIO0 SIO1 P/N: PM2145 CMD Address cycle Toggle bits Preamble bits A(n-1) … A0 7 6 5 4 3 2 D6 D4 D2 D0 An … A1 7 6 5 4 3 2 D7 D5 D3 D1 50 … … REV. 1.1, FEB. 18, 2016 MX25L12845G Figure 42. SDR 4I/O (10DC) CS# SCK … … Dummy cycle Command cycle Toggle bits Address cycle Preamble bits A(n-3) … A0 7 6 5 4 3 2 1 0 D4 D0 SIO1 A(n-2) … A1 7 6 5 4 3 2 1 0 D5 D1 SIO2 A(n-1) … A2 7 6 5 4 3 2 1 0 D6 D2 … SIO3 An … A3 7 6 5 4 3 2 1 0 D7 D3 … SIO0 CMD … … Figure 43. SDR 4I/O (8DC) CS# SCK … … Dummy cycle Command cycle Address cycle Toggle bits Preamble bits A(n-3) … A0 7 6 5 4 3 2 D4 D0 SIO1 A(n-2) … A1 7 6 5 4 3 2 D5 D1 SIO2 A(n-1) … A2 7 6 5 4 3 2 D6 D2 SIO3 An … A3 7 6 5 4 3 2 D7 D3 SIO0 P/N: PM2145 CMD 51 … … … … REV. 1.1, FEB. 18, 2016 MX25L12845G Figure 44. DTR4IO (DC=6) CS# SCK … … Dummy cycle Command cycle SIO0 Address cycle CMD Toggle Bits Learning pattern … A0 7 6 5 4 3 2 1 0 D4 D0 D4 D0 D4 D0 D4 D0 … … A1 7 6 5 4 3 2 1 0 D5 D1 D5 D1 D5 D1 D5 D1 … … A2 7 6 5 4 3 2 1 0 D6 D2 D6 D2 D6 D2 D6 D2 … … A3 7 6 5 4 3 2 1 0 D7 D3 D7 D3 D7 D3 D7 D3 … A(n-3) SIO1 A(n-2) SIO2 A(n-1) SIO3 An P/N: PM2145 52 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-19.Burst Read This device supports Burst Read in both SPI and QPI mode. To set the Burst length, following command operation is required to issue command: “C0h” in the first Byte (8-clocks), following 4 clocks defining wrap around enable with “0h” and disable with“1h”. The next 4 clocks are to define wrap around depth. Their definitions are as the following table: Data 00h 01h 02h 03h 1xh Wrap Around Yes Yes Yes Yes No Wrap Depth 8-byte 16-byte 32-byte 64-byte X The wrap around unit is defined within the 256Byte page, with random initial address. It is defined as “wrap-around mode disable” for the default state of the device. To exit wrap around, it is required to issue another “C0h” command in which data=‘1xh”. Otherwise, wrap around status will be retained until power down or reset command. To change wrap around depth, it is requried to issue another “C0h” command in which data=“0xh”. QPI “EBh” and SPI “EBh” support wrap around feature after wrap around is enabled. Burst read is supported in both SPI and QPI mode. The device is default without Burst read. Figure 45. Burst Read - SPI Mode CS# Mode 3 0 1 2 3 4 5 6 7 8 9 D7 D6 10 11 12 13 14 15 SCLK Mode 0 SIO C0h D5 D4 D3 D2 D1 D0 Figure 46. Burst Read - QPI Mode CS# Mode 3 0 1 2 3 SCLK Mode 0 SIO[3:0] C0h H0 MSB L0 LSB Note: MSB=Most Significant Bit LSB=Least Significant Bit P/N: PM2145 53 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-20.Performance Enhance Mode The device could waive the command cycle bits if the two cycle bits after address cycle toggles. Performance enhance mode is supported in both SPI and QPI mode. In QPI mode, "EBh" and SPI “EBh” commands support enhance mode. The performance enhance mode is not supported in dual I/O mode. To enter performance-enhancing mode, P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh can make this mode continue and skip the next 4READ instruction. To leave enhance mode, P[7:4] is no longer toggling with P[3:0]; likewise P[7:0]=FFh, 00h, AAh or 55h along with CS# is afterwards raised and then lowered. Issuing ”FFh” data cycle can also exit enhance mode. The system then will leave performance enhance mode and return to normal operation. After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low of the first clock as address instead of command cycle. Another sequence of issuing 4READ instruction especially useful in random access is : CS# goes low→sending 4READ instruction→3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling bit P[7:0]→ 4 dummy cycles (Default) →data out still CS# goes high → CS# goes low (reduce 4READ instruction) → 3-bytes random access address. P/N: PM2145 54 REV. 1.1, FEB. 18, 2016 MX25L12845G Figure 47. 4 x I/O Read enhance performance Mode Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 n SCLK Mode 0 Data Out 2 Data Out n A20 A16 A12 A8 A4 A0 P4 P0 D4 D0 D4 D0 D4 D0 SIO1 A21 A17 A13 A9 A5 A1 P5 P1 D5 D1 D5 D1 D5 D1 SIO2 A22 A18 A14 A10 A6 A2 P6 P2 D6 D2 D6 D2 D6 D2 SIO3 A23 A19 A15 A11 A7 A3 P7 P3 D7 D3 D7 D3 D7 D3 Command 6 ADD Cycles Data Out 1 Performance enhance indicator (Note 1) Configurable Dummy Cycle (Note 2) EBh SIO0 CS# n+1 ........... n+7 ...... n+9 ........... n+13 ........... Mode 3 SCLK 6 ADD Cycles Performance enhance indicator (Note 1) Data Out 1 Data Out 2 Data Out n Mode 0 Configurable Dummy Cycle (Note 2) SIO0 A20 A16 A12 A8 A4 A0 P4 P0 D4 D0 D4 D0 D4 D0 SIO1 A21 A17 A13 A9 A5 A1 P5 P1 D5 D1 D5 D1 D5 D1 SIO2 A22 A18 A14 A10 A6 A2 P6 P2 D6 D2 D6 D2 D6 D2 SIO3 A23 A19 A15 A11 A7 A3 P7 P3 D7 D3 D7 D3 D7 D3 Notes: 1. If not using performance enhance recommend to keep 1 or 0 in performance enhance indicator. 2. Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in configuration register. P/N: PM2145 55 REV. 1.1, FEB. 18, 2016 MX25L12845G Figure 48. 4 x I/O Read enhance performance Mode Sequence (QPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 A1 A0 8 9 10 11 12 13 14 15 16 17 H0 L0 H1 L1 SCLK Mode 0 SIO[3:0] EBh A5 A4 A3 A2 X X X X MSB LSB MSB LSB P(7:4) P(3:0) Data In Data Out performance enhance indicator Configurable Dummy Cycle (Note 1) CS# n+1 ............. SCLK Mode 0 SIO[3:0] A5 A4 A3 A2 A1 X A0 X X 6 Address cycles X H0 L0 H1 L1 MSB LSB MSB LSB P(7:4) P(3:0) Data Out performance enhance indicator Configurable Dummy Cycle (Note 1) Note: 1. Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in configuration register. P/N: PM2145 56 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-21.Performance Enhance Mode Reset To conduct the Performance Enhance Mode Reset operation in SPI mode, FFh data should be issued in 1I/O sequence. In QPI Mode, FFFFFFFFh data cycle, in 4 I/O should be issued. If the system controller is being Reset during operation, the flash device will return to the standard SPI operation. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. Figure 49. Performance Enhance Mode Reset for Fast Read Quad I/O (SPI Mode) Mode Bit Reset for Quad I/O CS# Mode 3 SCLK 0 1 2 3 4 5 6 Mode 3 7 Mode 0 Mode 0 SIO0 FFh SIO1 Don’t Care SIO2 Don’t Care SIO3 Don’t Care Figure 50. Performance Enhance Mode Reset for Fast Read Quad I/O (QPI Mode) Mode Bit Reset for Quad I/O CS# Mode 3 SCLK SIO[3:0] P/N: PM2145 0 1 2 3 4 5 6 Mode 0 7 Mode 3 Mode 0 FFFFFFFFh 57 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-22.Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (see "Table 4. Memory Organization") is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of the address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing SE instruction is: CS# goes low→ sending SE instruction code→ 3-byte on SI→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the Block is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB (WPSEL=1; Individual Sector Protect Mode), the Sector Erase (SE) instruction will not be executed on the block. Figure 51. Sector Erase (SE) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Mode 0 24-Bit Address Command SI 20h A23 A22 A2 A1 A0 MSB Figure 52. Sector Erase (SE) Sequence (QPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 SCLK Mode 0 24-Bit Address Command SIO[3:0] 20h A5 A4 A3 A2 A1 A0 MSB P/N: PM2145 58 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-23.Block Erase (BE32K) The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 32K-byte block erase operation. A Write Enable (WREN) instruction be executed to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE32K). Any address of the block (see "Table 4. Memory Organization") is a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed. Address bits [Am-A15] (Am is the most significant address) select the 32KB block address. The sequence of issuing BE32K instruction is: CS# goes low→ sending BE32K instruction code→ 3-byte address on SI→CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while during the Block Erase cycle is in progress. The WIP sets during the tBE32K timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the Block is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB (WPSEL=1; Individual Sector Protect Mode), the Block Erase (BE32K) instruction will not be executed on the block. Figure 53. Block Erase 32KB (BE32K) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Mode 0 Command SI 24-Bit Address 52h A23 A22 A2 A1 A0 MSB Figure 54. Block Erase 32KB (BE32K) Sequence (QPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 SCLK Mode 0 24-Bit Address Command SIO[3:0] 52h A5 A4 A3 A2 A1 A0 MSB P/N: PM2145 59 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-24.Block Erase (BE) The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (Please refer to "Table 4. Memory Organization") is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to define EAR bit. To enter the 4-byte address mode, please refer to the enter 4-byte mode (EN4B) Mode section. The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte address on SI→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the Block is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB (WPSEL=1; Individual Sector Protect Mode), the Block Erase (BE) instruction will not be executed on the block. Figure 55. Block Erase (BE) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Mode 0 Command SI 24-Bit Address D8h A23 A22 A2 A1 A0 MSB Figure 56. Block Erase (BE) Sequence (QPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 SCLK Mode 0 SIO[3:0] Command 24-Bit Address D8h A5 A4 A3 A2 A1 A0 MSB P/N: PM2145 60 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-25.Chip Erase (CE) The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed. The sequence of issuing CE instruction is: CS# goes low→sending CE instruction code→CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE timing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. When the chip is under "Block protect (BP) Mode" (WPSEL=0). The Chip Erase (CE) instruction will not be executed, if one (or more) sector is protected by BP3-BP0 bits. It will be only executed when BP3-BP0 all set to "0". When the chip is under "Advances Sector Protect Mode" (WPSEL=1). The Chip Erase (CE) instruction will be executed on unprotected block. The protected Block will be skipped. If one (or more) 4K byte sector was protected in top or bottom 64K byte block, the protected block will also skip the chip erase command. Figure 57. Chip Erase (CE) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 SCLK Mode 0 Command SI 60h or C7h Figure 58. Chip Erase (CE) Sequence (QPI Mode) CS# Mode 3 0 1 SCLK Mode 0 SIO[3:0] P/N: PM2145 Command 60h or C7h 61 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-26.Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7-A0 (The eight least significant address bits) should be set to 0. The last address byte (the 8 least significant address bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected page. If the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page and previous data will be disregarded. If the data bytes sent to the device has not exceeded 256, the data will be programmed at the request address of the page. There will be no effort on the other data bytes of the same page. The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at least 1-byte on data on SI→ CS# goes high. The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the tPP timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the page is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB (WPSEL=1; Individual Sector Protect Mode), the Page Program (PP) instruction will not be executed. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. P/N: PM2145 62 REV. 1.1, FEB. 18, 2016 MX25L12845G Figure 59. Page Program (PP) Sequence (SPI Mode) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK 1 0 7 6 5 3 2 1 0 2079 2 2078 3 2077 23 22 21 02h SI Data Byte 1 24-Bit Address 2076 Command 2075 Mode 0 4 1 0 MSB MSB 2074 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2073 2072 CS# SCLK Data Byte 2 7 SI 6 5 4 3 2 Data Byte 3 1 MSB 0 7 6 5 4 3 2 Data Byte 256 1 7 0 MSB 6 5 4 3 2 MSB Figure 60. Page Program (PP) Sequence (QPI Mode) CS# Mode 3 0 1 2 SCLK Mode 0 Command SIO[3:0] 02h Data In P/N: PM2145 24-Bit Address A5 A4 A3 A2 A1 A0 H0 L0 H1 L1 H2 L2 H3 L3 Data Byte Data Byte Data Byte Data Byte 1 2 3 4 63 H255 L255 ...... Data Byte 256 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-27.4 x I/O Page Program (4PP) The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and SIO3 as address and data input, which can improve programmer performance and the effectiveness of application. The other function descriptions are as same as standard page program. The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high. If the page is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB (WPSEL=1; Individual Sector Protect Mode), the Quad Page Program (4PP) instruction will not be executed. Figure 61. 4 x I/O Page Program (4PP) Sequence (SPI Mode only) CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 SCLK Mode 0 Data Data Data Data Byte 1 Byte 2 Byte 3 Byte 4 6 Address cycle A0 4 0 4 0 4 0 4 0 SIO1 A21 A17 A13 A9 A5 A1 5 1 5 1 5 1 5 1 SIO2 A22 A18 A14 A10 A6 A2 6 2 6 2 6 2 6 2 SIO3 A23 A19 A15 A11 A7 A3 7 3 7 3 7 3 7 3 SIO0 P/N: PM2145 Command 38h A20 A16 A12 A8 A4 64 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-28.Deep Power-down (DP) The Deep Power-down (DP) instruction is for setting the device to minimum power consumption (the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in deep power-down mode not standby mode. It's different from Standby mode. The sequence of issuing DP instruction is: CS# goes low→sending DP instruction code→CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction and softreset command. (those instructions allow the ID being reading out). When Power-down, or software reset command the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For DP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode. Figure 62. Deep Power-down (DP) Sequence (SPI Mode) CS# 0 Mode 3 1 2 3 4 5 6 tDP 7 SCLK Mode 0 Command B9h SI Stand-by Mode Deep Power-down Mode Figure 63. Deep Power-down (DP) Sequence (QPI Mode) CS# Mode 3 0 1 tDP SCLK Mode 0 Command SIO[3:0] B9h Stand-by Mode P/N: PM2145 65 Deep Power-down Mode REV. 1.1, FEB. 18, 2016 MX25L12845G 9-29.Enter Secured OTP (ENSO) The ENSO instruction is for entering the additional 4K-bit secured OTP mode. While device is in 4K-bit secured OTPmode, main array access is not available. The additional 4K-bit secured OTP is independent from main array and may be used to store unique serial number for system identifier. After entering the Secured OTP mode, follow standard read or program procedure to read out the data or update data. The Secured OTP data cannot be updated again once it is lock-down. The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP mode→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. Please note that after issuing ENSO command user can only access secure OTP region with standard read or program procedure. Furthermore, once security OTP is lock down, only read related commands are valid. 9-30.Exit Secured OTP (EXSO) The EXSO instruction is for exiting the additional 4K-bit secured OTP mode. The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP mode→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. 9-31.Read Security Register (RDSCUR) The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. The sequence of issuing RDSCUR instruction is : CS# goes low→sending RDSCUR instruction→Security Register data out on SO→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. 9-32.Write Security Register (WRSCUR) The WRSCUR instruction is for changing the values of Security Register Bits. The WREN (Write Enable) instruction is required before issuing WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any more. The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. P/N: PM2145 66 REV. 1.1, FEB. 18, 2016 MX25L12845G Security Register The definition of the Security Register bits is as below: Write Protection Selection bit. Please reference to "Write Protection Selection bit" Erase Fail bit. The Erase Fail bit is a status flag, which shows the status of last Erase operation. It will be set to "1", if the erase operation fails. It will be set to "0", if the last operation is success. Please note that it will not interrupt or stop any operation in the flash memory. Program Fail bit. The Program Fail bit is a status flag, which shows the status of last Program operation. It will be set to "1", if the program operation fails or the program region is protected. It will be set to "0", if the last operation is success. Please note that it will not interrupt or stop any operation in the flash memory. Erase Suspend bit. Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may use ESB to identify the state of flash memory. After the flash memory is suspended by Erase Suspend command, ESB is set to "1". ESB is cleared to "0" after erase operation resumes. Program Suspend bit. Program Suspend Bit (PSB) indicates the status of Program Suspend operation. Users may use PSB to identify the state of flash memory. After the flash memory is suspended by Program Suspend command, PSB is set to "1". PSB is cleared to "0" after program operation resumes. Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory or not. When it is "0", it indicates non-factory lock; "1" indicates factory-lock. Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured OTP area cannot be updated any more. While it is in 4K-bit secured OTP mode, main array access is not allowed. Table 9. Security Register Definition bit7 bit6 bit5 bit4 WPSEL E_FAIL P_FAIL Reserved 0=normal WP mode 1=individual mode (default=0) 0=normal Erase succeed 1=indicate Erase failed (default=0) 0=normal Program succeed 1=indicate Program failed (default=0) - 0=Erase is not suspended 1= Erase suspended (default=0) Non-volatile bit (OTP) Volatile bit Volatile bit Volatile bit Volatile bit P/N: PM2145 bit3 bit2 ESB PSB (Erase (Program Suspend bit) Suspend bit) 67 bit1 bit0 LDSO Secured OTP (indicate if indicator bit lock-down) 0 = not lock0=Program 0 = nondown is not factory 1 = lock-down suspended lock (cannot 1= Program 1 = factory program/ suspended lock erase (default=0) OTP) Non-volatile Non-volatile Volatile bit bit bit (OTP) (OTP) REV. 1.1, FEB. 18, 2016 MX25L12845G 9-33.Write Protection Selection (WPSEL) There are two write protection methods provided on this device, (1) Block Protection (BP) mode or (2) Individual Sector Protection mode. The protection modes are mutually exclusive. The WPSEL bit selects which protection mode is enabled. If WPSEL=0 (factory default), BP mode is enabled and Individual Sector Protection mode is disabled. If WPSEL=1, Individual Sector Protection mode is enabled and BP mode is disabled. The WPSEL command is used to set WPSEL=1. A WREN command must be executed to set the WEL bit before sending the WPSEL command. Please note that the WPSEL bit is an OTP bit. Once WPSEL is set to “1”, it cannot be programmed back to “0”. When WPSEL = 0: Block Lock (BP) protection mode, The memory array is write protected by the BP3~BP0 bits. When WPSEL =1: Individual Sector protection mode, Blocks are individually protected by their own SPB or DPB. On power-up, all blocks are write protected by the Dynamic Protection Bits (DPB) by default. The Individual Sector Protection instructions WRLR, RDLR, WRSPB, ESSPB, WRDPB, RDDPB, GBLK, and GBULK are activated. The BP3~BP0 bits of the Status Register are disabled and have no effect. Hardware protection is performed by driving WP#=0. Once WP#=0 all blocks and sectors are write protected regardless of the state of each SPB or DPB. The sequence of issuing WPSEL instruction is: CS# goes low → send WPSEL instruction to enable the Individual Sector Protect mode → CS# goes high. Write Protection Selection Start (Default in BP Mode) WPSEL=1 Set WPSEL Bit Individual Sector Protection P/N: PM2145 WPSEL=0 Block Protection (BP) 68 REV. 1.1, FEB. 18, 2016 MX25L12845G Figure 64. WPSEL Flow start WREN command RDSCUR command Yes WPSEL=1? No WPSEL disable, block protected by BP[3:0] WPSEL command RDSR command WIP=0? No Yes RDSCUR command WPSEL=1? No Yes WPSEL set successfully WPSEL set fail WPSEL enable. Block protected by Advance Sector Protection P/N: PM2145 69 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-34.Advanced Sector Protection Advanced Sector Protection can protect individual 4KB sectors in the bottom and top 64KB of memory and protect individual 64KB blocks in the rest of memory. There is one non-volatile Solid Protection Bit (SPB) and one volatile Dynamic Protection Bit (DPB) assigned to each 4KB sector at the bottom and top 64KB of memory and to each 64KB block in the rest of memory. A sector or block is write-protected from programming or erasing when its associated SPB or DPB is set to “1”. The Unprotect Solid Protect Bit (USPB) can temporarily override and disable the write-protection provided by the SPB bits. The figure below helps describing an overview of these methods. The device is default to the Solid mode when shipped from factory. The detail algorithm of advanced sector protection is shown as follows: Solid Protection mode permits the SPB bits to be modified after power-on or a reset. The figure below is an overview of Advanced Sector Protection Figure 65. Advanced Sector Protection Overview Start Set SPB Lock Bit ? SPBLKDN# = 0 SPB Lock bit locked All SPB can not be changeable SPBLKDN# = 1 SPB Lock bit Unlocked SPB is changeable Dynamic Protect Bit Register (DPB) DPB=1 sector protect Sector Array DPB=0 sector unprotect P/N: PM2145 SPB Access Register (SPB) Temporary Unprotect SPB bit (USPB) SPB=1 Write Protect USPB=0 SPB bit is disabled SPB=0 Write Unprotect USPB=1 SPB bit is effective DPB 0 SA 0 SPB 0 DPB 1 SA 1 SPB 1 DPB 2 SA 2 SPB 2 : : : : : : DPB N-1 SA N-1 SPB N-1 DPB N SA N SPB N 70 USPB REV. 1.1, FEB. 18, 2016 MX25L12845G 9-34-1. Lock Register The Lock Register is a 16-bit one-time programmable register. Lock Register bit [6] is SPB Lock Down Bit (SPBLKDN) which is an unique bit assigned to control all SPB bit status. When SPBLKDN is 1, SPB can be changed. When it is locked as 0, all SPB can not be changed anymore, and SPBLKDN bit itself can not be altered anymore, either. The Lock Register is programmed using the WRLR (Write Lock Register) command. A WREN command must be executed to set the WEL bit before sending the WRLR command. Lock Register Bits Field Name Function Type Default State 15 to 7 RFU Reserved OTP 1 6 SPBLKDN SPB Lock Down OTP 1 5 to 0 RFU Reserved OTP 1 Description Reserved for Future Use 1 = SPB changeable 0 = freeze SPB Reserved for Future Use Figure 66. Read Lock Register (RDLR) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK Mode 0 command 2Dh SI Register Out High-Z SO 7 6 5 4 3 2 Register Out 1 0 15 14 13 12 11 10 9 7 8 MSB MSB Figure 67. Write Lock Register (WRLR) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCLK Mode 0 SI SO P/N: PM2145 Command 2Ch High-Z Lock Register In 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 MSB 71 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-34-2.Solid Protection Bits The Solid Protection Bits (SPBs) are nonvolatile bits for enabling or disabling write-protection to sectors and blocks. The SPB bits have the same endurance as the Flash memory. An SPB is assigned to each 4KB sector in the bottom and top 64KB of memory and to each 64KB block in the remaining memory. The factory default state of the SPB bits is “0”, which has the sector/block write-protection disabled. When an SPB is set to “1”, the associated sector or block is write-protected. Program and erase operations on the sector or block will be inhibited. SPBs can be individually set to “1” by the WRSPB command. However, the SPBs cannot be individually cleared to “0”. Issuing the ESSPB command clears all SPBs to “0”. A WREN command must be executed to set the WEL bit before sending the WRSPB or ESSPB command. The RDSPB command reads the status of the SPB of a sector or block. The RDSPB command returns 00h if the SPB is “0”, indicating write-protection is disabled. The RDSPB command returns FFh if the SPB is “1”, indicating write-protection is enabled. In Solid Protection mode, the Unprotect Solid Protect Bit (USPB) can temporarily mask the SPB bits and disable the write-protection provided by the SPB bits. Note: If SPBLKDN=0, commands to set or clear the SPB bits will be ignored. SPB Register Bit Description 7 to 0 SPB (Solid Protection Bit) P/N: PM2145 Bit Status 00h = Unprotect Sector / Block FFh = Protect Sector / Block 72 Default Type 00h Non-volatile REV. 1.1, FEB. 18, 2016 MX25L12845G Figure 68. Read SPB Status (RDSPB) Sequence CS# 0 Mode 3 1 2 3 4 5 6 7 8 37 38 39 40 41 42 43 44 45 46 47 9 SCLK Mode 0 Command SI 32-Bit Address (Note) E2h A31 A30 A2 A1 A0 MSB Data Out High-Z SO 7 6 5 4 3 2 1 0 MSB Note: A31-A24 are don't care. Figure 69. SPB Erase (ESSPB) Sequence CS# 1 0 Mode 3 2 3 4 5 6 7 SCLK Mode 0 Command SI E4h High-Z SO Figure 70. SPB Program (WRSPB) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 37 38 39 SCLK Mode 0 SI Command 32-Bit Address (Note) E3h A31 A30 A2 A1 A0 MSB Note: A31-A24 are don't care P/N: PM2145 73 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-34-3.Dynamic Protection Bits The Dynamic Protection Bits (DPBs) are volatile bits for quickly and easily enabling or disabling write-protection to sectors and blocks. A DPB is assigned to each 4KB sector in the bottom and top 64KB of memory and to each 64KB block in the rest of the memory. The DBPs can enable write-protection on a sector or block regardless of the state of the corresponding SPB. However, the DPB bits can only unprotect sectors or blocks whose SPB bits are “0” (unprotected). When a DPB is “1”, the associated sector or block will be write-protected, preventing any program or erase operation on the sector or block. All DPBs default to “1” after power-on or reset. When a DPB is cleared to “0”, the associated sector or block will be unprotected if the corresponding SPB is also “0”. DPB bits can be individually set to “1” or “0” by the WRDPB command. The DBP bits can also be globally cleared to “0” with the GBULK command or globally set to “1” with the GBLK command. A WREN command must be executed to set the WEL bit before sending the WRDPB, GBULK, or GBLK command. The RDDPB command reads the status of the DPB of a sector or block. The RDDPB command returns 00h if the DPB is “0”, indicating write-protection is disabled. The RDDPB command returns FFh if the DPB is “1”, indicating write-protection is enabled. DPB Register Bit Description Bit Status 00h = Unprotect Sector / Block FFh = Protect Sector / Block 7 to 0 DPB (Dynamic Protection Bit) Default Type FFh Volatile Figure 71. Read DPB Register (RDDPB) Sequence CS# 0 Mode 3 1 2 3 4 5 6 7 8 37 38 39 40 41 42 43 44 45 46 47 9 SCLK Mode 0 Command SI 32-Bit Address E0h A31 A30 A2 A1 A0 MSB Data Out High-Z SO 7 6 5 4 3 2 1 0 MSB Figure 72. Write DPB Register (WRDPB) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 37 38 39 40 41 42 43 44 45 46 47 9 SCLK Mode 0 SI Command E1h A31 A30 A2 A1 A0 MSB P/N: PM2145 Data Byte 1 32-Bit Address 7 6 5 4 3 2 1 0 MSB 74 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-34-4.Temporary Un-protect Solid write protect bit (USPB) The Unprotect Solid Protect Bit is a volatile bit that defaults to “1” after power-on or reset. When USPB=1, the SPBs have their normal function. When USPB=0 all SPBs are masked and their write-protected sectors and blocks are temporarily unprotected (as long as their corresponding DPBs are “0“). The USPB provides a means to temporarily override the SPBs without having to issue the ESSPB and WRSPB commands to clear and set the SPBs. The USPB can be set or cleared as often as needed. Please refer to "9-34-6. Sector Protection States Summary Table" for the sector state with the protection status of DPB/SPB/USPB bits. 9-34-5.Gang Block Lock/Unlock (GBLK/GBULK) These instructions are only effective if WPSEL=1. The GBLK and GBULK instructions provide a quick method to set or clear all DPB bits at once. The WREN (Write Enable) instruction is required before issuing the GBLK/GBULK instruction. The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction →CS# goes high. The GBLK and GBULK commands are accepted in both SPI and QPI mode. The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed. 9-34-6.Sector Protection States Summary Table DPB SPB USPB 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 P/N: PM2145 Sector/Block Protection State Unprotected Unprotected Unprotected Protected Protected Protected Protected Protected 75 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-35.Program/Erase Suspend/Resume The device allow the interruption of Sector-Erase, Block-Erase or Page-Program operations and conduct other operations. After issue suspend command, the system can determine if the device has entered the Erase-Suspended mode through Bit2 (PSB) and Bit3 (ESB) of security register. (please refer to "Table 9. Security Register Definition") Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. 9-36.Erase Suspend Erase suspend allow the interruption of all erase operations. After the device has entered Erase-Suspended mode, the system can read any sector(s) or Block(s) except those being erased by the suspended erase operation. Reading the sector or Block being erase suspended is invalid. After erase suspend, WEL bit will be clear, only read related, resume and reset command can be accepted, including: 03h, 0Bh, 3Bh, 6Bh, BBh, EBh, 5Ah, C0h, 06h, 04h, 2Bh, 9Fh, AFh, 05h, ABh, 90h, B1h, C1h, B0h, 30h, 66h, 99h, 00h, 35h, F5h, 15h, 2Dh, E2h, E0h. If the system issues an Erase Suspend command after the sector erase operation has already begun, the device will not enter Erase-Suspended mode until tESL time has elapsed. Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may use ESB to identify the state of flash memory. After the flash memory is suspended by Erase Suspend command, ESB is set to "1". ESB is cleared to "0" after erase operation resumes. 9-37.Program Suspend Program suspend allows the interruption of all program operations. After the device has entered ProgramSuspended mode, the system can read any sector(s) or Block(s) except those being programmed by the suspended program operation. Reading the sector or Block being program suspended is invalid. After program suspend, WEL bit will be cleared, only read related, resume and reset command can be accepted, including: 03h, 0Bh, 3Bh, 6Bh, BBh, EBh, 5Ah, C0h, 06h, 04h, 2Bh, 9Fh, AFh, 05h, ABh, 90h, B1h, C1h, B0h, 30h, 66h, 99h, 00h, 35h, F5h, 15h, 2Dh, E2h, E0h. Program Suspend Bit (PSB) indicates the status of Program Suspend operation. Users may use PSB to identify the state of flash memory. After the flash memory is suspended by Program Suspend command, PSB is set to "1". PSB is cleared to "0" after program operation resumes. P/N: PM2145 76 REV. 1.1, FEB. 18, 2016 MX25L12845G Figure 73. Suspend to Read Latency tPSL / tESL CS# Suspend Command Read Command tPSL: Program Latency tESL: Erase Latency Figure 74. Resume to Read Latency tSE / tBE / tPP CS# Resume Command Read Command Figure 75. Resume to Suspend Latency tPRS / tERS CS# Resume Command Suspend Command tPRS: Program Resume to another Suspend tERS: Erase Resume to another Suspend P/N: PM2145 77 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-38.Write-Resume The Write operation is being resumed when Write-Resume instruction issued. ESB or PSB (suspend status bit) in Status register will be changed back to “0”. The operation of Write-Resume is as follows: CS# drives low → send write resume command cycle (30h) → drive CS# high. By polling Busy Bit in status register, the internal write operation status could be checked to be completed or not. The user may also wait the time lag of TSE, TBE, TPP for Sector-erase, Block-erase or Page-programming. WREN (command "06h") is not required to issue before resume. Please note that, if "performance enhance mode" is executed during suspend operation, the device can not be resumed. To restart the write command, disable the "performance enhance mode" is required. After the "performance enhance mode" is disabled, the write-resume command is effective. 9-39.No Operation (NOP) The “No Operation” command is only able to terminate the Reset Enable (RSTEN) command and will not affect any other command. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care during SPI mode. 9-40.Software Reset (Reset-Enable (RSTEN) and Reset (RST)) The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command and Reset (RST) command. It returns the device to standby mode. All the volatile bits and settings will be cleared then, which makes the device return to the default status as power on. To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed first to perform the Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable will be invalid. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. If the Reset command is executed during program or erase operation, the operation will be disabled, the data under processing could be damaged or lost. The reset time is different depending on the last operation. For details, please refer to "Table 15. Reset Timing(Other Operation)" for tREADY2. P/N: PM2145 78 REV. 1.1, FEB. 18, 2016 MX25L12845G Figure 76. Software Reset Recovery Stand-by Mode 66 CS# 99 tReady2 Mode Note: Refer to "Table 15. Reset Timing-(Other Operation)" for tREADY2 data. Figure 77. Reset Sequence (SPI mode) tSHSL CS# SCLK Mode 3 Mode 3 Mode 0 Mode 0 Command Command 99h 66h SIO0 Figure 78. Reset Sequence (QPI mode) tSHSL CS# MODE 3 MODE 3 MODE 3 SCLK MODE 0 SIO[3:0] P/N: PM2145 Command MODE 0 66h Command MODE 0 99h 79 REV. 1.1, FEB. 18, 2016 MX25L12845G 9-41.Read SFDP Mode (RDSFDP) The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3 address bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS# to high at any time during data out. SFDP is a JEDEC standard, JESD216B. Figure 79. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI SO 24 BIT ADDRESS 23 22 21 5Ah 3 2 1 0 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Cycle SI 7 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 SO 7 6 5 3 2 1 0 7 MSB MSB P/N: PM2145 4 80 6 5 4 3 2 1 0 7 MSB REV. 1.1, FEB. 18, 2016 MX25L12845G Table 10. Signature and Parameter Identification Data Values SFDP Table (JESD216B) below is for MX25L12845GM2I-10G, MX25L12845GMI-10G, MX25L12845GZNI-10G, MX25L12845GM2I-08G, MX25L12845GMI-08G and MX25L12845GZNI-08G Description SFDP Signature Comment Fixed: 50444653h Add (h) DW Add Data (h/b) Data (Byte) (Bit) (Note1) (h) 00h 07:00 53h 53h 01h 15:08 46h 46h 02h 23:16 44h 44h 03h 31:24 50h 50h SFDP Minor Revision Number Start from 00h 04h 07:00 06h 06h SFDP Major Revision Number Start from 01h This number is 0-based. Therefore, 0 indicates 1 parameter header. 05h 15:08 01h 01h 06h 23:16 02h 02h 07h 31:24 FFh FFh 00h: it indicates a JEDEC specified header. 08h 07:00 00h 00h Number of Parameter Headers Unused ID number (JEDEC) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Start from 00h 09h 15:08 06h 06h Start from 01h 0Ah 23:16 01h 01h How many DWORDs in the Parameter table 0Bh 31:24 10h 10h 0Ch 07:00 30h 30h Parameter Table Pointer (PTP) First address of JEDEC Flash Parameter table 0Dh 15:08 00h 00h 0Eh 23:16 00h 00h 0Fh 31:24 FFh FFh Unused P/N: PM2145 81 REV. 1.1, FEB. 18, 2016 MX25L12845G SFDP Table below is for MX25L12845GM2I-10G, MX25L12845GMI-10G, MX25L12845GZNI-10G, MX25L12845GM2I-08G, MX25L12845GMI-08G and MX25L12845GZNI-08G Description ID number (Macronix manufacturer ID) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) Comment it indicates Macronix manufacturer ID 10h 07:00 C2h C2h Start from 00h 11h 15:08 00h 00h Start from 01h 12h 23:16 01h 01h How many DWORDs in the Parameter table 13h 31:24 04h 04h 14h 07:00 10h 10h 15h 15:08 01h 01h 16h 23:16 00h 00h 17h 31:24 FFh FFh 4-byte Address Instruction parameter ID 18h 07:00 84h 84h Start from 00h 19h 15:08 00h 00h Start from 01h 1Ah 23:16 01h 01h How many DWORDs in the Parameter table 1Bh 31:24 02h 02h 1Ch 07:00 C0h C0h 1Dh 15:08 00h 00h 1Eh 23:16 00h 00h 1Fh 31:24 FFh FFh First address of Macronix Flash Parameter table Unused ID number (4-byte Address Instruction) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) First address of 4-byte Address Instruction table Unused P/N: PM2145 Add (h) DW Add Data (h/b) Data (Byte) (Bit) (Note1) (h) 82 REV. 1.1, FEB. 18, 2016 MX25L12845G Table 11. Parameter Table (0): JEDEC Flash Parameter Tables SFDP Table below is for MX25L12845GM2I-10G, MX25L12845GMI-10G, MX25L12845GZNI-10G, MX25L12845GM2I-08G, MX25L12845GMI-08G and MX25L12845GZNI-08G Description Comment Block/Sector Erase sizes 00: Reserved, 01: 4KB erase, 10: Reserved, 11: not supported 4KB erase Write Granularity 0: 1Byte, 1: 64Byte or larger Write Enable Instruction Required 0: not required 1: required 00h to be written to the for Writing to Volatile Status status register Registers Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) 01b 02 1b 03 0b 30h 0: use 50h instruction 1: use 06h instruction Write Enable Instruction Select for Note: If target flash status register is Writing to Volatile Status Registers nonvolatile, then bits 3 and 4 must be set to 00b. Contains 111b and can never be Unused changed 4KB Erase Instruction 01:00 31h E5h 04 0b 07:05 111b 15:08 20h (1-1-2) Fast Read (Note2) 0=not supported 1=supported 16 1b Address Bytes Number used in addressing flash array Double Transfer Rate (DTR) Clocking 00: 3Byte only, 01: 3 or 4Byte, 10: 4Byte only, 11: Reserved 18:17 00b 0=not supported 1=supported 19 1b 20 1b 32h Data (h) 20h F9h (1-2-2) Fast Read 0=not supported 1=supported (1-4-4) Fast Read 0=not supported 1=supported 21 1b (1-1-4) Fast Read 0=not supported 1=supported 22 1b 23 1b 33h 31:24 FFh 37h:34h 31:00 07FF FFFFh Unused Unused Flash Memory Density (1-4-4) Fast Read Number of Wait states (Note3) (1-4-4) Fast Read Number of Mode Bits (Note4) 0 0000b: Not supported; 0 0100b: 4 0 0110b: 6; 0 1000b: 8 Mode Bits: 000b: Not supported; 010b: 2 bits (1-4-4) Fast Read Instruction (1-1-4) Fast Read Number of Wait states (1-1-4) Fast Read Number of Mode Bits 39h 0 0000b: Not supported; 0 0100b: 4 0 0110b: 6; 0 1000b: 8 Mode Bits: 000b: Not supported; 010b: 2 bits (1-1-4) Fast Read Instruction P/N: PM2145 38h 3Ah 3Bh 83 04:00 0 0100b 07:05 010b 15:08 EBh 20:16 0 1000b 23:21 000b 31:24 6Bh FFh 44h EBh 08h 6Bh REV. 1.1, FEB. 18, 2016 MX25L12845G SFDP Table below is for MX25L12845GM2I-10G, MX25L12845GMI-10G, MX25L12845GZNI-10G, MX25L12845GM2I-08G, MX25L12845GMI-08G and MX25L12845GZNI-08G Description Comment (1-1-2) Fast Read Number of Wait states (1-1-2) Fast Read Number of Mode Bits 0 0000b: Not supported; 0 0100b: 4 0 0110b: 6; 0 1000b: 8 Mode Bits: 000b: Not supported; 010b: 2 bits (1-1-2) Fast Read Instruction (1-2-2) Fast Read Number of Wait states (1-2-2) Fast Read Number of Mode Bits 0 0000b: Not supported; 0 0100b: 4 0 0110b: 6; 0 1000b: 8 Mode Bits: 000b: Not supported; 010b: 2 bits 3Eh 3Fh 0=not supported 1=supported Unused (4-4-4) Fast Read 3Ch 3Dh (1-2-2) Fast Read Instruction (2-2-2) Fast Read Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) 0=not supported 1=supported 40h Unused 04:00 0 1000b 07:05 000b 15:08 3Bh 20:16 0 0100b 23:21 000b 31:24 BBh 00 0b 03:01 111b 04 1b 07:05 111b Data (h) 08h 3Bh 04h BBh FEh Unused 43h:41h 31:08 FFh FFh Unused 45h:44h 15:00 FFh FFh 20:16 0 0000b 23:21 000b 47h 31:24 FFh FFh 49h:48h 15:00 FFh FFh 20:16 0 0100b 23:21 010b 4Bh 31:24 EBh EBh 4Ch 07:00 0Ch 0Ch 4Dh 15:08 20h 20h 4Eh 23:16 0Fh 0Fh 4Fh 31:24 52h 52h 50h 07:00 10h 10h 51h 15:08 D8h D8h 52h 23:16 00h 00h 53h 31:24 FFh FFh (2-2-2) Fast Read Number of Wait states (2-2-2) Fast Read Number of Mode Bits 0 0000b: Not supported; 0 0100b: 4 0 0110b: 6; 0 1000b: 8 Mode Bits: 000b: Not supported; 010b: 2 bits (2-2-2) Fast Read Instruction Unused (4-4-4) Fast Read Number of Wait states (4-4-4) Fast Read Number of Mode Bits 0 0000b: Not supported; 0 0100b: 4 0 0110b: 6; 0 1000b: 8 Mode Bits: 000b: Not supported; 010b: 2 bits (4-4-4) Fast Read Instruction Erase Type 1 Size Sector/block size = 2^N bytes (Note5) 0Ch: 4KB; 0Fh: 32KB; 10h: 64KB Erase Type 1 Erase Instruction Erase Type 2 Size Sector/block size = 2^N bytes 00h: N/A; 0Fh: 32KB; 10h: 64KB Erase Type 2 Erase Instruction Erase Type 3 Size Sector/block size = 2^N bytes 00h: N/A; 0Fh: 32KB; 10h: 64KB Erase Type 3 Erase Instruction Erase Type 4 Size 00h: N/A, This sector type doesn't exist Erase Type 4 Erase Instruction P/N: PM2145 84 46h 4Ah 00h 44h REV. 1.1, FEB. 18, 2016 MX25L12845G SFDP Table below is for MX25L12845GM2I-10G, MX25L12845GMI-10G, MX25L12845GZNI-10G, MX25L12845GM2I-08G, MX25L12845GMI-08G and MX25L12845GZNI-08G Description Add (h) DW Add (Byte) (Bit) Comment Multiplier value: 0h~Fh (0~15) Multiplier from typical erase time Max. time = 2 * (Multiplier + 1) * to maximum erase time Typical Time Erase Type 1 Erase Time (Typical) EraseType 2 Erase Time (Typical) Erase Type 3 Erase Time (Typical) Erase Type 4 Erase Time (Typical) Multiplier from typical time to max time for Page or byte program Page Program Size Page Program Time (Typical) Byte Program Time, First Byte (Typical) Byte Program Time, Additional Byte (Typical) P/N: PM2145 Data (h/b) (Note1) 03:00 0110b 07:04 08 1 1101b 10:09 00b Count value: 00h~1Fh (0~31) Typical Time = (Count + 1) * Units 15:11 0 1011b Units 00: 1ms, 01: 16ms 10b: 128ms, 11b: 1s 17:16 01b 22:18 1 0111b 24:23 01b 29:25 0 0000b 31:30 00b 03:00 0010b 07:04 1000h 12:08 1 1111b 13 0b 15:14 17:16 1110b 18 0b 22:19 0000b 23 0b 54h Count value: 00h~1Fh (0~31) Typical Time = (Count + 1) * Units Units 00: 1ms, 01: 16ms 10b: 128ms, 11b: 1s 55h Count value: 00h~1Fh (0~31) Typical Time = (Count + 1) * Units Units 00: 1 ms, 01: 16 ms 10b: 128ms, 11b: 1s Count value: 00h~1Fh (0~31) Typical Time = (Count + 1) * Units Units 00: 1ms, 01: 16ms 10b: 128 ms, 11b: 1 s Multiplier value: 0h~Fh (0~15) Max. time = 2 * (Multiplier + 1) *Typical Time Page size = 2^N bytes 2^8 = 256 bytes, 8h = 1000b 56h 57h 58h Count value: 00h~1Fh (0~31) Typical Time = (Count + 1) * Units 59h Units 0: 8us, 1: 64us Count value: 0h~Fh (0~15) Typical Time = (Count + 1) * Units Units 0: 1us, 1: 8us Count value: 0h~Fh (0~15) Typical Time = (Count + 1) * Units Units 0: 1us, 1: 8us 85 5Ah Data (h) D6h 59h DDh 00h 82h 9Fh 03h REV. 1.1, FEB. 18, 2016 MX25L12845G SFDP Table below is for MX25L12845GM2I-10G, MX25L12845GMI-10G, MX25L12845GZNI-10G, MX25L12845GM2I-08G, MX25L12845GMI-08G and MX25L12845GZNI-08G Description Chip Erase Time (Typical) Reserved Prohibited Operations During Program Suspend Prohibited Operations During Erase Suspend Reserved Program Resume to Suspend Interval (Typical) Program Suspend Latency (Max.) Erase Resume to Suspend Interval (Typical) Erase Suspend Latency (Max.) Suspend / Resume supported Program Resume Instruction Program Suspend Instruction Erase Resume Instruction Erase Suspend Instruction P/N: PM2145 Comment Count value: 00h~1Fh (0~31) Typical Time = (Count + 1) * Units Units 00: 16ms, 01: 256ms 10: 4s, 11: 64s Reserved: 1b xxx0b: May not initiate a new erase anywhere xx0xb: May not initiate a new page program anywhere x1xxb: May not initiate a read in the program suspended page size 1xxxb: The erase and program restrictions in bits 1:0 are sufficient xxx0b: May not initiate a new erase anywhere xx1xb: May not initiate a page program in the erase suspended sector size xx0xb: May not initiate a page program anywhere x1xxb: May not initiate a read in the erase suspended sector size 1xxxb: The erase and program restrictions in bits 5:4 are sufficient Reserved: 1b Count value: 0h~Fh (0~15) Typical Time = (Count + 1) * 64us Count value: 00h~1Fh (0~31) Maximum Time = (Count + 1) * Units Units 00: 128ns, 01: 1us 10: 8us, 11: 64us Count value: 0h~Fh (0~15) Typical Time = (Count + 1) * 64us Count value: 00h~1Fh (0~31) Maximum Time = (Count + 1) * Units Units 00: 128ns, 01: 1us 10: 8us, 11: 64us 0= Support 1= Not supported Instruction to Resume a Program Instruction to Suspend a Program Instruction to Resume Write/Erase Instruction to Suspend Write/Erase 86 Add (h) DW Add (Byte) (Bit) 27:24 28 5Bh Data (h/b) (Note1) 0 1101b 30:29 10b 31 1b 03:00 0100b 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h Data (h) CDh 44h 07:04 0100b 08 1b 12:09 0001b 15:13 17:16 1 1000b 19:18 01b 23:20 0110b 28:24 1 1000b 30:29 01b 31 07:00 15:08 23:16 31:24 0b 30h B0h 30h B0h 03h 67h 38h 30h B0h 30h B0h REV. 1.1, FEB. 18, 2016 MX25L12845G SFDP Table below is for MX25L12845GM2I-10G, MX25L12845GMI-10G, MX25L12845GZNI-10G, MX25L12845GM2I-08G, MX25L12845GMI-08G and MX25L12845GZNI-08G Description Comment Reserved Reserved: 11b Bit 2: Read WIP bit [0] by 05h Read instruction Status Register Polling Device Bit 3: Read bit 7 of Status Register Busy by 70h Read instruction (0=not supported 1=support) Bit 07:04, Reserved: 1111b Count value: 00h~1Fh (0~31) Release from Deep Power-down Maximum Time = (Count + 1) * Units Units (RDP) Delay 00: 128ns, 01: 1us (Max.) 10: 8us, 11: 64us Release from Deep Power-down Instruction to Exit Deep Power Down (RDP) Instruction Enter Deep Power Down Instruction to Enter Deep Power Instruction Down Deep Power Down Supported 0: Supported 1: Not supported Methods to exit 4-4-4 mode 4-4-4 Mode Disable Sequences xx1xb: issue F5h instruction Methods to enter 4-4-4 mode 4-4-4 Mode Enable Sequences x_x1xxb: issue instruction 35h Performance Enhance Mode, 0-4-4 Mode Supported Continuous Read, Execute in Place 0: Not supported 1: Supported xx_xxx1b: Mode Bits[7:0] = 00h will terminate this mode at the end of the current read operation. xx_xx1xb: If 3-Byte address active, input Fh on DQ0-DQ3 for 8 clocks. If 4-Byte address active, input Fh on DQ0-DQ3 for 10 0-4-4 Mode Exit Method clocks. xx_x1xxb: Reserved xx_1xxxb: Input Fh (mode bit reset) on DQ0-DQ3 for 8 clocks. x1_xxxxb: Mode Bit[7:0]≠Axh 1x_xxxxb: Reserved xxx1b: Mode Bits[7:0] = A5h Note: QE must be set prior to using this mode 0-4-4 Mode Entry Method x1xxb: Mode Bit[7:0]=Axh 1xxxb: Reserved 000b: No QE bit. Detects 1-1-4/1-4 4 reads based on instruction Quad Enable (QE) bit 010b: QE is bit 6 of Status Register. Requirements where 1=Quad Enable or 0=not Quad Enable 111b: Not Supported HOLD and RESET Disable by bit 0: Not supported 4 of Ext. Configuration Register P/N: PM2145 87 Add (h) DW Add (Byte) (Bit) 01:00 64h 65h 66h 67h 68h Data (h/b) (Note1) 11b 07:02 11 1101b 12:08 1 1101b 14:13 01b 15 22:16 23 30:24 31 1010 1011b (ABh) 1011 1001b (B9h) 0b 03:00 1010b 07:04 08 0 0100b 09 1b 69h Data (h) F7h BDh D5h 5Ch 4Ah BEh 15:10 10 1111b 19:16 1001h 6Ah 29h 22:20 010b 23 0b REV. 1.1, FEB. 18, 2016 MX25L12845G SFDP Table below is for MX25L12845GM2I-10G, MX25L12845GMI-10G, MX25L12845GZNI-10G, MX25L12845GM2I-08G, MX25L12845GMI-08G and MX25L12845GZNI-08G Description Add (h) DW Add (Byte) (Bit) Comment Reserved 6Bh xxx_xxx1b: Non-Volatile Status Register 1, powers-up to last Volatile or Non-Volatile Register written value, use instruction and Write Enable Instruction for 06h to enable write Status Register 1 x1x_xxxxb: Reserved 1xx_xxxxb: Reserved 6Ch Reserved Soft Reset and Rescue Sequence Support Exit 4-Byte Addressing P/N: PM2145 Return the device to its default power-on state x1_xxxxb: issue reset enable instruction 66h, then issue reset instruction 99h. xx_xxxx_xxx1b: issue instruction E9h to exit 4-Byte address mode (write enable instruction 06h is not required) xx_xxxx_x1xxb: 8-bit volatile extended address register used to define A[31:A24] bits. Read with instruction C8h. Write instruction is C5h, data length is 1 byte. Return to lowest memory segment by setting A[31:24] to 00h and use 3-Byte addressing. xx_xx1x_xxxxb: Hardware reset xx_x1xx_xxxxb: Software reset (see bits 13:8 in this DWORD) xx_1xxx_xxxxb: Power cycle x1_xxxx_xxxxb: Reserved 1x_xxxx_xxxxb: Reserved 88 6Dh 6Eh Data (h/b) (Note1) Data (h) 31:24 FFh FFh 06:00 111 0000b 07 1b 13:08 01 0000b 15:14 11b 23:16 1111 1111b F0h D0h FFh REV. 1.1, FEB. 18, 2016 MX25L12845G SFDP Table below is for MX25L12845GM2I-10G, MX25L12845GMI-10G, MX25L12845GZNI-10G, MX25L12845GM2I-08G, MX25L12845GMI-08G and MX25L12845GZNI-08G Description Enter 4-Byte Addressing P/N: PM2145 Comment xxxx_xxx1b: issue instruction B7h (preceding write enable not required) xxxx_x1xxb: 8-bit volatile extended address register used to define A[31:24] bits. Read with instruction C8h. Write instruction is C5h with 1 byte of data. Select the active 128 Mbit memory segment by setting the appropriate A[31:24] bits and use 3-Byte addressing. xx1x_xxxxb: Supports dedicated 4-Byte address instruction set. Consult vendor data sheet for the instruction set definition. 1xxx_xxxxb: Reserved 89 Add (h) DW Add (Byte) (Bit) 6Fh 31:24 Data (h/b) (Note1) Data (h) 1111 1111b FFh REV. 1.1, FEB. 18, 2016 MX25L12845G Table 12. Parameter Table (1): 4-Byte Instruction Tables SFDP Table below is for MX25L12845GM2I-10G, MX25L12845GMI-10G, MX25L12845GZNI-10G, MX25L12845GM2I-08G, MX25L12845GMI-08G and MX25L12845GZNI-08G Description Support for (1-1-1) READ Command, Instruction=13h Support for (1-1-1) FAST_READ Command, Instruction=0Ch Support for (1-1-2) FAST_READ Command, Instruction=3Ch Support for (1-2-2) FAST_READ Command, Instruction=BCh Support for (1-1-4) FAST_READ Command, Instruction=6Ch Support for (1-4-4) FAST_READ Command, Instruction=ECh Support for (1-1-1) Page Program Command, Instruction=12h Support for (1-1-4) Page Program Command, Instruction=34h Support for (1-4-4) Page Program Command, Instruction=3Eh Support for Erase Command – Type 1 size, Instruction lookup in next Dword Support for Erase Command – Type 2 size, Instruction lookup in next Dword Support for Erase Command – Type 3 size, Instruction lookup in next Dword Support for Erase Command – Type 4 size, Instruction lookup in next Dword Support for (1-1-1) DTR_Read Command, Instruction=0Eh Support for (1-2-2) DTR_Read Command, Instruction=BEh Support for (1-4-4) DTR_Read Command, Instruction=EEh P/N: PM2145 Comment Add (h) DW Add Data (h/b) Data (Byte) (Bit) (Note1) (h) 0=not supported 1=supported 00 0b 0=not supported 1=supported 01 0b 0=not supported 1=supported 02 0b 03 0b 04 0b 0=not supported 1=supported 05 0b 0=not supported 1=supported 06 0b 0=not supported 1=supported 07 0b 0=not supported 1=supported 08 0b 0=not supported 1=supported 09 0b 0=not supported 1=supported 10 0b 11 0b 0=not supported 1=supported 12 0b 0=not supported 1=supported 13 0b 0=not supported 1=supported 14 0b 0=not supported 1=supported 15 0b 0=not supported 1=supported 0=not supported 1=supported 0=not supported 1=supported 90 C0h C1h 00h 00h REV. 1.1, FEB. 18, 2016 MX25L12845G SFDP Table below is for MX25L12845GM2I-10G, MX25L12845GMI-10G, MX25L12845GZNI-10G, MX25L12845GM2I-08G, MX25L12845GMI-08G and MX25L12845GZNI-08G Description Support for volatile individual sector lock Read command, Instruction=E0h Support for volatile individual sector lock Write command, Instruction=E1h Support for non-volatile individual sector lock read command, Instruction=E2h Support for non-volatile individual sector lock write command, Instruction=E3h Comment Add (h) DW Add Data (h/b) Data (Byte) (Bit) (Note1) (h) 0=not supported 1=supported 16 1b 0=not supported 1=supported 17 1b 18 1b 19 1b 23:20 1111b 0=not supported 1=supported C2h 0=not supported 1=supported FFh Reserved Reserved Reserved Reserved C3h 31:24 FFh FFh Instruction for Erase Type 1 FFh=not supported C4h 07:00 FFh FFh Instruction for Erase Type 2 FFh=not supported C5h 15:08 FFh FFh Instruction for Erase Type 3 FFh=not supported C6h 23:16 FFh FFh Instruction for Erase Type 4 FFh=not supported C7h 31:24 FFh FFh P/N: PM2145 91 REV. 1.1, FEB. 18, 2016 MX25L12845G Table 13. Parameter Table (2): Macronix Flash Parameter Tables SFDP Table below is for MX25L12845GM2I-10G, MX25L12845GMI-10G, MX25L12845GZNI-10G, MX25L12845GM2I-08G, MX25L12845GMI-08G and MX25L12845GZNI-08G Description Add (h) (Byte) Comment DW Add Data (h/b) (Bit) (Note1) Data (h) Vcc Supply Maximum Voltage 2000h=2.000V 2700h=2.700V 3600h=3.600V 111h:110h 07:00 15:08 00h 36h 00h 36h Vcc Supply Minimum Voltage 1650h=1.650V, 1750h=1.750V 2250h=2.250V, 2300h=2.300V 2350h=2.350V, 2650h=2.650V 2700h=2.700V 113h: 112h 23:16 31:24 00h 27h 00h 27h H/W Reset# pin 0=not supported 1=supported 00 1b H/W Hold# pin 0=not supported 1=supported 01 0b Deep Power Down Mode 0=not supported 1=supported 02 1b S/W Reset 0=not supported 1=supported 03 1b S/W Reset Instruction Reset Enable (66h) should be issued before Reset Instruction Program Suspend/Resume 0=not supported 1=supported 12 1b Erase Suspend/Resume 0=not supported 1=supported 13 1b 14 1b 15 1b 116h 23:16 C0h C0h 117h 31:24 64h 64h 115h: 114h Unused Wrap-Around Read mode 0=not supported 1=supported Wrap-Around Read mode Instruction 11:04 1001 1001b F99Dh (99h) Wrap-Around Read data length 08h:support 8B wrap-around read 16h:8B&16B 32h:8B&16B&32B 64h:8B&16B&32B&64B Individual block lock 0=not supported 1=supported 00 1b Individual block lock bit (Volatile/Nonvolatile) 0=Volatile 1=Nonvolatile 01 0b 09:02 1110 0001b (E1h) 10 0b 11 1b Individual block lock Instruction Individual block lock Volatile protect bit default protect status 0=protect 1=unprotect Secured OTP 0=not supported 1=supported Read Lock 0=not supported 1=supported 12 0b Permanent Lock 0=not supported 1=supported 13 0b Unused 15:14 11b Unused 31:16 FFh FFh 31:00 FFh FFh Unused P/N: PM2145 11Bh: 118h 11Fh: 11Ch 92 CB85h REV. 1.1, FEB. 18, 2016 MX25L12845G Note 1:h/b is hexadecimal or binary. Note 2:(x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2), and (4-4-4) Note 3:Wait States is required dummy clock cycles after the address bits or optional mode bits. Note 4:Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller if they are specified. (eg,read performance enhance toggling bits) Note 5:4KB=2^0Ch, 32KB=2^0Fh, 64KB=2^10h Note 6:All unused and undefined area data is blank FFh for SFDP Tables that are defined in Parameter Identification Header. All other areas beyond defined SFDP Table are reserved by Macronix. P/N: PM2145 93 REV. 1.1, FEB. 18, 2016 MX25L12845G 10. RESET Driving the RESET# pin low for a period of tRLRH or longer will reset the device. After reset cycle, the device is at the following states: - Standby mode - All the volatile bits such as WEL/WIP/SRAM lock bit will return to the default status as power on. - 3-byte address mode If the device is under programming or erasing, driving the RESET# pin low will also terminate the operation and data could be lost. During the resetting cycle, the SO data becomes high impedance and the current will be reduced to minimum. Figure 80. RESET Timing CS# tRHSL SCLK tRH tRS RESET# tRLRH tREADY1 / tREADY2 Table 14. Reset Timing-(Power On) Symbol Parameter tRHSL Reset# high before CS# low tRS Reset# setup time tRH Reset# hold time tRLRH Reset# low pulse width tREADY1 Reset Recovery time Min. 10 15 15 10 35 Typ. Max. Unit us ns ns us us Min. 10 15 15 10 40 35 310 12 25 100 40 Typ. Max. Unit us ns ns us us us us ms ms ms ms Table 15. Reset Timing-(Other Operation) Symbol tRHSL tRS tRH tRLRH Parameter Reset# high before CS# low Reset# setup time Reset# hold time Reset# low pulse width Reset Recovery time (During instruction decoding) Reset Recovery time (for read operation) Reset Recovery time (for program operation) tREADY2 Reset Recovery time(for SE4KB operation) Reset Recovery time (for BE64K/BE32KB operation) Reset Recovery time (for Chip Erase operation) Reset Recovery time (for WRSR operation) P/N: PM2145 94 REV. 1.1, FEB. 18, 2016 MX25L12845G 11. POWER-ON STATE The device is at the following states after power-up: - Standby mode (please note it is not deep power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage until the VCC reaches the following levels: - VCC minimum at power-up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and the flash device has no response to any command. For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The write, erase, and program command should be sent after the below time delay: - tVSL after VCC reached VCC minimum level The device can accept read command after VCC reached VCC minimum and a time delay of tVSL. Please refer to the "Figure 87. Power-up Timing". Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uF) - At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any command. The data corruption might occur during this stage if a write, program, erase cycle is in progress. P/N: PM2145 95 REV. 1.1, FEB. 18, 2016 MX25L12845G 12. ELECTRICAL SPECIFICATIONS Table 16. ABSOLUTE MAXIMUM RATINGS RATING VALUE Ambient Operating Temperature Industrial grade -40°C to 85°C Storage Temperature -65°C to 150°C Applied Input Voltage -0.5V to VCC+0.5V Applied Output Voltage -0.5V to VCC+0.5V VCC to Ground Potential -0.5V to 4.0V NOTICE: 1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 2. Specifications contained within the following tables are subject to change. 3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see "Figure 81. Maximum Negative Overshoot Waveform" and "Figure 82. Maximum Positive Overshoot Waveform". Figure 81. Maximum Negative Overshoot Waveform 20ns Figure 82. Maximum Positive Overshoot Waveform 20ns 20ns Vss Vcc + 2.0V Vss-2.0V Vcc 20ns 20ns 20ns Table 17. CAPACITANCE TA = 25°C, f = 1.0 MHz Symbol Parameter CIN COUT P/N: PM2145 Min. Typ. Max. Unit Input Capacitance 8 pF VIN = 0V Output Capacitance 10 pF VOUT = 0V 96 Conditions REV. 1.1, FEB. 18, 2016 MX25L12845G Figure 83. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL Input timing reference level 0.8VCC Output timing reference level 0.7VCC AC Measurement Level 0.8V 0.2VCC 0.5VCC Note: Input pulse rise and fall time are <5ns Figure 84. OUTPUT LOADING 25K ohm DEVICE UNDER TEST CL +3V 25K ohm CL=30pF Including jig capacitance P/N: PM2145 97 REV. 1.1, FEB. 18, 2016 MX25L12845G Table 18. DC CHARACTERISTICS (Temperature = -40°C to 85°C, VCC = 2.7V - 3.6V) Symbol Parameter Notes Min. Typ. Max. Units Test Conditions ILI Input Load Current 1 ±2 uA VCC = VCC Max, VIN = VCC or GND ILO Output Leakage Current 1 ±2 uA VCC = VCC Max, VOUT = VCC or GND ISB1 VCC Standby Current 1 15 100 uA VIN = VCC or GND, CS# = VCC ISB2 Deep Power-down Current 3 20 uA VIN = VCC or GND, CS# = VCC 25 mA f=133MHz, (4 x I/O read) SCLK=0.1VCC/0.9VCC, SO=Open 20 mA f=104MHz, (4 x I/O read) SCLK=0.1VCC/0.9VCC, SO=Open 15 mA f=84MHz, SCLK=0.1VCC/0.9VCC, SO=Open 12 20 mA 10 12 mA 1 10 25 mA Erase in Progress, CS#=VCC 1 14 25 mA Erase in Progress, CS#=VCC -0.5 0.8 V 0.7VCC VCC+0.4 V 0.2 V IOL = 100uA V IOH = -100uA ICC1 VCC Read VIL VCC Program Current (PP) VCC Write Status Register (WRSR) Current VCC Sector/Block (32K, 64K) Erase Current (SE/BE/BE32K) VCC Chip Erase Current (CE) Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage ICC2 ICC3 ICC4 ICC5 1 12 1 VCC-0.2 Program in Progress, CS# = VCC Program status register in progress, CS#=VCC Notes : 1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds). 2. Typical value is calculated by simulation. P/N: PM2145 98 REV. 1.1, FEB. 18, 2016 MX25L12845G Table 19. AC CHARACTERISTICS (Temperature = -40°C to 85°C, VCC = 2.7V - 3.6V) Symbol fSCLK fRSCLK fTSCLK Alt. fC fR fT fQ tCH(1) tCLH tCL(1) tCLL (2) tCLCH tCHCL(2) tSLCH tCSS tCHSL tDVCH tDSU tCHDX tDH tCHSH tSHCH tSHSL tSHQZ (2) tCSH tDIS tCLQV tV tCLQX tWHSL(3) tSHWL(3) tDP(2) tHO tRES1 (2) tRES2(2) tW tBP tPP tSE tBE32 tBE tCE tESL(6) tPSL(6) tPRS(7) tERS(8) tQVD(9) P/N: PM2145 Parameter Clock Frequency for all commands (except Read) Clock Frequency for READ instructions Clock Frequency for 2READ instructions Clock Frequency for 4READ instructions Others (fSCLK) Clock High Time Normal Read (fRSCLK) Others (fSCLK) Clock Low Time Normal Read (fRSCLK) Clock Rise Time (peak to peak) Clock Fall Time (peak to peak) CS# Active Setup Time (relative to SCLK) CS# Not Active Hold Time (relative to SCLK) Data In Setup Time Data In Hold Time CS# Active Hold Time (relative to SCLK) CS# Not Active Setup Time (relative to SCLK) Read CS# Deselect Time Write/Erase/Program Output Disable Time Clock Low to Output Valid Loading: 30pF Loading: 30pF/15pF Loading: 15pF Output Hold Time Write Protect Setup Time Write Protect Hold Time CS# High to Deep Power-down Mode CS# High to Standby Mode without Electronic Signature Read CS# High to Standby Mode with Electronic Signature Read Write Status/Configuration Register Cycle Time Byte-Program Page Program Cycle Time Sector Erase Cycle Time Block Erase (32KB) Cycle Time Block Erase (64KB) Cycle Time Chip Erase Cycle Time Erase Suspend Latency Program Suspend Latency Latency between Program Resume and next Suspend Latency between Erase Resume and next Suspend Data Output Valid Time Difference among all SIO pins 99 Min. D.C. Typ. 3.3 7 3.3 7 0.1 0.1 3 3 2 2 3 3 7 30 10 Unit MHz MHz MHz MHz ns ns ns ns V/ns V/ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us 30 us 30 40 30 1.5 400 1000 2000 200 25 25 us ms us ms ms ms ms s us us us us ps 8 8 6 0 20 100 15 0.25 30 180 380 55 0.3 0.3 Max. 120 50 80(5) 80(5) 100 400 600 REV. 1.1, FEB. 18, 2016 MX25L12845G Notes: 1. tCH + tCL must be greater than or equal to 1/ Frequency. 2. Typical values given for TA=25°C. Not 100% tested. 3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. 4. Test condition is shown as "Figure 83. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL" and "Figure 84. OUTPUT LOADING". 5. By default dummy cycle value. Please refer to the "Table 1. Read performance Comparison". 6. Latency time is required to complete Erase/Program Suspend operation until WIP bit is "0". 7. For tPRS, minimum timing must be observed before issuing the next program suspend command. However, a period equal to or longer than the typical timing is required in order for the program operation to make progress. 8. For tERS, minimum timing must be observed before issuing the next erase suspend command. However, a period equal to or longer than the typical timing is required in order for the erase operation to make progress. 9. Not 100% tested. P/N: PM2145 100 REV. 1.1, FEB. 18, 2016 MX25L12845G 13. OPERATING CONDITIONS At Device Power-Up and Power-Down AC timing illustrated in "Figure 85. AC Timing at Device Power-Up" and "Figure 86. Power-Down Sequence" are for the supply voltages and the control signals at device power-up and power-down. If the timing in the figures is ignored, the device will not operate correctly. During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL. Figure 85. AC Timing at Device Power-Up VCC VCC(min) GND tVR tSHSL CS# tSLCH tCHSL tCHSH tSHCH SCLK tDVCH tCHCL tCHDX LSB IN MSB IN SI High Impedance SO Symbol tVR tCLCH Parameter VCC Rise Time Notes 1 Min. 20 Max. 500000 Unit us/V Notes: 1.Sampled, not 100% tested. 2.For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "Table 19. AC CHARACTERISTICS (Temperature = -40°C to 85°C, VCC = 2.7V - 3.6V)". P/N: PM2145 101 REV. 1.1, FEB. 18, 2016 MX25L12845G Figure 86. Power-Down Sequence During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation. VCC CS# SCLK Figure 87. Power-up Timing VCC VCC(max) Chip Selection is Not Allowed VCC(min) tVSL Device is fully accessible VWI time P/N: PM2145 102 REV. 1.1, FEB. 18, 2016 MX25L12845G Figure 88. Power Up/Down and Voltage Drop For Power-down to Power-up operation, the VCC of flash device must below VPWD for at least tPWD timing. Please check the table below for more detail. VCC VCC (max.) Chip Select is not allowed VCC (min.) tVSL Full Device Access Allowed VPWD (max.) tPWD Time Table 20. Power-Up/Down Voltage and Timing Symbol tVSL VWI VPWD tPWD tVR VCC Parameter VCC(min.) to device operation Write Inhibit Voltage VCC voltage needed to below VPWD for ensuring initialization will occur The minimum duration for ensuring initialization will occur VCC Rise Time VCC Power Supply Min. 1200 1.5 300 20 2.7 Max. 2.5 0.9 500000 3.6 Unit us V V us us/V V Note: These parameters are characterized only. 13-1.INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). P/N: PM2145 103 REV. 1.1, FEB. 18, 2016 MX25L12845G 14. ERASE AND PROGRAMMING PERFORMANCE Parameter Min. Typ. (1) Write Status Register Cycle Time Max. (2) Unit 40 ms Sector Erase Cycle Time (4KB) 30 400 ms Block Erase Cycle Time (32KB) 0.18 1 s Block Erase Cycle Time (64KB) 0.38 2 s Chip Erase Cycle Time 55 200 s Byte Program Time (via page program command) 15 30 us 0.25 1.5 ms Page Program Time Erase/Program Cycle 100,000 cycles Note: 1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and all zero pattern. 2. Under worst conditions of 85°C and 2.7V. 3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command. 4. The maximum chip programming time is evaluated under the worst conditions of 0°C, VCC=3.3V, and 100K cycle with 90% confidence level. 15. ERASE AND PROGRAMMING PERFORMANCE (Factory Mode) Parameter Min. Typ. Max. Unit Sector Erase Cycle Time (4KB) 18 ms Block Erase Cycle Time (32KB) 100 ms Block Erase Cycle Time (64KB) 200 ms 45 s 0.16 ms Chip Erase Cycle Time Page Program Time Erase/Program Cycle 50 cycles Notice: 1. Factory Mode must be operated in 20°C to 45°C and VCC 3.0V-3.6V. 2. The Maximum Erase/Program cycles should not exceed 50 cycles. 3. During factory mode, Suspend command (B0) cannot be executed. P/N: PM2145 104 REV. 1.1, FEB. 18, 2016 MX25L12845G 16. DATA RETENTION Parameter Condition Min. Data retention 55˚C 20 Max. Unit years 17. LATCH-UP CHARACTERISTICS Min. Max. Input Voltage with respect to GND on all power pins, SI, CS# -1.0V 2 VCCmax Input Voltage with respect to GND on SO -1.0V VCC + 1.0V -100mA +100mA Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. P/N: PM2145 105 REV. 1.1, FEB. 18, 2016 MX25L12845G 18. ORDERING INFORMATION Please contact our regional sales for the latest product selection and available form factors. PART NO. TEMPERATURE PACKAGE MX25L12845GMI-10G -40°C to 85°C 16-SOP (300mil) MX25L12845GM2I-10G -40°C to 85°C 8-SOP(200mil) MX25L12845GZNI-10G -40°C to 85°C 8-WSON (6x5mm) MX25L12845GMI-08G -40°C to 85°C 16-SOP (300mil) Support Factory Mode MX25L12845GM2I-08G -40°C to 85°C 8-SOP(200mil) Support Factory Mode MX25L12845GZNI-08G -40°C to 85°C 8-WSON (6x5mm) Support Factory Mode P/N: PM2145 106 Remark REV. 1.1, FEB. 18, 2016 MX25L12845G 19. PART NAME DESCRIPTION MX 25 L 12845G M2 I 10 G OPTION: G: RoHS Compliant and Halogen-free SPEED: 10: 104MHz 08: 133MHz TEMPERATURE RANGE: I: Industrial (-40°C to 85°C) PACKAGE: M: 16-SOP (300mil) M2: 8-SOP(200mil) ZN: 8-WSON (6x5mm) DENSITY & MODE: 12845G: 128Mb TYPE: L: 3V DEVICE: 25: Serial NOR Flash P/N: PM2145 107 REV. 1.1, FEB. 18, 2016 MX25L12845G 20. PACKAGE INFORMATION 20-1.16-PIN SOP (300mil) P/N: PM2145 108 REV. 1.1, FEB. 18, 2016 MX25L12845G 20-2.8-pins SOP (200mil) P/N: PM2145 109 REV. 1.1, FEB. 18, 2016 MX25L12845G 20-3.8-land WSON (6x5mm) P/N: PM2145 110 REV. 1.1, FEB. 18, 2016 MX25L12845G 21. REVISION HISTORY Revision No.Description 1.0 1. Content correction 2. Removed "ADVANCED INFORMATION" to align with product status 3. Updated Max. ISB1, Typ. Block/Chip Erase cycle time and Typ. Byte Program Time 4. Added Preamble Bit 5. Updated SFDP tables 6. Added DPB and USPB, GBLK and GBULK information to Advanced Sector Protection chapter 7. Added tQVD parameter and updated Output Timing (DTR mode) figure. Page P4,8,69,72,96 All P84-85,95-96 P101 P32,48-51 P79-91 P13,18,21 67,73-74 P98-99 P14 1. Added MX25L12845GMI-08G, MX25L12845GM2I-08G and P106,107 1.1 MX25L12845GZNI-08G Part No. 2. Added Factory Mode information P17,22-23,104 3. Added a statement for product ordering information P106 P/N: PM2145 111 Date JUN/05/2015 FEB/18/2016 REV. 1.1, FEB. 18, 2016 MX25L12845G Except for customized products which has been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or distributors shall be released from any and all liability arisen therefrom. Copyright© Macronix International Co., Ltd. 2014~2016. All rights reserved, including the trademarks and tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Audio, Rich Book, Rich TV, and FitCAM. The names and brands of third party referred thereto (if any) are for identification purposes only. For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 112