NB4N855S D

NB4N855S
3.3 V, 1.5 Gb/s Dual
AnyLevel™ to LVDS
Receiver/Driver/Buffer/
Translator
Description
NB4N855S is a clock or data Receiver/Driver/Buffer/Translator
capable of translating AnyLevel input signal (LVPECL, CML, HSTL,
LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the distance,
noise immunity of the system design, and transmission line media, this
device will receive, drive or translate data or clock signals up to
1.5 Gb/s or 1.0 GHz, respectively. This device is pin−for−pin plug in
compatible to the SY55855V in a 3.3 V applications.
The NB4N855S has a wide input common mode range of
GND + 50 mV to VCC − 50 mV. This feature is ideal for translating
differential or single−ended data or clock signals to 350 mV typical
LVDS output levels.
The device is offered in a small 10 lead MSOP package. NB4N855S
is targeted for data, wireless and telecom applications as well as high
speed logic interface where jitter and package size are main
requirements.
Application notes, models, and support documentation are available
at www.onsemi.com.
http://onsemi.com
MARKING
DIAGRAM*
10
1
Micro−10
M SUFFIX
CASE 846B
A
Y
W
G
855S
AYWG
G
1
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Features
•
•
•
•
•
•
•
•
•
Guaranteed Input Clock Frequency up to 1.0 GHz
Guaranteed Input Data Rate up to 1.5 Gb/s
490 ps Maximum Propagation Delay
1.0 ps Maximum RMS Jitter
180 ps Maximum Rise/Fall Times
Single Power Supply; VCC = 3.3 V ±10%
Temperature Compensated TIA/EIA−644 Compliant LVDS Outputs
GND + 50 mV to VCC − 50 mV VCMR Range
This is a Pb−Free Device
D0
Q0
D0
Q0
D1
Q1
D1
Q1
VOLTAGE (50 mV/div)
Functional Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
Device DDJ = 7 ps
TIME (133 ps/div)
Figure 1. Typical Output Waveform at 1.5 Gb/s with K28.5
(VINPP = 100 mV, Input Signal DDJ = 24 ps)
© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 4
1
Publication Order Number:
NB4N855S/D
NB4N855S
D0
1
10
D0
2
9
Q0
D1
3
8
Q0
D1
4
7
Q1
GND
5
6
Q1
VCC
Figure 2. Pin Configuration and Block Diagram
(Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
D0
LVPECL, CML, LVCMOS,
LVTTL, LVDS
Noninverted Differential Clock/Data D0 Input.
2
D0
LVPECL, CML, LVCMOS,
LVTTL, LVDS
Inverted Differential Clock/Data D0 Input.
3
D1
LVPEL, CML, LVDS LVCMOS,
LVTTL
4
D1
LVPECL, CML, LVDS
LVCMOS LVTTL
5
GND
−
6
Q1
LVDS Output
Inverted Q1 output. Typically loaded with 100 W receiver termination
resistor across differential pair.
7
Q1
LVDS Output
Noninverted Q1 output. Typically loaded with 100 W receiver termination
resistor across differential pair.
8
Q0
LVDS Output
Inverted Q0 output. Typically loaded with 100 W receiver termination
resistor across differential pair.
9
Q0
LVDS Output
Noninverted Q0 output. Typically loaded with 100 W receiver termination
resistor across differential pair.
10
VCC
−
Noninverted Differential Clock/Data D1 Input.
Inverted Differential Clock/Data D1 Input.
Ground. 0 V.
Positive Supply Voltage.
http://onsemi.com
2
NB4N855S
Table 2. ATTRIBUTES
Characteristics
Value
Moisture Sensitivity (Note 1)
Micro−10
Pb Pkg
Pb−Free Pkg
Level 1
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 200 V
> 1 kV
Transistor Count
281
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
VCC
Positive Power Supply
GND = 0 V
VI
Positive Input
GND = 0 V
IOSC
Output Short Circuit Current
Line−to−Line (Q to Q)
Line−to−End (Q or Q to GND)
Q to Q
Q or Q to GND
TA
Operating Temperature Range
Micro−10
Tstg
Storage Temperature Range
qJA
Thermal Resistance (Junction−to−Ambient) (Note 2)
0 lfpm
500 lfpm
qJC
Thermal Resistance (Junction−to−Case)
1S2P (Note 4)
Tsol
Wave Solder
Pb
Pb−Free
<3 Sec @ 248°C
<3 Sec @ 260°C
Condition 2
Rating
Unit
3.8
V
VI = VCC
3.8
V
Continuous
Continuous
12
24
mA
−40 to +85
°C
−65 to +150
°C
Micro−10
Micro−10
177
132
°C/W
°C/W
Micro−10
40
°C/W
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board − 1S2P (1 signal, 2 power).
http://onsemi.com
3
NB4N855S
Table 4. DC CHARACTERISTICS, CLOCK INPUTS, LVDS OUTPUTS VCC = 3.0 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C
Symbol
ICC
Characteristic
Min
Power Supply Current (Note 3)
Typ
Max
Unit
40
53
mA
DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Figures 10 and 12)
Vth
Input Threshold Reference Voltage Range (Note 4)
GND +100
VCC − 100
mV
VIH
Single−ended Input HIGH Voltage
Vth + 100
VCC
mV
VIL
Single−ended Input LOW Voltage
GND
Vth − 100
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 11 and 13)
VIHD
Differential Input HIGH Voltage
100
VCC
mV
VILD
Differential Input LOW Voltage
GND
VCC − 100
mV
VCMR
Input Common Mode Range (Differential Configuration)
GND + 50
VCC − 50
mV
VID
Differential Input Voltage (VIHD − VILD)
100
VCC
mV
450
mV
25
mV
1375
mV
1.0
25
mV
1425
1600
mV
LVDS OUTPUTS (Note 5)
VOD
Differential Output Voltage
DVOD
Change in Magnitude of VOD for Complementary Output States (Note 6)
250
VOS
Offset Voltage (Figure 9)
DVOS
Change in Magnitude of VOS for Complementary Output States (Note 6)
VOH
Output HIGH Voltage (Note 7)
VOL
Output LOW Voltage (Note 8)
0
1.0
1125
0
900
1075
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Dx/Dx at the DC level within VCMR and output pins loaded with RL = 100 W across differential.
4. Vth is applied to the complementary input when operating in single−ended mode.
5. LVDS outputs require 100 W receiver termination resistor between differential pair. See Figure 8.
6. Parameter guaranteed by design verification not tested in production.
7. VOHmax = VOSmax + ½ VODmax.
8. VOLmax = VOSmin − ½ VODmax.
http://onsemi.com
4
NB4N855S
Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V; (Note 9)
−40°C
Characteristic
VOUTPP
Output Voltage Amplitude (@ VINPPMIN) fin ≤ 1.0 GHz
(Figure 3)
fin= 1.5 GHz
230
200
350
300
230
200
350
300
230
200
350
300
mV
fDATA
Maximum Operating Data Rate
1.5
2.5
1.5
2.5
1.5
2.5
Gb/s
tPLH,
tPHL
Differential Input to Differential Output
Propagation Delay
330
410
490
330
410
490
330
410
490
ps
tSKEW
Duty Cycle Skew (Note 10)
Within −Device Skew (Note 11)
Device to Device Skew (Note 12)
8
10
20
45
35
100
8
10
20
45
35
100
8
10
20
45
35
100
ps
tJITTER
RMS Random Clock Jitter (Note 13)
0.5
0.5
6
7
10
20
1
1
15
20
25
40
0.5
0.5
6
7
10
20
1
1
15
20
25
40
0.5
0.5
6
7
10
20
1
1
15
20
25
40
Deterministic Jitter (Note 14)
Crosstalk Induced Jitter (Note 15)
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 16)
tr
tf
Output Rise/Fall Times @ 250 MHz
(20% − 80%)
100
Q, Q
50
110
Max
Min
Typ
85°C
Symbol
fin = 1.0 GHz
fin = 1.5 GHz
fDATA = 622 Mb/s
fDATA = 1.5 Gb/s
fDATA = 2.488 Gb/s
Typ
25°C
Min
VCC−
GND
100
180
50
Max
Min
Typ
VCC−
GND
100
180
50
110
110
Max
Unit
ps
VCC−
GND
mV
180
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. Measured by forcing VINPPMIN with 50% duty cycle clock source and VCC − 1400 mV offset. All loading with an external RL = 100 W across
“D” and “D” of the receiver. Input edge rates 150 ps (20%−80%).
10. See Figure 7 differential measurement of tskew = |tPLH − tPHL| for a nominal 50% differential clock input waveform @ 250 MHz.
11. The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition.
12. Skew is measured between outputs under identical transition @ 250 MHz.
13. RMS jitter with 50% Duty Cycle clock signal.
14. Deterministic jitter with input NRZ data at PRBS 223−1 and K28.5.
15. Crosstalk Induced Jitter is the additive Deterministic jitter to channel one with channel two active both running at 622 Gb/s PRBS 223 −1 as
an asynchronous signals.
16. Input voltage swing is a single−ended measurement operating in differential mode.
OUTPUT VOLTAGE AMPLITUDE (mV)
400
350
300
−40°C
250
85°C
200
25°C
150
100
50
0
0
0.5
1
1.5
2
2.5
INPUT CLOCK FREQUENCY (GHz)
Figure 3. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fin) and Temperature (@ VCC = 3.3 V)
http://onsemi.com
5
3
VOLTAGE (50 mV/div)
VOLTAGE (50 mV/div)
NB4N855S
Device DDJ = 6 ps
Device DDJ = 6 ps
TIME (322 ps/div)
TIME (322 ps/div)
VOLTAGE (50 mV/div)
VOLTAGE (50 mV/div)
Figure 4. Typical Output Waveform at 1.5 Gb/s with 223−1
(VINPP = 100 mV (left) & VINPP = 400 mV (right), Input Signal DDJ = 24 ps)
Device DDJ = 10 ps
Device DDJ = 10 ps
TIME (80 ps/div)
TIME (80 ps/div)
Figure 5. Typical Output Waveform at 2.488 Gb/s with 223−1
(VINPP = 100 mV (left) & VINPP = 400 mV (right), Input Signal DDJ = 30 ps)
RC
RC
1.25 kW
1.25 kW
Dx
1.25 kW
1.25 kW
I
Dx
Figure 6. Input Structure
http://onsemi.com
6
NB4N855S
D
VINPP = VIH(D) − VIL(D)
D
Q
VOUTPP = VOH(Q) − VOL(Q)
Q
tPHL
tPLH
Figure 7. AC Reference Measurement
Q
LVDS
Driver
Device
Zo = 50 W
HI Z Probe
D
100 W
Q
Zo = 50 W
Oscilloscope
D
HI Z Probe
Figure 8. Typical LVDS Termination for Output Driver and Device Evaluation
QN
VOH
VOS
VOD
VOL
QN
Figure 9. LVDS Output
D
VIH
D
Vth
VIL
Vth
D
D
Figure 10. Differential Input Driven
Single−Ended
Figure 11. Differential Inputs Driven
Differentially
VCC
VCC
VIHmax
Vthmax
D
VIL
VILmax
VCMR
Vth
Vthmin
GND
VIH(MAX)
VIH
VINPP = VIHD − VILD
VIL
VIHmin
D
VIH
VILmin
VEE
VIL(MIN)
Figure 13. VCMR Diagram
Figure 12. Vth Diagram
http://onsemi.com
7
NB4N855S
ORDERING INFORMATION
Device
NB4N855SMR4G
Package
Shipping†
Micro−10
(Pb−Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D
http://onsemi.com
8
NB4N855S
PACKAGE DIMENSIONS
Micro−10
CASE 846B−03
ISSUE D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION “A” DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE
BURRS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. DIMENSION “B” DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. 846B−01 OBSOLETE. NEW STANDARD
846B−02
−A−
−B−
K
D 8 PL
0.08 (0.003)
PIN 1 ID
G
0.038 (0.0015)
−T− SEATING
PLANE
M
T B
S
A
S
DIM
A
B
C
D
G
H
J
K
L
C
H
L
J
MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10
0.95
1.10
0.20
0.30
0.50 BSC
0.05
0.15
0.10
0.21
4.75
5.05
0.40
0.70
INCHES
MIN
MAX
0.114
0.122
0.114
0.122
0.037
0.043
0.008
0.012
0.020 BSC
0.002
0.006
0.004
0.008
0.187
0.199
0.016
0.028
SOLDERING FOOTPRINT*
10X
1.04
0.041
0.32
0.0126
3.20
0.126
8X
10X
4.24
0.167
0.50
0.0196
SCALE 8:1
5.28
0.208
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
AnyLevel is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer
purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
http://onsemi.com
9
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NB4N855S/D