NB3N853531E D

NB3N853531E
3.3 V Xtal or
LVTTL/LVCMOS Input 2:1
MUX to 1:4 LVPECL Fanout
Buffer
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Description
The NB3N853531E is a low skew 3.3 V supply 1:4 clock
distribution fanout buffer. An input MUX selects either a
Fundamental Parallel Mode Crystal or a LVCMOS/LVTTL Clock by
using the CLK_SEL pin (HIGH for Crystal, LOW for Clock) with
LVCMOS / LVTTL levels.
The single ended CLK input is translated to four LVPECL Outputs.
Using the crystal input, the NB3N853531E can be a Clock Generator.
A CLK_EN pin can enable or disable the outputs synchronously to
eliminate runt pulses using LVCMOS/LVTTL levels (HIGH to enable
outputs, LOW to disable outputs).
MARKING
DIAGRAM
TSSOP−20
DT SUFFIX
CASE 948E
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
NB3N
531E
ALYWG
G
A
L
Y
W
G
Four Differential 3.3 V LVPECL Outputs
Selectable Crystal or LVCMOS/LVTTL CLOCK Inputs
Up to 266 MHz Clock Operation
Output to Output Skew: 30 ps (Max)
Device to Device Skew 200 ps (Max)
Propagation Delay 1.8 ns (Max)
Operating Range: VCC = 3.3 ±5% V( 3.135 to 3.465 V)
Additive Phase Jitter, RMS: 0.053 ps (Typ)
Synchronous Clock Enable Control
Industrial Temp. Range (−40°C to 85°C)
Pb−Free TSSOP−20 Package
Ambient Operating Temperature Range −40°C to +85°C
These are Pb−Free Devices
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 7 of this data sheet.
CLK_EN
Pullup
D
Q
CLK
Q0
Q0
Pulldown
0
Q1
XTAL_IN
Q1
OSC
1
XTAL_OUT
Q2
Q2
CLK_SEL
Pulldown
Q3
Q3
Figure 1. Simplified Logic Diagram
© Semiconductor Components Industries, LLC, 2012
March, 2012 − Rev. 6
1
Publication Order Number:
NB3N853531E/D
NB3N853531E
VEE
1
20
Q0
CLK_EN
2
19
Q0
CLK_SEL
3
18
VCC
CLK
4
17
Q1
nc
5
16
Q1
XTAL_IN
6
15
Q2
XTAL_OUT
7
14
Q2
nc
8
13
VCC
nc
9
12
Q3
10
11
Q3
VCC
Figure 2. Pinout Diagram (Top View)
Table 1. PIN DESCRIPTION
Open Default
Pin
Name
I/O
Description
1
VEE
2
CLK_EN
LVCMOS /
LVTTL
Pullup
Synchronized Clock Enable when HIGH. When LOW, outputs are
disabled (Qx HIGH, Qx LOW)
3
CLK_SEL
LVCMOS /
LVTTL
Pulldown
Clock Input Select (HIGH selects crystal, LOW selects CLK input)
4
CLK
LVCMOS /
LVTTL
Pulldown
Clock Input. Float open when unused.
5, 8, 9
nc
6
XTAL_IN
Crystal
Crystal Oscillator Input (used with pin 7). Float open when unused.
7
XTAL_OUT
Crystal
Crystal Oscillator Output (used with pin 6). Float open when unused.
10, 13, 18
VCC
11, 14, 16,
19
Q[3:0]
LVPECL
Complement Differential Outputs (See AND8020 for termination)
12, 15, 17,
20
Q[3:0]
LVPECL
True Differential Outputs (See AND8020 for termination)
Negative (Ground) Power Supply pin must be externally connected to
power supply to guarantee proper operation.
No Connect
Positive Power Supply pins must be externally connected to power
supply to guarantee proper operation.
Table 2. FUNCTIONS
Inputs
Outputs
CLK_EN
CLK_SEL
Input Function
Output Function
Qx
Qx
0
0
CLK input selected
Disabled
LOW
HIGH
0
1
Crystal Inputs Selected
Disabled
LOW
HIGH
1
0
CLK input selected
Enabled
CLK0
Invert of
CLK1
1
1
Crystal Inputs Selected
Enabled
CLK1
Invert of
CLK1
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 3.
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2
NB3N853531E
CLK
CLK_EN
Disabled
Enabled
Q[0:3]
Q[0:3]
Figure 3. CLK_EN Timing Diagram
Table 3. ATTRIBUTES (Note 2)
Value
Characteristics
Internal Input Pullup Resistor
50 kW
Internal Input Pulldown Resistor
50 kW
Cin Input Capacitance
4 pF
ESD Protection
Human Body Model
Machine Model
> 2 kV
> 200 V
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2)
Level 1
Flammability Rating
Oxygen Index
UL 94 V−0 @ 0.125 in
28 to 34
Transistor Count
333 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS (Note 3)
Symbol
Parameter
VCC
Supply Voltage
Vin
Input Voltage
Iout
Output Current
Condition 1
Condition 2
Continuous
Surge
TA
Operating Temperature Range, Industrial
Tstg
Storage Temperature Range
θJA
Thermal Resistance (Junction−to−Ambient)
θJC
Thermal Resistance (Junction−to−Case)
Tsol
Wave Solder
Rating
Unit
4.6
V
−0.5 v VI v VCC + 0.5
V
50
100
mA
−40 to v +85
°C
−65 to +150
°C
°C/W
0 lfpm
Single−Layer
PCB (700 mm2,
2 oz)
128
200 lfpm
Multi−Layer
PCB (700 mm2,
2 oz)
94
(Note 4)
TSSOP−20
23 to 41
°C/W
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously.
If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
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NB3N853531E
Table 5. CRYSTAL CHARACTERISTICS AND CONNECTIONS
Parameter
Min
Mode of Oscillation
Typ
Max
Unit
Fundamental Parallel
Frequency
12
40
MHz
Equivalent Series Resistance (ESR)
50
W
Shunt Capacitance
7
pF
Drive Level
1
mW
Max
Unit
60
mA
Table 6. DC CHARACTERISTICS VCC = 3.3 ±5% V (3.135 to 3.465 V), VEE = 0 V, TA = −40°C to +85°C (Note 5)
Symbol
Characteristic
Min
Typ
IEE
Power Supply Current
VIH
Input HIGH Voltage
2
VCC + 0.3
V
VIL
Input LOW Voltage
−0.3
0.8
V
IIH
Input High Current (VCC = 3.456 V)
CLK, CLK_SEL = 3.456 V
CLK_EN = 3.456 V
150
5
mA
IIL
Input LOW Current (VCC = 3.456 V)
CLK, CLK_SEL = 3.456 V
CLK_EN = 3.456 V
−5
−150
mA
VOH
Output HIGH Voltage
VCC − 1.4
VCC − 0.9
V
VOL
Output LOW Voltage
VCC − 2.0
VCC − 1.7
V
0.6
1.0
V
VOUTSWING
Output Voltage Swing (peak−to−peak)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Outputs terminated 50 W to VCC − 2.0 V, see Figure 4.
Table 7. AC CHARACTERISTICS VCC = 3.3 ±5% V (3.135 to 3.465 V), VEE = 0 V, TA = −40°C to +85°C (Note 6)
Characteristic
Symbol
FMAX
Min
Max
Unit
0
266
MHz
Propagation Delay (Notes 7 and 9)
1.1
1.8
ns
tSKEWDC
Duty Cycle Skew same path similar conditions at 50 MHz (Notes 7, 8 and 9)
46
54
%
tSKEWO−O
Output to Output Skew Within A Device (Notes 7, 8 and 9)
30
ps
tSKEWD−D
Device to Device Skew similar path and conditions (Notes 7, 8 and 9)
200
ps
tPD
Maximum Operating Frequency
Typ
tJIT
Additive Phase Noise Jitter (RMS) @ 155.52 MHz (Integrated from 12 kHz to
20 MHz) See Figure 6. (Note 9)
tr/tf
Output rise and fall times (20% and 80% points) (Note 9)
0.053
225
ps
600
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Outputs terminated 50 W to VCC − 2.0 V, see Figure 4.
7. Measured under the same supply voltage, output loading, and input conditions.
8. Similar conditions.
9. Limits do not apply to overdriving XTAL_IN.
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NB3N853531E
2V
Qx
VCC
Zo = 50 W
50 W
LVPECL
Qx
Zo = 50 W
VEE
50 W
−1.3 ± 0.165 V
Figure 4. Typical Test Setup and Termination for Evaluation. A split supply of VCC = 2.0 V and VEE = −1.3 +0.165 V
allows a convenient direct connection termination into typical oscilloscope 50 W to GND impedance modules.
For Application termination schemes see AND8020.
VCC/2
Input
VCC/2
tPD
tPW
Output
tPD
80% 80%
Output
20%
tPeriod
tSKEW DC % + ǒt PWńt PeriodǓ
20%
tF
tR
Duty Cycle Skew − tSKEWDC
Propagation Delay tPD
Input
Input
CLKx
Part #1
Output
tSKEW0−0
tSKEW0−0
tSKEWD−D
tSKEWD−D
Part #2
Output
CLKy
Output−to−Output Skew tSKEW0−0
Device−to−Device Skew, tSKEWD−D
Figure 5. AC Measurement Reference
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100
NB3N853531E
NB3N853531E
Source Generator
Figure 6. For 155.52 MHz Carrier, the NB3N853531E Additive Phase Noise (dBc/Hz) verses SSB Offset Frequency
(Hz) Integrated Jitter from 12 kHz to 20 MHz (Upper Heavy Line) is 88.1 fs RMS. The E8663B Source Generator
Additive Phase Noise (Lower Light Line) is 70.1 fs RMS. Where tJIT = /(tJIToutput)2 − (tJITinput)2 = 53 fs
Application − Crystal Input Interface
Figure 7 shows the NB3N853531E device crystal
oscillator interface using a typical parallel resonant crystal.
A parallel crystal with loading capacitance CL = 18 pF could
use Series Load Caps C1 = 32 pF and C2 = 32 pF as nominal
values, after subtracting a typical 4 pF of stray cap per line.
The frequency accuracy and duty cycle skew can be fine
tuned by adjusting the C1 and C2 values. For example,
increasing the C1 and C2 values will reduce the operational
frequency. Note R1 is optional and may be 0 W.
32 pF
C1
XTAL_IN/CLK
X1 18 pF
Parallel Resonant
Crystal
32 pF
C2
R1*
XTAL_OUT
Figure 7. NB3N853531E Crystal Oscillator Interface
*R1 is optional. Assuming 4 pF stray cap per pin.
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NB3N853531E
Figure 8. NB3N853531E Phase Noise with 25 MHz Crystal
ORDERING INFORMATION
Package
Shipping†
NB3N853531EDTG
TSSOP−20
(Pb−Free)
75 Units / Rail
NB3N853531EDTR2G
TSSOP−20
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NB3N853531E
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
20X
0.15 (0.006) T U
2X
L
0.10 (0.004)
S
L/2
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
K REF
20
M
T U
S
V
K
K1
S
J J1
11
B
−U−
PIN 1
IDENT
SECTION N−N
0.25 (0.010)
N
1
10
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
G
D
0.100 (0.004)
−T− SEATING
H
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SOLDERING FOOTPRINT*
PLANE
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
NB3N853531E
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent
rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.
Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries,
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or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an
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For additional information, please contact your local
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NB3N853531E/D