Data Sheet

TDA8932B
Class-D audio amplifier
Rev. 04 — 18 December 2008
Product data sheet
1. General description
The TDA8932B is a high efficiency class-D amplifier with low power dissipation.
The continuous time output power is 2 × 15 W in stereo half-bridge application (RL = 4 Ω)
or 1 × 30 W in mono full-bridge application (RL = 8 Ω). Due to the low power dissipation
the device can be used without any external heat sink when playing music. Due to the
implementation of thermal foldback, even for high supply voltages and/or lower load
impedances, the device continues to operate with considerable music output power
without the need for an external heat sink.
The device has two full-differential inputs driving two independent outputs. It can be used
in a mono full-bridge configuration (BTL) or in a stereo half-bridge configuration (SE).
2. Features
Operating voltage from 10 V to 36 V asymmetrical or ±5 V to ±18 V symmetrical
Mono-bridged tied load (full-bridge) or stereo single-ended (half-bridge) application
Application without heat sink using thermally enhanced small outline package
High efficiency and low-power dissipation
Thermally protected and thermal foldback
Current limiting to avoid audio holes
Full short-circuit proof across load and to supply lines (using advanced current
protection)
n Switchable internal or external oscillator (master-slave setting)
n No pop noise
n Full-differential inputs
n
n
n
n
n
n
n
3. Applications
n
n
n
n
n
n
Flat panel television sets
Flat panel monitor sets
Multimedia systems
Wireless speakers
Mini and micro systems
Home sound sets
TDA8932B
NXP Semiconductors
Class-D audio amplifier
4. Quick reference data
Table 1.
Quick reference data
VP = 22 V; fosc = 320 kHz; Tamb = 25 °C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VP
supply voltage
asymmetrical supply
10
22
36
V
IP
supply current
Sleep mode
-
145
195
µA
Iq(tot)
total quiescent
current
Operating mode; no load, no
snubbers and no filter
connected
-
40
50
mA
13.8
15.3
-
W
14.0
15.5
-
W
23.8
26.5
-
W
15.5
17.2
-
W
28.9
32.1
-
W
49.5
55.0
-
W
Stereo SE channel; Rs < 0.1 Ω[1]
Po(RMS)
RMS output power
continuous time output power
per channel;
THD+N = 10 %; fi = 1 kHz
RL = 4 Ω; VP = 22 V
RL = 8 Ω; VP = 30 V
short time output power per
channel; THD+N = 10 %;
fi = 1 kHz
[2]
RL = 4 Ω; VP = 29 V
Mono BTL; Rs < 0.1
Po(RMS)
Ω[1]
RMS output power
continuous time output power;
THD+N = 10 %; fi = 1 kHz
RL = 4 Ω; VP = 12 V
RL = 8 Ω; VP = 22 V
short time output power;
THD+N = 10 %; fi = 1 kHz
RL = 8 Ω; VP = 29 V
[2]
[1]
Output power is measured indirectly; based on RDSon measurement.
[2]
Two layer application board (55 mm × 45 mm), 35 µm copper, FR4 base material in free air with natural
convection.
5. Ordering information
Table 2.
Ordering information
Type number
TDA8932BT
Package
Name
Description
Version
SO32
plastic small outline package; 32 leads;
body width 7.5 mm
SOT287-1
TDA8932BTW HTSSOP32 plastic thermal enhanced thin shrink small outline
package; 32 leads; body width 6.1 mm; lead pitch
0.65 mm; exposed die pad
TDA8932B_4
Product data sheet
SOT549-1
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
2 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
6. Block diagram
OSCREF
OSCIO
10
VDDA
31
8
28
IN1P
2
OSCILLATOR
29
DRIVER
HIGH
PWM
MODULATOR
VSSD
IN1N
INREF
IN2P
26
DRIVER
LOW
3
21
MANAGER
12
20
15
DRIVER
HIGH
PWM
MODULATOR
IN2N
27
CTRL
22
CTRL
23
DRIVER
LOW
14
PROTECTIONS:
OVP, OCP, OTP,
UVP, TF, WP
VDDP1
OUT1
VSSP1
BOOT2
VDDP2
OUT2
VSSP2
VDDA
STABILIZER 11 V
DIAG
BOOT1
4
25
STAB1
VSSP1
VDDA
STABILIZER 11 V
CGND
POWERUP
7
6
REGULATOR 5 V
18
DREF
VSSD
5
VDDA
11
30
TEST
STAB2
VSSP2
MODE
ENGAGE
24
VSSA
TDA8932B
13
19
HVPREF
HVP1
HVP2
HALF SUPPLY VOLTAGE
9
1, 16, 17, 32
001aaf597
VSSA
Fig 1.
VSSD(HW)
Block diagram
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
3 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
7. Pinning information
7.1 Pinning
VSSD(HW)
1
IN1P
2
32 VSSD(HW)
31 OSCIO
VSSD(HW)
1
IN1P
2
32 VSSD(HW)
31 OSCIO
IN1N
3
30 HVP1
IN1N
3
30 HVP1
DIAG
4
DIAG
4
ENGAGE
5
29 VDDP1
28 BOOT1
ENGAGE
5
29 VDDP1
28 BOOT1
POWERUP
6
27 OUT1
POWERUP
6
27 OUT1
CGND
7
CGND
7
VDDA
8
26 VSSP1
25 STAB1
VDDA
8
26 VSSP1
25 STAB1
VSSA
9
24 STAB2
VSSA
9
OSCREF 10
23 VSSP2
OSCREF 10
HVPREF 11
22 OUT2
HVPREF 11
TDA8932BT
TDA8932BTW
23 VSSP2
22 OUT2
INREF 12
21 BOOT2
INREF 12
21 BOOT2
TEST 13
TEST 13
IN2N 14
20 VDDP2
19 HVP2
IN2N 14
20 VDDP2
19 HVP2
IN2P 15
18 DREF
IN2P 15
18 DREF
17 VSSD(HW)
VSSD(HW) 16
17 VSSD(HW)
VSSD(HW) 16
001aaf598
Fig 2.
24 STAB2
001aaf599
Pin configuration SO32
Fig 3.
Pin configuration HTSSOP32
7.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
VSSD(HW)
1
negative digital supply voltage and handle wafer connection
IN1P
2
positive audio input for channel 1
IN1N
3
negative audio input for channel 1
DIAG
4
diagnostic output; open-drain
ENGAGE
5
engage input to switch between Mute mode and Operating mode
POWERUP
6
power-up input to switch between Sleep mode and Mute mode
CGND
7
control ground; reference for POWERUP, ENGAGE and DIAG
VDDA
8
positive analog supply voltage
VSSA
9
negative analog supply voltage
OSCREF
10
input internal oscillator setting (only master setting)
HVPREF
11
decoupling of internal half supply voltage reference
INREF
12
decoupling for input reference voltage
TEST
13
test signal input; for testing purpose only
IN2N
14
negative audio input for channel 2
IN2P
15
positive audio input for channel 2
VSSD(HW)
16
negative digital supply voltage and handle wafer connection
VSSD(HW)
17
negative digital supply voltage and handle wafer connection
DREF
18
decoupling of internal (reference) 5 V regulator for logic supply
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
4 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
Table 3.
Pin description …continued
Symbol
Pin
Description
HVP2
19
half supply output voltage 2 for charging single-ended capacitor for
channel 2
VDDP2
20
positive power supply voltage for channel 2
BOOT2
21
bootstrap high-side driver channel 2
OUT2
22
PWM output channel 2
VSSP2
23
negative power supply voltage for channel 2
STAB2
24
decoupling of internal 11 V regulator for channel 2 drivers
STAB1
25
decoupling of internal 11 V regulator for channel 1 drivers
VSSP1
26
negative power supply voltage for channel 1
OUT1
27
PWM output channel 1
BOOT1
28
bootstrap high-side driver channel 1
VDDP1
29
positive power supply voltage for channel 1
HVP1
30
half supply output voltage 1 for charging single-ended capacitor for
channel 1
OSCIO
31
oscillator input in slave configuration or oscillator output in master
configuration
VSSD(HW)
32
negative digital supply voltage and handle wafer connection
Exposed die
pad
-
HTSSOP32 package only[1]
[1]
The exposed die pad has to be connected to VSSD(HW).
8. Functional description
8.1 General
The TDA8932B is a mono full-bridge or stereo half-bridge audio power amplifier using
class-D technology. The audio input signal is converted into a Pulse Width Modulated
(PWM) signal via an analog input stage and PWM modulator. To enable the output power
Diffusion Metal Oxide Semiconductor (DMOS) transistors to be driven, this digital PWM
signal is applied to a control and handshake block and driver circuits for both the high side
and low side. A 2nd-order low-pass filter converts the PWM signal to an analog audio
signal across the loudspeakers.
The TDA8932B contains two independent half-bridges with full differential input stages.
The loudspeakers can be connected in the following configurations:
• Mono full-bridge: Bridge Tied Load (BTL)
• Stereo half-bridge: Single-Ended (SE)
The TDA8932B contains common circuits to both channels such as the oscillator, all
reference sources, the mode functionality and a digital timing manager. The following
protections are built-in: thermal foldback, temperature, current and voltage protections.
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
5 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
8.2 Mode selection and interfacing
The TDA8932B supports four operating modes, selected using pins POWERUP and
ENGAGE:
• Sleep mode: with low supply current.
• Mute mode: the amplifiers are switching idle (50 % duty cycle), but the audio signal at
the output is suppressed by disabling the Vl-converter input stages. The capacitors on
pins HVP1 and HVP2 have been charged to half the supply voltage (asymmetrical
supply only).
• Operating mode: the amplifiers are fully operational with output signal.
• Fault mode.
Pins POWERUP and ENGAGE are referenced to pin CGND.
Table 4 shows the different modes as a function of the voltages on the POWERUP and
ENGAGE pins.
Table 4.
Mode selection
Mode
Sleep
Mute
Operating
Fault
[1]
Pin
POWERUP
ENGAGE
DIAG
< 0.8 V
< 0.8 V
don’t care
2 V to 6.0
V[1]
2 V to 6.0
V[1]
2.4 V to 6.0
2 V to 6.0
V[1]
don’t care
< 0.8
V[1]
>2V
V[1]
>2V
< 0.8 V
In case of symmetrical supply conditions the voltage applied to pins POWERUP and ENGAGE must never
exceed the supply voltage (VDDA, VDDP1 or VDDP2).
If the transition between Mute mode and Operating mode is controlled via a time constant,
the start-up will be pop free since the DC output offset voltage is applied gradually to the
output between Mute mode and Operating mode. The bias current setting of the
VI-converters is related to the voltage on pin ENGAGE:
• Mute mode: the bias current setting of the VI-converters is zero (VI-converters
disabled)
• Operating mode: the bias current is at maximum
The time constant required to apply the DC output offset voltage gradually between Mute
mode and Operating mode can be generated by connecting a 470 nF decoupling
capacitor to pin ENGAGE.
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
6 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
VP
POWERUP
DREF
HVPREF
HVP1, HVP2
ENGAGE
2.0 V (typical)
1.2 V (typical)
≤ 0.8 V
AUDIO
audio
AUDIO
AUDIO
OUT1, OUT2
PWM
PWM
PWM
DIAG
OSCIO
operating
mute
operating
fault
operating
sleep
001aaf885
Fig 4.
Start-up sequence
8.3 Pulse width modulation frequency
The output of the amplifier is a PWM signal with a carrier frequency of approximately
320 kHz. Using a 2nd-order low-pass filter in the application results in an analog audio
signal across the loudspeaker. The PWM switching frequency can be set by an external
resistor Rosc connected between pins OSCREF and VSSD(HW). The carrier frequency can
be set between 300 kHz and 500 kHz. Using an external resistor of 39 kΩ, the carrier
frequency is set to an optimized value of 320 kHz (see Figure 5).
If two or more TDA8932B devices are used in the same audio application, it is
recommended to synchronize the switching frequency of all devices. This can be realized
by connecting all OSCIO pins together and configure one of the TDA8932B in the
application as clock master, while the other TDA8932B devices are configured in slave
mode.
Pin OSCIO is a 3-state input or output buffer. Pin OSCIO is configured in master mode as
an oscillator output and in slave mode as an oscillator input. Master mode is enabled by
applying a resistor while slave mode is entered by connecting pin OSCREF directly to pin
VSSD(HW) (without any resistor).
The value of the resistor also sets the frequency of the carrier which can be estimated by
the following formula:
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
7 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
9
12.45 × 10
f osc = ---------------------------Rosc
(1)
Where:
fosc = oscillator frequency (Hz)
Rosc = oscillator resistor (on pin OSCREF) (Ω)
001aad758
550
fosc
(kHz)
450
350
250
25
30
35
40
45
Rosc (kΩ)
Fig 5.
Oscillation frequency as a function of resistor Rosc
Table 5 summarizes how to configure the TDA8932B in master or slave configuration.
For device synchronization see Section 14.6 “Device synchronization”.
Table 5.
Master or slave configuration
Configuration
Pin
OSCREF
OSCIO
Master
Rosc > 25 kΩ to VSSD(HW)
output
Slave
Rosc = 0 Ω; shorted to VSSD(HW)
input
8.4 Protection
The following protection is included in the TDA8932B:
•
•
•
•
•
Thermal Foldback (TF)
OverTemperature Protection (OTP)
OverCurrent Protection (OCP)
Window Protection (WP)
Supply voltage protection:
– UnderVoltage Protection (UVP)
– OverVoltage Protection (OVP)
– UnBalance Protection (UBP)
• ElectroStatic Discharge (ESD)
The reaction of the device to the different fault conditions differs per protection.
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
8 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
8.4.1 Thermal Foldback (TF)
If the junction temperature of the TDA8932B exceeds the threshold level (Tj > 140 °C) the
gain of the amplifier is decreased gradually to a level where the combination of dissipation
(P) and the thermal resistance from junction to ambient [Rth(j-a)] results in a junction
temperature around the threshold level.
This means that the device will not completely switch off, but remains operational at lower
output power levels. Especially with music output signals this feature enables high peak
output power while still operating without any external heat sink other than the
printed-circuit board area.
If the junction temperature still increases due to external causes, the OTP shuts down the
amplifier completely.
8.4.2 OverTemperature Protection (OTP)
If the junction temperature Tj > 155 °C, then the power stage will shut down immediately.
8.4.3 OverCurrent Protection (OCP)
When the loudspeaker terminals are short-circuited or if one of the demodulated outputs
of the amplifier is short-circuited to one of the supply lines, this will be detected by the
OCP.
If the output current exceeds the maximum output current (IO(ocp) > 4 A), this current will
be limited by the amplifier to 4 A while the amplifier outputs remain switching (the amplifier
is NOT shutdown completely). This is called current limiting.
The amplifier can distinguish between an impedance drop of the loudspeaker and a
low-ohmic short-circuit across the load or to one of the supply lines. This impedance
threshold depends on the supply voltage used:
• In case of a short-circuit across the load, the audio amplifier is switched off completely
and after approximately 100 ms it will try to restart again. If the short-circuit condition
is still present after this time, this cycle will be repeated. The average dissipation will
be low because of this low duty cycle.
• In case of a short to one of the supply lines, this will trigger the OCP and the amplifier
will be shut down. During restart the window protection will be activated. As a result
the amplifier will not start until 100 ms after the short to the supply lines is removed.
• In case of impedance drop (e.g. due to dynamic behavior of the loudspeaker) the
same protection will be activated. The maximum output current is again limited to 4 A,
but the amplifier will NOT switch off completely (thus preventing audio holes from
occurring). The result will be a clipping output signal without any artifacts.
8.4.4 Window Protection (WP)
The WP checks the PWM output voltage before switching from Sleep mode to Mute mode
(outputs switching) and is activated:
• During the start-up sequence, when pin POWERUP is switched from Sleep mode to
Mute mode. In the event of a short-circuit at one of the output terminals to VDDP1,
VSSP1, VDDP2 or VSSP2 the start-up procedure is interrupted and the TDA8932B waits
for open-circuit outputs. Because the check is done before enabling the power stages,
no large currents will flow in the event of a short-circuit.
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
9 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
• When the amplifier is completely shut down due to activation of the OCP because a
short-circuit to one of the supply lines is made, then during restart (after 100 ms) the
window protection will be activated. As a result the amplifier will not start until the
short-circuit to the supply lines is removed.
8.4.5 Supply voltage protection
If the supply voltage drops below 10 V, the UnderVoltage Protection (UVP) circuit is
activated and the system will shut down directly. This switch-off will be silent and without
pop noise. When the supply voltage rises above the threshold level, the system is
restarted again after 100 ms.
If the supply voltage exceeds 36 V the OverVoltage Protection (OVP) circuit is activated
and the power stages will shut down. It is re-enabled as soon as the supply voltage drops
below the threshold level. The system is restarted again after 100 ms.
It should be noted that supply voltages > 40 V may damage the TDA8932B. Two
conditions should be distinguished:
1. If the supply voltage is pumped to higher values by the TDA8932B application itself
(see also Section 14.3), the OVP is triggered and the TDA8932B is shut down. The
supply voltage will decrease and the TDA8932B is protected against any overstress.
2. If a supply voltage > 40 V is caused by other or external causes, then the TDA8932B
will shut down, but the device can still be damaged since the supply voltage will
remain > 40 V in this case. The OVP protection is not a supply voltage clamp.
An additional UnBalance Protection (UBP) circuit compares the positive analog supply
voltage (VDDA) and the negative analog supply voltage (VSSA) and is triggered if the
voltage difference between them exceeds a certain level. This level depends on the sum
of both supply voltages. The unbalance threshold levels can be defined as follows:
• LOW-level threshold: VP(th)(ubp)l < 8⁄5 × VHVPREF
• HIGH-level threshold: VP(th)(ubp)h > 8⁄3 × VHVPREF
In a symmetrical supply the UBP is released when the unbalance of the supply voltage is
within 6 % of its starting value.
Table 6 shows an overview of all protection and the effect on the output signal.
Table 6.
Protection
Protection overview
Restart
When fault is removed
Every 100 ms
OTP
no
yes
OCP
yes
no
WP
yes
no
UVP
no
yes
OVP
no
yes
UBP
no
yes
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
10 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
8.5 Diagnostic input and output
Whenever a protection other than TF is triggered, pin DIAG is forced LOW level (see
Table 6). An internal reference supply will pull-up the open-drain DIAG output to
approximately 2.4 V. This internal reference supply can deliver approximately 50 µA.
Pin DIAG refers to pin CGND. The diagnostic output signal during different short
conditions is illustrated in Figure 6. Using pin DIAG as input, a voltage < 0.8 V will put the
device into Fault mode.
Vo
Vo
2.4 V
2.4 V
amplifier
restart
0V
≈ 50 ms ≈ 50 ms
no restart
0V
short to
supply line
shorted load
001aad759
Fig 6.
Diagnostic output for different short-circuit conditions
8.6 Differential inputs
For a high common-mode rejection ratio and a maximum of flexibility in the application,
the audio inputs are fully differential. By connecting the inputs anti-parallel, the phase of
one of the two channels can be inverted, so that the amplifier can operate as a mono BTL
amplifier. The input configuration for a mono BTL application is illustrated in Figure 7.
In SE configuration it is also recommended to connect the two differential inputs in
anti-phase. This has advantages for the current handling of the power supply at low signal
frequencies and minimizes supply pumping (see also Section 14.8).
IN1P
OUT1
IN1N
audio
input
IN2P
OUT2
IN2N
001aad760
Fig 7.
Input configuration for mono BTL application
8.7 Output voltage buffers
When pin POWERUP is set HIGH, the half supply output voltage buffers are switched on
in asymmetrical supply configuration. The start-up will be pop free since the device starts
switching when the capacitor on pin HVPREF and the SE capacitors are completely
charged.
Output voltage buffers:
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
11 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
• Pins HVP1 and HVP2: The time required for charging the SE capacitor depends on its
value. The half supply voltage output is disabled when the TDA8932B is used in a
symmetrical supply application.
• Pin HVPREF: This output voltage reference buffer charges the capacitor on pin
HVPREF.
• Pin INREF: This output voltage reference buffer charges the input reference capacitor
on pin INREF. Pin INREF applies the bias voltage for the inputs.
9. Internal circuitry
Table 7.
Internal circuitry
Pin
Symbol
1
VSSD(HW)
16
VSSD(HW)
17
VSSD(HW)
32
VSSD(HW)
Equivalent circuit
1, 16,
17, 32
VDDA
VSSA
001aad784
2
IN1P
3
IN1N
12
INREF
14
IN2N
15
IN2P
VDDA
2 kΩ
± 20 %
2, 15
V/I
48 kΩ
± 20 %
12
HVPREF
48 kΩ
± 20 %
2 kΩ
± 20 %
3, 14
V/I
VSSA
4
001aad785
DIAG
VDDA
2.5 V
50 µA
500 Ω
± 20 %
4
100 kΩ
± 20 %
VSSA
CGND
001aaf607
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
12 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
Table 7.
Internal circuitry …continued
Pin
Symbol
5
ENGAGE
Equivalent circuit
VDDA
2.8 V
Iref = 50 µA
2 kΩ
± 20 %
5
100 kΩ
± 20 %
VSSA
CGND
001aaf608
6
POWERUP
VDDA
6
VSSA
7
CGND
001aad788
CGND
VDDA
7
VSSA
001aad789
8
VDDA
8
VSSA
VSSD
001aad790
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
13 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
Table 7.
Internal circuitry …continued
Pin
Symbol
9
VSSA
Equivalent circuit
VDDA
9
VSSD
001aad791
10
OSCREF
VDDA
Iref
10
VSSA
11
001aad792
HVPREF
VDDA
11
VSSA
13
001aaf604
TEST
VDDA
13
VSSA
001aad795
18
DREF
VDD
18
VSSD
001aag025
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
14 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
Table 7.
Internal circuitry …continued
Pin
Symbol
19
HVP2
30
HVP1
Equivalent circuit
VDDA
19, 30
VSSA
20
VDDP2
23
VSSP2
26
VSSP1
29
VDDP1
001aag026
20, 29
23, 26
001aad798
21
BOOT2
28
BOOT1
21, 28
OUT1, OUT2
001aad799
22
OUT2
27
OUT1
VDDP1,
VDDP2
22, 27
VSSP1,
VSSP2
24
STAB2
25
STAB1
001aag027
VDDA
24, 25
VSSP1,
VSSP2
31
001aag028
OSCIO
DREF
31
VSSD
001aag029
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
15 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
10. Limiting values
Table 8.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
[1]
−0.3
+40
V
IN1P, IN1N, IN2P, IN2N
[2]
−5
+5
V
OSCREF, OSCIO, TEST
[3]
VSSD(HW) − 0.3 5
V
POWERUP, ENGAGE,
DIAG
[4]
VCGND − 0.3
6
V
all other pins
[5]
VSS − 0.3
VDD + 0.3 V
[6]
4
-
VP
supply voltage
Vx
voltage on pin x
asymmetrical supply
IORM
repetitive peak output
current
Tj
junction temperature
-
150
°C
Tstg
storage temperature
−55
+150
°C
Tamb
ambient temperature
−40
+85
°C
P
power dissipation
Vesd
electrostatic discharge
voltage
maximum output
current limiting
A
-
5
W
HBM
[7]
−2000
+2000
V
MM
[8]
−200
+200
V
Unit
[1]
VP = VDDP1 − VSSP1 = VDDP2 − VSSP2.
[2]
Measured with respect to pin INREF; Vx < VDD + 0.3 V.
[3]
Measured with respect to pin VSSD(HW); Vx < VDD + 0.3 V.
[4]
Measured with respect to pin CGND; Vx < VDD + 0.3 V.
[5]
VSS = VSSP1 = VSSP2; VDD = VDDP1 = VDDP2.
[6]
Current limiting concept.
[7]
Human Body Model (HBM); Rs = 1500 Ω; C = 100 pF
For pins 2, 3, 11, 14 and 15 Vesd = ±1800 V.
[8]
Machine Model (MM); Rs = 0 Ω; C = 200 pF; L = 0.75 µH.
11. Thermal characteristics
Table 9.
Symbol
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
SO32 package
Rth(j-a)
thermal resistance from junction
to ambient
Ψj-lead
thermal characterization
parameter from junction to lead
Ψj-top
thermal characterization
parameter from junction to top of
package
free air natural convection
JEDEC test board
[1]
-
41
44
K/W
2 layer application board
[2]
-
44
-
K/W
-
-
30
K/W
-
-
8
K/W
[3]
TDA8932B_4
Product data sheet
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Rev. 04 — 18 December 2008
16 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
Table 9.
Symbol
Thermal characteristics …continued
Parameter
Conditions
Min
Typ
Max
Unit
HTSSOP32 package
Rth(j-a)
thermal resistance from junction
to ambient
Ψj-lead
thermal characterization
parameter from junction to lead
Ψj-top
thermal characterization
parameter from junction to top of
package
Rth(j-c)
thermal resistance from junction
to case
free air natural convection
JEDEC test board
[1]
-
47
50
K/W
2 layer application board
[4]
-
48
-
K/W
-
-
30
K/W
-
-
2
K/W
-
4.0
-
K/W
[3]
free air natural convection
[1]
Measured on a JEDEC high K-factor test board (standard EIA/JESD 51-7) in free air with natural convection.
[2]
Two layer application board (55 mm × 45 mm), 35 µm copper, FR4 base material in free air with natural convection.
[3]
Strongly depends on where the measurement is taken on the package.
[4]
Two layer application board (55 mm × 40 mm), 35 µm copper, FR4 base material in free air with natural convection.
12. Static characteristics
Table 10. Static characteristics
VP = 22 V; fosc = 320 kHz; Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
asymmetrical supply
10
22
36
V
symmetrical supply
±5
±11
±18
V
Supply
VP
IP
supply current
Sleep mode; no load
-
145
195
µA
Iq(tot)
total quiescent current
Operating mode; no load, no
snubbers and no filter connected
-
40
50
mA
Tj = 25 °C
-
150
-
mΩ
Tj = 125 °C
-
234
-
mΩ
0
-
6.0
V
-
1
20
µA
Series resistance output power switches
RDSon
drain-source on-state
resistance
Power-up input: pin
POWERUP[1]
VI
input voltage
II
input current
VIL
LOW-level input voltage
0
-
0.8
V
VIH
HIGH-level input voltage
2
-
6.0
V
2.4
2.8
3.1
V
0
-
6.0
V
VI = 3 V
Engage input: pin ENGAGE[1]
VO
output voltage
VI
input voltage
open pin
IO
output current
-
50
60
µA
VIL
LOW-level input voltage
0
-
0.8
V
VIH
HIGH-level input voltage
2.4
-
6.0
V
VI = 0 V
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
17 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
Table 10. Static characteristics …continued
VP = 22 V; fosc = 320 kHz; Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Diagnostic output: pin
VO
Conditions
Min
Typ
Max
Unit
protection activated; see Table 6
-
-
0.8
V
Operating mode
2
2.5
3.3
V
with respect to pin VSSA
-
2.1
-
V
DIAG[1]
output voltage
Bias voltage for inputs: pin INREF
VO(bias)
bias output voltage
Half supply voltage
Pins HVP1 and HVP2
VO
output voltage
half supply voltage to charge SE
capacitor
0.5VP −
0.2
0.5VP
0.5VP +
0.2
V
IO
output current
VHVP1 = VO − 1 V;
VHVP2 = VO − 1 V
-
50
-
mA
output voltage
half supply reference voltage in
Mute mode
0.5VP −
0.2
0.5VP
0.5VP +
0.2
V
4.5
4.8
5.1
V
Pin HVPREF
VO
Reference voltage for internal logic: pin DREF
VO
output voltage
Amplifier outputs: pins OUT1 and OUT2
|VO(offset)|
output offset voltage
SE; with respect to pin HVPREF
Mute mode
-
-
15
mV
Operating mode
-
-
100
mV
Mute mode
-
-
20
mV
Operating mode
-
-
150
mV
10
11
12
V
BTL
Stabilizer output: pins STAB1 and STAB2
VO
output voltage
Mute mode and Operating mode;
with respect to pins VSSP1 and
VSSP2
Voltage protection
VP(uvp)
undervoltage protection
supply voltage
8.0
9.2
9.9
V
VP(ovp)
overvoltage protection
supply voltage
36.1
37.4
40
V
VP(th)(ubp)l
low unbalance protection
threshold supply voltage
VHVPREF = 11 V
-
-
18
V
VP(th)(ubp)h
high unbalance protection
threshold supply voltage
VHVPREF = 11 V
29
-
-
V
current limiting
4
5
-
A
155
-
160
°C
Current protection
IO(ocp)
overcurrent protection
output current
Temperature protection
Tact(th_prot)
thermal protection activation
temperature
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
18 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
Table 10. Static characteristics …continued
VP = 22 V; fosc = 320 kHz; Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Tact(th_fold)
thermal foldback activation
temperature
Conditions
Min
Typ
Max
Unit
140
-
150
°C
Oscillator reference; pin OSCIO[2]
VIH
HIGH-level input voltage
4.0
-
5
V
VIL
LOW-level input voltage
0
-
0.8
V
VOH
HIGH-level output voltage
4.0
-
5
V
VOL
LOW-level output voltage
0
-
0.8
V
Nslave(max)
maximum number of slaves
12
-
-
-
[1]
Measured with respect to pin CGND.
[2]
Measured with respect to pin VSSD(HW).
driven by one master
13. Dynamic characteristics
Table 11. Switching characteristics
VP = 22 V; Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rosc = 39 kΩ
-
320
-
kHz
range
300
-
500
kHz
Internal oscillator
fosc
oscillator frequency
Timing PWM output: pins OUT1 and OUT2
tr
rise time
IO = 0 A
-
10
-
ns
tf
fall time
IO = 0 A
-
10
-
ns
tw(min)
minimum pulse width
IO = 0 A
-
80
-
ns
Table 12. SE characteristics
VP = 22 V; RL = 2 × 4 Ω; fi = 1 kHz; fosc = 320 kHz; Rs < 0.1 Ω[1]; Tamb = 25 °C; unless otherwise specified.
Symbol
THD+N
Parameter
total harmonic
distortion-plus-noise
Gv(cl)
closed-loop voltage gain
|∆Gv|
voltage gain difference
Conditions
Min
Typ
fi = 1 kHz
-
0.015
0.05
%
fi = 6 kHz
-
0.08
0.10
%
29
30
31
dB
-
0.5
1
dB
70
80
-
dB
fi = 100 Hz
-
60
-
dB
fi = 1 kHz
40
50
-
dB
Po = 1 W
Vi = 100 mV; no load
αcs
channel separation
Po = 1 W; fi = 1 kHz
SVRR
supply voltage rejection ratio
Operating mode
Max
Unit
[2]
[3]
|Zi|
input impedance
differential
70
100
-
kΩ
Vn(o)
output noise voltage
Operating mode; Rs = 0 Ω
[4]
-
100
150
µV
Mute mode
[4]
-
70
100
µV
-
100
-
µV
VO(mute)
mute output voltage
Mute mode; Vi = 1 V (RMS) and
fi = 1 kHz
TDA8932B_4
Product data sheet
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Rev. 04 — 18 December 2008
19 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
Table 12. SE characteristics …continued
VP = 22 V; RL = 2 × 4 Ω; fi = 1 kHz; fosc = 320 kHz; Rs < 0.1 Ω[1]; Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CMRR
common mode rejection ratio
Vi(cm) = 1 V (RMS)
-
75
-
dB
ηpo
output power efficiency
Po = 15 W
VP = 22 V; RL = 4 Ω
90
92
-
%
VP = 30 V; RL = 8 Ω
91
93
-
%
THD+N = 0.5 %; fi = 1 kHz
10.9
12.1
-
W
THD+N = 0.5 %; fi = 100 Hz
-
12.1
-
W
THD+N = 10 %; fi = 1 kHz
13.8
15.3
-
W
THD+N = 10 %; fi = 100 Hz
-
15.3
-
W
THD+N = 0.5 %; fi = 1 kHz
11.1
12.3
-
W
THD+N = 0.5 %; fi = 100 Hz
-
12.3
-
W
THD+N = 10 %; fi = 1 kHz
14.0
15.5
-
W
THD+N = 10 %; fi = 100 Hz
-
15.5
-
W
THD+N = 0.5 %
19.0
21.1
-
W
THD+N = 10 %
23.8
26.5
-
W
Po(RMS)
RMS output power
continuous time output power per
channel
[5]
RL = 4 Ω; VP = 22 V
RL = 8 Ω; VP = 30 V
short time output power per channel
[5]
RL = 4 Ω; VP = 29 V
[1]
Rs is the series resistance of inductor and capacitor of low-pass LC filter in the application.
[2]
THD+N is measured in a bandwidth of 20 Hz to 20 kHz, AES17 brick wall.
[3]
Maximum Vripple = 2 V (p-p); Rs = 0 Ω.
[4]
B = 20 Hz to 20 kHz, AES17 brick wall.
[5]
Output power is measured indirectly; based on RDSon measurement.
Two layer application board (55 mm × 45 mm), 35 µm copper, FR4 base material in free air with natural convection.
Table 13. BTL characteristics
VP = 22 V; RL = 8 Ω; fi = 1 kHz; fosc = 320 kHz; Rs < 0.1 Ω[1]; Tamb = 25 °C; unless otherwise specified.
Symbol
THD+N
Gv(cl)
SVRR
Parameter
total harmonic
distortion-plus-noise
Conditions
Min
Typ
Max
Unit
fi = 1 kHz
-
0.007
0.1
%
fi = 6 kHz
-
0.05
0.1
%
35
36
37
dB
Po = 1 W
closed-loop voltage gain
supply voltage rejection ratio
Operating mode
input impedance
-
75
-
dB
fi = 1000 Hz
70
75
-
dB
-
80
-
dB
35
50
differential
TDA8932B_4
Product data sheet
[3]
fi = 100 Hz
sleep; fi = 100 Hz
|Zi|
[2]
[3]
kΩ
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
20 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
Table 13. BTL characteristics …continued
VP = 22 V; RL = 8 Ω; fi = 1 kHz; fosc = 320 kHz; Rs < 0.1 Ω[1]; Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Vn(o)
output noise voltage
Rs = 0 Ω
Min
Typ
Max
Unit
Operating mode
[4]
-
100
150
µV
Mute mode
[4]
-
70
100
µV
VO(mute)
mute output voltage
Mute mode; Vi = 1 V (RMS) and
fi = 1 kHz
-
100
-
µV
CMRR
common mode rejection ratio
Vi(cm) = 1 V (RMS)
-
75
-
dB
ηpo
output power efficiency
Po = 15 W; VP = 12 V and RL = 4 Ω
88
90
-
%
Po = 30 W; VP = 22 V and RL = 8 Ω
90
92
-
%
Po(RMS)
RMS output power
continuous time output power
[5]
RL = 4 Ω; VP = 12 V
THD+N = 0.5 %; fi = 1 kHz
11.8
13.2
-
W
THD+N = 0.5 %; fi = 100 Hz
-
13.2
-
W
THD+N = 10 %; fi = 1 kHz
15.5
17.2
-
W
THD+N = 10 %; fi = 100 Hz
-
17.2
-
W
THD+N = 0.5 %; fi = 1 kHz
23.1
25.7
-
W
THD+N = 0.5 %; fi = 100 Hz
-
25.7
-
W
THD+N = 10 %; fi = 1 kHz
28.9
32.1
-
W
-
32.1
-
W
THD+N = 0.5 %
18.5
20.6
-
W
THD+N = 10 %
23.9
26.6
-
W
THD+N = 0.5 %
36.0
40.0
-
W
THD+N = 10 %
49.5
55.0
-
W
RL = 8 Ω; VP = 22 V
THD+N = 10 %; fi = 100 Hz
short time output power
[5]
RL = 4 Ω; VP = 15 V
RL = 8 Ω; VP = 29 V
[1]
Rs is the series resistance of inductor and capacitor of low-pass LC filter in the application.
[2]
THD+N is measured in a bandwidth of 20 Hz to 20 kHz, AES17 brick wall.
[3]
Maximum Vripple = 2 V (p-p); Rs = 0 Ω.
[4]
B = 20 Hz to 20 kHz, AES17 brick wall.
[5]
Output power is measured indirectly; based on RDSon measurement.
Two layer application board (55 mm × 45 mm), 35 µm copper, FR4 base material in free air with natural convection.
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
21 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
14. Application information
14.1 Output power estimation
The output power Po at THD+N = 0.5 %, just before clipping, for the SE and BTL
configuration can be estimated using Equation 2 and Equation 3.
SE configuration:
P o ( 0.5% )
2
RL
 --------------------------------------------------------- × (1 – t
×
f
)
×
V
w ( min )
osc
P
 R L + R DSon + R s + R ESR
= -----------------------------------------------------------------------------------------------------------------------------------------8 × RL
(2)
BTL configuration:
P o ( 0.5% )
2
RL
 ---------------------------------------------------- × (1 – t
× f osc ) × V P
w
(
min
)
 R L + 2 × ( R DSon + R s )
= ------------------------------------------------------------------------------------------------------------------------------------2 × RL
(3)
Where:
VP = supply voltage VDDP1 − VSSP1 (V) or VDDP2 − VSSP2 (V)
RL = load impedance (Ω)
RDSon = on-resistance power switch (Ω)
Rs = series resistance output inductor (Ω)
RESR = equivalent series resistance SE capacitor (Ω)
tw(min) = minimum pulse width (s); 80 ns typical
fosc = oscillator frequency (Hz); 320 kHz typical with Rosc = 39 kΩ
The output power Po at THD+N = 10 % can be estimated by:
P o ( 10% ) = 1.25 × P o ( 0.5% )
(4)
Figure 8 and Figure 9 show the estimated output power at THD+N = 0.5 % and
THD+N = 10 % as a function of the supply voltage for SE and BTL configurations at
different load impedances. The output power is calculated with: RDSon = 0.15 Ω (at
Tj = 25 °C), Rs = 0.05 Ω, RESR = 0.05 Ω and IO(ocp) = 4 A (minimum).
TDA8932B_4
Product data sheet
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Rev. 04 — 18 December 2008
22 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
001aad768
40
Po
(W)
RL = 4 Ω
Po
(W)
RL = 4 Ω
30
001aad769
40
30
6Ω
6Ω
20
10
10
0
0
10
20
30
VP (V)
10
40
20
30
40
VP (V)
a. THD+N = 0.5 %
Fig 8.
8Ω
20
8Ω
b. THD+N = 10 %
SE output power as a function of supply voltage
001aad770
80
Po
(W)
001aad771
80
RL = 8 Ω
Po
(W)
RL = 8 Ω
60
60
6Ω
6Ω
40
40
4Ω
4Ω
20
20
0
0
10
20
30
40
10
20
VP (V)
40
VP (V)
a. THD+N = 0.5 %
Fig 9.
30
b. THD+N = 10 %
BTL output power as a function of supply voltage
TDA8932B_4
Product data sheet
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Rev. 04 — 18 December 2008
23 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
14.2 Output current limiting
The peak output current IO(max) is internally limited above a level of 4 A (minimum). During
normal operation the output current should not exceed this threshold level of 4 A
otherwise the output signal is distorted. The peak output current in SE or BTL
configurations can be estimated using Equation 5 and Equation 6.
SE configuration:
0.5 × V P
I O ( max ) ≤ ---------------------------------------------------------- ≤ 4 A
R L + R DSon + R s + R ESR
(5)
BTL configuration:
VP
I O ( max ) ≤ ------------------------------------------------------ ≤ 4 A
R L + 2 × ( R DSon + R s )
(6)
Where:
VP = supply voltage VDDP1 − VSSP1 (V) or VDDP2 − VSSP2 (V)
RL = load impedance (Ω)
RDSon = on-resistance power switch (Ω)
Rs = series resistance output inductor (Ω)
RESR = equivalent series resistance SE capacitor (Ω)
Example:
A 4 Ω speaker in the BTL configuration can be used up to a supply voltage of 18 V without
running into current limiting. Current limiting (clipping) will avoid audio holes but it causes
a comparable distortion like voltage clipping.
14.3 Speaker configuration and impedance
For a flat frequency response (second-order Butterworth filter) it is necessary to change
the low-pass filter components Llc and Clc according to the speaker configuration and
impedance. Table 14 shows the practical required values.
Table 14.
Filter component values
Configuration
RL (Ω)
Llc (µH)
Clc (nF)
SE
4
22
680
6
33
470
8
47
330
4
10
1500
6
15
1000
8
22
680
BTL
14.4 Single-ended capacitor
The SE capacitor forms a high-pass filter with the speaker impedance. So the frequency
response will roll-off with 20 dB per decade below f-3dB (3 dB cut-off frequency).
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
24 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
The 3 dB cut-off frequency is equal to:
1
f –3dB = ----------------------------------2π × R L × Cse
(7)
Where:
f-3dB = 3 dB cut-off frequency (Hz)
RL = load impedance (Ω)
Cse = single-ended capacitance (F); see Figure 36
Table 15 shows an overview of the required SE capacitor values in case of 60 Hz, 40 Hz
or 20 Hz 3 dB cut-off frequency.
Table 15.
SE capacitor values
Impedance (Ω)
Cse (µF)
f-3dB = 60 Hz
f-3dB = 40 Hz
f-3dB = 20 Hz
4
680
1000
2200
6
470
680
1500
8
330
470
1000
14.5 Gain reduction
The gain of the TDA8932B is internally fixed at 30 dB for SE (or 36 dB for BTL). The gain
can be reduced by a resistive voltage divider at the input (see Figure 10).
R1
audio in
470 nF
R3
R2
100
kΩ
470 nF
001aad762
Fig 10. Input configuration for reducing gain
When applying a resistive divider, the total closed-loop gain Gv(tot) can be calculated by
Equation 8 and Equation 9:
R EQ
G v ( tot ) = G v ( cl ) + 20 log -----------------------------------------R EQ + ( R1 + R2 )
(8)
Where:
Gv(tot) = total closed-loop voltage gain (dB)
Gv(cl) = closed-loop voltage gain, fixed at 30 dB for SE (dB)
REQ = equivalent resistance, R3 and Zi (Ω)
R1 = series resistor (Ω)
R2 = series resistor (Ω)
TDA8932B_4
Product data sheet
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Rev. 04 — 18 December 2008
25 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
R3 × Z
R EQ = ------------------i
R3 + Z i
(9)
Where:
REQ = equivalent resistance (Ω)
R3 = parallel resistor (Ω)
Zi = internal input impedance (Ω)
Example:
Substituting R1 = R2 = 4.7 kΩ, Zi = 100 kΩ and R3 = 22 kΩ in Equation 8 and Equation 9
results in a gain of Gv(tot) = 26.3 dB.
14.6 Device synchronization
If two or more TDA8932B devices are used in one application it is recommended that all
devices are synchronized running at the same switching frequency to avoid beat tones.
Synchronization can be realized by connecting all OSCIO pins together and configuring
one of the TDA8932B devices as master, while the other TDA8932B devices are
configured as slaves (see Figure 11).
A device is configured as master when connecting a resistor between pins OSCREF and
VSSD(HW) setting the carrier frequency. Pin OSCIO of the master is then configured as an
oscillator output for synchronization. The OSCREF pins of the slave devices should be
shorted to VSSD(HW) configuring pin OSCIO as an input.
master
slave
IC1
IC2
TDA8932B
TDA8932B
OSCREF VSSD(HW) OSCIO
Cosc
100 nF
OSCIO
VSSD(HW) OSCREF
Rosc
39 kΩ
001aaf600
Fig 11. Master slave concept in two chip application
14.7 Thermal behavior (printed-circuit board considerations)
The TDA8932B is available in two different thermally enhanced packages:
TDA8932BT in a SO32 (SOT287-1) package for reflow and wave solder process
TDA8932BTW in an HTSSOP32 (SOT549-1) package for reflow solder process only
The SO32 package has special thermal corner-leads, increasing the power capability
(reducing the overall Rth(j-a). To benefit from the corner leads pins VSSD(HW) (pins 1, 16, 17
and 32) should be attached to a copper plane. The SO32 package is very suitable for
applications with limited space for a thermal plane (in a single layer PCB design).
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
26 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
The HTSSOP32 package has an exposed die-pad that reduces significantly the overall
Rth(j-a). Therefore it is required to solder the exposed die-pad (at VSSD level) to a copper
plane for cooling. The HTSSOP package will have a low thermal resistance when used on
a multi-layer PCB with sufficient space for one or two thermal planes.
Increasing the area of the thermal plane, the number of planes or the copper thickness
can reduce further the thermal resistance Rth(j-a) of both packages.
Typical thermal resistance Rth(j-a) of the SO32 package soldered at a small 2-layer
application board (55 mm × 45 mm), 35 µm copper, FR4 base material is 44 K/W.
Typical thermal resistance Rth(j-a) of the HTSSOP32 package soldered at a small 2-layer
application board (55 mm × 40 mm), 35 µm copper, FR4 base material is 48 K/W.
Equation 10 shows the relation between the maximum allowable power dissipation P and
the thermal resistance from junction to ambient.
T j ( max ) – T amb
R th ( j – a ) = ----------------------------------P
(10)
Where:
Rth(j-a) = thermal resistance from junction to ambient
Tj(max) = maximum junction temperature
Tamb = ambient temperature
P = power dissipation which is determined by the efficiency of the TDA8932B
The power dissipation is shown in Figure 22 (SE) and Figure 34 (BTL).
The thermal foldback will limit the maximum junction temperature to 140 °C.
14.8 Pumping effects
When the amplifier is used in a SE configuration, a so-called 'pumping effect' can occur.
During one switching interval, energy is taken from one supply (e.g. VDDP1), while a part of
that energy is delivered back to the other supply line (e.g. VSSP1) and visa versa. When
the power supply cannot sink energy, the voltage across the output capacitors of that
power supply will increase.
The voltage increase caused by the pumping effect depends on:
•
•
•
•
•
Speaker impedance
Supply voltage
Audio signal frequency
Value of decoupling capacitors on supply lines
Source and sink currents of other channels
The pumping effect should not cause a malfunction of either the audio amplifier and/or the
power supply. For instance, this malfunction can be caused by triggering of the
undervoltage or overvoltage protection of the amplifier.
Pumping effects in a SE configuration can be minimized by connecting audio inputs in
anti-phase and changing the polarity of one speaker. This is illustrated in Figure 12.
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
27 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
IN1P
audio
in1
OUT1
IN1N
IN2N
audio
in2
OUT2
IN2P
001aad763
Fig 12. SE application for reducing pumping effects
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
28 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
14.9 SE curves measured in reference design
001aad772
102
THD+N
(%)
10
10
1
1
10−1
001aad773
102
THD+N
(%)
(1)
10−1
(1)
(2)
(2)
(3)
10−2
10−3
10−2
10−1
1
10−2
10
102
Po (W/channel)
a. VP = 22 V; RL = 2 × 4 Ω
(3)
10−3
10−2
10−1
1
10
102
Po (W/channel)
b. VP = 30 V; RL = 2 × 8 Ω
(1) fi = 6 kHz
(2) fi = 100 Hz
(3) fi = 1 kHz
Fig 13. Total harmonic distortion-plus-noise as a function of output power per channel
001aad774
102
THD+N
(%)
10
10
1
001aad775
102
THD+N
(%)
1
(1)
(1)
(2)
10−1
10−1
10−2
10−2
10−3
10
102
103
104
105
(2)
10−3
10
102
103
fi (Hz)
a. VP = 22 V; RL = 2 × 4 Ω
104
105
fi (Hz)
b. VP = 30 V; RL = 2 × 8 Ω
(1) Po = 10 W
(2) Po = 1 W
Fig 14. Total harmonic distortion-plus-noise as a function of frequency
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
29 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
001aad776
40
001aad777
0
SVRR
(dB)
Gv
(dB)
−20
30
−40
(1)
−60
(2)
20
(1)
(2)
−80
10
10
102
103
104
105
−100
10
102
103
104
Vi = 100 mV (RMS); Ri = 0 Ω; Cse = 1000 µF
(1) VP = 30 V; RL = 2 × 8 Ω
Vripple = 500 mV (RMS) referenced to ground; Ri = 0 Ω
(shorted input)
(1) VP = 30 V; RL = 2 × 8 Ω
(2) VP = 22 V; RL = 2 × 4 Ω
(2) VP = 22 V; RL = 2 × 4 Ω
Fig 15. Gain as a function of frequency
Fig 16. Supply voltage ripple rejection as a function of
frequency
001aad778
120
S/N
(dB)
105
fi (Hz)
fi (Hz)
001aad779
0
αcs
(dB)
(2)
−20
(1)
80
−40
−60
40
−80
0
10−2
10−1
1
10
102
Po (W/channel)
Ri = 0 Ω; 20 kHz brick-wall filter AES17
(1)
(2)
−100
10
102
103
105
fi (Hz)
Po = 1 W; CHVPREF = 47 µF
(1) VP = 22 V; RL = 2 × 4 Ω
(1) VP = 22 V; RL = 2 × 4 Ω
(2) VP = 30 V; RL = 2 × 8 Ω
(2) VP = 30 V; RL = 2 × 8 Ω
Fig 17. Signal-to-noise ratio as a function of output
power per channel
Fig 18. Channel separation as a function of frequency
TDA8932B_4
Product data sheet
104
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
30 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
001aaf886
32
Po
(W/channel)
(1)
24
001aaf889
6
P
(W)
(2)
(1)
4
16
(3)
(4)
2
(2)
8
0
0
10
14
18
22
26
30
10
34
38
VP (V)
fi = 1 kHz (short time PO); dashed line will require heat
sink for continuous time output power
(1) RL = 2 × 4 Ω; THD+N = 10 %
14
18
22
26
30
34
38
VP (V)
fi = 1 kHz; power dissipation in junction only; short time
Po at THD+N = 10 %; dashed line will require heat sink
for continuous time output power
(1) RL = 2 × 4 Ω
(2) RL = 2 × 4 Ω; THD+N = 0.5 %
(2) RL = 2 × 8 Ω
(3) RL = 2 × 8 Ω; THD+N = 10 %
(4) RL = 2 × 8 Ω; THD+N = 0.5 %
Fig 19. Output power per channel as a function of
supply voltage
001aad780
100
Fig 20. Power dissipation as a function of supply
voltage
001aad781
3.0
(2)
ηpo
(%)
(1)
P
(W)
80
2.0
60
(2)
(1)
40
1.0
20
0
0
5
10
15
20
Po (W/channel)
2 × Po
0
10−2
10−1
1
10
102
Po (W/channel)
fi = 1 kHz; power dissipation in junction only
fi = 1 kHz; η PO = ------------------------2 × Po + p
(1) VP = 22 V; RL = 2 × 4 Ω
(2) VP = 30 V; RL = 2 × 8 Ω
(1) VP = 22 V; RL = 2 × 4 Ω
(2) VP = 30 V; RL = 2 × 8 Ω
Fig 21. Output power efficiency as a function of
output power per channel
Fig 22. Power dissipation as a function of output
power per channel (two channels driven)
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
31 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
001aaf887
32
Po
(W/channel)
Po
(W/channel)
(3)
24
001aaf888
32
24
(2)
(2)
16
16
(1)
(1)
8
8
0
0
0
120
240
360
480
600
0
120
240
360
480
t (s)
a. RL = 2 × 4 Ω; fi = 1 kHz; 2 layer SO32 application
board (55 mm × 45 mm) without heat sink
600
t (s)
b. RL = 2 × 8 Ω; fi = 1 kHz; 2 layer SO32 application
board (55 mm × 45 mm) without heat sink
(1) VP = 22 V
(1) VP = 30 V
(2) VP = 26 V
(2) VP = 34 V
(3) VP = 29 V
Fig 23. Output power per channel as a function of time
001aaf890
4
Vo
(V)
001aaf891
4
Vo
(V)
3
3
operating
2
2
1
1
sleep
0
0
0.5
operating
mute
0
1
1.5
2
2.5
3
VPOWERUP (V)
Vi = 100 mV (RMS value); fi = 1 kHz; VENGAGE > 3 V
Fig 24. Output voltage as a function of voltage on pin
POWERUP
0
1
1.5
2
2.5
3
VENGAGE (V)
Vi = 100 mV (RMS value); fi = 1 kHz; VPOWERUP > 2 V
Fig 25. Output voltage as a function of voltage on pin
ENGAGE
TDA8932B_4
Product data sheet
0.5
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
32 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
14.10 BTL curves measured in reference design
001aad782
102
THD+N
(%)
10
10
1
1
(1)
10−1
001aad783
102
THD+N
(%)
10−1
(1)
(2)
(3)
10−2
10−2
(2)
(3)
10−3
10−2
10−1
1
102
10
10−3
10−2
10−1
1
102
10
Po (W)
Po (W)
a. VP = 12 V; RL = 4 Ω
b. VP = 22 V; RL = 8 Ω
(1) fi = 6 kHz
(2) fi = 1 kHz
(3) fi = 100 Hz
Fig 26. Total harmonic distortion-plus-noise as a function of output power
001aae114
102
001aae115
102
THD+N
(%)
THD+N
(%)
10
10
1
1
10−1
10−1
(1)
(2)
10−2
10−2
(1)
(2)
10−3
10
102
103
104
105
10−3
10
102
103
fi (Hz)
a. VP = 12 V; RL = 4 Ω
104
105
fi (Hz)
b. VP = 22 V; RL = 8 Ω
(1) Po = 10 W
(2) Po = 1 W
Fig 27. Total harmonic distortion-plus-noise as a function of frequency
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
33 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
001aae116
40
001aae117
0
SVRR
(dB)
Gv
(dB)
(2)
(1)
−20
30
−40
−60
20
(1)
−80
10
10
102
103
104
105
(2)
−100
102
10
103
104
105
fi (Hz)
fi (Hz)
Vi = 100 mV (RMS); Ri = 0 Ω
Vripple = 500 mV (RMS) referenced to ground; Ri = 0 Ω
(shorted input)
(1) VP = 12 V; RL = 4 Ω
(1) VP = 22 V; RL = 8 Ω
(2) VP = 22 V; RL = 8 Ω
(2) VP = 12 V; RL = 4 Ω
Fig 28. Gain as a function of frequency
Fig 29. Supply voltage ripple rejection as a function of
frequency
001aae118
120
S/N
(dB)
001aaf893
70
Po
(W)
60
(2)
50
(1)
80
(3)
40
(1)
30
(4)
(2)
40
20
10
0
10−2
10−1
1
102
10
0
10
14
18
22
Po (W)
Ri = 0 Ω; 20 kHz brick-wall filter AES17
26
30
34
VP (V)
fi = 1 kHz (short time PO); dashed line will require heat
sink for continuous time output power
(1) RL = 4 Ω; VP = 12 V
(1) RL = 4 Ω; THD+N = 10 %
(2) RL = 8 Ω; VP = 22 V
(2) RL = 4 Ω; THD+N = 0.5 %
(3) RL = 8 Ω; THD+N = 10 %
(4) RL = 8 Ω; THD+N = 0.5 %
Fig 30. Signal-to-noise ratio as a function of output
power
Fig 31. Output power as a function of supply voltage
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
34 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
001aaf896
32
(3)
Po
(W)
50
(2)
40
(1)
30
Po
(W)
001aaf899
60
(3)
24
16
(2)
(1)
20
8
10
0
0
0
120
240
360
480
600
0
120
240
360
480
t (s)
600
t (s)
a. RL = 4 Ω; fi = 1 kHz; 2 layer SO32 application
board (55 mm × 45 mm) without heat sink
b. RL = 8 Ω; fi = 1 kHz; 2 layer SO32 application
board (55 mm × 45 mm) without heat sink
(1) VP = 12 V
(1) VP = 22 V
(2) VP = 13.5 V
(2) VP = 26 V
(3) VP = 15 V
(3) VP = 29 V
Fig 32. Output power as a function of time
001aae119
100
ηpo
(%)
001aae120
3.0
(1)
80
P
(W)
(2)
2.0
60
40
(2)
1.0
(1)
20
0
0
10
20
30
0
10−2
10−1
Po (W)
1
102
10
Po (W)
fi = 1 kHz; power dissipation in junction only
Po
( Po + p )
fi = 1 kHz; η PO = --------------------
(1) VP = 12 V; RL = 4 Ω
(2) VP = 22 V; RL = 8 Ω
(1) VP = 12 V; RL = 4 Ω
(2) VP = 22 V; RL = 8 Ω
Fig 33. Output power efficiency as a function of
output power
Fig 34. Power dissipation as a function of output
power
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
35 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
001aaf904
6
P
(W)
4
(2)
(1)
2
0
10
14
18
22
26
30
34
VP (V)
fi = 1 kHz; power dissipation in junction only; short time Po at THD+N = 10 %; dashed line will require heat sink for continuous
time output power
(1) RL = 4 Ω
(2) RL = 8 Ω
Fig 35. Power dissipation as a function of supply voltage
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
36 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
14.11 Typical application schematics (simplified)
VP
Rvdda
VP
VPA
10 Ω
Cvdda
100 nF
Cvddp
220 µF
(35 V)
GND
VSSD(HW)
Cin
IN1P
Cin
470 nF
IN1N
470 nF
DIAG
ENGAGE
MUTE control
Cen
470 nF
POWERUP
CGND
SLEEP control
Cosc
VDDA
VPA
VSSA
100 nF
Rosc
OSCREF
39 kΩ
Chvpref
47 µF (25 V)
HVPREF
Chvp
100 nF
INREF
Cinref
100 nF
Cin
470 nF
TEST
IN2N
Cin
470 nF
IN2P
VSSD(HW)
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8
25
9
U1
TDA8932B
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
VSSD(HW)
OSCIO
HVP1
VP
VDDP1
BOOT1
OUT1
Cvddp
100 nF
Cbo
15
nF
Chvp
100 nF
Llc
VSSP1
STAB1
Rsn
10 Ω
STAB2
Csn
470 pF
Llc
OUT2
VDDP2
HVP2
Cse
Cstab
100 nF
VSSP2
BOOT2
Clc
Cbo
15
nF
Rsn
10 Ω
VP
Cvddp
100 nF
Csn
470 pF
Clc
Cse
DREF
VSSD(HW)
Cdref
100 nF
Chvp
100 nF
001aaf601
Fig 36. Typical simplified application diagram for 2 × SE (asymmetrical supply)
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
37 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
VP
Rvdda
VP
10 Ω
VPA
Cvdda
100 nF
Cvddp
220 µF
(35 V)
GND
VSSD(HW)
Cin
Cin
IN1P
1 µF
IN1N
1 µF
DIAG
MUTE
control
ENGAGE
Cen
470 nF
POWERUP
CGND
SLEEP
control
Cosc
VDDA
VPA
VSSA
100 nF
Rosc
OSCREF
39 kΩ
HVPREF
INREF
Chvp
100 nF
Cinref
100 nF
TEST
IN2N
IN2P
VSSD(HW)
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8
9
10
Rhvp
470 Ω
OSCIO
VP
VDDP1
BOOT1
OUT1
Cvddp
100 nF
Cbo
15 nF
VSSP1
Rsn
10 Ω
12
21
20
14
19
15
18
16
17
Cstab
100 nF
VSSP2
Clc
Llc
OUT2
BOOT2
VDDP2
HVP2
Clc
Csn
470 pF
24
22
Chvp
100 nF
Llc
25
U1
TDA8932B
STAB2
23
Rhvp
470 Ω
HVP1
STAB1
11
13
VSSD(HW)
Cbo
15 nF
Rsn
10 Ω
VP
Cvddp
100 nF
Csn
470 pF
Cdref
100 nF
Chvp
100 nF
DREF
VSSD(HW)
001aaf602
Fig 37. Typical simplified application diagram for 1 × BTL (asymmetrical supply)
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
38 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
VDD
Rvdda
VDD
VDDA
10 Ω
Cvdda
100 nF
Cvddp
220 µF
(25 V)
Cvssa
100 nF
Cvssp
220 µF
(25 V)
GND
Rvssa
VSS
VSSA
10 Ω
VSS
VSSD(HW)
VSSA
1
Cin
IN1P
470 nF
Cin
IN1N
470 nF
DIAG
ENGAGE
MUTE control
Cen
470 nF
POWERUP
CGND
SLEEP control
Cosc
VSSA
100 nF
Rosc
VDDA
VDDA
VSSA
VSSA
OSCREF
39 kΩ
HVPREF
INREF
Cinref
100 nF
Cin
470 nF
TEST
IN2N
Cin
IN2P
32
2
31
3
30
4
29
5
28
6
27
7
26
8
9
VDD
VDDP1
BOOT1
OUT1
22
12
21
20
19
18
470 nF
17
VSSP2
Cvddp
100 nF
Cbo
15 nF
VSSP1
24
11
15
VSSD(HW)
16
VSSA
HVP1
Llc
Cstab
100 nF
Csn
470 pF
Cvssp
100 nF
Cbo
15 nF
VDDP2
VDD
Cvddp
100 nF
HVP2
Clc
VSS
OUT2
BOOT2
Rsn
10 Ω
VSS
Cvssp
100 nF
25
U1
TDA8932B
STAB2
23
14
VSSA
OSCIO
STAB1
10
13
VSSD(HW)
Llc
Rsn
10 Ω
Csn
470 pF
Clc
DREF
VSSD(HW)
Cdref
100 nF
VSSA
001aaf603
Fig 38. Typical simplified application diagram for 2 × SE (symmetrical supply)
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
39 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
VDD
Rvdda
VDD
10 Ω
VDDA
Cvdda
100 nF
Cvddp
220 µF
(25 V)
Cvssa
100 nF
Cvssp
220 µF
(25 V)
GND
Rvssa
VSS
VSSA
10 Ω
VSS
VSSA
VSSD(HW)
Cin
Cin
IN1P
1 µF
IN1N
1 µF
DIAG
MUTE
control
ENGAGE
Cen
470 nF
POWERUP
CGND
SLEEP
control
Cosc
VDDA
100 nF
VSSA
Rosc
VDDA
VSSA
OSCREF
VSSA
39 kΩ
HVPREF
INREF
Cinref
100 nF
TEST
IN2N
IN2P
VSSA
VSSD(HW)
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8
9
10
VSSD(HW)
VSSA
OSCIO
HVP1
VDD
VDDP1
BOOT1
OUT1
VSSP1
23
11
22
12
21
13
20
14
19
15
18
16
17
Cstab
100 nF
Cvssp
100 nF
Cbo
15 nF
VDDP2
VDD
HVP2
Clc
Csn
470 pF
VSS
OUT2
BOOT2
Rsn
10 Ω
VSS
25
U1
TDA8932B
STAB2
VSSP2
Llc
Cvssp
100 nF
STAB1
24
Cvddp
100 nF
Cbo
15 nF
Cvddp
100 nF
Clc
Llc
Rsn
10 Ω
Csn
470 pF
DREF
VSSD(HW)
Cdref
100 nF
VSSA
001aaf606
Fig 39. Typical simplified application diagram for 1 × BTL (symmetrical supply)
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
40 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
15. Package outline
SO32: plastic small outline package; 32 leads; body width 7.5 mm
SOT287-1
D
E
A
X
c
y
HE
v M A
Z
17
32
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
16
1
0
detail X
w M
bp
e
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
2.65
0.3
0.1
2.45
2.25
0.25
0.49
0.36
0.27
0.18
20.7
20.3
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.2
1.0
0.25
0.25
0.1
0.95
0.55
0.01
0.02
0.01
0.011
0.007
0.81
0.80
0.30
0.29
0.05
0.419
0.394
inches
0.1
0.012 0.096
0.004 0.089
0.043
0.055
0.016
0.047
0.039
0.01
0.01
0.037
0.004
0.022
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
OUTLINE
VERSION
SOT287-1
REFERENCES
IEC
JEDEC
JEITA
MO-119
EUROPEAN
PROJECTION
ISSUE DATE
00-08-17
03-02-19
Fig 40. Package outline SOT287-1 (SO32)
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
41 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads;
body width 6.1 mm; lead pitch 0.65 mm; exposed die pad
SOT549-1
E
D
A
X
c
y
HE
exposed die pad side
v M A
Dh
Z
32
17
A2
Eh
(A3)
A
A1
pin 1 index
θ
Lp
L
detail X
16
1
w M
bp
e
2.5
0
5 mm
scale
DIMENSIONS (mm are the original dimensions).
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
Dh
E(2)
Eh
e
HE
L
Lp
v
w
y
Z
θ
mm
1.1
0.15
0.05
0.95
0.85
0.25
0.30
0.19
0.20
0.09
11.1
10.9
5.1
4.9
6.2
6.0
3.6
3.4
0.65
8.3
7.9
1
0.75
0.50
0.2
0.1
0.1
0.78
0.48
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT549-1
REFERENCES
IEC
JEDEC
JEITA
MO-153
EUROPEAN
PROJECTION
ISSUE DATE
03-04-07
05-11-02
Fig 41. Package outline SOT549-1 (HTSSOP32)
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
42 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
43 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
16.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 42) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 16 and 17
Table 16.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 17.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 42.
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
44 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 42. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
17. Abbreviations
Table 18.
Abbreviations
Acronym
Description
BTL
Bridge Tied Load
DMOS
Double diffused Metal Oxide Semiconductor
ESD
ElectroStatic Discharge
OCP
OverCurrent Protection
OTP
OverTemperature Protection
OVP
OverVoltage Protection
PWM
Pulse Width Modulation
SE
Single-Ended
TF
Thermal Foldback
UBP
UnBalance Protection
UVP
UnderVoltage Protection
WP
Window Protection
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
45 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
18. Revision history
Table 19.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
TDA8932B_4
20081218
Product data sheet
-
TDA8932B_3
Modifications:
•
IP values amended in Table 1 and Table 10
TDA8932B_3
20070621
Product data sheet
-
TDA8932B_2
TDA8932B_2
20070329
Preliminary data sheet
-
TDA8932B_1
TDA8932B_1
20070214
Objective data sheet
-
-
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
46 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
19.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
TDA8932B_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 18 December 2008
47 of 48
TDA8932B
NXP Semiconductors
Class-D audio amplifier
21. Contents
1
2
3
4
5
6
7
7.1
7.2
8
8.1
8.2
8.3
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.5
8.6
8.7
9
10
11
12
13
14
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
14.9
14.10
14.11
15
16
16.1
16.2
16.3
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Mode selection and interfacing . . . . . . . . . . . . . 6
Pulse width modulation frequency . . . . . . . . . . 7
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Foldback (TF) . . . . . . . . . . . . . . . . . . . 9
OverTemperature Protection (OTP) . . . . . . . . . 9
OverCurrent Protection (OCP) . . . . . . . . . . . . . 9
Window Protection (WP). . . . . . . . . . . . . . . . . . 9
Supply voltage protection . . . . . . . . . . . . . . . . 10
Diagnostic input and output . . . . . . . . . . . . . . 11
Differential inputs . . . . . . . . . . . . . . . . . . . . . . 11
Output voltage buffers. . . . . . . . . . . . . . . . . . . 11
Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 12
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16
Thermal characteristics. . . . . . . . . . . . . . . . . . 16
Static characteristics. . . . . . . . . . . . . . . . . . . . 17
Dynamic characteristics . . . . . . . . . . . . . . . . . 19
Application information. . . . . . . . . . . . . . . . . . 22
Output power estimation. . . . . . . . . . . . . . . . . 22
Output current limiting. . . . . . . . . . . . . . . . . . . 24
Speaker configuration and impedance . . . . . . 24
Single-ended capacitor . . . . . . . . . . . . . . . . . . 24
Gain reduction . . . . . . . . . . . . . . . . . . . . . . . . 25
Device synchronization . . . . . . . . . . . . . . . . . . 26
Thermal behavior (printed-circuit board
considerations) . . . . . . . . . . . . . . . . . . . . . . . . 26
Pumping effects . . . . . . . . . . . . . . . . . . . . . . . 27
SE curves measured in reference design. . . . 29
BTL curves measured in reference design . . . 33
Typical application schematics (simplified) . . . 37
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 41
Soldering of SMD packages . . . . . . . . . . . . . . 43
Introduction to soldering . . . . . . . . . . . . . . . . . 43
Wave and reflow soldering . . . . . . . . . . . . . . . 43
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 43
16.4
17
18
19
19.1
19.2
19.3
19.4
20
21
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
45
46
47
47
47
47
47
47
48
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 18 December 2008
Document identifier: TDA8932B_4
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