Comparing Micron N25Q032A / N25Q064A with Macronix MX25L3235E / MX25L6435E

APPLICATION NOTE
Comparing Micron N25Q032A/064A with Macronix MX25L3235E/6435E
1. Introduction
This application note serves as a guide to compare the Micron N25Q032A and N25Q064A with the Macronix
MX25L3235E and MX25L6435E 3V 32Mb and 64Mb Serial Flash. The document does not provide detailed
information on each individual device, but highlights the similarities and differences between them. The
comparison covers the general features, performance, command codes, and other differences.
If common features are used in standard traditional modes, they may need only minimal software modification.
The information provided in this document is based on datasheets listed in Section 9. Newer versions of the
datasheets may override the contents of this document.
2. Features
Both flash device families have similar features and functions as shown in Table 2-1.
Table 2-1: Feature Comparison
Feature
VCC Voltage Range
Sector Size
Program Buffer Size
Security OTP
HOLD# or RESET# Pin
Normal Read Clock Frequency
Maximum Fast Read Clock Frequency*1
Dual Output (DREAD) (1-1-2)
Dual I/O (2READ) (1-2-2)
Quad Output (QREAD) (1-1-4)
Quad I/O (4READ) (1-4-4)
Configurable Dummy Cycle
Block Protection Mode (BP bits)
Individual Sector Protection Mode (Volatile)*2
XIP / Performance Enhanced Mode*3
Program/Erase Suspend & Resume
Adjustable Output Driver
Deep Power Down
S/W Reset Command
Program/Erase Cycles
Macronix MX25L_35E
2.7V-3.6V
4KB/32KB/64KB
256Byte
512Byte
Hold#
50MHz
104MHz
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
100K
Micron N25Q_A
2.7V-3.6V
4KB/64KB
256Byte
64Byte
Hold# or Reset#
54MHz
108MHz
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
100K
Notes:
1. Maximum clock frequency with 8 dummy cycles.
2: Please see App Note section 4-6 for detailed comparison of Individual Sector Protection.
3. Macronix supports 1-4-4 Quad I/O mode XIP; Micron supports XIP in all Fast Read modes.
P/N: AN0260
1
Ver.1, Sep. 30, 2013
APPLICATION NOTE
Comparing Micron N25Q032A/064A with Macronix MX25L3235E/6435E
Table 2-2: Read Performance
I/O Mode
Macronix MX25L_35E
Default
Max Speed
Dummy
@ Default
Cycles
Dummy Cycles
Fast Read
(1-1-1)
Dual Output (DREAD)
( 1-1-2)
Dual I/O (2READ)
(1-2-2)
Quad Output (QREAD)
(1-1-4)
Quad I/O (4READ)
(1-4-4)
Micron N25Q_A
Default
Max Speed
Dummy
@ Default
Cycles
Dummy Cycles
8
104MHz
8
108MHz
4
86MHz
8
108MHz
4
86MHz
8
108MHz
6
86MHz*1
8
108MHz
6
86MHz*1
8
108MHz
Note 1: 104MHz with 8 Dummy clock cycles.
3. Package and Pinout
Both devices are available in similar packages with similar footprints. Pinout definitions are identical with the
two minor exceptions shown in Table 3-2. Where Macronix has a HOLD#/SIO3 pin, Micron has either a
HOLD#/DQ3 or a RESET#/DQ3 pin. If the Micron device has a HOLD# pin, then the devices are pin compatible.
If the Micron device has a Reset# pin, but the Reset# function is not used, then the devices are also pin
compatible. Macronix does not support the VPP (10V Fast Programming Voltage) function available on
Micron’s W#/VPP/DQ2 pin. This function is normally only used on external programmers to accelerate
Program/Erase operations and is generally not used for “in-circuit” programming. Please consult the latest
Macronix datasheet for new package additions.
Table 3-1: Packages
Packages
8-WSON (6x5mm)
8-WSON (8x6mm)
8-USON (4x3mm)
8-SOP (150mil)
8-SOP (209mil)
16-SOP (300mil)
24-TFBGA (4x6 ball array)
24-TFBGA (5x5 ball array)
MX25L_35E
32Mb, 64Mb
64Mb
32Mb, 64Mb
32Mb, 64Mb
64Mb
Note*1
N25Q_A
32Mb, 64Mb
32Mb, 64Mb
32Mb
32Mb
32Mb, 64Mb
32Mb, 64Mb
64Mb
32Mb, 64Mb
Note 1: 24-TFBGA (5x5 ball array) is currently available in MX25L_55/56E family. Contact Macronix sales.
P/N: AN0260
2
Ver.1, Sep. 30, 2013
APPLICATION NOTE
Comparing Micron N25Q032A/064A with Macronix MX25L3235E/6435E
Table 3-2: Pin Definition Comparison (8-SOP and 8-WSON)
Pin #1
Pin #2
Pin #3
Macronix
MX25L_35E
CS#
SO/SIO1
WP#/SIO2
S#
DQ1
W#/ VPP /DQ2
Macronix does not support VPP
Pin #4
GND
VSS
-
Pin #5
Pin #6
SI/SIO0
SCLK
DQ0
C
-
Pin #7
HOLD#/SIO3
HOLD#/DQ3 or
RESET#/DQ3
Dedicated Micron part numbers offer RESET#
instead of HOLD#.
Pin #8
VCC
VCC
-
Pin Number
Micron
N25Q_A
Comments
Figures 3-1 through 3-4 show that supported packages have similar footprints and pinouts.
Figure 3-1: 8-WSON (6x5mm)
CS#
1
8
VCC
SO/SIO1
2
7
HOLD#/SIO3
WP#/SIO2
3
6
SCLK
GND
4
5
SI/SIO0
MX25L_35E
S#
1
8
VCC
DQ1
2
7
HOLD#/DQ3
6
C
5
DQ0
WP#/Vpp/DQ2 p
3
VSS
4
S#
N25Q0_A
Figure 3-2: 8-SOP (209 mil)
CS#
SO/SIO1
1
2
WP#/SIO2
3
GND
4
P/N: AN0260
MX25L_35E
8
VCC
7
6
HOLD#/SIO3
5
SI/SIO0
SCLK
DQ1
1
2
WP#/Vpp/DQ2
3
VSS
4
3
N25Q0_A
8
VCC
7
6
HOLD#/DQ3
5
DQ0
C
Ver.1, Sep. 30, 2013
APPLICATION NOTE
Comparing Micron N25Q032A/064A with Macronix MX25L3235E/6435EF
Figure 3-3: 16-SOP (300mil)
HOLD#/SIO3
16
SCLK
HOLD#/DQ3
1
16
C
SI/SIO0
VCC
2
15
DQ0
3
15
14
NC
DNU
3
14
DNU
NC
4
13
NC
DNU
4
13
DNU
NC
5
12
NC
DNU
5
12
DNU
NC
6
11
NC
DNU
6
11
DNU
CS#
7
10
GND
S#
7
10
VSS
SO/SIO1
8
9
DQ1
8
9
VCC
1
2
NC
MX25L_35E
Note: NC = Not Connected.
WP#/SIO2
N25Q0_A
WP#/Vpp/DQ2
DNU = Do Not Use.
Figure 3-4: 24-TFBGA (6x8mm with 4x6 Ball Array)
MX25L6435E
N25Q064A
4
NC
VCC
WP#
SIO2
HLD#
SIO3
NC
NC
4
NC
VCC
WP#/
VPP/
DQ2
HLD#
DQ3
NC
NC
3
NC
GND
NC
SI
SIO0
NC
NC
3
NC
VSS
NC
DQ0
NC
NC
2
NC
SCLK
CS#
SO
SIO1
NC
NC
2
NC
C
S#
DQ1
NC
NC
1
NC
NC
NC
NC
NC
NC
1
NC
NC
NC
NC
NC
NC
A
B
C
D
E
F
A
B
C
D
E
F
Note: NC = Not Connected
P/N: AN0260
4
Ver.1, Sep. 30, 2013
APPLICATION NOTE
Comparing Micron N25Q032A/064A with Macronix MX25L3235E/6435EF
4. Key Feature and Operational Differences
4-1 Status Register and Configuration Register Differences
Both devices use registers to control device behavior and report status. The registers and bits used are similar
but not identical. Both the Micron and Macronix devices use BP bits to select groups of memory areas for
protection.
The N25Q032/64A Block Protection bits BP[3:0] are located in Status Register (bits [6,4:2]). The Top/Bottom bit
is located in Status Register bit 5 and selects whether block protection starts at the top or bottom of memory.
The BP[3:0] and Top/Bottom bits are nonvolatile and reprogrammable.
The MX25L32/6435E Block Protection bits BP[3:0] are located in Status Register bits [5:2]. The Top/Bottom bit
is located in the Configuration Register bit 3. The protected areas are the same.
Table 4-1: Status Register
Register Bit
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Macronix MX25L32/6435E
WIP; 1=write operation
WEL; 1=write enable
BP0; BP protection
BP1; BP protection
BP2; BP protection
BP3; BP protection
QE; 1=Quad mode enable
SRWD; 1=SR write disable
Table 4-2: Nonvolatile Configuration Register
Register Bit
Macronix MX25L32/6435E
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
P/N: AN0260
Reserved
Reserved
Reserved
TB; 1=Bottom area protect
Reserved
Reserved
Reserved
DC; Dummy cycle
5
Micron N25Q032/64A
WIP; 1=write operation
WEL; 1=write enable
BP0; BP protection
BP1; BP protection
BP2; BP protection
T/B; Top/Bottom Protect
BP3; BP protection
SRWE/D; 1=SR write disable
Micron N25Q032/64A
Reserved
Reserved
Dual I/O protocol
Quad I/O protocol
Reset/hold
Reserved
Output Driver Strength
Output Driver Strength
Ver.1, Sep. 30, 2013
APPLICATION NOTE
Comparing Micron N25Q032A/064A with Macronix MX25L3235E/6435EF
Table 4-3: Macronix Security Register vs. Micron Flag Status Register
Register Bit
Macronix MX25L32/6435E
Micron N25Q032/64A
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
4Kb Secured OTP; 1=factory lock
LDSO; 1=OTP lock down
Reserved
Reserved
Continuous Program Mode
P_FAIL; 1=Program fail
E_FAIL; 1=Erase fail
WPSEL; 1=Individual WP
Reserved
Protection
Program suspend
Vpp
Program; 1=Program fail
Erase; 1=Erase fail
Erase Suspend
Program/Erase Controller
4-2 Quad I/O Mode
Micron’s Quad I/O mode is entered by setting a bit in the Nonvolatile Configuration Register (NVCR[3]) or by
setting a bit in the Enhanced Volatile Configuration Register (VCR).
The MX25L32/6435E requires bit 6 of the Status Register to be set =1 to enable Quad I/O mode operation. The
WP# and Hold# pin functions are disabled in Quad mode.
4-3 XIP Differences
The XIP (eXecute In Place) feature (Macronix refers to this as Performance Enhance Mode) is only used during
Fast Read operations and eliminates the need to input read commands prior to entering an address and
reading data. This is an overhead reduction feature that increases data throughput. Both devices offer this
feature, but entry and exit methods are different. Macronix supports 1-4-4 Quad I/O mode XIP; Micron supports
XIP in all Fast Read modes.
4-4. Block/Sector Sizes
The MX25L_35F has uniform 64KB blocks that are each subdivided into two 32KB blocks and sixteen 4KB
sectors. The N25Q0_A has uniform 64KB main blocks subdivided into 4KB sectors. No change is necessary to
erase block size or erase commands when migrating from the Micron to Macronix flash, even though Macronix
offers an additional 32KB block erase option.
4-5. Block Protection Mode
Both the Micron and Macronix devices use BP bits to select groups of memory areas for write protection.
Although the location of the bits in the Status and Configuration Registers may be different, the protected
regions are similar.
P/N: AN0260
6
Ver.1, Sep. 30, 2013
APPLICATION NOTE
Comparing Micron N25Q032A/064A with Macronix MX25L3235E/6435EF
4-6 Individual Sector Protection Differences
Both devices have the ability to write protect individual 64KB sectors/blocks of memory. Individual Sector
Protection does not use the nonvolatile BP bits in the Status Register. With the Micron flash, it is possible to use
both methods of write protection (BP bits and Individual Sector Protection) simultaneously, and the protected
area is the combination of the two. When using the Macronix flash, either BP bit Protection or Individual Sector
Protection can be selected exclusively, with the default being the use of the BP bits.
The N25Q_A have one volatile Lock Register for each 64KB sector to control the sector’s program/erase
protection status. The protection can be turned on or off at any time unless the sector’s Lock Register has been
locked by the application. Once locked, its associated sector will remain in the protected or unprotected state
until the next power cycle or reset. All sectors not protected by the Status Register BP configuration will be
unprotected after power up and all Lock Registers will be unlocked.
The MX25L_35E have one volatile protection register for each of the top sixteen 4KB sectors, bottom sixteen
4KB sectors, and the remaining middle 64KB blocks (the MX25L3235E has 62 middle blocks and the
MX25L6435E has 126 middle blocks). These protection registers can only be used after permanently disabling
the Status Register BP protection bits. This is done by executing the WPSEL instruction once. Please note that
this irreversible and Individual Sector Protection method will be permanently selected.
After permanently selecting the Individual Sector Protection method for the MX25L_35E, all sectors and blocks
will be locked by default on power up. Sectors/blocks must be unlocked before they can be programmed or
erased. Unlocking sectors/blocks can be done on an individual basis with the SBULK (Single Block Unlock)
command or on all sectors/blocks with the GBULK (Global Block Unlock) command. Sectors and blocks can be
relocked as necessary with the SBLK (Single Block Lock) command or GBLK (Global Block Lock) command.
Since the smallest individual sector protection size in the N25Q_A is 64KB, if an application is currently
locking/unlocking the top and/or bottom 64KB sector(s), it will need to lock/unlock each of the 16 top and/or
bottom 4KB sectors in the MX25L_35E for equivalent results.
4-7. Secure OTP Differences
Both device families provide a secure One Time Programmable (OTP) area outside of the main memory array
for user defined storage. The sizes, features, and access methods are different.
The N25Q0_A has commands to directly read and program the 64 byte OTP area and does not need to
explicitly open this area for read and write operations. The MX25L_35E operates in the OTP area using normal
read and program instructions after explicitly opening the OTP area with the Enter Secured OTP (ENSO)
command. While the OTP area is open, the main array is not accessible. When finished in the OTP area, the
Exit Secure OTP (EXSO) command must be issued to return to the Read Main Array mode. The MX25L_35E
OTP area has 512 bytes available for user data. The user may permanently lock the whole OTP area to prevent
new data from being stored there. This area can optionally be programmed with user supplied data and factory
locked by Macronix.
P/N: AN0260
7
Ver.1, Sep. 30, 2013
APPLICATION NOTE
Comparing Micron N25Q032A/064A with Macronix MX25L3235E/6435EF
5. Performance
Table 5-1 and 5-2 show that the two devices have similar AC and DC performance.
Table 5-1: AC Parameter Comparison
Parameter
Clock High / Low Time
Symbol
Macronix
Micron
tCH / tCL
tCH / tCL
Clock Low to Output Valid
tCLQV
tCLQV
Data In Setup Time
Data In Hold Time
tDVCH
tCHDX
tDVCH
tCHDX
tPP
tPP
Erase 4KB Subsector/Sector
tSSE
tSE
Erase 32KB Sector
tBE32
-
Erase 64KB Sector/Block
tBE
tSE
Bulk Erase / Chip Erase (32Mb)
tCE
tBE
Bulk Erase / Chip Erase (64Mb)
tCE
tBE
Page Program Time (256 Bytes)
Condition
min
max 10pF, x1
max 10pF, x4
max 15pF, x1
max 15pF, x4
max 30pF, x1
max 30pF, x4
min
min
typ
max
typ
max
typ
max
typ
max
typ
max
typ
max
Macronix
MX25L_35E
4.5ns
5ns
6ns
6ns
6ns
7ns
8ns
2ns
3ns
1.4ms
3ms
60ms
300ms
500ms
2s
700ms
2s
25s
50s
50s
80s
Micron
N25Q_A
4ns
5ns
5ns
7ns
7ns
2ns
3ns
0.4ms
5ms
250ms
800ms
700ms
3s
30s
60s
60s
120s
Macronix
MX25L_35E
+/- 2uA
80uA
5uA
40uA
35mA
19mA
25mA
Micron
N25Q_A
+/- 2uA
100uA
20mA
15mA
20mA
Table 5-2: DC Parameter Comparison
Parameter
Leakage Current
Standby Current
Symbol
Macronix
Micron
ILI/ILO
ILI/ILO
ISB1
ICC1
Condition
Deep Power Down Current
ISB2
ICC2
VCC Read Current (Fast Read)
ICC1
ICC3
VCC Program Current
VCC Write Status Register
Current
VCC Erase Current
ICC2
ICC4
max
max
typ
max
max 108MHz, x4
max 104MHz, x4
max 108MHz, x1
max 104MHz, x1
max
ICC3
ICC5
max
20mA
20mA
ICC4,5
ICC6
max
25mA
20mA
P/N: AN0260
8
Ver.1, Sep. 30, 2013
APPLICATION NOTE
Comparing Micron N25Q032A/064A with Macronix MX25L3235E/6435EF
6. Command Code
Both devices use the same basic command set, but there are a few minor differences highlighted in Table 6-1.
Table 6-1: Command Code Comparison
Instruction
Type
Read ID
Read
Write
OTP
P/N: AN0260
Instruction
Description
RDID
REMS
REMS2/4
READ
FAST_READ
DOFR
DIOFR
QOFR
QIOFR
W4READ
RDSFDP
WREN
WRDI
PP
CP
4PP
SE
BE 32K
SE 64K
CE
ENSO
EXSO
ROTP
POTP
Read Identification
Read Electronic Manufacturer ID
Multi I/O Read ID
Read Data Bytes
Read Data Bytes at Higher Speed
Dual Output Fast Read
Dual Input/Output Fast Read
Quad Output Fast Read
Quad Input/Output Fast Read
Quad Input/Output Fast Read (4-dummy)
Read Serial Flash Discoverable Parameters
Write Enable
Write Disable
Page Program
Continuous Program
Dual Input Fast Program (1-1-2)
Dual I/O Fast Program (1-2-2)
Quad Input Fast Program (1-1-4)
Quad Page Program (1-4-4)
Sector Erase 4KB
Block Erase 32KB
Block Erase 64KB
Chip Erase
Enter Secured OTP
Exit Secured OTP
Read OTP Area
Program OTP Area
9
Macronix
MX25L_35E
9Fh
90h
EFh/DFh
03h
0Bh
3Bh
BBh
6Bh
EBh
E7h
5Ah
06h
04h
02h
ADh
38h
20h
52h
D8h
60 or C7h
B1h
C1h
-
Micron
N25Q_A
9Eh/9Fh
AFh
03h
0Bh
3Bh
BBh
6Bh
EBh
5Ah
06h
04h
02h
A2h
D2h
32h
12h
20h
D8h
C7h
4Bh
42h
Ver.1, Sep. 30, 2013
APPLICATION NOTE
Comparing Micron N25Q032A/064A with Macronix MX25L3235E/6435EF
Table 6-1: Command Code Comparison - Continued
Instruction
Type
Instruction
RDSR
WRSR
RDSCUR
WRSCUR
RDLR
WRLR
RFSR
CLFSR
-
Registers
and
Other
P/N: AN0260
PGM/ERS
Suspend
PGM/ERS
Resume
ESRY
DSRY
RSTEN
RST
NOP
DP
RDP
WPSEL
GBLK
GBULK
SBLK
SBULK
RDBLOCK
Macronix
MX25L_35E
05h
01h
2Bh
2Fh
-
Micron
N25Q_A
05h
01h
E8h
E5h
70h
50h
15h
B5h
-
B1h
-
85h
81h
-
65h
-
61h
Program or Erase Suspend
-
75h
Program or Erase Resume
-
7Ah
70h
80h
66h
99h
00h
B9h
ABh
68h
7Eh
98h
36h
39h
3Ch
-
Description
Read Status Register
Write Status Register
Read Security Register
Write Security Register
Read Lock Register
Write Lock Register
Read Flag Status Register
Clear Flag Status Register
Read Non-volatile
Configuration Register
Write Non-volatile
Configuration Register
Read Volatile Configuration Register
Write Volatile Configuration Register
Read Enhance Volatile Configuration
Register
Write Enhance Volatile Configuration
Register
Enable SO to output RY/BY#
Disable SO to output RY/BY#
Reset Enable
Reset Memory
No Operation
Deep Power Down
Release From Deep Power Down
Write Protect Selection (OTP)
Gang Block Lock
Gang Block Unlock
Single Block Lock
Single Block UnLock
Read Block Lock
10
Ver.1, Sep. 30, 2013
APPLICATION NOTE
Comparing Micron N25Q032A/064A with Macronix MX25L3235E/6435EF
7. Manufacturer and Device ID
Table 7-1: Manufacturer and Device ID Comparison
Macronix
Micron
ID Type
Manufacturer ID
JEDEC Device ID
Unique ID
MX25L3235E
C2h
2016h
N/A
MX25L6435E
C2h
2017h
N/A
N25Q32A
20h
BA16h
17 Bytes
N25Q64A
20h
BA17h
17 Bytes
8. Summary
The Macronix MX25L3235E/6435E and Micron N25Q032/64A have similar commands, functions, and features.
The devices are command compatible for basic read, program, and erase (4KB and 64KB) operations. The
devices are essentially pin compatible if the Reset# function is not used. A more detailed analysis should be
done if “special” functions such as XIP, Suspend/Resume, or Individual Sector Protection are used. If common
features are used in standard traditional modes, they may need only minimal software modification.
9. References
Table 9-1 shows the datasheet versions used for comparison in this application note. For the most current,
detailed Macronix specification, please refer to the Macronix Website at http://www.macronix.com/.
Table 9-1: Datasheet Version
Datasheet
Location
Date Issued
Version
MX25L3235E
Macronix Website
APR. 2013
1.3
MX25L6435E
Macronix Website
APR. 2012
1.2
n25q_32mb_3v_65nm
Micron Website
APR. 2013
I
n25q_64mb_3v_65nm
Micron Website
AUG. 2013
K
P/N: AN0260
11
Ver.1, Sep. 30, 2013
APPLICATION NOTE
Comparing Micron N25Q032A/064A with Macronix MX25L3235E/6435EF
10. Appendix
Table 10-1 shows the basic part number and package information cross reference between Macronix
MX25L3235E and Micron N25Q032A parts.
Table 10-2 shows the basic part number and package information cross reference between Macronix
MX25L6435E and Micron N25Q064A parts.
Table 10-1: 32Mb Part Number Cross Reference
Macronix Part No.
MX25L3235EM2I-10G
MX25L3235EM2I-10G
MX25L3235EM2I-10G
MX25L3235EM2I-10G
MX25L3235EMI-10G
MX25L3235EMI-10G
MX25L3235EMI-10G
MX25L3235EMI-10G
MX25L3235EZNI-10G
MX25L3235EZNI-10G
MX25L3235EZNI-10G
MX25L3235EZNI-10G
Micron Part No.
N25Q032A13ESE40
N25Q032A23ESE40
N25Q032A33ESE40
N25Q032A43ESE40
N25Q032A13ESF40
N25Q032A23ESF40
N25Q032A33ESF40
N25Q032A43ESF40
N25Q032A13EF640
N25Q032A23EF640
N25Q032A33EF640
N25Q032A43EF640
Package
8-SOP
8-SOP
8-SOP
8-SOP
16-SOP
16-SOP
16-SOP
16-SOP
8-WSON
8-WSON
8-WSON
8-WSON
Dimension
209 mil
209 mil
209 mil
209 mil
300 mil
300 mil
300 mil
300 mil
6x5 mm
6x5 mm
6x5 mm
6x5 mm
Note
Hold# pin, Micron XIP
Hold# pin, basic XIP
Reset# pin, Micron XIP
Reset# pin, basic XIP
Hold# pin, Micron XIP
Hold# pin, basic XIP
Reset# pin, Micron XIP
Reset# pin, basic XIP
Hold# pin, Micron XIP
Hold# pin, basic XIP
Reset# pin, Micron XIP
Reset# pin, basic XIP
Table 10-2: 64Mb Part Number Cross Reference
Macronix Part No.
MX25L6435EM2I-10G
MX25L6435EM2I-10G
MX25L6435EM2I-10G
MX25L6435EM2I-10G
MX25L6435EMI-10G
MX25L6435EMI-10G
MX25L6435EMI-10G
MX25L6435EMI-10G
MX25L6435EZNI-10G
MX25L6435EZNI-10G
MX25L6435EZNI-10G
MX25L6435EZNI-10G
MX25L6435EZ2I-10G
MX25L6435EZ2I-10G
MX25L6435EZ2I-10G
MX25L6435EZ2I-10G
MX25L6435EXCI-10G
MX25L6435EXCI-10G
MX25L6435EXCI-10G
MX25L6435EXCI-10G
P/N: AN0260
Micron Part No.
N25Q064A13ESE40
N25Q064A23ESE40
N25Q064A33ESE40
N25Q064A43ESE40
N25Q064A13ESF40
N25Q064A23ESF40
N25Q064A33ESF40
N25Q064A43ESF40
N25Q064A13EF640
N25Q064A23EF640
N25Q064A33EF640
N25Q064A43EF640
N25Q064A13EF840
N25Q064A23EF840
N25Q064A33EF840
N25Q064A43EF840
N25Q064A13E1440
N25Q064A23E1440
N25Q064A33E1440
N25Q064A43E1440
Package
8-SOP
8-SOP
8-SOP
8-SOP
16-SOP
16-SOP
16-SOP
16-SOP
8-WSON
8-WSON
8-WSON
8-WSON
8-WSON
8-WSON
8-WSON
8-WSON
24-TFBGA
24-TFBGA
24-TFBGA
24-TFBGA
12
Dimension
209 mil
209 mil
209 mil
209 mil
300 mil
300 mil
300 mil
300 mil
6x5 mm
6x5 mm
6x5 mm
6x5 mm
8x6 mm
8x6 mm
8x6 mm
8x6 mm
6x4 ba
6x4 ba
6x4 ba
6x4 ba
Note
Hold# pin, Micron XIP
Hold# pin, basic XIP
Reset# pin, Micron XIP
Reset# pin, basic XIP
Hold# pin, Micron XIP
Hold# pin, basic XIP
Reset# pin, Micron XIP
Reset# pin, basic XIP
Hold# pin, Micron XIP
Hold# pin, basic XIP
Reset# pin, Micron XIP
Reset# pin, basic XIP
Hold# pin, Micron XIP
Hold# pin, basic XIP
Reset# pin, Micron XIP
Reset# pin, basic XIP
Hold# pin, Micron XIP
Hold# pin, basic XIP
Reset# pin, Micron XIP
Reset# pin, basic XIP
Ver.1, Sep. 30, 2013
APPLICATION NOTE
Comparing Micron N25Q032A/064A with Macronix MX25L3235E/6435EF
11. Revision History
Revision
1.0
P/N: AN0260
Description
Initial Release
13
Date
September 6, 2013
Ver.1, Sep. 30, 2013
APPLICATION NOTE
Comparing Micron N25Q032A/064A with Macronix MX25L3235E/6435EF
Except for customized products which have been expressly identified in the applicable agreement, Macronix's
products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or
household applications only, and not for use in any applications which may, directly or indirectly, cause death,
personal injury, or severe property damages. In the event Macronix products are used in contradicted to their
target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its
actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or
distributors shall be released from any and all liability arisen therefrom.
Copyright© Macronix International Co., Ltd. 2013. All rights reserved, including the trademarks and tradename
thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit,
Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC,
Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Au-dio, Rich Book, Rich TV, and FitCAM. The names
and brands of third party referred thereto (if any) are for identification purposes only
For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com
P/N: AN0260
14
Ver.1, Sep. 30, 2013
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