ECLinPS Plus Spice Modeling Kit

AND8009/D
ECLinPS Plus™
SPICE Modeling Kit
Prepared by:
Senad Lomigora, Paul Shockman
ON Semiconductor Broadband Applications Engineering
http://onsemi.com
APPLICATION NOTE
Objective
Schematic Information
The objective of ”AND8009 ECLinPS Plus SPICE
Modeling Kit” is to provide sufficient circuit schematic and
SPICE parameter information to allow system level
interconnect modeling of the ECLinPS Plus logic line
devices. The kit is not intended to provide sufficient
information to perform whole device logic modeling.
The kit contains representative input and output
schematics, netlists, and waveforms used for the ECLinPS
Plus devices. The buffer, package, and ESD subcircuit
models may be connected to simulate driver and receiver
interconnect characteristics as shown in Figure 1. A specific
device may be modeled as shown in Figure 2. No Function
Logic modeling is provided.
ESD
PACKAGE
PACKAGE
ESD
BUFFER
INTERCONNECT
BUFFER
INPUT BUFFER
OUTPUT BUFFER
Figure 1. Interconnect Model Template
DEVICE
PACKAGE
BUFFER
BUFFER
ESD
PACKAGE
FUNCTIONAL LOGIC
NOT MODELED
ESD
OUTPUT BUFFER
INPUT BUFFER
Figure 2. DEVICE Model Template
© Semiconductor Components Industries, LLC, 2005
November, 2005 − Rev. 11
1
Publication Order Number:
AND8009/D
AND8009/D
termination models must be added for proper buffer
behavior. Output buffers are shown as differential. When
simulating a single−ended output, both differential outputs
should utilize ESD, package, and termination models to
maintain properly balanced loading.
There are four terminals on all transistor models: Emitter,
Base, Collector, and Substrate (biased to VEE). It should be
noted that circuits can be used single ended by replacing INB
with VBB. Table 1 describes the nomenclature used in the
schematics and netlists.
To simulate a different operating modes all levels, except
VCS, are adjusted with respect to VCC. The VCS is adjusted
with respect to VEE ([VEE + 1.1 V $ 50 mV)
Package
Various simplified input and output package case models
may be found in the Appendix Section, Package RLC.
Specific device package pin models may be modified
according to IBIS model parasitics values.
Table 1. Schematics and Netlist Nomenclature
Parameter
Function Description
VCC
3.3 V FOR LVPECL OR (0 V) FOR LVECL
VCCO
1.6 V − 2.0 V HSTL Output Positive Supply
VCS
Internal Reference Voltage ([VEE + 1.1 V
$ 50 mV)
VHSTL
HSTL Internal Constant Voltage Source
VEE
−3.3 V FOR LVECL OR (0 V) FOR LVPECL
GND
0V
VTT
VCC − 2 V TERMINATION PLANE
IN
TRUE INPUT TO CKT
INB or IN
INVERTED INPUT TO CKT
Q
TRUE OUTPUT OF CKT
QB or Q
INVERTED OUTPUT OF CKT
EP16 Buffer Model
The EP16 interconnect has been completely modeled to
provide a working schematic and output waveforms as
examples of the ECLinPS Plus line. The typical input buffer
may be driven with the output buffer, OBUF01. (See
Figure 28, simplified EP16 SPICE model and Figure 29
typical output waveform.)
SPICE Netlists
The netlists are organized as a group of subcircuits. In
each subcircuit model netlist, the model name is followed by
a list of external node interconnects.
Temperature Compensation Network for 100EP
Input Buffer
The output netlists include temperature compensation
network circuitry for 100EP style output buffers. The circuit
components of the temperature compensation networks are
shown in Figure 29. For simulating 10EP style outputs these
components should either be deleted or commented out of
the subcircuit netlists. Subcircuit models such as the Input
or Output Buffer, Package, Input ESD and Output ESD
should connect to supplies through hierarchical, passed
parameters such as VCC, VEE, etc., for proper simulation and
not separately attached to independent power supplies.
A typical input buffer schematic (Figure 3) and netlist are
representing structures currently in use on most existing
devices in this family. Specific devices may have unique
input buffer models per Table 2. The ESD and package
models should be added for more accurate model behavior.
An internal input pulldown resistor is shown in the ESD
network, Figure 26. Some devices may also display an
internal pullup resistor to VCC. Refer to specific device data
sheet pinout and logic diagram for internal input resistor.
The input buffers may be shown as differential, but may be
modified to represent a single−ended structure by using a
DC bias on the non driven input (at the signal pin common
mode voltage). It is unnecessary to include an ESD or
package model for the VBB pins of the models because VBB
is intended as an internal node for most applications. If VBB
is modeled as an external node it is usually bypassed because
it is a constant voltage, and adding ESD and Package
parameters provide no additional benefit.
SPICE Parameter Information
In addition to the schematics and netlists is a listing of the
SPICE parameters for the transistors referenced in the
schematics and netlists. These parameters represent a typical
device of a given transistor. Varying the typical parameters
will affect the DC and AC performance of the structures; but
for the type of modeling intended by this note, the actual delay
times are not necessary and are not modeled, as a result
variation of the device parameters are meaningless. The
performance levels are more easily varied by other methods
and will be discussed in the next section. The resistors
referenced in the schematics are polysilicon and have no
parasitic capacitance in the real circuit and none is required
in the model. The schematics display the only devices needed
in the SPICE netlists.
Output Buffer
An output buffer schematic and netlist may or may not
require the temperature compensation (TC) network
structure depending on the specific device series. All
100 series devices will require the TC network. A 10 series
device does not include a TC network. ESD, package, and
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2
AND8009/D
• To adjust the VOH:
Modeling Information
The bias drivers for the devices are not detailed since their
circuitry would result in a substantial increase of model
complexity and simulation time. Instead, these internal
reference voltages (VBB, VCS, VHSTL, etc.) should be driven
with ideal constant voltage sources.
The schematics and SPICE parameters will provide a
typical output waveshape, which can be seen in Figures 29,
30, and 31. Simple adjustments can be made to the models
allowing output characteristics to simulate conditions at or
near the corners of the data book specifications. Consistent
cross−point voltages need to be maintained.
Adjust the VOH and VOL level by the same amount by
varying VCC. The output levels will follow changes in
VCC at a 1:1 ratio.
• To adjust the VOL only:
Adjust the VOL level independently of the VOH level by
increasing or decreasing the collector load resistance.
Note that the VOH level will also change slightly due to
a IBASER drop across the collector load resistor. VOL can
be changed by varying the VCS supply, and therefore the
gate current through the current source resistor.
• To adjust rise and fall times:
Summary
The information included in this kit provides adequate
information to run a SPICE level system interconnect
simulation. Device input or output models are presented in
Table 2. For EP and LVEP series devices not listed in Table 2,
consult www.onsemi.com (Technical Support).
Produce the desired rise and fall times output slew rates
by adjusting collector load resistors to change the gates
tail current. The VCS voltage will affect the tail current
in the output differential, which will interact with the
load resistor and collector resistor to determine tr and tf
at the output.
Table 2. ECLinPS PLUS INPUT/OUTPUT SELECTION TABLE
Device
Package A
Package B
Input ESD
Input Buffer
Output Buffer
Output ESD
EP01
8−lead SO
8−lead TSSOP
IN_ESD
TYPICAL INBUF
OBUF01
OUT_ESD
EP05
8−lead SO
8−lead TSSOP
IN_ESD
TYPICAL INBUF
OBUF01
OUT_ESD
EP08
8−lead SO
8−lead TSSOP
IN_ESD
TYPICAL INBUF
OBUF01
OUT_ESD
EP11
8−lead SO
8−lead TSSOP
IN_ESD
TYPICAL INBUF
OBUF01
OUT_ESD
EP14
20−lead TSSOP
N/A
IN_ESD
TYPICAL INBUF
OBUF03
OUT_ESD
EP16
8−lead SO
8−lead TSSOP
IN_ESD
TYPICAL INBUF
OBUF01
OUT_ESD
EP17
20−lead SO
20−lead TSSOP
IN_ESD
TYPICAL INBUF
OBUF06
OUT_ESD
EP29
20−lead TSSOP
N/A
IN_ESD
TYPICAL INBUF
OBUF03
OUT_ESD
EP31
8−lead SO
8−lead TSSOP
IN_ESD
TYPICAL INBUF
OBUF01
OUT_ESD
EP32
8−lead SO
8−lead TSSOP
IN_ESD
TYPICAL INBUF
OBUF01
OUT_ESD
EP33
8−lead SO
8−lead TSSOP
IN_ESD
TYPICAL INBUF
OBUF02
OUT_ESD
EP35
8−lead SO
8−lead TSSOP
IN_ESD
TYPICAL INBUF
OBUF01
OUT_ESD
EP40
20−lead TSSOP
N/A
IN_ESD
TYPICAL INBUF
OBUF09
OUT_ESD
EP51
8−lead SO
8−lead TSSOP
IN_ESD
TYPICAL INBUF
OBUF01
OUT_ESD
EP52
8−lead SO
8−lead TSSOP
IN_ESD
TYPICAL INBUF
OBUF01
OUT_ESD
EP56
20−lead SO
20−lead TSSOP
IN_ESD
TYPICAL INBUF
OBUF04
OUT_ESD
EP57
20−lead TSSOP
N/A
IN_ESD
TYPICAL INBUF
OBUF04
OUT_ESD
EP58
8−lead SO
8−lead TSSOP
IN_ESD
TYPICAL INBUF
OBUF01
OUT_ESD
EP89
8−lead SO
8−lead TSSOP
IN_ESD
TYPICAL INBUF
OBUF05
OUT_ESD
EP90
20−lead TSSOP
N/A
IN_ESD
TYPICAL INBUF
OBUF04
OUT_ESD
EP016
32−lead LQFP
N/A
IN_ESD
TYPICAL INBUF
OBUF02
OUT_ESD
EP016A
32−lead LQFP
N/A
IN_ESD
TYPICAL INBUF
OBUF02
OUT_ESD
EP101
32−lead LQFP
N/A
IN_ESD
TYPICAL INBUF
OBUF06
OUT_ESD
EP105
32−lead LQFP
N/A
IN_ESD
TYPICAL INBUF
OBUF06
OUT_ESD
EP116
32−lead LQFP
N/A
IN_ESD
TYPICAL INBUF
OBUF06
OUT_ESD
EP131
32−lead LQFP
N/A
IN_ESD
TYPICAL INBUF
OBUF02
OUT_ESD
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3
AND8009/D
Table 2. ECLinPS PLUS INPUT/OUTPUT SELECTION TABLE
Device
Package A
Package B
Input ESD
Input Buffer
Output Buffer
Output ESD
EP139
20−lead SO
20−lead TSSOP
IN_ESD
TYPICAL INBUF
OBUF07
OUT_ESD
EP140
8−lead SO
N/A
IN_ESD
TYPICAL INBUF
OBUF09
OUT_ESD
EP142
32−lead LQFP
N/A
IN_ESD
TYPICAL INBUF
OBUF03
OUT_ESD
EP195
32−lead LQFP
N/A
IN_ESD
TYPICAL INBUF
OBUF04
OUT_ESD
EP196
32−lead LQFP
N/A
IN_ESD
TYPICAL INBUF
OBUF04
OUT_ESD
EP210S
32−lead LQFP
N/A
IN_ESD
TYPICAL INBUF
OBUF10
OUT_ESD
EP223
64−lead LQFP
N/A
IN_ESD
TYPICAL INBUF
OBUF11
OUT_ESD
EP445
32−lead LQFP
N/A
IN_ESD
TYPICAL INBUF
OBUF03
OUT_ESD
EP446
32−lead LQFP
N/A
IN_ESD
TYPICAL INBUF
OBUF04
OUT_ESD
EP451
32−lead LQFP
N/A
IN_ESD
TYPICAL INBUF
OBUF03
OUT_ESD
EP809
32−lead LQFP
N/A
IN_ESD
TYPICAL INBUF
OBUF11
OUT_ESD
LVEP11
8−lead SO
8−lead TSSOP
IN_ESD
TYPICAL INBUF
OBUF08
OUT_ESD
LVEP14
20−lead TSSOP
N/A
IN_ESD
TYPICAL INBUF
OBUF03
OUT_ESD
LVEP16
8−lead SO
8−lead TSSOP
IN_ESD
TYPICAL INBUF
OBUF08
OUT_ESD
LVEP17
20−lead TSSOP
24−lead QFN
IN_ESD
TYPICAL INBUF
OBUF03
OUT_ESD
LVEP34
16−lead SO*
16−lead TSSOP*
IN_ESD
TYPICAL INBUF
OBUF03
OUT_ESD
LVEP56
20−lead TSSOP
24−lead QFN
IN_ESD
TYPICAL INBUF
OBUF01
OUT_ESD
LVEP111
32−lead LQFP
N/A
IN_ESD
TYPICAL INBUF
OBUF03
OUT_ESD
LVEP210
32−lead LQFP
N/A
IN_ESD
TYPICAL INBUF
OBUF03
OUT_ESD
LVEP221
52−lead LQFP
N/A
IN_ESD
TYPICAL INBUF
OBUF03
OUT_ESD
LVEP222
52−lead LQFP
N/A
IN_ESD
TYPICAL INBUF
OBUF03
OUT_ESD
LVEP224
64−lead LQFP
N/A
IN_ESD
TYPICAL INBUF
OBUF03
OUT_ESD
NV4N840M
QFN−32
−
−
50 W to VCC
OBUF12
−
NB4L16M
QFN−16
−
−
50 W to VCC
OBUF14
−
NB4N527S
QFN−16
−
−
INBUF02
OBUF13
−
NB4N855S
Micro−10
−
−
INBUF02
OBUF13
−
NB4N507A
SOIC−16
−
−
INBUF04
OBUF15
−
*For package model, please consult manufacturer at www.onsemi.com (Technical Support).
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4
AND8009/D
Netlists and Schematics
0 Vdc
+
−
VCC
0
R1
125
1
R2
125
R3
125
Q7 Q8
Q9
Q10
Q15 Q16
Q17
Q18
TNA TNA
TNA
TNA
TNA TNA
TNA
TNA
3
IN
0
−1.33 Vdc
−
+
4
Q1
Q2
IN
Q4
8
5
TNA
INB
+
Q3
TNA TNA
TNA
INB
0 VCS
−
V1 = −1.7 V
+ V2
V2 = −0.95 V
−
TD = 1 n
−2.1 Vdc
VCS
TR = 0.15 n
TF = 0.15 n
VEE
PW = 1 n
+ V1
PER = 6 n
VEE
−3.3 Vdc −
10
Q11 Q12
Q13
Q14
Q19 Q20
Q21
Q22
TNA TNA
TNA
7
R5
67
TNA
TNA TNA
TNA
9
R6
67
TNA
6
R4
125
Figure 3. Typical INBUF
.SUBCKT TYPICAL INBUF IN INB VCS VEE
Q_Q1
3 IN 5 TNA
Q_Q2
3 IN 5 TNA
Q_Q3
4 INB 5 TNA
Q_Q4
4 INB 5 TNA
Q_Q5
5 VCS 6 TNA
Q_Q6
5 VCS 6 TNA
Q_Q7
1 3 8 TNA
Q_Q8
1 3 8 TNA
Q_Q9
1 3 8 TNA
Q_Q10
1 3 8 TNA
Q_Q11
8 VCS 7 TNA
Q_Q12
8 VCS 7 TNA
Q_Q13
8 VCS 7 TNA
Q_Q14
8 VCS 7 TNA
Q_Q15
1 4 10 TNA
Q_Q16
1 4 10 TNA
Q_Q17
1 4 10 TNA
Q_Q18
1 4 10 TNA
Q_Q19
10 VCS 9 TNA
Q_Q20
10 VCS 9 TNA
Q_Q21
10 VCS 9 TNA
Q_Q22
10 VCS 9 TNA
R_R1
2 1 125
R_R2
3 2 125
R_R3
4 2 125
R_R4
VEE 6 125
R_R5
VEE 7 67
R_R6
VEE 9 67
V_V1
VEE 0 −3.3Vdc
V_V2
VCS 0 −2.1Vdc
V_IN
IN 0 −1.33Vdc
V_VCC
1 0 0Vdc
V_INB
INB 0
+PULSE −1.7V −0.95V 1n 0.15n 0.15n 1n 6n
.END TYPICAL INBUF
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5
AND8009/D
LVPECL OUTPUT Buffer OBUF01
VCC
R2
120
R1
120
ESD
Q10
TNC
Q11
TNC
Q1
Q2
TNB
TND TND
Q3
INTD
Q4
TNB
5
Q6
TND
Q5
TND
8 SOIC PKG
VCC
D3
ESDM
INTDb
D1
ESDS
D2
ESDS
D4
ESDM
D5
ESDM
R12
.154
L1
2.17nH
71
D6
ESDM
9
VEE
VEE
VCC
Q7
Q8
Q9
TND
TND
TNB
4
R3
T1
C4
.364p
VEE
VCS
4 NS
Q
2
6
D13
ESDM
28
VEE
D11
ESDS
D12
ESDS
D14
ESDM
D15
ESDM
R13
.154
L2
2.17nH
81
D16
ESDM
4 NS
Qb
2
T2
10
C5
.364p
VEE
VEE
VEE
VCC
INPUT Buffer
Resistor Network
R117
333
Die Pad
ESD
VCC
16 QFN PKG
R107
.1
D
151
L101
.8nH
R1011
50
R1010
50
Db
R111
1.25K
17
C105
19
R109
1.25K
.09p
VT PINS
VTT
2
VCC2
R108
.1
161
L102
.8nH
VCC
C107
.364p
D111
ESDS
C106
.364p
D112
ESDM
VEE
VEE
2
18
20
C104
R112
1.25K
.09p
23
21
Q101
TNE
VCC2
C108
.364p
D113
ESDM
R118
244
VEE
VEE
INTDb
+
+
VCC
3.3Vdc −
+
0
VTT
VEE
+
VCS2
.95Vdc −
VCS
1.07Vdc −
0
VCS2
VTT
1.3Vdc −
0
0
0
V1 = 2.35
V2 = 1.95
TD = 1n
TR = 0.165n
TF = 0.165n
PW = 0.585n
PER = 1.5n
Figure 4.
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6
TNE
27
22
LVPECL OUTPUT BUFFER Internal Stimulus
(666.6 MHz)
VCS
Q104
Q105
TNE
VCS2
D114 R114
ESDS
92
LVPECL SUPPLIES
VCC
24
Q103
Q102
TNE
TNE
26
C109
.364p
VEE
VCC
VEE
R113
92
R115
333
VEE
VCC2
R110
1.25K
25
+
−
INTDb
0
INTD
V1 = 1.95
V2 = 2.35
TD = 1n
TR = 0.165n
TF = 0.165n
PW = 0.585n
PER = 1.5n
+
−
INTD
0
R116
333
AND8009/D
* OBUF01 driving INBUF02
V_INTD
INTD 0 +PULSE 2.35 1.95 1n 0.165n 0.165n 0.585n 1.5n
V_INTDb
INTDB 0 +PULSE 1.95 2.35 1n 0.165n 0.165n 0.585n 1.5n
V_VCC
$G_VCC 0 3.3Vdc
V_VCS
$G_VCS 0 1.07Vdc
V_VCS2
$G_VCS2 0 .95Vdc
V_VTT
$G_VTT 0 1.3Vdc
.SUBCKT OBUF01 INTD INTDb VCC VCS VEE VTT D DB
C_C4
0 9 .364p
C_C5
0 10 .364p
D_D1
5 $G_VCC ESDS
D_D2
5 $G_VCC ESDS
D_D3
0 5 ESDM
D_D4
0 5 ESDM
D_D5
0 5 ESDM
D_D6
0 5 ESDM
D_D11
6 $G_VCC ESDS
D_D12
6 $G_VCC ESDS
D_D13
0 6 ESDM
D_D14
0 6 ESDM
D_D15
0 6 ESDM
D_D16
0 6 ESDM
L_L1
7 9 2.17nH
L_L2
8 10 2.17nH
Q_Q1
2 INTD 1 TNB
Q_Q2
2 INTD 1 TND
Q_Q3
2 INTD 1 TND
Q_Q4
3 INTDB 1 TNB
Q_Q5
3 INTDB 1 TND
Q_Q6
3 INTDB 1 TND
Q_Q7
1 $G_VCS 4 TND
Q_Q8
1 $G_VCS 4 TND
Q_Q9
1 $G_VCS 4 TNB
Q_Q10
$G_VCC 2 6 TNC
R_R1
2 $G_VCC 120
R_R2
3 $G_VCC 120
R_R3
0 4 28
R_R12
5 7 .154
R_R13
6 8 .154
T_T1
9 0 D 0 Z0=50 TD=4000ps
T_T2
10 0 DB 0 Z0=50 TD=4000ps
.END OBUF01
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AND8009/D
.SUBCKT INBUF02 D DB VCC VCS VEE
C_C104
0 18 .09p
C_C105
0 17 .09p
C_C106
0 19 .364p
C_C107
19 $G_VCC2 .364p
C_C108
0 20 .364p
C_C109
20 $G_VCC2 .364p
D_D111
19 $G_VCC ESDS
D_D112
0 19 ESDM
D_D113
0 20 ESDM
D_D114
20 $G_VCC2 ESDS
L_L101
15 17 .8nH
L_L102
16 18 .8nH
Q_Q101
23 21 26 TNE
Q_Q102
23 21 26 TNE
Q_Q103
24 22 26 TNE
Q_Q104
24 22 26 TNE
Q_Q105
26 $G_VCS2 27 TNE
Q_Q11
$G_VCC 3 5 TNC
R_R107
D 15 .1
R_R108
DB 16 .1
R_R109
19 17 1.25K
R_R110
18 20 1.25K
R_R111
19 $G_VCC 1.25K
R_R112
$G_VCC 20 1.25K
R_R113
19 21 92
R_R114
22 20 92
R_R115
23 25 333
R_R116
24 25 333
R_R117
25 $G_VCC 333
R_R118
0 27 244
R_R1010
$G_VTT DB 50
R_R1011
D $G_VTT 50
.END INBUF02
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AND8009/D
INBUF04 INPUT BUFFER
INPUT Buffer
VCC
Resistor
Network
ESD
16 SOIC PKG
VCC
VCC
100 ps Delay
T1
R101
.154
OE
L101
2 1
2.17nH
2
D101
ESDS
3
D102
C101
ESDM
.364p
VCC
D103 R104
ESDS 92
3.300V
R102
C102
37.5K
.364p
4
R103
ESDM
R106
8160
8160
5
6
Q101
Q103
TNE
TNE
Q102
.364p
7
688.8mV
TNE
0
0
R105
C103
D104
75K
0
73.48uA
3.593pA
Die Pad
0
0
TTLREF
1.500V
VCS
Q104
TNE
1.050uA
8
−75.00uA
612.0mV
R107
8160
0
OE LVTTL INPUT BUFFER
Stimulus (100 MHz)
OPERATIONAL SUPPLIES
VCC
TTLREF
VCS
OE
+
+
+
VCS
1.427Vdc −
TTLREF
−
1.5Vdc
VCC
−
3.3Vdc
0
0
0
V1 = 0.05
V2 = 3.25
TD = 1n
TR = 2n
TF = 2n
PW = 3n
PER = 10n
Figure 5. INBUF04 Input Buffer
NETLIST for INBUF04
V_OE
OE 0 PULSE 0.05 3.25 1n 2n 2n 3n 10n
V_TTLREF $G_TTLREF 0 1.5Vdc
V_VCC
$G_VCC 0 3.3Vdc
V_VCS
$G_VCS 0 1.427Vdc
SUBCKT INBUF04
C_C101
0 3 .364p
C_C102
4 $G_VCC .364p
C_C103
0 4 .364p
D_D101
3 $G_VCC ESDS
D_D102
0 3 ESDM
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9
OE
+
−
0
AND8009/D
D_D103
3 $G_VCC ESDM
D_D104
0 3 ESDS
L_L101
2 3 2.17nH
Q_Q101
5 4 7 TNE
Q_Q102
4 4 $G_TTLREF TNE
Q_Q103
6 $G_TTLREF 7 TNE
Q_Q104
7 $G_VCS 8 TNE
R_R101
1 2 .154
R_R102
4 $G_VCC 37.5K
R_R103
4 0 75K
R_R104
3 4 92
R_R105
5 $G_VCC 8160
R_R106
6 $G_VCC 8160
R_R107
0 8 8160
T_T1
OE 0 1 0 Z0=50 TD=100ps
END INBUF04
3.48V
3.00V
2.00V
1.00V
0V
−0.43V
20.2ns
24.0ns
V(R101:1)
28.0ns
32.0ns
36.0ns
Time
Figure 6. Typical LVCMOS Driving INBUF04 Input Buffer at 100 MHz
http://onsemi.com
10
40.0ns
AND8009/D
TC Network
for 100EP
VCC
R1
120
283 W
2
IN
+
V1 = −0.95
V2 = −1.5
TD = 1 n
TR = 0.165 n
TF = 0.165 n
PW = 0.585 n
PER = 1.5 n
Q1
TNB
Q2
TND
+
R2
120
TNA
TNA
Q3
TND
Q10
TNC
Q4
TND
Q5
TND
Q6
TNB
INB
Q
IN
−
1
Q7
TND
0
+
−2.22 Vdc
−
Q8
TND
VCS
0
+
Q9
TNB
INB
−
V1 = −1.5
V2 = −0.95
TD = 1 n
TR = 0.165 n
TF = 0.165 n
PW = 0.585 n
PER = 1.5 n
R3
28
+
−3.3 Vdc
−
−
Q11
TNC
3
VEE
QB
4
5
R4
50
0
R5
50
VTT
+
−2 Vdc
−
VTT
0
0
Termination
Figure 7. OBUF01
.SUBCKT OBUF01 IN INB VCS VCC VEE VTT
Q_Q1
2 IN 1 TNB
Q_Q2
2 IN 1 TND
Q_Q3
2 IN 1 TND
Q_Q4
3 INB 1 TND
Q_Q5
3 INB 1 TND
Q_Q6
3 INB 1 TNB
Q_Q7
1 VCS 10 TND
Q_Q8
1 VCS 10 TND
Q_Q9
1 VCS 10 TNB
Q_Q10
VCC 2 5 TNC
Q_Q11
VCC 3 4 TNC
R_R1
2 VCC 120
R_R2
3 VCC 120
R_R3
VEE 10 28
R_R4
VTT 4 50
R_R5
VTT 5 50
V_IN
IN 0
+PULSE −0.95 −1.5 1n 0.165n 0.165n 0.585n 1.5n
V_INB
INB 0
+PULSE −1.5 −0.95 1n 0.165n 0.165n 0.585n 1.5n
V_VCC
VCC 0 0Vdc
V_VEE
VEE 0 −3.3Vdc
V_VTT
VTT 0 −2Vdc
V_VCS
VCS 0 −2.22Vdc
.END OBUF01
http://onsemi.com
11
VCC
0 Vdc
0
AND8009/D
TC Network
for 100EP
VCC
VCC +
−
0 Vdc
R1
240
0
283 W
2
IN
V1 = −0.95
V2 = −1.55
TD = 1 n
TR = 0.158 n
TF = 0.196 n
PW = 0.573 n
PER = 1.5 n
+
R2
240
TNA
TNA
Q3
TNC
INB
Q2
TNB
Q1
TNB
Q4
TNC
3
5
INB
0
V1 = −1.55
V2 = −0.95
TD = 1 n
TR = 0.158 n
TF = 0.196 n
PW = 0.573 n
PER = 1.5 n
+
−
0
1
R4
50
VTT
IN
−
QB
4
Q5
TNB
−2 Vdc
+
R5
50
VTT
−
6
R3
56
+
−2.2 Vdc
+ VEE
−3.3 Vdc
− VEE
0
Figure 8. OBUF02
.SUBCKT OBUF02 IN INB VCC VCS VEE VTT
Q_Q1
2 IN 5 TNB
Q_Q2
3 INB 5 TNB
Q_Q3
VCC 2 4 TNC
Q_Q4
VCC 3 1 TNC
Q_Q5
5 VCS 6 TNB
R_R1
2 VCC 240
R_R2
3 VCC 240
R_R3
VEE 6 56
R_R4
VTT 4 50
R_R5
VTT 1 50
V_IN
IN 0
+PULSE −0.95 −1.55 1n 0.158n 0.196n 0.573n 1.5n
V_INB
INB 0
+PULSE −1.55 −0.95 1n 0.158n 0.196n 0.573n 1.5n
V_VCC
VCC 0 0Vdc
V_VEE
VEE 0 −3.3Vdc
V_VTT
VTT 0 −2Vdc
V_VCS
VCS 0 −2.2Vdc
.END OBUF02
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12
−
0
VCS
0
Q
Termination
AND8009/D
TC Network
for 100EP
VCC
VCC
+
R1
245
0 Vdc −
0
V1 = −0.95
V2 = −1.5
TD = 1 n
TR = 0.195 n
TF = 0.195 n
PW = 0.555 n
PER = 1.5 n
+
283 W
2
IN
R2
245
TNA
Q1
TNB
TNA
Q4
TNC
3
Q3
TNC
INB
Q2
TNB
1
QB
4
R4
50
IN
+
V1 = −1.5
V2 = −0.95
TD = 1 n
TR = 0.195 n
TF = 0.195 n
PW = 0.555 n
PER = 1.5 n
R5
50
VTT
−
0
Q
INB
−
Q5
TNB
−2 Vdc
5
R3
69
0
−3.3 Vdc
+
−
VTT
−
+
−2.17 Vdc
VEE
VEE
0
Figure 9. OBUF03
.SUBCKT OBUF03 IN INB VCC VCS VEE VTT
Q_Q1
2 IN 1 TNB
Q_Q2
3 INB 1 TNB
Q_Q3
VCC 2 4 TNC
Q_Q4
VCC 3 6 TNC
Q_Q5
1 VCS 5 TNB
R_R1
2 VCC 245
R_R2
3 VCC 245
R_R3
VEE 5 69
R_R4
VTT 4 50
R_R5
VTT 6 50
V_IN
IN 0
+PULSE −0.95 −1.5 1n 0.195n 0.195n 0.555n 1.5n
V_INB
INB 0
+PULSE −1.5 −0.95 1n 0.195n 0.195n 0.555n 1.5n
V_VCC
VCC 0 0Vdc
V_VEE
VEE 0 −3.3Vdc
V_VTT
VTT 0 −2Vdc
V_VCS
VCS 0 −2.17Vdc
.END OBUF03
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13
+
−
0
VCS
0
Termination
6
AND8009/D
TC Network
for 100EP
VCC
VCC
0 Vdc
+
R1
180
−
0
IN
V1 = −0.95
V2 = −1.55
TD = 1 n
TR = 0.165 n
TF = 0.165 n
PW = 0.585 n
PER = 1.5 n
+
Q1
TNB
283 W
1
Q2
TND
R2
180
TNA
TNA
Q3
TND
Q11
TNC
2
Q10
TNC
Q4
TND
Q5
TND
Q6
TNB
INB
Q
QB
IN
5
−
0
+
−2.29 Vdc
−
Q7
TND
Q8
TND
Q9
TNB
+
V1 = −1.55
V2 = −0.95
TD = 1 n
TR = 0.165 n
TF = 0.165 n
PW = 0.585 n
PER = 1.5 n
6
VCS
R3
30
0
+
−3.3 Vdc
−
INB
−
3
R4
50
0
R5
50
VTT
+
−2 Vdc
VEE
4
VTT
−
0
0
Termination
Figure 10. OBUF04
.SUBCKT OBUF04 IN INB VCS VCC VEE VTT
Q_Q1
1 IN 5 TNB
Q_Q2
1 IN 5 TND
Q_Q3
1 IN 5 TND
Q_Q4
2 INB 5 TND
Q_Q5
2 INB 5 TND
Q_Q6
2 INB 5 TNB
Q_Q7
5 VCS 6 TND
Q_Q8
5 VCS 6 TND
Q_Q9
5 VCS 6 TNB
Q_Q10
VCC 1 4 TNC
Q_Q11
VCC 2 3 TNC
R_R1
1 VCC 180
R_R2
2 VCC 180
R_R3
VEE 6 20
R_R4
VTT 3 50
R_R5
VTT 4 50
V_IN
IN 0
+PULSE −0.95 −1.55 1n 0.165n 0.165n 0.585n 1.5n
V_INB
INB 0
+PULSE −1.55 −0.95 1n 0.165n 0.165n 0.585n 1.5n
V_VCC
VCC 0 0Vdc
V_VEE
VEE 0 −3.3Vdc
V_VTT
VTT 0 −2Vdc
V_VCS
VCS 0 −2.29Vdc
.END OBUF04
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14
AND8009/D
TC Network
for 100EP
VCC
VCC
0 Vdc
+
R1
250
−
0
IN
V1 = −0.95
V2 = −1.5
TD = 1 n
TR = 0.165 n
TF = 0.165 n
PW = 0.585 n
PER = 1.5 n
+
Q1
TNB
Q13
TNC
2
283 W
1
Q2
TND
R2
250
TNA
TNA
Q3
TND
Q14
TNC
Q4
TND
Q5
TND
INB
Q6
TNB
Q
−
0
+
−
QB
IN
Q7
TND
Q8
TND
Q9
TND
Q10
TNB
Q11
TNB
Q12
TNB
−
VEE
0
Figure 11. OBUF05
.SUBCKT OBUF05 IN INB VCS VCC VTT VEE
Q_Q1
1 IN 5 TNB
Q_Q2
1 IN 5 TND
Q_Q3
1 IN 5 TND
Q_Q4
2 INB 5 TND
Q_Q5
2 INB 5 TND
Q_Q6
2 INB 5 TNB
Q_Q7
5 VCS 6 TND
Q_Q8
5 VCS 6 TND
Q_Q9
5 VCS 6 TND
Q_Q10
5 VCS 6 TNB
Q_Q11
5 VCS 6 TNB
Q_Q12
5 VCS 6 TNB
Q_Q13
VCC 2 3 TNC
Q_Q14
VCC 1 4 TNC
R_R1
1 VCC 285
R_R2
2 VCC 285
R_R3
VEE 6 38
R_R4
VTT 3 50
R_R5
VTT 4 50
V_IN
IN 0 −1.33Vdc
+PULSE −0.95 −1.5 1n 0.165n 0.165n 0.585n 1.5n
V_INB
INB 0
+PULSE −1.5 −0.95 1n 0.165n 0.165n 0.585n 1.5n
V_VEE
VEE 0 −3.3Vdc
V_VCC
VCC 0 0Vdc
V_VTT
VTT 0 −3Vdc
V_VCS
VCS 0 −2.25Vdc
.END OBUF05
http://onsemi.com
15
3
4
R4
50
V1 = −1.5
V2 = −0.95
TD = 1 n
TR = 0.165 n
TF = 0.165 n
PW = 0.585 n
PER = 1.5 n
R3
36
+
−3.3 Vdc
−
INB
0
6
−2.25 Vdc
VCS
0
+
5
R5
50
VTT
+
−3 Vdc
−
VTT
0
Termination
AND8009/D
TC Network
for 100EP
VCC
VCC
0 Vdc
+
R1
177
−
0
IN
+
V1 = −0.95
V2 = −1.5
TD = 1 n
TR = 0.165 n
TF = 0.165 n
PW = 0.585 n
PER = 1.5 n
Q7
TNC
2
283 W
1
Q1
TNB
R2
177
TNA
TNA
Q8
TNC
Q2
TND
Q3
TND
IN
Q4
TNB
INB
Q
QB
6
−
0
Q5
TND
+
−2.25 Vdc
−
INB
−
R3
37.5
+
−3.3 Vdc
−
VEE
0
0
V1 = −1.5
V2 = −0.95
TD = 1 n
TR = 0.165 n
TF = 0.165 n
PW = 0.585 n
PER = 1.5 n
Figure 12. OBUF06
.SUBCKT OBUF06 IN INB VCC VCS VEE VTT
Q_Q1
1 IN 6 TNB
Q_Q2
1 IN 6 TND
Q_Q3
2 INB 6 TND
Q_Q4
2 INB 6 TNB
Q_Q5
6 VCS 5 TND
Q_Q6
6 VCS 5 TNB
Q_Q7
VCC 2 3 TNC
Q_Q8
VCC 1 4 TNC
R_R1
1 VCC 177
R_R2
2 VCC 177
R_R3
VEE 5 37.5
R_R4
VTT 3 50
R_R5
VTT 4 50
V_IN
IN 0
+PULSE −0.95 −1.5 1n 0.165n 0.165n 0.585n 1.5n
V_INB
INB 0
+PULSE −1.5 −0.95 1n 0.165n 0.165n 0.585n 1.5n
V_VEE
VEE 0 −3.3Vdc
V_VCC
VCC 0 0Vdc
V_VTT
VTT 0 −2Vdc
V_VCS
VCS 0 −2.25Vdc
.END OBUF06
http://onsemi.com
16
3
4
R4
50
5
VCS
0
+
Q6
TNB
R5
50
VTT
+
−2 Vdc
VTT
−
0
Termination
AND8009/D
TC Network
for 100EP
1
VCC
+
R1
245
0 Vdc −
0
IN
6
R2
245
TNA
283 W
2
+
11
TNA
Q1
Q3
TNC
Q2
TNB
V1 = −0.95
V2 = −1.5
TD = 1 n
TR = 0.195 n
TF = 0.195 n
PW = 0.555 n
PER = 1.5 n
Q4
TNC
TNB
3
QB
IN
INB
−
10
+
INB
0
R4
50
13
R3
55
−
+
−3.3 Vdc
−
5
7
8
9
Q5
TNB
0
V1 = −1.5
V2 = −0.95
TD = 1 n
TR = 0.195 n
TF = 0.195 n
PW = 0.555 n
PER = 1.5 n
Q
R5
50
4
+
−2.22 Vdc
VEE
0
Figure 13. OBUF07
.SUBCKT OBUF07
Q_Q1
2 6 3 TNB
Q_Q2
11 10 3 TNB
Q_Q3
1 2 8 TNC
Q_Q4
1 11 7 TNC
Q_Q5
3 9 13 TNB
R_R1
2 1 245
R_R2
11 1 245
R_R3
5 13 55
R_R4
4 8 50
R_R5
4 7 50
V_IN
6 0
+PULSE −0.95 −1.5 1n 0.195n 0.195n 0.555n 1.5n
V_INB
10 0
+PULSE −1.5 −0.95 1n 0.195n 0.195n 0.555n 1.5n
V_VEE
5 0 −3.3Vdc
V_VCC
1 0 0Vdc
V_VTT
4 0 −2Vdc
V_VCS
9 0 −2.22Vdc
.END OBUF07
http://onsemi.com
17
−
+
VCS
0
−2 Vdc
VTT
−
0
Termination
AND8009/D
TC Network
for 100EP
VCC
VCC
0 Vdc
+
R1
175
−
0
IN
+
Q2
TND
Q11
TNC
2
283 W
1
Q1
TNB
R2
175
TNA
TNA
Q3
TND
Q10
TNC
Q4
TND
Q5
TND
Q6 INB
TNB
Q
QB
INB
V1 = −0.95
−
V2 = − 1.5
TD = 1 n
TR = 0.195 n
0
TF = 0.195 n
PW = 0.555 n
PER = 1.5 n
5
+
−2.36
Vdc −
Q7
TND
Q8
TND
Q9
TNB
+
6
VCS
V1 = −1.5
V2 = − 0.95
TD = 1 n
TR = 0.195 n
TF = 0.195 n
PW = 0.555 n
PER = 1.5 n
R3
17
0
+
−3.3 Vdc
−
VEE
0
INB
−
3
4
R4
50
0
R5
50
VTT
+
−2 Vdc
−
V2
0
Termination
Figure 14. OBUF08
.SUBCKT OBUF08 IN INB VCC VCS VEE VTT
Q_Q1
1 IN 5 TNB
Q_Q2
1 IN 5 TND
Q_Q3
1 IN 5 TND
Q_Q4
2 INB 5 TND
Q_Q5
2 INB 5 TND
Q_Q6
2 INB 5 TNB
Q_Q7
5 VCS 6 TND
Q_Q8
5 VCS 6 TND
Q_Q9
5 VCS 6 TNB
Q_Q10
VCC 1 4 TNC
Q_Q11
VCC 2 3 TNC
R_R1
1 VCC 175
R_R2
2 VCC 175
R_R3
VEE 6 17
R_R4
VTT 3 50
R_R5
VTT 4 50
V_INB
INB 0
+PULSE −1.5 −0.95 1n 0.195n 0.195n 0.555n 1.5n
V_IN
IN 0
+PULSE −0.95 −1.5 1n 0.195n 0.195n 0.555n 1.5n
V_VEE
VEE 0 −3.3Vdc
V_VTT
VTT 0 −2Vdc
V_VCS
VCS 0 −2.36Vdc
V_VCC
VCC 0 0Vdc
.END OBUF08
http://onsemi.com
18
AND8009/D
TC Network
for 100EP
VCC
VCC
+
3.3 Vdc
R1
61.25
−
0
IN
IN
Q1
TNB
+
V1 = 1.2
−
V2 = 1
TD = 1 n
0
TR = 0.13 n
TF = 0.13 n
1.25
PW = 0.5 n
Vdc
PER = 1.26 n
R2
61.25
TNA
1
Q8
TNC
2
283 W
TNA
Q9
TNC
Q2
TND
Q3
TND
Q4 INB
TNB
5
6
R4
4
R5
4
Q
QB
3
VCS Q5
TND
+
−
Q6
TND
Q7
TND
+
V1 = 1
V2 = 1.2
TD = 1 n
TR = 0.13 n
TF = 0.13 n
PW = 0.5 n
PER = 1.26 n
4
VCS
0
R3
14
VEE
0
INB
−
R6
50
0
R7
50
VTT
+
1.3
Vdc −
VTT
0
Figure 15. OBUF09
.SUBCKT OBUF09 IN INB VCC VCS VTT VEE Q QB
Q_Q1
1 IN 3 TNB
Q_Q2
1 IN 3 TND
Q_Q3
2 INB 3 TND
Q_Q4
2 INB 3 TNB
Q_Q5
3 VCS 4 TND
Q_Q6
3 VCS 4 TND
Q_Q7
3 VCS 4 TND
Q_Q8
VCC 2 5 TNC
Q_Q9
VCC 1 6 TNC
R_R1
1 VCC 61.25
R_R2
2 VCC 61.25
R_R3
VEE 4 14
R_R4
Q 5 4
R_R5
QB 6 4
R_R6
VTT Q 50
R_R7
VTT QB 50
V_INB
INB 0
+PULSE 1 1.2 1n 0.13n 0.13n 0.5n 1.26n
V_IN
IN 0
+PULSE 1.2 1 1n 0.13n 0.13n 0.5n 1.26n
V_VCS
VCS 0 1.25Vdc
V_VCC
VCC 0 3.3Vdc
V_VTT
VTT 0 1.3Vdc
.END OBUF09
http://onsemi.com
19
Termination
AND8009/D
VCC
2.5 +
VCC
R6
90
1
−
0
R1
280
TC Network
for 100EP
TNA
IN
+
V1 = 1.7
−
V2 = 1.5
TD = 1 n
0
TR = 0.1 n
TF = 0.1 n
PW = 1 n
PER = 2.2 n
Q3
TNC
Q1
TNB
Q4
TNC
2
283 W
3
IN
R2
280
TNA
Q2
TND
4
R4
100
INB
INB
+
V1 = 1.5
−
V2 = 1.7
TD = 1 n
0
TR = 0.1 n
TF = 0.1 n
PW = 1 n
PER = 2.2 n
Q
QB
Termination
Q5
TNB
Q6
TNB
5
R3
74
6
R5
13
7
R7
13
VEE
+
−
VCS
0.99
Vdc
+
−
VCS
0
Figure 16. OBUF10
.SUBCKT OBUF10 IN INB VCC VCS VEE Q QB
Q_Q1
3 IN 4 TNB
Q_Q2
2 INB 4 TNB
Q_Q3
VCC 3 QB TNC
Q_Q4
VCC 2 Q TNC
Q_Q5
4 VCS 5 TNB
Q_Q6
QB VCS 6 TNB
Q_Q7
Q VCS 7 TNB
R_R1
3 1 295
R_R2
2 1 295
R_R3
VEE 5 64.3
R_R4
QB Q 100
R_R5
VEE 6 10
R_R6
1 VCC 61.25
R_R7
VEE 7 10
V_IN
IN 0
+PULSE 1.5 1.7 1n 0.1n 0.1n 1n 2.6n
V_INB
INB 0
+PULSE 1.7 1.5 1n 0.1n 0.1n 1n 2.6n
V_VCC
VCC 0 2.5
V_VEE
VEE 0 0Vdc
V_VCS
VCS 0 0.99Vdc
.END OBUF10
http://onsemi.com
20
Q7
TNB
0
VEE
0 Vdc
AND8009/D
VHSTL Internal Constant Voltage Source
VHSTL
+
VHSTL
R1
2.0 Vdc −
490
VCCO
R2
490
Q9
Q10
Q11
VCC0+
1.8 Vdc −
Q12
Q8 TNC
TNC
TNC
1
0
2
IN
Q2
Q1
INB
3
IN
TNB
TNB
+
+
V1 = 1.3
V2 = 1.5
−
−
TD = 1.0 n
Q4
Q3
0
4
0
TR = 0.5 n
TF = 0.5 n
+
5
VCS
PW = 5.0 n
PER = 11 n
1.3 Vdc −
TND TND
0
Q5
Q6
TNC
TNC
INB
V1 = 1.5
V2 = 1.3
TD = 1.0 n
TR = 0.5 n
TF = 0.5 n
PW = 5.0 n
PER = 11 n
R3
225
TNC
Q7
TNC
0
TNC
Q
QB
R4
50
R5
50
VTT
0
Termination
0
Figure 17. OBUF11
.SUBCKT OBUF11 IN INB VCCO VHSTL Q QB
Q_Q1
1 IN 3 TNB
Q_Q2
2 INB 3 TNB
Q_Q3
3 4 5 TND
Q_Q4
3 4 5 TND
Q_Q5
VCCO 2 Q TNC
Q_Q6
VCCO 2 Q TNC
Q_Q7
VCCO 2 Q TNC
Q_Q8
VCCO 2 Q TNC
Q_Q9
VCCO 1 QB TNC
Q_Q10
VCCO 1 QB TNC
Q_Q11
VCCO 1 QB TNC
Q_Q12
VCCO 1 QB TNC
R_R1
1 VHSTL 490
R_R2
2 VHSTL 490
R_R3
0 5 225
R_R4
0 Q 50
R_R5
0 QB 50
V_IN
IN 0
+PULSE 1.3 1.5 1n 0.5n 0.5n 5n 11n
V_INB
INB 0
+PULSE 1.5 1.3 1n 0.5n 0.5n 5n 11n
V_VCCO
VCCO 0 1.8Vdc
V_VHSTL
VHSTL 0 2.0Vdc
V_VCS
4 0 1.3Vdc
.END OBUF11
http://onsemi.com
21
AND8009/D
OUTPUT Buffer
VCC
ESD
QFN PKG
VCC
R1
50
R2
50
1
Q1
INTD
D1
ESDS
2
Q4
TNB
Q2
TNB
R3
3
0.4
D2
ESDM
TNB
0.9nH
C4
.300p
VEE
4
Q9
TNB
5
D3
ESDS
Q10
Q11
TNB
TNB
6
8.259mA
8.255mA
R4
Q
2
VEE
12.4
TNB
1
VCC
INTD
Q7
L1
7
Q5
TNB
VCS
R12
12
R5
R13
L2
8
1
0.4
D4
ESDS
Q
2
0.9nH
VEE
C5
.300p
VEE
12
VEE
Receiver
Termination
VCC
T−line delay
1000 ps
T1
D
16 QFN PKG
392.0uA
R1011
50
L101
0.9nH
2
V
1
9
Die Cap
R101
0.4
11
C103
.6p
C101
.300p
VEE
VEE
T2
L102
0.9nH
D
2
R1010
50
7.671mA
VCC
10
R102
0.4
12
C104
.6p
C102
.300p
VEE
2.5 GHz Operational Frequency
3.3 V LVPECL Supply Mode Operation
VCC
VCS
+
+
INTD
VEE
V1 = 2.45
V2 = 2.25
TD = 1n
TR = 0.125n
TF = 0.125n
PW = 0.075n
PER = 0.4n
VCS
0.97Vdc −
16.19mA
0
1
VEE
VEE
VCC
3.3Vdc −
VEE
V
T−line delay
1000 ps
154.9uA
0
0
+
−
INTD
INTD
163.3uA
0
V1 = 2.25
V2 = 2.45
TD = 1n
TR = 0.125n
TF = 0.125n
PW = 0.075n
PER = 0.4n
+
−
INTD
6.381uA
0
Figure 18. OBUF12 Driving Typical Receiver with Termination and 1000 ps T−Line Delay
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22
AND8009/D
Netlist
V_VCC
V_VCS
V_INTD
V_INTDb
for OBUF12 Driving Typical Receiver with Termination and 1000 ps T−line delay
$G_VCC 0 3.3Vdc
$G_VCS 0 0.97Vdc
INTD 0 +PULSE 2.25 2.45 1n 0.125n 0.125n 0.075n 0.4n
INTDB 0 +PULSE 2.45 2.25 1n 0.125n 0.125n 0.075n 0.4n
.SUBCKT OBUF12 VCC VCS VEE INT INTb Q Qb
Q_Q1
1 INTD 3 TNB
Q_Q10 4 $G_VCS 6 TNB
Q_Q11 4 $G_VCS 6 TNB
Q_Q2
1 INTD 3 TNB
Q_Q4
2 INTDB 4 TNB
Q_Q5
2 INTDB 4 TNB
Q_Q7
3 $G_VCS 5 TNB
Q_Q9
3 $G_VCS 5 TNB
D_D1
1 $G_VCC ESDS
D_D2
0 1 ESDM
D_D3
2 $G_VCC ESDS
D_D4
0 2 ESDS
C_C4
0 Q .300p
C_C5
0 QB .300p
R_R1
1 $G_VCC 50
R_R2
2 $G_VCC 50
R_R3
4 3 12.4
R_R4
0 5 12
R_R5
0 6 12
L_L1
7 Q 0.9nH
L_L2
8 QB 0.9nH
.END OBUF12
.SUBCKT RECEIVER VCC VEE D Db
T_T1
Q 0 D 0 Z0=50 TD=1000ps
T_T2
QB 0 DB 0 Z0=50 TD=1000ps
C_C101 0 D .300p
C_C102 0 DB .300p
C_C103 0 11 .6p
C_C104 0 12 .6p
L_L101 9 D 0.9nH
L_L102 10 DB 0.9nH
R_R101 11 9 0.4
R_R1010 DB $G_VCC 50
R_R1011 D $G_VCC 50
R_R102 12 10 0.4
R_R12
1 7 0.4
R_R13
2 8 0.4
.END RECEIVER
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23
AND8009/D
3.287V
3.200V
3.100V
3.000V
2.913V
5.120ns
5.200ns
V(R1010:1)
V(R1011:1)
5.300ns
V(R1011:1)
5.400ns
5.500ns
Time
Figure 19. OBUF12 at 2.5 GHz Operation Frequency; VOUTamp at 360 mVPP; VOH at 3.28 V; VOL at 2.92 V; tr/tf
(20% − 80%) is 86 ps (With Receiver Load)
http://onsemi.com
24
AND8009/D
OUTPUT Buffer
VCC
Q1
TNB
2
INTD
Q2
TNB
Q4
Q3
TNB
TNB
ESD
TERMINATION
INTD
R2
50
VCC
R1
50
3
4
Q5
TNB
INTDX
D2
ESDM
Trace Delay
Trace Delay
RECEIVER: 8 SOIC PKG
1
L1
11
2
T1
Q
.1
R12
V
1000 ps
C4
.9pF
VEE
TNB
VCS
Q9
TNB
8
7
D3
ESDM
VEE
C104
.364p
VEE
V
1
25
Q10
TNB
50 ps
100
D4
ESDS
5
.154
R107
L101
1
2 17
15 2.17nH
R100
VCC
6 R5
13
VEE
VEE
VEE
INTDX
T101
9 .8nH
VEE
Q8
Q6
Q7
TNB TNB
16 QFM PKG
D1
ESDS
.1
R13
L2
12
2
T2
T102
Q
14
10 .8nH
1000 ps
C5
.9pF
VEE
VEE
VEE
50 ps
VEE
VEE
L102
1
2 18
D119
.154 16 2.17nH
.364p
R108
VEE
VEE
R3
50
R4
50
VEE
LVPECL Mode Supplies
VCC
+
VCC
3.3Vdc −
VCS
VCS
.96Vdc
0
+
−
0
INTD
INTD
INTDX
INTDX
VEE
0
V1 = 2.45
V2 = 1.9
TD = .1n
TR = 0.075n
TF = 0.075n
PW = .525n
PER = 1.2n
+
INTD
−
0
V1 = 1.9
V2 = 2.45
TD = .1n
TR = 0.075n
TF = 0.075n
PW = .525n
PER = 1.2n
+
INTD
−
0
V1 = 1.425
V2 = 1.225
TD = .1n
TR = 0.075n
TF = 0.075n
PW = .525n
PER = 1.2n
+
INTDX
−
0
Figure 20. OBUF13 With Termination And Receiver Package Load
SPICE NETLIST for OBUF13:
V_VCC
$G_VCC 0 3.3Vdc
V_VCS
$G_VCS 0 .96Vdc
V_INTD
INTD 0 PULSE 2.45 1.9 .1n 0.075n 0.075n .525n 1.2n
V_INTDb
INTDB 0 PULSE 1.9 2.45 .1n 0.075n 0.075n .525n 1.2n
V_INTDX
INTDX 0 PULSE 1.225 1.425 .1n 0.075n 0.075n .525n 1.2n
V_INTDXb
INTDXB 0 PULSE 1.425 1.225 .1n 0.075n 0.075n .525n 1.2n
.SUBCKT OBUF13
C_C104
0 13 .364p
C_C4
0 11 .9pF
C_C5
0 12 .9pF
C_D119
0 14 .364p
D_D1
3 $G_VCC ESDS
D_D2
0 3 ESDM
D_D3
0 4 ESDM
http://onsemi.com
25
V1 = 1.225
V2 = 1.425
TD = .1n
TR = 0.075n
TF = 0.075n
PW = .525n
PER = 1.2n
+
INTDX
−
0
AND8009/D
D_D4
4 $G_VCC ESDS
L_L1
9 11 .8nH
L_L101
11 13 2.17nH
L_L102
12 14 2.17nH
L_L2
10 12 .8nH
Q_Q1
$G_VCC INTDB 2 TNB
Q_Q10
6 $G_VCS 8 TNB
Q_Q2
$G_VCC INTDB 2 TNB
Q_Q3
$G_VCC INTD 1 TNB
Q_Q4
$G_VCC INTD 1 TNB
Q_Q5
4 INTDX 6 TNB
Q_Q6
4 INTDX 6 TNB
Q_Q7
3 INTDXB 5 TNB
Q_Q8
3 INTDXB 5 TNB
Q_Q9
5 $G_VCS 7 TNB
R_R1
3 1 50
R_R100
Q QB 100
R_R107
9 11 .154
R_R108
10 12 .154
R_R12
3 9 .1
R_R13
4 10 .1
R_R2
4 2 50
R_R3
0 7 50
R_R4
0 8 50
R_R5
5 6 25
T_T1
11 0 Q 0 Z0=50 TD=1000ps
T_T101
Q 0 9 0 Z0=50 TD=50ps
T_T102
QB 0 10 0 Z0=50 TD=50ps
T_T2
12 0 QB 0 Z0=50 TD=1000ps
.END OBUF13
1.400V
1.300V
1.200V
1.100V
1.052V
45.662ns
V(Q)
45.800ns
V(QB)
46.000ns
46.200ns
46.400ns
46.600ns 46.744ns
Time
Figure 21. OBUF13 Typical Waveform at 1.0 GHz with Termination and Receiver Package Load (95ps tr/tf)
http://onsemi.com
26
AND8009/D
OUTPUT Buffer
VCC
ESD
QFN PKG
VCC
R1
50
R2
50
D1
ESDS
1
INTD
Q3
TNB
Q5
TNB
Q4
TNB
Q6
TNB
364.6uA
L1
R3
3
7.819mA
0.9nH
C4
.300p
VEE
Q9
TNB
Q10
TNB
D3
ESDS
Q11
TNB
5
8.635mA
R4
VEE
4
12.4
Q7
TNB
Q12
TNB
R5
R13
D4
ESDS
Q13
TNB
8 1
L2
8.077mA
2
0.9nH
0.4
C5
.300p
VEE
6
8.638mA
12
Q
2
VCC
INTD
VEE
12
VEE
Receiver
Termination
Die Cap
16 QFN PKG
VCC
T−line delay
1000 ps
T1
364.6uA
R1011
50
D
L101
0.9nH
2
V
1
9
R101
0.4
11
C103
.6p
C101
.300p
VEE
VEE
VEE
T−line delay
1000 ps
V
VCS
7 1
0.4
D2
ESDM
Q2
TNB
Q1
TNB
R12
T2
D
L102
0.9nH
2
R1010
50
8.077mA
1
10
R102
0.4
12
C104
.6p
C102
.300p
VEE
VEE
VCC
VEE
3.3 V LVPECL Supply Mode Operation
VCC
+
VCS
4 GHz Operational Frequency
INTD
VEE
V1 = 2.425
V2 = 2.225
TD = 1n
TR = 0.05n
TF = 0.05n
PW = 0.075n
PER = 0.25n
VCS +
0.96Vdc
−
VCC
3.3Vdc −
0
0
0
+
−
INTD
0
INTD
V1 = 2.225
V2 = 2.425
TD = 1n
TR = 0.05n
TF = 0.05n
PW = 0.075n
PER = 0.25n
Figure 22. OBUF14 With Termination And Reciever Package Load
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27
+
−
INTD
0
Q
AND8009/D
NETLIST for OBUF14
V_INTD
INTD 0 +PULSE 2.225 2.425 1n 0.05n 0.05n 0.075n 0.25n
V_INTDb
INTDB 0 +PULSE 2.425 2.225 1n 0.05n 0.05n 0.075n 0.25n
V_VCC
$G_VCC 0 3.3Vdc
V_VCS
$G_VCS 0 0.96Vdc
.SUBCKT OBUF14 VCC VCS INTD INTDb Q Qb
Q_Q1
1 INTD 3 TNB
Q_Q2
1 INTD 3 TNB
Q_Q3
1 INTD 3 TNB
Q_Q4
2 INTDB 4 TNB
Q_Q5
2 INTDB 4 TNB
Q_Q6
2 INTDB 4 TNB
Q_Q7
3 $G_VCS 5 TNB
Q_Q9
3 $G_VCS 5 TNB
Q_Q10
3 $G_VCS 5 TNB
Q_Q11
4 $G_VCS 6 TNB
Q_Q12
4 $G_VCS 6 TNB
Q_Q13
4 $G_VCS 6 TNB
R_R1
1 $G_VCC 50
R_R2
2 $G_VCC 50
R_R3
4 3 12.4
R_R4
0 5 12
R_R5
0 6 12
R_R12
1 7 0.4
R_R13
2 8 0.4
D_D1
1 $G_VCC ESDS
D_D2
0 1 ESDM
D_D3
2 $G_VCC ESDS
D_D4
0 2 ESDS
C_C4
0 Q .300p
C_C5
0 QB .300p
L_L1
7 Q 0.9nH
L_L2
8 QB 0.9nH
.END OBUF14
.SUBCKT RECEIVER VCC VCS D Db
T_T1
Q 0 D 0 Z0=50 TD=1000ps
T_T2
QB 0 DB 0 Z0=50 TD=1000ps
C_C101
0 D .300p
C_C102
0 DB .300p
C_C103
0 11 .6p
C_C104
0 12 .6p
L_L101
9 D 0.9nH
L_L102
10 DB 0.9nH
R_R101
11 9 0.4
R_R102
12 10 0.4
R_R1010
DB $G_VCC 50
R_R1011
D $G_VCC 50
.END RECEIVER
http://onsemi.com
28
AND8009/D
3.277V
3.200V
3.100V
3.000V
2.900V
7.333ns
7.400ns
V(R1010:1)
V(R1011:1)
7.500ns
V(R1011:1)
Time
7.600ns
7.700ns
Figure 23. OBUF14 Typical Output Waveform at 4 GHz Operation; Amplitude 345 mVPP; VOL 2.91,
VOH 3.26 tr/tf 60 ps
http://onsemi.com
29
AND8009/D
3
Q2
TNC
INTD
Q1
TNC
1
D2
ESDS
D3
ESDM
D4
ESDM
7 1
5
L1
2.17nH
2
9
VCC
800 ps Delay
T1
R50
270
VDD
VDD
VDD
VCC
VCC
Q3
TND
Q5
TND
Q4
TND
Q6
TND
Q7
TNB
Q8
TNB
D5
ESDS
4
D7
ESDM
2
R1
9.5
15.05mA
R51
62
Q
C3
.364p
R3
.154
VDD
INTD
VCSD
D1
ESDS
TERMINATION
DRIVER Trace
DRIVER SOIC 16 PKG
V
DRIVER ESD
VCC
D6
ESDS
6
8 1
L2
2.17nH
R2
.154
D8
ESDM
2
10
800 ps Delay
T2
R52
62
Q
R53
270
C4
.364p
VDD
VDD
V
DRIVER − Open Collector (OC)
OUTPUT Buffer
VDD
VDD
VDD
RECEIVER
INPUT Buffer
R101
125
RECEIVER Input Trace
RECEIVER 8 SOIC PKG
VCC
RECEIVER ESD
10 ps Delay
T101
13 1
11
L101
2.17nH
R107
.154
2
15
C101
.364p
14 1
12
R108
.154
2
16
C102
.364p
VDD
VDD
R109
D103
ESDM
D104
ESDM
92
VDD
VCC
VDD
L102
2.17nH
D102
ESDS
17
C103
.6p
TNA
+
3.3Vdc
+
D105
ESDS
D106
ESDS
R110
D107
ESDM
D108
ESDM
92
−
0
Q103
TNA
Q105
TNA
Q106
TNA
23
R104
125
C104
.6p
VDD
INTERNAL STIMULUS SOURCES at 100 MHz
VCSD
INTD
VDD
VCSD
1.01Vdc −
0
Q102
TNA
22
VDD
VDD
+
VCSR
1.05Vdc −
R103
125
20
18
INTD
VCSR
Q101
VDD
OPERATIONAL SUPPLIES
VCC
R102
125
19
VCSR
VDD
10 ps Delay
T102
D101
ESDS
21
RECEIVER
Die Pad
Cap
0
0
V1 = 2.3
V2 = 2.1
TD = 1n
TR = .25n
TF = .25n
PW = 4.75n
PER = 10n
INTD
+
−
0
V1 = 2.1
V2 = 2.3
TD = 1n
TR = .25n
TF = .25n
PW = 4.75n
PER = 10n
INTD
+
−
0
Figure 24. An OBUF15 Open Collector Output Buffer Driving A Typical LVPECL Receiver
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30
Q104
TNA
AND8009/D
NETLIST for OBUF15
V_INTD
INTD 0 PULSE 2.1 2.3 1n .25n .25n 4.75n 10n
V_INTDb
INTDB 0 PULSE 2.3 2.1 1n .25n .25n 4.75n 10n
V_VCC
$G_VCC 0 3.3Vdc
V_VCSD
$G_VCSD 0 1.01Vdc
V_VCSR
$G_VCSR 0 1.05Vdc
SUBCKT OBUF15
Q_Q1
3 INTDB 1 TNC
Q_Q2
4 INTD 1 TNC
Q_Q3
1 $G_VCSD 2 TND
Q_Q4
1 $G_VCSD 2 TND
Q_Q5
1 $G_VCSD 2 TND
Q_Q6
1 $G_VCSD 2 TND
Q_Q7
1 $G_VCSD 2 TNB
Q_Q8
1 $G_VCSD 2 TNB
R_R1
0 2 9.5
D_D1
3 $G_VCC ESDS
D_D2
3 $G_VCC ESDS
D_D3
0 3 ESDM
D_D4
0 3 ESDM
D_D5
4 $G_VCC ESDS
D_D6
4 $G_VCC ESDS
D_D7
0 4 ESDM
D_D8
0 4 ESDM
R_R2
4 8 .154
R_R3
3 7 .154
L_L1
7 9 2.17nH
L_L2
8 10 2.17nH
C_C3
0 9 .364p
C_C4
0 10 .364p
T_T1
9 0 Q 0 Z0=50 TD=800ps
T_T2
10 0 QB 0 Z0=50 TD=800ps
R_R50
Q 0 270
R_R51
Q $G_VCC 62
R_R52
QB $G_VCC 62
R_R53
0 QB 270
.END
SUBCKT RECEIVER
C_C101
0 15 .364p
C_C102
0 16 .364p
C_C103
0 17 .6p
C_C104
0 18 .6p
D_D101
15 $G_VCC ESDS
D_D102
15 $G_VCC ESDS
D_D103
0 15 ESDM
D_D104
0 15 ESDM
D_D105
16 $G_VCC ESDS
D_D106
16 $G_VCC ESDS
D_D107
0 16 ESDM
D_D108
0 16 ESDM
L_L101
13 15 2.17nH
L_L102
14 16 2.17nH
Q_Q101
19 17 22 TNA
Q_Q102
19 17 22 TNA
Q_Q103
20 18 22 TNA
Q_Q104
20 18 22 TND
Q_Q105
22 $G_VCSR 23 TNA
Q_Q106
22 $G_VCSR 23 TNA
R_R101
21 $G_VCC 125
R_R102
19 21 125
R_R103
20 21 125
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31
AND8009/D
R_R104
R_R107
R_R108
R_R109
R_R110
T_T101
T_T102
.END RECEIVER
0 23 125
11 13 .154
12 14 .154
15 17 92
16 18 92
Q 0 11 0 Z0=50 TD=10ps
QB 0 12 0 Z0=50 TD=10ps
2.718V
2.400V
2.000V
1.917V
16.5ns
18.0ns
V(QB)
20.0ns
22.0ns
24.0ns
26.0ns
28.0ns
Time
V(Q)
Figure 25. OBUF15 Output Driving LVPECL Receiver Typical Waveforms at 100 MHz; VOH 1.94 V; VOL 2.68 V; Vamp
736 mV; 199 ps tr/tf at 2.09 V and 2.53 V (20%/80%)
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32
AND8009/D
VCC
RB1
185
*RPU
D1
IN
D4
D5
D2
D6
D7
D3
D8
RB2
185
RPD
75 k
D9
PAD
Pulldown Resistor
VEE
* See device data sheet
Figure 26. Input ESD
.SUBCKT IN_ESD VCC VEE IN PAD
D1
IN
VCC
ESDM
D2
IN
VCC
ESDM
D3
IN
VCC
ESDM
D4
VEE
IN
ESDM
D5
VEE
IN
ESDS
D6
VEE
IN
ESDM
D7
VEE
IN
ESDS
D8
VEE
IN
ESDM
D9
VEE
IN
ESDS
RPD
IN
VEE
75K
RPU
IN
VCC
36.5K
RB1
IN
PAD
185
RB2
IN
PAD
185
.ENDS IN_ESD
VCC
D1
PAD
D3
D4
D2
D5
D6
VEE
Figure 27. Output ESD
.SUBCKT OUT_ESD
D1
OUT
D2
OUT
D3
VEE
D4
VEE
D5
VEE
D6
VEE
.ENDS OUT_ESD
VCC VEE OUT
VCC
ESDM
VCC
ESDM
OUT
ESDM
OUT
ESDS
OUT
ESDM
OUT
ESDS
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33
OUT
AND8009/D
The following is an example of a typical run−deck file which might be used to simulate Figure 28 to produce output waveform
shown in Figure 29.
TYPICAL TEST CIRCUIT
VCC
VEE
VCS
VTT
VIN
VINB
.GROUND
.TRAN
VCC
VEE
VCS
VTT
IN
INB
0
0.2NS
0
0
0
0
0
0
0V
−3.3V
−2.2V
−2.0V
PULSE(−1.7 −0.95 5NS 5NS 5NS 50NS 110NS)
PULSE(−0.95 −1.7 5NS 5NS 5NS 50NS 110NS)
120NS
R1
120
IN
OBUF01
Q3
Q11
TNC
Q4
Q5
Q10
Q6
INB
TND
TNB
−1.33 Vdc
0
TND
Q7
TND
TND
Q8
TND
VCC
TNC
+
QB
TNB
V1 = 1.5 V
V2 = −0.95 V
TD = 1 n
TR = 0.15 n
TF = 0.15 n
PW = 1 n
PER = 6 n
Q9
TND
−
0 Vdc
Q
+
R4
50
−
0
−2 Vdc
TNB
R5
50
+
−
0
R3
28
Termination
125
R2B
125
Q7B
R3B
125
TNA
IN’
Q1B
TNA
Q2B
TNA
−2.2 Vdc
+
−
Q6B
TNA
VCS
−3.3 Vdc
Q3B Q4B
TNA
Q5B
+
−
VEE
0
−
Q2
0
+
Q1
R2
120
TNA
Q8B
TNA
IN’B
Q9B Q10B
TNA
TNA
Q15B Q16B
Q17B Q18B
TNA
TNA
TNA
TNA
TYPICAL
INPUT
BUFFER
TNA
Q11B Q12B
TNA
TNA
R4B
125
Q13B Q14B
TNA
R5B
67
Figure 28. EP16 Buffer
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34
TNA
Q19B Q20B Q21B Q22B
TNA
TNA
TNA
TNA
R6B
67
AND8009/D
−0.865 V
VOH = 932.6 mV
80%
−1.200 V
tr = 174.7 ps
CROSS POINT
Vout
tf = 131.8 ps
20%
−1.600 V
−1.837 V
9.9
VOL = 1720 mV
10.0
10.1
10.2
10.3
10.4
10.5
10.6
Time (ns)
Figure 29. Typical Generic Output Waveform
2.34 V
VOH = 2.281 V
80%
2.20 V
tr = 125.1 ps
CROSS POINT
Vout
tf = 118 ps
2.00 V
20%
1.84 V
1.509
VOL = 1.88 V
1.600
1.700
1.800
1.900
2.000
2.100
Time (ns)
Figure 30. OBUF09 Reduced Swing Output
Waveform (EP40/140)
1.4 V
80%
VOH = 1.42 V
tr = 179 ps
Vout
CROSS POINT
1.2 V
tf = 140 ps
20%
1.0 V
VOL = 0.946 V
4.854 5.000
5.200
5.400
5.600
5.800
6.000
Time (ns)
Figure 31. LVDS Output Waveform (EP210’s)
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35
6.188
AND8009/D
******************
Transistor and Diodes Nominal SPICE Models*
*******************
*****************************************************************************
.MODEL TNA NPN (IS=8.12e−18 BF=192 NF=1 VAF=75.6 IKF=1.49e−02
+ ISE=9.14e−17 NE=2 BR=15.8 VAR=2.76 IKR=2.2e−03 ISC=2.62e−16
+ NC=1.578 RB=327 IRB=4.8e−05 RBM=0.001 RE=10 RC=15 CJE=2.0e−14
+ VJE=.8867 MJE=.2868 TF=9.02e−12 ITF=7.6e−03 XTF=2.8 VTF=3.4 PTF=41.56 TR=1NS
+ CJC=5.6e−15 VJC=.6324 MJC=.3006 XCJC=.3 CJS=4.8e−15 VJS=.4193 MJS=.2563
+ EG=1.119 XTI=3.999 XTB=0.8826 FC=0.9)
*****************************************************************************
.MODEL TNB NPN (IS=2.71e−17 BF=172 NF=1 VAF=71.4 IKF=4.38e−02
+ ISE=1.33e−15 NE=2 BR=17.9 VAR=2.76 IKR=3.0e−03 ISC=2.22e−16
+ NC=1.578 RB=67 IRB=6.47e−05 RBM=0.001 RE=3 RC=4 CJE=5.09e−14
+ VJE=.8867 MJE=.2868 TF=9.02e−12 ITF=2.53e−02 XTF=2.8 VTF=3.4 PTF=41.56 TR=1NS
+ CJC=20.6e−15 VJC=.6324 MJC=.3006 XCJC=.3 CJS=1.7e−14 VJS=.4193 MJS=.2563
+ EG=1.119 XTI=3.999 XTB=0.8826 FC=0.9)
*****************************************************************************
.MODEL TNC NPN (IS=6.55e−17 BF=103 NF=1 VAF=90 IKF=2.91e−01
+ ISE=8.85e−15 NE=2 BR=15.7 NR=1 VAR=3.82 IKR=2.01e−02 ISC=1.48e−15
+ NC=2 RB=10.5 IRB=4.39e−04 RBM=0.29 RE=0.351 RC=9 CJE=3.5e−13
+ VJE=.8167 MJE=.1973 TF=8.99e−12 ITF=1.3e−01 XTF=5.67 VTF=1.86 PTF=41.43 TR=6.405e−10
+ CJC=1.4e−13 VJC=.6401 MJC=.2674 XCJC=1 CJS=9.3e−14 VJS=.5002 MJS=.1706
+ EG=1.135 XTI=4.177 XTB=0.6322 FC=0.961)
*****************************************************************************
.MODEL TND NPN (IS=1.36e−17 BF=180 NF=1 VAF=87.6 IKF=2.19e−02
+ ISE=6.65e−16 NE=2 BR=16.9 VAR=2.76 IKR=1.5e−03 ISC=1.11e−16
+ NC=1.578 RB=136 IRB=3.24e−05 RBM=0.001 RE=6 RC=8 CJE=1.02e−13
+ VJE=.8867 MJE=.2868 TF=9.02e−12 ITF=1.27e−02 XTF=2.8 VTF=3.4 PTF=41.56 TR=1NS
+ CJC=10.3e−15 VJC=.6324 MJC=.3006 XCJC=.3 CJS=9.94e−15 VJS=.4193 MJS=.2563
+ EG=1.119 XTI=3.999 XTB=0.8826 FC=0.9)
*****************************************************************************
.MODEL TNE NPN (IS=2.68e−18 BF=223 NF=1 VAF=56.0 IKF=3.96e−03
+ ISE=3.07e−17 NE=2 BR=13.9 VAR=2.76 IKR=7.23e−04 ISC=6.08e−17
+ NC=1.578 RB=386 IRB=1.3e−05 RBM=0.001 RE=26 RC=28 CJE=6.0e−15
+ VJE=.8867 MJE=.2868 TF=9.02PS ITF=2.6e−03 XTF=2.8 VTF=3.4 PTF=41.56 TR=1NS
+ CJC=3.4e−15 VJC=.6324 MJC=.3006 XCJC=.3 CJS=3.4e−15 VJS=.4193 MJS=.2563
+ EG=1.119 XTI=3.999 XTB=0.8826 FC=0.9)
*****************************************************************************
.MODEL ESDM D (IS=1.55E−14 CJO=160fF RS=12 VJ=.58 M=.25 BV=9)
*****************************************************************************
.MODEL ESDS D (IS=1.55E−14 CJO=29fF VJ=.624 M=.571)
*****************************************************************************
*SPICE MODELS 4.5
http://onsemi.com
36
AND8009/D
APPENDIX: PACKAGE RLC MODELS
Package
R (W)
L (nH)
C (pF)
1.5
0.188
1
SOIC−8
2
TSSOP−8
0.048
1.9
0.089
3
SOIC−20 W
0.136
3.04
0.158
4
TSSOP−20
0.033
1.76
0.98
5
QFN−24
0.055
1.29
0.05
6
LQFP−32
0.67
2.38
0.13
7
LQFP−52
0.88
3.3
0.072
8
LQFP−64
0.10
0.67
0.05
9
QFN−16
0.039
0.75
0.13
10
QFN−32
0.42
1.39
0.142
11
TSSOP−10
0.048
1.9
0.089
12
SOIC−16
0.152
2.714
0.364
13
TSSOP−16
0.044
0.82
0.41
ECLinPS Plus is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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AND8009/D
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