### A Simple DC SPICE Model for the LLC Converter

```AND8255/D
A Simple DC SPICE Model
for the LLC Converter
Prepared by: Christophe Basso
ON Semiconductor
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APPLICATION NOTE
The LLC Topology
Figure 1 shows the structure of this resonant converter. A
50% duty cycle half−bridge delivers high voltage square
waves swinging from 0 to the input voltage Vin to a
resonating circuit. By adjusting the frequency via a
voltage−controlled oscillator (VCO), the feedback loop can
adjust the output level depending on the power demand.
The resonant LLC topology, member of the Series
Resonant Converters (SRC), begins to be widely used in
consumer applications such as LCD TVs or plasma display
panels. In these particular applications, the output power level
ranges from 100 W up to 600 W. Designing an LLC converter
requires to know the evolution of its DC transfer function in
order to properly select the various elements the resonant
circuit is made of. This application note shows us how a
simple SPICE model operated in DC sweep, can help us in
designing an LLC converter using the NCP1395 controller.
Vin
Qb
Vout
Ls
Cs
N:1
Lm
+
C
RL
Q
Figure 1. The LLC Topology Uses a Half−Bridge to Drive the
Resonant Circuit
The resonating circuit is made of a capacitor, Cs, in series
with two inductors, Ls and Lm . One of these inductors, Lm ,
represents the magnetizing inductor of the transformer and
creates one resonating point together with Ls and Cs . We can
quickly see that the reflection of the load over this inductor
will either make it disappear from the circuit (Lm is fully
short−circuited by a reflected RL of low value at heavy load
currents) or will make it stay in series with the series
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 2
inductor Ls in light load conditions. As a result, depending
between a minimum and a maximum:
F max + Fs +
F min +
1
1
2p ǸLsCs
1
2p Ǹ(Ls ) Lm)Cs
(eq. 1)
(eq. 2)
Publication Order Number:
AND8255/D
AND8255/D
The frequency of operation depends on the power
demand. For a low power demand, the operating frequency
is rather high, away from the resonating point. To the
contrary, at high power, the control loop reduces the
switching frequency and approaches one of the resonant
frequency to deliver the necessary amount of current to the
load. The principle of the LLC operation assumes that the
circuit operates close to its resonant frequency. Hence,
sinusoidal variables are in play. Therefore, as the vast
majority of harmonics are removed, we can imagine the
circuit as a bandpass filter for the square wave excitation.
This technique is called First Harmonic Approximation
(FHA) and consists of replacing the square wave input (the
half−bridge signal) by its fundamental value. The peak
fundamental of a 50% duty cycle square wave signal
toggling between 0 and Vin is:
Vfund, peak + 2
p Vin
(eq. 3)
Hence, the equivalent circuit of Figure 2:
Vout
Ls
Cs
N:1
+
Lm
+
C
Vfund
Cs
Ls
RL
+
Vfund
Figure 2. Using FHA, we can draw an equivalent
“sinusoidal” schematic of our LLC converter.
If we want to study our resonant network using FHA, we
must get rid of the diode bridge and find a way to place an
equivalent resistor “seen” from the left side of the bridge.
Figure 3 is the circuit we actually would like to have. If we
closely look at Figure 2, we can see a current−fed structure,
otherwise stated, into a network made of the transformer and
Lm
Figure 3. An equivalent load is reflected
on the primary inductance Lm.
the load. This can be further demonstrated by the direct
connection of the capacitor across the bridge output, without
a smoothing inductor as it is the case with Series Parallel
Resonant converter. This observation will help deriving the
equivalent resistor Rac , as indicated by Figure 4 where we
purposely removed the transformer for the sake of simplicity:
i(v4) in amperes
6.00
4.00
2.00
0
−2.00
Isource
10.0m
Rac
30.0m
50.0m
70.0m
time in seconds
90.0m
Vout
Iout
isource in amperes
Isource
AC
DC
+
C
RL
2.00
1.00
0
−1.00
−2.00
10.0m
30.0m
50.0m
70.0m
time in seconds
Rac
90.0m
Figure 4. A simplified representation helps us to derive Rac in a few
lines of algebra.
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AND8255/D
The upper left corner of Figure 4 represents the AC source delivering current to the equivalent load resistor we are looking
for, Rac . The power delivered by this source is simply the rms current squared multiplied by the resistor:
ǒ
Ǔ
Isource, peak 2
Isource, peak2
Pin + Isource, rms2Rac +
Rac
Rac +
Ǹ2
2
(eq. 4)
The output power can be quickly expressed since the current that flows in RL is the average current of Iout (all the AC current
flows into C). Hence:
Pout + (Iout, avg)2 RL +
peak 2
ǒ2Isource,
Ǔ RL + 4Rp2L Isource, peak2
p
Assuming we have a 100% efficiency, then the input
power equals the output power:
Isource, peak2
4RL
Rac +
Isource, peak2
2
p2
If we now include the transformer as on Figure 1, the final
Rac +
(eq. 6)
8RL
p2
(eq. 7)
2Vin/pi
Cs
Ls
Iout
Io
+
+
Vfund
Vin
8RLN2
p2
(eq. 8)
Figure 3 shows the equivalent FHA schematic. What we
want is to refine this model with all equivalent components:
we must find a relationship between the DC output voltage
actually applied across RL and the DC input voltage Vin .
Figure 5 displays the idea behind this reasoning, again with
the transformer removed for simplicity:
Rac +
(eq. 5)
AC
Rac
Lm
Vout
C
+
DC
RL
Figure 5. We want to find the relationship between the output of our
equivalent network and the real DC output voltage.
The current flowing into Rac is the following:
Io, peak +
Vo, peak
Rac
The final equivalent model looks like the following:
(eq. 9)
2.Vin/pi
Cs
Ls
4.N.Vout/pi
Replacing Rac by its definition (Equation 7):
Io, peak +
Vo, peak p2
8RL
+
Vfund
(eq. 10)
Lm
Rac
The DC voltage applied to the load is nothing else than the
DC component (the averaged value) of the rectified
half−wave Io,peak . Thus:
Iout +
Vo, peak p2 2
Vo, peak p
p+
8RL
4RL
Figure 6. The Final FHA Model of our
LLC Converter
(eq. 11)
Now, the output voltage is simply Equation 11 multiplied
by RL :
Vout +
Vo, peak p
Vo, peak p
RL +
4
4RL
We can see now that if we compute the transfer ratio
between Vout and Vin , several factors will need to appear in
order to get the right levels. Let us start with the transfer ratio
of Figure 6 that can be obtained via the following lines:
(eq. 12)
Therefore, the output voltage obtained across Rac has the
following value, now including the transformer:
V 4N
Vo, peak + out
p
4NVout
p
2Vin +
p
(eq. 13)
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M
(eq. 14)
AND8255/D
Rearranging Equation 14:
Vout
+ 1 M
2N
Vin
M+
(eq. 15)
sLm Ŧ Rac
sLm Ŧ Rac ) sLs ) sC1
(eq. 16)
s
Now, it is time to calculate M…
The brute force result of this module calculation is the following ugly result:
M+
Ǹ
w2 L 2 s
Rac2
2Z02
ac2
)1*R
Z0 +
Where:
1
2
1
) ratio
) ratio
)
2
R
1
ac2Cs2w2
ǸCLss
ratio +
ǸLLms
Lm
Lm ) Ls
2
pCsw2
2Z02
p 2 w2
*L
Rac +
Equation 17 simplifies to a simple impedance divider:
M+
*L
)L
1
p2Cs2w4
8RLN2
p2
2V
Vi + pin
(eq. 17)
Q+
M (Fsw, Rac)
N2RL
Z0
Vo +
4NVout
p
(eq. 18)
Rac +
This represents a design factor when selecting the
magnetizing inductance and the series inductance if no−load
condition can occur. Hence, once the turn−ratio and these
elements has been selected, you can immediately see if the
converter will accept no−load conditions, whatever the
VCO excursion is. Fortunately, the NCP1395 authorizes
skip cycle and will naturally prevent loss of regulation in this
particular case by interrupting the switching frequency as
the feedback loop reaches a user−selectable level.
8RLN2
p2
Figure 7. The output voltage generates a voltage
across Rac . But this voltage is not Vout 0
How do we link the current I crossing Rac to our real
output current flowing through the load? Let us express it
using Ohm’s law:
I+
Assembling Sources for the DC Model
We almost now have eveything needed to start assembling
our Analog Behavioral Modeling sources (ABM) to build
the model. Figure 7 represents the frame of the model where
Rac receives a current proportional to M and the input
voltage:
Vo
4NVout p2N2
2MVi
+
+
p
8RL
Rac
Racp
(eq. 19)
Replacing Vi by Equation 3, we have an updated current
definition:
2V
4MVin
I + 2M pin +
Racp
Racp2
(eq. 20)
We can also replace Rac thus:
I+
4MVin p2
MVin
+
p2 8N2RL
2N2RL
Fsw
Vin
Ffund +
2V (Vin)
p
M (Fsw, Rac)
Vrac
FfundM
+
Out
+
+
V(out)
Rac +
I(Vrac)
2 V(FfundM)
pV(Rac)
Figure 8. The model looks for the current circulating inside Rac and forces
a proportional current on the output node.
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(eq. 21)
AND8255/D
• B5: The error voltage is expressed in V and further
Further to a few experiments on SPICE, we found that
Equation 19 gave better results than Equation 21 in terms of
initial bias point calculation. We thus adopted it for the
model whose final theoretical architecture appears on
Figure 8. We can recognize sources performing the
previously derived equations like the fundamental
amplitude calculation or the output current generator. The
node “out” can directly connect to the load via a transformer
and the Rac value gets calculated via a separated source. Its
result directly enters the M generator to further drive the
final current source. Figure 9 portrays the real SPICE
arrangement using INTUSOFT’s IsSpice. Some precautions
are taken to avoid division by zero during the bias point
calculations. This is “+1u” add on to some terms. Here are
the various sources functions:
•
•
•
•
•
•
M
fsw
B5
Voltage
V(err)*100k
parameters
•
converted to kHz via B5: 1.0 V = 100 kHz
B6: It calculates the fundamental based on a
half−bridge configuration and the input node vin
B1: Elaborates ω from B5
B7: This source calculates Rac according to Equation 7
B3: It is the M parameter as Equation 17 describes it
B2: Calculates the input current drawn from the source
based on the total converter efficiency ETA
B4: The final current source delivering Equation 19
current level
A few parameters need to be passed to get all the
necessary coefficients the above equations require
B3
Voltage
sqrt(1/(V(w)^2*{Ls}^2/(V(Rac)^2+1u)+1−2*{Z0}^2/(V(Rac)^2+1u)+2/{Ratio}+1/{Ratio}^2+
+1/(V(Rac)^2*{Cs}^2*V(w)^2+1u)−2/({Lm}*{Cs}*V(w)^2+1u)−
+2*{Z0}^2/({Lm}^2*V(w)^2+1u)+1/({Lm}^2*{Cs}^2*V(w)^4+1u)+1u))
Ratio=4
Lm=600u
Ls=Lm/Ratio
Cs=33n
N=8
Eta=0.9
pi=3.14159
Z0=sqrt(Ls/Cs)
fund
w
B6
Voltage
V(Vin)*2/{pi}
B1
Voltage
V(Fsw)*2*{pi}
Vrac
out
vin
Rac
1
B2
Current
(I(Vrac)*V(out)/{ETA})/V(vin)
B7
Voltage
B4
Current
(V(M)*V(fund)/(V(Rac)+1u))*2/{pi}
(V(out)/abs(I(Vrac)))*8/({pi}^2+1u)
Figure 9. The Final Model in INTUSOFT’s IsSpice
Based on this configuration, we have encapsulated the
model under a simple symbol and placed in an application
circuit. This is what appears on Figure 10. In this circuit, a
DC source is connected to the error input and generates the
control frequency. Here, 572 mV corresponds to 57.2 kHz.
The parameters column, on the left side, includes the
selected elements for this 24 V/250 W converter operated
from a 380 V input voltage. The various sources are placed
there to display some operating parameters we will need for
the final curve display.
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AND8255/D
X3
LLC
Parameters
Vin=380
Vout = 24V
ÎÎ
Vin
Out
380
2
Rupper=(Vout−2.495)/(2.495/10k)
ÎÎ
Pout =250W
Fmax= 250k
Fmin = 50k
Q=2
Î
Î
Lm=600u
Ratio=4
Ls=Lm/Ratio
Cs=33n
pi=3.14159
N=8
Eta=0.9
M
1.01
ÎÎ
Î
ÎÎ Î
Fs=1/(2*pi*sqrt(Ls*Cs))
Fm=1/(2*pi*sqrt((Ls+Lm)*Cs))
Z0=sqrt(Ls/Cs)
V5
{Fs}
R4
ÎÎ
Î
ÎÎ
ÎÎ
VFoverFs
B4
Voltage
V(f)*100k/{Fs}
67.4
71.5k
V17
{Fm}
Vsweep
572m
AC = 1
Z0
Fs
Fm
32.0k
Vout
C1
2.2m
0.800
B3
Voltage
(V(vout)/{Vin})*2*{N}
vout
24.0
8
FoverFs
VM
3
24.0
f
0.572
192
R1
50m
Error
Vin
{Vin}
Î ÎÎ
Î ÎÎÎÎ
ÎÎ
X2
XFMR
RATIO = 1/N
LLC model
V6
{Z0}
2.30
V4
ÎÎ
FmoverFs
0.447
V7
{Fm/Fs}
Figure 10. The model once encapsulated is ready for the DC sweep.
If we now sweep the source Vsweep from 100 mV (10 kHz)
to 2.0 V (200 kHz) and monitor M (the ratio as defined by
Equation 15) we can check for the model validity to predict
voltage conversion ratios. We can then adjust the ratio
1 vm
8.00
2 vm#a6
3 vm#a7
4 vm#a8
between the magnetizing inductance Lm and the series
inductance Ls and see how M is affected while the quality
ǒ
coefficient Q is varied Q +
Ǔ
N2RL
:
Z0
5 vm#a9
Fs =
Lm
=2
Ls
Plot1
vm, vm#a6, vm#a7, vm#a8, vm#a9 in volts
Q = 10
M=
6.00
2 NVout
Vin
Q=5
1
2 p LC
s s
Z0 =
Ls
Cs
N 2RL
Q=
Z0
4.00
Fsw
Fs
Q=2
Q=1
2.00
1
2
3
4
5
0
Q = 0.5
200m
600m
1.00
vfoverfs in volts
1.40
Figure 11. The transfer function for a ratio between Lm and Ls of 2.
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1.80
AND8255/D
1 vm
3 vm#a2
4 vm#a3
5 vm#a4
Fs =
Lm
=4
Ls
4.50
Plot1
vm, vm#a1, vm#a2, vm#a3, vm#a4 in volts
2 vm#a1
Q = 10
2 NVout
M=
Vin
3.50
Q=5
1
2p LC
s s
Ls
Cs
Z0 =
Q=
N 2R L
Z0
2.50
Fsw
Fs
Q=2
Q=1
1.50
1
2
3
Q = 0.5
500m
4
5
200m
600m
1.00
vfoverfs in volts
1.40
1.80
Figure 12. Same as above, but the ratio is 4.
1 vm
Plot1
vm, vm#a5, vm#a6, vm#a7, vm#a8 in volts
4.00
2 vm#a5
Lm
=6
Ls
3 vm#a6
4 vm#a7
5 vm#a8
Fs =
Q = 10
2 NVout
M=
Vin
3.00
1
2p LC
s s
Z0 =
Q=
Q=5
2.00
Ls
Cs
N 2 RL
Z0
Fsw
Fs
Q=2
Q=1
1.00
1
2
3
4
5
Q = 0.5
0
200m
600m
1.00
vfoverfs in volts
1.40
Figure 13. Same as above, but the ratio is 6.
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1.80
AND8255/D
1 vm
1.60
2 vm#a1
3 vm#a2
4 vm#a3
Lm
= variable
Ls
5 vm#a5
Lm/Ls = 2
Fs =
Lm/Ls = 4
Plot1
vm, vm#a1, vm#a2, vm#a3, vm#a5 in volts
Q=2
1
2p LC
s s
Z0 =
Lm/Ls = 6
Ls
Cs
1.20
N 2R L
Q=
Z0
Lm/Ls = 10
800m
Lm/Ls = 8
4
3
2
1
2 NVout
M=
Vin
5
400m
Fsw
Fs
0
200m
600m
1.00
vfoverfs in volts
1.40
1.80
Figure 14. Conversion ratio for a given quality coefficient (Q = 2) but the ratio is varied from 2 to 10.
•
•
1. As the ratio between the magnetizing inductance
Lm and the series inductance Ls increases, the
transfer ratio between Vin and Vout goes down
(max M = 7 on Figure 11, ratio = 2 and max M =
3.5 on Figure 13, for a ratio of 6).
2. The separation between Fmax and Fmin
(Equations 1 and 2) widens and thus requires a
larger regulation−frequency range:
Figure 11: for Q = 5, we obtain a DM of 1 for a Df of
0.065
Figure 13: for Q = 5, we obtain a DM of 1 for a Df of
1.2
3. From Figure 14, as the ratio increases, the DC gain
flattens and regulating in light load conditions
becomes difficult (weak variation of M versus fsw ).
modulator section we are going to describe thus accounts for
this threshold but also for the upper limit above which the
variation slope is null (6.0 V). By changing minimum and
maximum frequency limits, the small signal slope of the
VCO is also changed what the modulator also reflects.
Figure 15 shows the internal section of this box:
X6
AMPSIMP
VHIGH = Fmax/100 k
VLOW = Fmin/100 k
R21
10 k
+
−
Out
In
R20
10 k
R22
10 k
R19
10 k
The Internal Modulator
The NCP1395 features a Voltage−Controlled Oscillator
(VCO) switching from 50 kHz up to 1.0 MHz. You drive its
pin number 5 to increase or decrease the frequency.
However, for security reasons, there is a threshold above
which the sweep actually starts. Below this threshold (1.3 V
typical), the frequency does not change and stays at the
minimum value imposed by the resistor on pin 1. The
+
V16
1.6
Figure 15. The modulator introduces a threshold
and tailors the minimum and maximum switching
frequency excursions.
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AND8255/D
Once wired together, the final test circuit looks like that of Figure 16:
X3
LLC
X2
XFMR
RATIO = 1/N
LLC model
Out
Vin
Parameters
192
3
vout
Vout
24.0
Error
320
R1
50m
2
Vin=320
Vout = 24V
0.571
Vin
{Vin}
24.0
R16
8
Rupper=(Vout−2.495)/(2.495/10k)
C1
2.2m
Pout =100W
Fmax= 250k
Fmin = 40k
Q=2
X10
1395MOD
Fmax = Fmax
Fmin = Fmin
Lm=600u
Ratio=6
Ls=Lm/Ratio
Cs=33n
pi=3.14159
N=8
Eta=0.95
mod
Fs=1/(2*pi*sqrt(Ls*Cs))
Fm=1/(2*pi*sqrt((Ls+Lm)*Cs))
Z0=sqrt(Ls/Cs)
out
NCP1395
VCO modulator
ÎÎ
ÎÎ
X4
AMPSIMP
VHIGH = 8
VLOW = 100m
Vmod
ÎÎ
6
1.57
in
V4
2.5
2.50
10
2.50
4
vout
R3
{Rupper}
R13
10k
Figure 16. The complete test circuit including the LLC DC model and its VCO modulator.
• When the distance between Fsw and Fmax reduces, that
Running a DC point analysis gives the operating
frequency for given input and output conditions. The output
capacitor has been kept in place, but does not play any role
in DC. The right side OPAMP just helps to close the loop in
DC and have the right operating point automatically setup,
e.g. 24 V at a given output power level. In this example, the
system delivers 100 W and operates at a switching
frequency of 57 kHz. The voltage on the NCP1395 pin
reaches 1.6 V to deliver these 57 kHz.
Unfortunately, it is not possible to use this model as a
small−signal tool to reveal the Bode plot of an LLC
converter. This is because the LLC converter operates in
various regions, depending on its switching frequency and
the distance of this switching frequency to the resonating
frequency imposed by Ls and Cs . As such, the LLC converter
behaves as different order systems depending on the region
where it operates:
• For switching frequencies away from the resonant
frequency Fmax (set by Ls and Cs , Equation 1), the
low−frequency small−signal response shows a first
order behavior with a single pole given by the load and
the output capacitor:
fp +
1
is to say the feedback loop answers to an increased
power demand, root−locus analysis shows that the
double pole splits: one pole moves toward the high
frequency region whereas the other one goes down the
low frequency area until it joins the pole given by
Equation 22: the LLC converter now shows a second
order behavior.
Design Example Using the Model
Let us see how we can use the DC model to select the right
components for a design example. The specifications could
look like the following:
• Vin,max = 400 Vdc
• Vin,min = 350 Vdc
• Vout = 24 V
• Iout,max = 10 A
• Iout min = No load
• Fsw,min= 70 kHz
Since we can easily implement skip cycle in the
NCP1395, the no−load condition does not represent a
significant problem at the design phase. For this particular
design, we will arbitrarily adopt a ratio of 6 between Lm and
Ls and an operating quality factor Q of 1. Another
application note will detail how these choices affect the LLC
operation and in particular, component stress. To help select
the resonant devices, we can use Figure 17 graphic
representation of M:
(eq. 22)
In this operating mode, a high−frequency double pole
exists, but its location does not significantly affects the
low frequency portion of the Bode plot. This double pole
is located at the beat frequency between the switching Fsw
and Fmax , the series resonant frequency.
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AND8255/D
1 vm
Lm
=6
Ls
4.00
Plot1
vm, vm#a5, vm#a6, vm#a7, vm#a8 in volts
2 vm#a5
3 vm#a6
4 vm#a7
5 vm#a8
Fs =
Q = 10
M=
3.00
1
2 p LC
s s
Z0 =
2 NVout
Vin
Q=
Q=5
2.00
Ls
Cs
N 2R L
Z0
Fsw
Fs
Q=2
Q=1
Mmax = 0.985
1.00
1
2
3
4
5
Q = 0.5
0
200m
600m
1.00
vfoverfs in volts
1.40
1.80
Figure 17. This picture shows the different transfer ratio depending on the loading and the
operating frequency.
From this plot, after locating the curve displaying Q = 1,
we go on its right side to operate on ZVS at full load. We can
see a maximum M value of 0.985 and a ratio between the
resonant frequency Fs and the switching frequency Fsw of
1.035. Hence we can immediately calculate our component
values following the steps:
In Equation 1, we can insert Equation 25:
Ls +
ǸCLss or Cs + ZLs2
(eq. 27)
2
Q + N RL
Z0
hence Z0 +
(eq. 28)
2 2.3
N2RL
+ 7.2
+ 120
1
Q
Therefore, according to Equation 27, the final Ls
calculation becomes:
Ls +
(eq. 24)
2
120
+ 282 mH
p 67.6 k
(eq. 29)
4. Due to the selected ratio of 6, we obtain Lm :
3. We have purposely selected an operating Q of 1.
Knowing the relationship between Q and the
characteristic impedance of the resonating
network, we can obtain Ls definition:
Z0 +
Z0
2pFs
From our previous definitions, we know:
Transformer featuring a turn−ratio of Np:Ns = 7:1.
2. From Figure 17 abcisse, the relationship between
the resonant frequency and the switching
frequency is 1.035. Hence, the resonant frequency
will be set to:
Fsw, min
+ 70k + 67.6 kHz
1.035
1.035
(eq. 26)
Ls
Z02
V
1. Turn ratio from Equation 15: out + M then
2N
Vin
MVin, min
N+
+ 0.985 350 + 7.2 (eq. 23)
2 24
2Vout
Fs +
1
1
+
Ǹ
2p ǸLsCs
2p Ls
Fs +
Lm + LsRatio + 1.7 mH
(eq. 30)
5. The resonant capacitor value is straightforward
due to Equation 26:
Cs +
(eq. 25)
0
http://onsemi.com
10
1
+
39.5
4p2Fs2Ls
1
4.569Meg
282u
+ 20 nF
(eq. 31)
AND8255/D
6. The RMS current circulating in the inductor but
also the capacitor is [1]:
ILs, rms +
Ǹ
1)
A 3.0 A/600 V capacitor will then be selected.
8. Based on the selected value, we can check the
no−load conditions and see what value M will
take, using Equations 15 and 18:
Ǹ2 p·I
out, max
4N
ǒp3Fsw, minLmIout, maxǓ
4N2Vout
2
LmVin, max
+ 23.8 V
(Lm ) Ls)2N
+ 1.7 A
Hence, no load regulation could theoretically be
ensured without entering skip−cycle.
Calculated values can now be entered in the LLC model
and the output voltage observed, versus the swept frequency.
Figure 18 shows output results at two different input
voltages:
(eq. 32)
7. The peak voltage across the resonating capacitor
will be:
Ǹ2 I
Vin, max
Ls, rms
)
+ 488 V (eq. 33)
2
2pFsw, minCs
1 vout
2 vout#a1
35.0
24 V
Vin = 400 V
25.0
Plot1
vout, vout#a1 in volts
VCs, peak +
15.0
Vin = 350 V
5.00
2
1
Vout (V)
72 kHz
82 kHz
−5.00
Fsw (100 kHz)
309m
907m
(eq. 34)
1.50
vf in volts
2.10
2.70
Figure 18. Frequency Variations Full Load at Different Input Voltages
http://onsemi.com
11
AND8255/D
1 vout
2 vout#a2
3 vout#a3
4 vout#a4
180
Plot1
vout, vout#a2, vout#a3, vout#a4 in volts
140
10 W, Fsw = 77.1 kHz
100
50 W, Fsw = 76.4 kHz
60.0
250 W, Fsw = 72 kHz
100 W, Fsw = 75.1 kHz
1
2
3
20.0
4
209m
607m
1.00
vf in volts
1.40
1.80
Figure 19. Frequency Evaluation for Variable Load Conditions, Input Voltage is 350 Vdc
Figure 19 plots the evolution of the switching frequency
versus different load conditions. Design choices imply a
frequency variation of 5.0 kHz between light load and full
load. Different choices of Lm and Ls would have given wider
or narrower variations.
the operating frequency deviates from the resonant
frequency. Nevertheless, the model can be useful for a quick
test of calculated components and see whether the operating
frequency and output voltage are within the range of interest.
References
1. M. Jovanovic, “Principle of Resonant Power
Conversion”, in−house seminar, Toulouse 2004.
2. NCP1395 data sheet, www.onsemi.com.
Conclusion
This paper details how a simplified DC model for the LLC
converter was derived. Based on first harmonic
approximation, the precision of the approach fades away as
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