Designing NCP1337

AND8266/D
Designing NCP1337
Prepared by: Nicolas CYR
ON Semiconductor
http://onsemi.com
APPLICATION NOTE
Description
NCP1337 is a valley−switching controller offering
various features making it ideal to build efficient
quasi−resonant power supplies. It incorporates a wealth of
protective features that eases the design of any specific
application and the compliance to the specifications of
modern power supplies, including reliability and standby
efficiency.
This controller is the ideal candidate where low
part−count is the key parameter, particularly in AC/DC
adapters, consumer electronics or auxiliary supplies.
•
•
Features
• Quasiresonant Operation: Valley−switching operation is
•
•
ensured whatever the operating conditions are, thanks
to the internal Soxyless circuitry. As a result, there are
virtually no primary switch turn−on losses and no
secondary diode recovery losses, and EMI and video
noise perturbations are reduced. The converter also
stays a first−order system and accordingly eases the
feedback loop design.
Dynamic Self−Supply (DSS): Due to its Very High
Voltage Integrated Circuit (VHVIC) technology,
ON Semiconductor’s NCP1337 allows for a direct pin
connection to the high−voltage DC rail. A dynamic
current source charges up a capacitor and thus provides
a fully independent VCC level. As a result, low power
applications will not require any auxiliary winding to
supply the controller. In applications where this
winding is anyway required, the DSS will simplify the
VCC capacitor selection.
Overcurrent Protection (OCP): When the feedback
voltage is at its maximum value, a fault is detected. If
this fault is present for more than 80 ms, NCP1337
enters an auto−recovery soft burst mode. All pulses are
stopped and the VCC capacitor discharges down to 5.0
V. Then, by monitoring the VCC level, the startup
current source is activated ON and OFF to create a
burst mode. After the current source being activated
twice, the controller tries to restart, with a 4 ms
soft−start. If the fault has gone, the SMPS resumes
operation. If the fault is still there, the burst sequence
© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 1
•
•
•
1
starts again. The soft−start together with a minimum
frequency clamp allow to reduce the noise generated in
the transformer in short−circuit conditions.
Over Voltage Protection (OVP): By continuously
monitoring the VCC voltage level, the NCP1337 stops
switching whenever an over−voltage condition is
detected
Brown−out Detection (BO): By monitoring the level on
pin 1 during normal operation, the controller protects
the SMPS against low mains condition. When pin 1
voltage falls below 500 mV, the controller stops pulsing
until this level goes back and resumes operation. By
adjusting the resistor divider connected between the
high input voltage and this pin, start and stop levels are
programmable.
Overpower Compensation (OPC): An internal current
source injects out of Pin 3 (CS pin) a current
proportional to the voltage applied on pin 1. As this
voltage is an image of the input voltage, by inserting a
resistor in series with Pin 3, it is possible to create an
offset on the current sense signal that will compensate
the effect of the input voltage variation.
External Latch Trip Point: By externally forcing a level
on pin 1 (e.g. with a signal coming from a temperature
sensor) greater than 3 V (but below 5 V), it is possible
to disable the output of the controller. Once the voltage
goes back below 3 V, the controller is enabled and
starts. If the voltage is forced over 5 V, the controller is
permanently latched−off: to resume normal operation,
the VCC voltage should go below 4 V, which implies to
unplug the SMPS from the mains.
Standby Ability: Under low load conditions, NCP1337
enters a soft ripple mode: when the CS setpoint
becomes lower than 20% of the maximum peak current,
output pulses are stopped, then switching is starting
again when FB loop forces a setpoint higher than 25%.
As this occurs at low peak current, with soft−skip
activated, and as the TOFF is clamped, noise−free
operation is guaranteed, even with a cheap transformer.
Publication Order Number:
AND8266/D
AND8266/D
TYPICAL APPLICATION
The above features makes NCP1337 well suited for offline applications of a wide power range. A typical application is shown
in Figure 1.
VOUT
+
BO
+
Cbulk
VCC
NCP1337
1
8
+
2
3
6
4
5
VCC
Rcomp
Figure 1. NCP1337 Typical Application Example
PIN BY PIN IMPLEMENTATION
Pin 1: “BO” pin
Brown−out
to an internal 10 mA current source which is turned on when
the voltage on BO pin is above 500 mV. The brown−out
protection is not latched: when the input voltage (VIN) is
below the target, the controller stops pulsing but it recovers
operation, after a soft−start, as soon as VIN goes back within
the acceptable range.
SMPS are designed for a given input voltage range. When
the input voltage is too low, the power supply tends to
compensate by sinking more current from the line to deliver
the same output power. As a result, the power components
may suffer from an excessive heating and ultimately the
SMPS may be destroyed. Another consequence is that as
when the electricity network weakens, its voltage tends to
decrease, and as in this case SMPS tend to sink more current,
electricity network gets weaker and weaker and eventually
collapses (it is the reason why this protection is called
‘brown−out’ protection).
A simple solution to protect at the same time the power
supply and the network is to stop the SMPS controller when
the input voltage is too low. For this purpose Pin 1 offers a
comparator with hysteresis able to stop the controller if the
voltage applied is too low. By applying an image of the input
voltage on the pin, it becomes possible to authorize
operation above a certain level of mains only. The controller
monitors this voltage and when the Pin 1 voltage is too low
(i.e., when Vpin1 is below 500 mV), the controller stops
pulsing and keeps disabled until this level exceeds 500 mV.
In order to prevent the instabilities that could result from the
input voltage ripple, an hysteresis is programmable thanks
VIN
10 mA
BO
+
−
BOK
+
500 mV
Figure 2. Internal Configuration of BO Protection
http://onsemi.com
2
AND8266/D
Startup level is directly given by the resistor divider
connected between VIN and BO pin, knowing that the
threshold of the internal comparator is 500 mV.
Once the controller has started, an internal 10 mA current
source is activated and flows out of BO pin, creating a
voltage offset across the equivalent resistance of the resistor
divider.
Those two conditions lead to the following equations:
RBOhigh ) RBOlow
RBOlow
+
BO
@ VIN(ON) + 500 mV (eq. 1)
RBOhigh ) RBOlow
RBOlow
)
RBOhigh @ RBOlow
RBOhigh ) RBOlow
@ VIN(OFF)
Latch
+
−
Disable
5V
+
and
+
−
3V
Figure 3. Internal Implementation of Disable and
Latch Comparators
(eq. 2)
@ 10 mA + 500 mV
To perform a disable function, the voltage on BO pin must
go above 3 V, and over 5 V for a latch function.
In case of a primary OVP, where VAUX or VCC is
monitored, a direct connection of a zener diode between the
monitored voltage and BO pin is not able to toggle the Latch
comparator: in such configuration, only the disable function
will be activated.
To have a latched protection, the OVP signal must be
buffered with a high gain PNP transistor (see Figure 4) in
order to raise BO voltage above 5 V faster than the SMPS
reaction to the disable comparator (which is toggled first).
With VIN(ON) the turn−on and VIN(OFF) the turn−off input
voltages.
Solving these equations gives the recommended values
for RBOhigh and RBOlow, but in reality there could be a
non−negligible ripple on the DC input voltage (depending
on the size of the bulk capacitor), and it may be necessary to
increase the hysteresis in order to obtain the desired turn−off
level.
It is as well recommended to add a capacitor between
BO pin and ground to filter any noise, and to ensure a DC
voltage. But this capacitor value should be small enough
otherwise it may introduce a delay between input voltage
collapsing and power supply turn−off (a 10 nF capacitor
gives good results).
We will see later that Overpower Protection is dependent
on VBO voltage: to have an accurate protection, VBO should
be proportional to the input voltage of the SMPS stage. But
in the case there is a front−end PFC stage, there is a dilemma:
once PFC has started, VBULK is not any more an image of the
mains voltage: it means that even if VIN goes below
VIN(OFF), PFC stage will still try to maintain VBULK high,
and the Brown−out protection is not effective. So connecting
BO to the real VIN is recommended, even if overpower
protection is less accurate. A solution to improve this
protection is to use a “follower boost” type of PFC in which
the output follows the input.
VIN
VCC
BO
Figure 4. How to Perform a Latched OTP or OVP
Latch
This pin also performs a second function: it provides two
comparators to temporarily (autorecovery) or permanently
(latched) stop the controller by an external condition
(Figure 3).
Pin 2: “FB” pin
In order to simplify the implementation of a primary
regulation, the FB circuitry is a shunt regulator with a fixed
voltage of 3 V, combined with a current to voltage translator.
This means that the FB information is a current, which is
internally converted to a voltage that sets the setpoint for the
current−mode control. In case of a secondary regulation, the
optocoupler transistor must be connected between VCC and
FB pin.
http://onsemi.com
3
AND8266/D
G0 = 70 dB
3 MHz Pole
+
−
FB
N = 6.6
40 mA
+
Internal
Setpoint
N=1
3.0 V
15.4 kW
0.5 V
20 kHz
Filter
Figure 5. Internal Circuitry of FB Pin
Maximum CS pin voltage VCSlimit is 0.5 V, corresponding
to a FB current of 50 mA: when the current on FB pin is lower
than 40 mA, an internal flag IPflag is raised and the fault
timer is started. If IPflag stays asserted until TIMER pin
voltage reaches 5 V, FAULT is detected and the controller
enters protection mode: pulses are stopped, and VCC
capacitor is discharged by the internal current consumption
ICC3 down to VCCLATCH. Then the VCC capacitor is
charged again to VCCON and discharged to VCCLATCH
without attempting to restart. A new startup phase takes
place only the second time VCC reaches VCCON after the
fault detection. This ensures a low−frequency burst mode
safe for the power supply if the overload is still present.
When the faulty condition disappears, the controller
resumes normal operation after the next restart attempt
(Figure 6).
http://onsemi.com
4
AND8266/D
Restart on 2nd cycle
VCC
VCCON
VCCMIN
VCCLATCH
CS
Setpoint
Overload is removed here
Overload
Fault
When the current setpoint rises
above fault level, FAULT flag is
activated.
CS
VCSLimit
Output pulses
are stopped.
FAULT
TIMER
80 ms
SS
When FAULT flag
is activated, timer
is restarted.
80 ms Fault Timer
Normal Startup
Figure 6. Typical Behavior in Overload Conditions
Pin 3: “CS” Pin
maximum peak primary current at the lowest input voltage
and maximum output load.
This pin performs two distinct functions: primary peak
current reading and compensation for overpower protection.
RSENSE +
Peak Current Reading
It is classically performed through the reading of the
voltage appearing through a sense resistor connected
between switching MOSFET’s source and ground. The
internal maximum current sense level VCSlimit is 0.5 V, so
RSENSE must be calculated by Equation 3, with IpkMAX the
0.5
IpkMAX
(eq. 3)
A leading edge blanking (LEB) prevents any spike
appearing during the first 350 ns after TON to toggle falsely
the internal current sense comparator. This LEB is usually
enough, but if for some reasons an additional filtering is
necessary, it is still possible to add externally an RC filter.
http://onsemi.com
5
AND8266/D
Overpower Compensation
In the quasi−resonant mode of operation, the slope of the current during ON time is;
VIN
LP
(eq. 4)
and during OFF time, it is;
N @ VOUT
(eq. 5)
LP
Thus for a given peak current Ipk, TON is shorter at high VIN than at low VIN, and TOFF is constant: so the switching frequency
FSW is higher at high VIN (see Figure 7).
Figure 7. TON Behavior at a Biven Ipk for Different VIN
Knowing Equation 6 (with h the efficiency), it is clear that for a given Ipk, POUT is higher at high VIN than at low VIN. So
for a constant output power, the peak current is lower at high VIN than at low VIN (see Figure 8).
1
POUT + h @ PIN + h @ LP @ Ipk2 @ FSW
2
(eq. 6)
Figure 8. Ipk Behavior at a Given POUT for Different VIN
http://onsemi.com
6
AND8266/D
As the overload detection of NCP1337 is based on peak current detection, if an overpower protection is needed the voltage
applied on CS pin at POUTmax must be the same at high VIN and low VIN. The solution consists in adding a compensation offset
proportional to VIN to the voltage sensed across the sense resistor. NCP1337 offers the possibility to easily create this offset
by activating an internal current source proportional to VBO during TON: this current flows out of pin CS and create an offset
proportional to VBO (which is proportional to VIN) through a series resistor (see Figure 9).
To further simplify the design of the compensation, the offset current is null when VBO is equal to 0.5 V, corresponding to
the minimum allowed input voltage.
NCP1337
VIN
BO
To BO Comparator
1
70 mS x VBO − 35 mA
CS
Comparator
−
+
CS
LEB
3
ROPP
RSENSE
Figure 9. Internal Overpower Compensation Circuitry on CS Pin
Design Steps:
VOFFset + ROPP @ (VBOHV @ 70 @ 10−6 * 35 @ 10−6)
• Estimate peak current Ipk values at minimum VIN and
(eq. 9)
maximum VIN for the maximum output power allowed.
By neglecting the delay between core reset and the real
valley (it is small compared to the switching period at
high output power), we can estimate Ipk at a given VIN
by Equation 7. Thus calculate IpkmaxLV and IpkmaxHV,
respectively max peak currents at low and high input
voltages.
Ipk +
ǒ
Ǔ
2 @ POUT
1
1
@
)
h
VIN N @ VOUT
Which gives the following equation.
ROPP +
IpkMAX LV
(eq. 10)
Reference ground for the controller.
Pin 5: “DRV” Pin
current to flow at the minimum input voltage:
RSENSE +
@
IpkMAX LV
0.5
VBOHV @ 70 @ 10−6 * 35 @ 10−6
Pin 4: “GND” Pin
(eq. 7)
• Calculate the sense resistor to allow the maximum peak
0.5
IpkMAX LV * IpkMAX HV
This pin performs two distinct functions: it drives the
switching MOSFET and detects the “valley” of the drain
voltage thanks to the “Soxyless” detector.
(eq. 8)
• As we know what is the value of VBO for a given VIN,
MOSFET Driving
By offering up to ±500 mA peak, this pin allows to drive
large QG MOSFETs without adding any additional
components.
we can calculate the needed offset resistor ROPP
knowing that:
http://onsemi.com
7
AND8266/D
Valley Detection
Mosfet (modelized by the CRSS capacitance between Gate
and Drain): a negative current (flowing out of DRV pin)
takes place during the decreasing part of the Drain
oscillation, and a positive current (entering into the DRV
pin) during the increasing part (see figure 10).
The Drain valley corresponds to the inversion of the
current (i.e. the zero crossing): by detecting this point, the
NCP1337 can switch on when the drain voltage is minimum,
and thus always ensure a true valley turn−on.
The “Valley point detection” is based on the observation
of the Power MOSFET Drain voltage variations. When the
transformer is fully demagnetized, the Drain voltage
evolution from the plateau level down to the VIN asymptote
is governed by the resonating energy transfer between the LP
transformer inductor and the global capacitance present on
the Drain. These voltage oscillations create a current
oscillation in the parasitic capacitor across the switching
Lprim
Isoxy
VSWITCH
TSWING
CRSS
DRV
t
Figure 10. Soxyless Concept
The current in the Power MOSFET gate is:
IGATE = VRINGING / ZC (with ZC the capacitance
impedance), so IGATE = VRINGING • (2 • p • FRES • CRSS)
The magnitude of this gate current depends on the
MOSFET, the resonating frequency FRES and the voltage
swing VRINGING present on the Drain at the end of the
plateau voltage.
The dead time TSWING is given by the equation:
TSWING + 0.5ńFRES + p * ǸLP * CDRAIN
However two cases can occur that will require an additional
tuning:
• The detector is not sensitive enough (CRSS is too
small): the first valley(s) is (are) detected, but not the
following ones, leading to an instability at light load
(see Figure 11). In this case it is necessary to increase
the gate to drain capacitance by adding an external
capacitor (see Figure 12). A 4.7 pF or 10 pF capacitor
is enough to increase the sensitivity of the detector and
cancel the instability. This added capacitor must be a
high voltage model as it must sustain the drain voltage.
(eq. 11)
Where LP is the primary transformer inductance and
CDRAIN the total capacitance present on the MOSFET
Drain.
This capacitance includes the snubber capacitor if any, the
transformer windings stray capacitance plus the parasitic
MOSFET capacitances COSS and CRSS.
The detector’s threshold has been designed to work
perfectly with the most recent high voltage MOSFETs for
which the CRSS capacitance is usually in the range of 12 pF
to 15 pF. But it will work perfectly in most situations even
with a CRSS as low as 5 pF or as high as 50 pF.
http://onsemi.com
8
AND8266/D
LPRIM
OK
4.7 pF / 1 kV
NOT DETECTED
CRSS
DRV
Figure 11. Instability at Lower Load
Figure 12. External Gate−to−Drain Capacitor
• The detector is too sensitive (CRSS is too big): in multiple−output applications the small oscillation created by the early
demagnetization of one of the output windings is detected, leading to a CCM operation (see Figure 13). A 470 pF or
1 nF capacitor connected between MOSFET’s gate and ground reduces the sensitivity (see Figure 14).
LPRIM
TOO SENSITIVE
CRSS
OK
DRV
1 nF
Figure 13. Instability with Multiple Outputs
Figure 14. Gate−to−Ground Capacitor
Finally, if the NCP1337 is not connected directly to the MOSFET, but through an external driver or a buffer, an external
gate−to−drain capacitor must be added as there is no current path from the drain node to the DRV Pin (Figure 15).
LPRIM
10 pF / 1 kV
DRV
Buffer
Figure 15. External Gate−to−Drain Capacitor When a
Buffer is Used
http://onsemi.com
9
AND8266/D
Pin 6: “VCC” Pin
TSTARTUPMAX + CVCC @
This is the supply pin for the controller. NCP1337 features
a high voltage current source between Pins 8 (“HV”) and 6
(“VCC”) which turns on during startup to charge the VCC
capacitor, but also operates in Dynamic Self−Supply mode
(DSS), alternatively turning on and off to maintain the
voltage on VCC pin between VCCON and VCCMIN. If the
current consumption on the DRV pin is too high for the DSS
capability, or for the power dissipated in the package, an
auxiliary supply should take the hand and supply the VCC
once the controller has started. Using an auxiliary supply
also helps to reduce the standby power in no−load
conditions, by supplying the NCP1337 from a low voltage
instead of the high input voltage.
The VCC capacitor is selected by taking into account the
startup time, the duty ratio in protection mode and the ability
to maintain VCC above VCCmin in order to disable the startup
circuit at light loads.
• The startup time (see Figure 16)
The startup time TSTARTUP is the sum of T1 and T2, which
both depend on the VCC capacitor:
)
IC2MIN
VCConMAX * VCCINHIB
(eq. 12)
IC1MIN
VCC
VCCON
IC1
VCCINHIB
IC2
T1
T2 Time
Figure 16. Dual Startup Current Source
• The duty ratio of the protection mode: the working
period duration is given by the internal Fault timer, but
the “OFF” period is dependent on the VCC capacitor
charging and discharging times (see Figure 17).
Restart on 2nd cycle
VCC
VCCINHIB
VCCON
VCCOFF
VCCLATCH
TIMER
80ms
80ms fault timer
Working ratio
ON
OFF
T0 T1 T2
T3
T4
Figure 17. Duty Ratio in Short−Circuit Conditions
http://onsemi.com
10
AND8266/D
The off time duration of the short−circuit protection mode TSCoff is the sum of two discharging and two charging times of
the VCC capacitor. By neglecting T0, we can estimate a minimum value for TSCoff:
ǒ
TSCoffmin + CVCC @ 2 @
VCCMINmin * VCCLATCHmax
ICC3
)2@
• The amount of energy stored and thus the ability to
VCCONmin * VCCLATCHmax
IC1 min
)
VCCON * VCCMIN
ICC3
Ǔ
(eq. 13)
too long, a solution consists in splitting the VCC
capacitor into two different components: a tank
capacitor is used to store energy for no−load operation,
whereas the VCC capacitor stays small enough to ensure
a fast startup (Figure 18).
keep VCC above VCCMIN (and thus not activate the
DSS) when the power supply operates in low load
conditions. If a big capacitor is needed to run in
auxiliary supply mode at no load, but the startup time is
VCC
CVCC
10 m
+
CTANK
100 m
16 V
+
AUX
Figure 18. Split Capacitor on VCC Pin
Pin 7: Unused Pin
Eventually the drive current can also be calculated by:
This pin is left unconnected to ensure a wider creepage
distance between the high voltage pin and the VCC pin.
IDRV + FSW @ QG
With FSW the switching frequency and QG the selected
MOSFET’s gate charge.
The maximum allowable power dissipation PMAX can be
computed knowing the maximum operating ambient
temperature, TAmax, together with the maximum allowable
junction temperature TJmax:
Pin 8: “HV” pin
An internal current source is connected between the HV
and VCC pins, and is able to supply the controller from a
minimum dc voltage of 60 V. It is highly recommended to
add a series resistor RHV between the high voltage rail and
the pin to protect NCP1337 against negative spikes that
could appear due to a resonance between the primary
inductor and the bulk capacitor.
PMAX + (TJmax * TAmax) @ RqJA
(eq. 16)
with RqJA the junction−to−air thermal resistance, which
notably depends on the package.
In case the power dissipation exceeds PMAX, several
solutions exist to rectify the problem:
• The first one consists in adding some copper area
around the NCP1337 package footprint, which will help
to decrease the junction−to−air thermal resistance.
• Calculate the resistor RHV in series with the HV pin in
order to split the power budget between this resistor and
the package. The resistor is calculated by leaving at
least 60 Vdc on Pin 8 at minimum input voltage (you
can refer to the application note AND8069 available
from www.onsemi.com).
• If the power consumption budget is really too high for
the DSS alone, connect a diode between the auxiliary
winding and the VCC pin, which will disable the DSS
operation (by ensuring VCC > VCCMIN).
Power Dissipation
When the NCP1337 is directly supplied from the dc rail
through the internal DSS circuitry, the DSS being an
auto−adaptive circuit (e.g. the ON/OFF Duty Cycle adjusts
itself depending on the current demand), the current flowing
through the DSS is the direct image of the NCP1337 current
consumption. As a result, the total power dissipation can be
estimated using:
ǒVHVdc * VCCON *2 VCCMINǓ @ ICC2
(eq. 15)
(eq. 14)
The real current consumption is actually given by the sum
of the internal consumption of the NCP1337 and the driving
current IDRV for the selected MOSFET. The best method to
evaluate this total consumption is probably to run the final
circuit from a 50 Vdc source applied to HV pin and measure
the average current flowing into this pin. Replacing ICC2 by
this measured current will give a more accurate estimation
of the dissipated power.
http://onsemi.com
11
AND8266/D
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
http://onsemi.com
12
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
AND8266/D
Similar pages