Determining the Free-Running Frequency for QR Systems

AND8089/D
Determining the
Free-Running Frequency for
QR Systems
Christophe BASSO
ON Semiconductor
14, rue Paul Mesplé – BP1112 – 31035 TOULOUSE Cedex 1 – France
33 (0)5 34 61 11 54 e–mail: [email protected]
INTRODUCTION
A quasi–square wave Switch–Mode Power Supply offers
many advantages such as a soft EMI signature and a constant
efficiency over a broad output load range. However, by
nature, a Quasi–Resonant (QR) supply exhibits a highly
variable switching frequency which depends on the
input / output operating conditions. This short application
note details how to evaluate the switching frequency at a
given operating point and thus gives the designer the
necessary insight to dimension his system.
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APPLICATION NOTE
dictate the rising slope of the drain voltage. When the
leakage inductance is reset, the drain reaches a plateau made
of Vin plus the reflected output voltage Vr. Finally, when the
core is fully reset, a damped oscillation takes place on the
drain and successive “valleys” (minimal) appear. If the
reflected voltage is selected to be strong enough compared
to Vin (ideal is when Vr = Vin), then the MOSFET can be
re–started with a null drain–source voltage, minimizing all
associated capacitive losses: this is called Zero–Voltage
Switching (ZVS) operation. The “demag” winding offers an
image of the core’s flux and helps to detect the reset event
(when Iprimary = 0). Unfortunately, ZVS can only be
obtained if sufficient voltage is reflected on the drain.
Figure 2 portrays a typical signal where the reflected voltage
Vr, is too low compared to Vin. When operating on universal
mains up to 275 VAC, tradeoffs have to be made to ensure
ZVS operation at high line but also to limit the MOSFET
BVdss to a reasonable value (a cost sensitive parameter…).
An 800 V device, for instance, can be a good choice to allow
QR operation over a large portion of the universal mains, for
instance on a single output power supply.
A Flyback Working in QR Mode
A Flyback working in QR mode is nothing else than a
standard PWM–driven Flyback circuit to which a resonating
tank has been added. Figure 1 shows the basic configuration
of a converter that could be controlled through a dedicated
circuit like ON Semiconductor NCP1205 or NCP1207.
On this circuit, the resonating tank is made of Lp – Cp, the
primary inductance and the resonating capacitor. When the
switch closes, the current builds–up in the primary
inductance and the drain voltage is close to zero. At the
switch opening, the leakage inductance together with Cp
1:N
Leakage
Demag
+
+
Vin
Vout
Lleak
QR Controller
Vr
1
2 Lp Cp
Vin
Cp
Valleys
Figure 1. A QR Flyback Converter
 Semiconductor Components Industries, LLC, 2002
July, 2002 – Rev. 0
Figure 2. A Typical Drain–Source Signal of a QR
Converter
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A Succession of Events
current Iprimary(t) and the driver waveshape to detail
exactly when the MOSFET is re–activated.
To the light of this picture, it can be noticed that the
primary current Iprimary(t) and Vds(t) being in quadrature,
switching the MOSFET when Vds(t) equals zero also
engenders Zero Current Switching (ZCS)! However, care
must be taken to introduce the proper delay when core reset
is detected. If this delay is too long or too short, then
ZVS/ZCS can no longer be maintained and losses
increase…
To calculate the operating frequency of a QR converter,
one needs to account for all the parasitic elements involved
in the structure. For example, the leakage inductance plays
a significant role in slowing down the drain–source signal.
Neglecting it leads to a large error, especially if the
resonating capacitor has been increased to reduce the
dVds/dt and avoid a clamping network. To fully understand
the time sequences, Figure 3 shows a QR converter truly
operating in ZVS. Are present on this picture the
drain–source signal Vds(t), the internal primary inductance
Ip Lleak V N (V
in
out Vf)
Cp
Ip
Core is
reset!
Vds
0
Ton
TL Toff
Vds = 200 V / div
= 200 mA / div
X = 3.67 S / div
Tw
Figure 3. A Converter Truly Working in ZVS with a Smooth Vds Transition
TLeak:
Let’s review, one by one, the events shown on Figure 3:
At the switch opening, the voltage cannot instantaneously
increase and the perfidious leakage inductance delays the
transfer of the primary current to the secondary. Vds rises
with a slope imposed by the peak current present at the
switch opening: Vds(t) slope is:
Ton:
The switch closes, forcing a voltage (Vin) across the
primary inductance Lp. The current increases with a slope
of:
Vin
(eq. 1)
Lp
When Ip is reached, the controller dictates the opening of
the switch. Therefore, Ton is equal to:
Ip
(eq. 3)
Cp
if we neglect all other capacitance at the drain node. The
peak voltage is given by the characteristic impedance of the
resonating
tank
made
by
Lleak
and
Cp :
L
(eq. 2)
Ton Ip p
Vin
With: Lp the primary inductance, Vin the input voltage, Ip
the peak current.
Vds max Ip Vin N (Vout Vf)
Lleak
Cp
(eq. 4)
The secondary diode starts to conduct at the time Vds(t)
reaches N x (Vout + Vf). Therefore, combining eq. 3 and eq.
4, we obtain the “rising” time:
TL [Ip Lleak
Cp
Vin N (Vout Vf)] Cp
Ip
(eq. 5)
With: Vout the output voltage, Vf the diode’s forward
drop, N the Np/Ns turn ratio, Lleak the leakage inductance,
Cp the resonating capacitor.
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AND8089/D
Toff:
Tw:
Toff represents the time needed to bring the peak current
back to zero through the reflected voltage applied over Lp.
Therefore, Toff can easily be derived:
Without entering into complex calculations, one can see
that the valley occurs at half the natural ringing period
imposed by Lp and Cp. Tw is thus defined by:
Lp
(eq. 6)
N (Vout Vf)
With: Vout the output voltage, Vf the diode’s forward drop,
N the Np/Ns turn ratio
Tw Lp Cp
(eq. 7)
However, when complete calculations are undertaken, it
shows that this result is only valid for lightly damped
resonating tanks, which is often the case.
Toff Ip We now have everything needed to compute the switching frequency by summing up all these events and reversing the result:
Fsw L
Ip Vinp [Ip
1
Lleak
VinN(VoutVf)]Cp
Cp
Ip
(eq. 8)
Ip N(Voutp Vf) Lp Cp
L
The unknown equation remains the peak current Ip. To obtain it, we need to start from the classical Flyback power transfer
formula:
Pout
1
2
n 2 Lp Ip Fsw
(eq. 9)
re–arranging it gives:
Ip 2LpPoutFsw
(eq. 10)
Now, let’s plug equation 10 into equation 8 to obtain a third order equation of Ip:
L
Lp
I Lp Cp (Ip Ip2 2 Pout [ p Ip Vin
Lp
N (Vout Vf) p
Lleak V N (V V )) Cp]
in
0
f I
Cp
p
(eq. 11)
This third order equation can be examined with a mathematical solver to obtain a rather complicated formula:
1
Ip 6
36 I1 Io2 108 I2 Io 8 Io3 12 3 Io2 ( 4 I13 Io I12 Io2 18 I1 Io I2 27 I22 4 12 Io2) 12 I1 Io 4 Io2
1
[36 I1 Io2 108 I2 Io 8 Io3 12 3 Io2 ( 4 I13 Io I12 Io2 18 I1 Io I2 27 I22 4 I2 Io2] 3
with :
a
b
Cp
Lp
P
(Vin Vr)
Io 2 out
Vin Vr
Lleak
Lp
I1 a (1 b) Vin Vr
Vin Vr
I2 a2 (Vin Vr)
Once Ip is known, the switching frequency can be computed via equation 8.
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1 Io
3
(eq. 12)
AND8089/D
typical curves given by the spreadsheet for a 30 W SMPS
featuring the following component values:
Lp = 1.4 mH
Lleak = 15 H
Vout = 16.8 V
Pout = 30 W
Np: Ns = 16.6
Cp = 1.5 nF
To ease the designer work, we have entered this formula
into an Excel spreadsheet available to download from ON
Semiconductor web site (www.onsemi.com), NCP1205 or
NCP1207 related sections. By entering the power supply
parameters, you can quickly view the evolution of the
switching frequency with the selected primary inductance
Lp, the input voltage or select the inductance that brings the
desired switching frequency in worse case conditions, e.g.
highest output power and lowest input line. Below are some
0.500
0.450
1.000
0.400
0.900
Ippeck
0.350
0.800
0.300
0.700
0.250
0.600
IpRMS
0.200
0.500
0.150
0.400
0.100
0.300
0.050
0.200
120
170
220
270
INPUT VOLTAGE (V)
320
PRIMARY RMS CURRENT (A)
PRIMARY PEAK CURRENT (A)
1.100
0.000
370
Figure 4. Peak Current Vs. Input Voltage
Primary Current Evolution with the Input Voltage
0.445
80.0
0.440
70.0
IpRMS
60.0
0.435
50.0
0.430
40.0
0.425
30.0
0.420
20.0
Fswitching
10.0
0.0
5.0E–04
1.0E–03
1.5E–03
2.0E–03
0.415
2.5E–03
PRIMARY RMS CURRENT (A)
SWITCHING FREQUENCY (kHz)
90.0
0.410
3.0E–03
PRIMARY INDUCTANCE
Figure 5. Free–Running Frequency vs. Lp.
(This graph lets you select the inductance value that will bring the desired frequency at low line)
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AND8089/D
valley switching, e.g. starting right in the middle of the
wave, or the above equations are no longer valid. The below
graph compares the frequency variation with the input
voltage measured on the board or calculated:
To check our calculations, the above 30 W prototype has
been built using the NCP1205, a new QR controller
featuring a soft frequency foldback with a Voltage
Controller Oscillator. It is very important to ensure true
SWITCHING FREQUENCY (kHz)
90
80
Measured
70
60
Calculated
50
40
30
120
170
220
270
320
INPUT LINE (DC)
Figure 6. Switching Frequency vs. Vin @ Pout = 30 W
Acknowledgements
As one can see, both graphs are in good agreement and the
high–line error is better than 10%, confirming the validity of
our assumptions. The complete description of the board is
the object of a dedicated application note, also available
from the ON Semiconductor web site, NCP1205 and
NCP1207 related sections.
The author wishes to thank his colleagues François
Lhermite and Joël Turchi for fruitful discussions related to
quasi–resonant converters.
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Notes
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Notes
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