AND8128/D Low Cost AC−DC 5.0 W Adapter with NCP1215 Prepared by: Petr Lidak ON Semiconductor http://onsemi.com APPLICATION NOTE • Frequency Foldback: Since the switch−off time INTRODUCTION increases when power demand decreases, the switching frequency naturally diminishes in light load conditions. This helps to minimize switching losses and offers excellent standby power performance. • Secondary or Primary Regulation: The feedback loop arrangement allows secondary or primary side regulation without significant additional external components. By exploitation of all above−mentioned features one can build an AC−DC adapter with the NCP1215 in quite an efficient way. Since the operation of the NCP1215 differs significantly from the standard fixed frequency current mode controllers, a more detailed explanation of the operation will follow. The goal of this paper is to present a design example of a 5.0 W rated AC−DC adapter for consumer products like the mobile phone, walkman, walkie−talkie, MPEG players, digital camera, various battery chargers, etc. This sort of adapter is specified at very low cost to not hamper the selling price of the above products. However, this does not imply that an adapter designer has to sacrifice safety, precision and standby performance. By implementing the NCP1215 dedicated for switched−mode power supply (SMPS) control one can build an adapter that can meet all those requirements. This can be achieved with the help of the following NCP1215 basic features: • Current Mode Control: Cycle−by−cycle primary current observation is helping to prevent any significant primary overcurrent which would cause transformer’s core saturation and consequent serious power supply failure. • Negative Primary Current Sensing: Negative current sensing offers an elegant way to drive a MOSFET without a) reducing the available gate−source voltage as the sense resistor voltage grows−up b) deteriorating the voltage image of the primary current via the strong turn−on pulse due to the input capacitance. The programming resistor offers another degree of freedom when selecting the voltage across the sense resistor. Furthermore, the programming resistor together with pin capacitance forms low−pass filter which cleans up the residual noise generated at main switch turn−on by charging process of all parasitic capacitances included in transformer’s windings, snubbers, output diode, and printed circuit board traces. • Very Low Start−up Current: The patented internal supply block is specially designed to offer a very low current consumption during start−up. It allows the use of a very high value external start−up resistor, greatly reducing dissipation, efficiency and standby power consumption. Semiconductor Components Industries, LLC, 2003 September, 2003 − Rev. 0 Summary of NCP1215 Operation There can be identified two basic categories of the power losses within any SMPS. These are the conduction and switching losses. The conduction losses become dominant at rather high output power levels. But the situation can completely change when the demanded output power decreases to low or standby level. In this situation, switching losses become a major contributor of the power leak. This situation is typical for standard control IC’s working with fixed switching frequency. It can be even worse for SMPS based on very popular self−oscillating concept where at light load condition the switching frequency usually escalates to very high values. The idea behind the NCP1215 operation is to reduce the switching losses of the SMPS during this light load or standby operation. This can be simply ensured by keeping constant primary ON time. As a result, output regulation is obtained by adjusting the OFF time duration. This is exactly the way the NCP1215 is working. Experimental results have proven the concept with an excellent standby consumption in no−load conditions. 1 Publication Order Number: AND8128/D AND8128/D portion of the maximum value. This little current reduction helps to get away from audio range and to lower the level of the audio noise. It increases the standby self−consumption, but not significantly. For higher output power levels the peak primary current continuously increases up to its maximum. The resulting block diagram of the internal structure can be seen in Figure 1. From that figure the basic element of the idea described above is the current source connected to the CS pin. Its value varies between 12.5 and 50 A depending on the signal coming from the feedback block. The resulting transfer characteristic can be seen in Figure 2. If the switching frequency decreases as the output power demand goes down, it will move in the opposite direction when responding to an output increase. In light load conditions, the frequency can go really low and operation within the audible range is feasible. Since the peak primary current is set to maximum for the working range, power pulses at audio frequency induce an audible whistle coming mainly from the transformer. The power supply user does not appreciate this whistle. The solution is a compromise between those two extremes. The result is the control apparatus that has in light load condition fixed peak primary current to a certain FB Feedback Loop Control VDD Iref − Voffset + 0−7 V Ct − + Reference Regulator + − VCC 12/8.5 V Undervoltage Lockout Off−Time Comparator 10 A Gate Driver Set CS Q 12.5−50 A Current Sense Comparator GND + − Reset Q Figure 1. Representative Block Diagram http://onsemi.com 2 Gate AND8128/D V CS Pin Source Current 50 A VDD POUT Goes Down Ct Pin Voltage POUT Goes Up P3 12.5 A P2 Voffset 0 A 50 A 100 A P1 140 A FB Pin Sink Current Figure 3. Ct Pin Voltage (Pout1 Pout2 Pout3) 3 The variable current source dictates through the CS pin and external resistors the peak primary current. The OFF time is generated by a timer consisting of the OFF time comparator, a 10 A current source, a discharge switch and the external timing capacitor. The signal that can be observed on the CT pin has the shape as depicted in Figure 3. J1 1 Line 2.2 nF/Y L1 2 − S250 + 1 T1 2.2 mH C1 + C2 4 + R3 4 J2 1 Neutral Due to this shape the IC can allow an OFF time of several seconds or can even stop the switching. This was the basic summary of the IC operation. The practical design of the AC−DC adapter will follow. C7 D1 2.2 F/ 400 V 2.2 F/ 400 V D5 100 nF 3 2M7 IC1 1 NC1 FB 8 10 nF C4 2 CT 47 pF 12 k R1 2.7 NC2 7 X NCP1215 3 CS VCC 6 R5 220 C6 220 nF GND Gate 470 F/ 25 V 4.7 H 10 F/25 V + 1 R10 1k C9 BC846B 2 5 J3 1 +6.5 V@ 800 mA R6 220 D3 MURA160T3 W2 4 5 P6SMB200AT3 D4 X L2 D5 MBRS360T3 C8 + LL4148 C3 8 C5 2M7 R4 R2 t toff−min Figure 2. Current Sense Regulation Characteristic Q2 BZX55C5V6 R7 100 D6 R8 1.0 Q1 IRFRC20 ISO1 R9 2.2 J4 1 GND W1 SFH6156 Figure 4. Schematic Diagram of the AC/DC 5.0 W Adapter with NCP1215 The 5.0 W AC−DC Adapter Board The adapter depicted in Figure 4 has the maximum and performance ratings: Output Voltage Output Current Min. Input Voltage Max. Input Voltage Max. Switching Frequency http://onsemi.com 3 6.5 VDC 0.8 A 90 VAC 275 VAC 75 kHz AND8128/D Using the AC specification of the input voltage the bulk capacitor voltage range can be calculated as follows: For an adapter output voltage of 6.5 V, the number of turns for the secondary winding can be calculated accounting Schottky diode for output rectifier as follows: Vbulk− min VAC− min 2 90 · 2 127 VDC Vbulk− max VAC− max 2 265 · 2 375 VDC ns The power conversion efficiency of 80% for this size adapter would be appropriate. The input power then can be estimated as follows: Using the calculated number of the secondary winding turns the number of turns for auxiliary winding can be calculated: The average value of the input current at minimum input voltage is: naux Pin Iin−avg 6.5 51.2 mA 127 Vbulk− min The suitable reflected primary winding voltage for 600 V rated MOSFET switch is: 600 375 100 125 V Using calculated flyback voltage the maximum duty cycle can be calculated: Vflbk 125 0.496 0.5 125 127 Vflbk Vbulk− min max Vs Vfwd · ns (14.5 1) · 8 17.7 18 turns 6.5 0.5 V RCS CS 0.5 2.442 2.7 0.2047 Ippk The following equation determines peak primary current: 2 · Iin−avg (Vaux Vfwd) Primary Current Control The peak primary current is known from initial calculations. The current sense method allows choosing the voltage drop across the current sense resistor. Let’s use a value of 0.5 V. The value of the current sense resistor can then be evaluated as follows: Vflbk 600 V Vbulk− max Vspike Ippk max · Vbulk− min (6.5 0.5)(1 0.5)150 8.26 8 turns 0.5 · 127 V ·I Pin out out 6.5 · 0.8 6.5 W 0.8 max (Vs Vfwd)(1 max)np The voltage drop across the sense resistor needs to be recalculated: −3 2 · 51.2 · 10 204.7 mA 0.5 VCS RCS · Ippk 2.7 · 0.2047 0.553 V Transformer Design Using a specified maximum switching frequency of 75 kHz at nominal output power the primary inductance can be calculated: Using the above results the value of the shift resistor is: V · max 127 · 0.5 Lp bulk− min 4.14 mH Ippk · fsw− max 0.2047 · 75 · 103 OFF Time Control The value of the timing capacitor for the off time control has to be calculated for minimum bulk capacitor voltage since at this condition the converter should be able to deliver the specified maximum output power. The value of the timing capacitor is then given by the following equation: V Rshift CS 0.553 11.06 k 12 k ICS 50 · 10−6 The highest switching frequency occurs at the highest input voltage and its value can be estimated as follows: f max −high f max −low Vbulk− max Vbulk− min max 1 Lp · Ippk fsw Vbulk− min CT 1.2 · 106 75 · 103 375 0.5 110.7 kHz 127 The EF16 core for transformer was selected. It features a cross−section area Ae = 20.1 mm2. The N67 magnetic allows to use maximum operating flux density Bmax = 0.28 Tesla. The number of turns of the primary winding is: −3 1 4.14 · 10 · 0.2047 75 · 103 127 55.5 pF 0.12 · 106 Taking into account the parasitic internal capacitance connected to the CT pin the external timing capacitor should be around 10 pF smaller. The value of 47 pF for the external timing capacitor would be appropriate. Lp · Ippk −3 np 4.14 · 10 · 0.2047 150 turns B max · Ae 0.28 · 20.1 · 10−6 The AL factor of the transformer’s core can be calculated: AL Lp (np)2 −3 4.14 · 10 184 nH (150)2 http://onsemi.com 4 AND8128/D Start−up Circuit The value of the start−up resistor for corresponding to a start−up time of 300 ms and a Vcc capacitor of 300 nF is following: Rstart−up R6 R7 R8 R9 R10 T1 Vbulk− min Vstart−up CVcc tstart−up ICC−startMAX 220, R1206 100, R1206 1, R1206 2.2, R1206 1.0 k, R1206 A9765−A, Coilcraft, 1102 Silver Lake Road CARY IL 60013 Email: [email protected] Tel.: 847−639−6400 Fax: 847−639−1469 127 12 10 · 10−6 200 · 10−9 0.2 5.77 M 5.6 M Feedback Loop The output voltage is sensed on the secondary side by series connection of the Zener diode and the LED diode inside the optocoupler. Resistor R6 reduces the maximum current that can possibly flow through the optocoupler’s diode. Resistor R10 introduces a bias current for Zener diode to move its operating point toward steeper part of the V−A characteristic. A simple circuit consisting of the sensing resistor R8//R9, resistor R7 and transistor Q2 also implements an output current limitation. The current limitation can be disabled by jumper W1. The control signal from secondary side is being delivered to the primary side through the optocoupler ISO1. The optocoupler injects a current from supply capacitor to feedback pin 1. Capacitor C3 is a bypass capacitor against the high frequency noise pick−up. PCB Layout The NCP1215 is designed to have low power consumption when operating. For this reason the output currents injected out of the CS and CT pin is pretty low. Also the FB pin can be affected. Therefore proper printed circuit board layout is essential for a reliable operation of the converter in the whole operating range. It is important to ensure good grounding technique and keep all high frequency current loop and high voltage areas as small as possible to avoid both magnetic and electric field radiations. The PCB layout can be seen in Figure 5. Bill of Materials C1 2.2 F/400 V C2 2.2 F/400 V C3 10 nF, C0805 C4 47 pF, C0805 C5 100 nF, C0805 C6 220 nF, C0805 C7 2.2 nF/Y1 C8 470 F/25 V C9 10 F/25 V D1 S250 D2 LL4148 D3 MURA160T3, ON Semiconductor D4 P6SMB200AT3, ON Semiconductor D5 MBRS360T3, ON Semiconductor D6 BZX55C5V6 IC1 NCP1215, ON Semiconductor ISO1 SFH6156 L1 2.2 mH L2 4.7 H Q1 IRFRC20 Q2 BC846B R1 2.7, R0805 R2 12 k, R0805 R3, R4 2M7, R1206 R5 220, R0805 Figure 5. Printed Circuit Board Layout − Bottom Side The top side is assembled with through hole components only. To locate those components the picture of the related silkscreen can be seen in Figure 6. T1 +6.8 V/0.8 A C2 C9 L1 L2 C8 C1 W2 C7 90−27SVAC ON Semiconductor NCP1215 Demo board 5 W AC/DC Power Supply Figure 6. Silkscreen − Top Side http://onsemi.com 5 W1 AND8128/D The bottom side is dedicated for SMD components. Figure 7 shows their positions. Figure 9 shows the same waveforms but at no load condition. D4 R3 D5 D3 R4 Q1 R9 R6 R8 D6 R7 R5 C5 C6 R1 ISO1 R2 Q2 R10 IC1 C4 C3 D1 Figure 7. Silkscreen − Bottom Side The physical dimensions of the board are 52.5*32.5 mm. Practical Results The application was measured at different conditions. The following pictures depict the typical waveforms at several most important points. Figure 8 demonstrates the control signals at current sense pin CS (middle trace) and OFF−time timing capacitor’s voltage (bottom trace) connected to pin CT. The gate driver output is depicted on the top trace for proper synchronization. The picture was captured at minimum input voltage of 127 VDC and nominal load. Figure 9. CS and CT Pin Voltage at 127 VDC and No Load Figure 10 demonstrates the start−up sequence of the supply voltage at 127 VDC input voltage. The top trace is the gate driver voltage. The bottom trace is the IC supply voltage measured on the VCC pin. Figure 10. Supply Voltage Start−Up at 127 VDC The same situation but at input voltage of 375 VDC is depicted in Figure 11. Figure 8. CS and CT Pin Voltage at 127 VDC and Full Load http://onsemi.com 6 AND8128/D SWITCHING FREQUENCY (kHz) 60 55 50 45 40 35 30 0 1 2 3 4 5 OUTPUT POWER (W) Figure 11. Supply Voltage Start−Up at 375 VDC Figure 13. Switching Frequency vs. Output Power at 127 VDC Since the adapter has incorporated the output current limitation, Figure 12 shows the output V−A characteristics. The dependency of the switching frequency on the input voltage can be estimated when comparing Figure 13 with Figure 14. 7.0 60 SWITCHING FREQUENCY (kHz) OUTPUT VOLTAGE (V) 6.8 6.6 6.4 6.2 6.0 5.8 5.6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 OUTPUT CURRENT (A) 55 50 45 40 35 30 0 Figure 12. Output V−A Characteristics 1 2 3 4 OUTPUT POWER (W) Figure 14. Switching Frequency vs. Output Power at 375 VDC The switching frequency variation over the operating load range is essential for NCP1215 operation. Figure 13 demonstrates the operation of the variable OFF−time block and also frequency compression at 127 VDC. http://onsemi.com 7 5 AND8128/D EFFICIENCY (%) One of the most important parameters that characterize the power supply is the power conversion efficiency. Figure 15 shows achieved results at low line and Figure 16 at high line. 80 Last but not least the parameter one can be interested in is the power consumption at no−load condition. Due to the frequency fold−back the achieved values are outstanding. At low line the power supply consumed only 20.3 mW and at high line due to the increased power loss in start−up resistors the consumption increased up to 57.7 mW. 75 Gate−Source Resistor Design Guidelines In some applications, there is a need to wire a resistor between the MOSFET gate and source connections. This can preclude an eventual MOSFET destruction if, in the production stage, the converter is powered whilst the gate is left unconnected. However, dealing with an extremely low startup current implies a careful selection of the gate−source resistance. With the NCP1215, the gate−source resistor must be calculated to allow the growth of the VCC capacitor to 4.0 V in order to not interfere with the power−on sequence. The following equation helps deriving Rgate−source, accounting for the minimum rectified input voltage and the startup resistor: Vinmin x Rgate−source/(Rgate−source + Rstartup) 4.0 V. If we take a Vinmin of 100 VDC, a startup resistor of 4.0 M, then Rgate−source equals 180 k as a minimum normalized value. 70 65 60 55 50 45 0 1 2 4 3 5 6 OUTPUT POWER (W) Figure 15. Power Conversion Efficiency at 127 VDC 80 EFFICIENCY (%) 75 70 65 60 55 0 1 2 3 4 5 OUTPUT POWER (W) Figure 16. Power Conversion Efficiency at 375 VDC http://onsemi.com 8 AND8128/D Notes http://onsemi.com 9 AND8128/D ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. 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