Data Sheet

TDA9897; TDA9898
Multistandard hybrid IF processing
Rev. 04 — 25 May 2009
Product data sheet
1. General description
The Integrated Circuit (IC) is suitable for Intermediate Frequency (IF) processing including
global multistandard Analog TV (ATV), Digital Video Broadcast (DVB) and mono FM radio
using only 1 IC and 1 to 3 fixed Surface Acoustic Waves (SAWs) (application dependent).
TDA9898 includes, TDA9897 excludes L and L-accent standard.
2. Features
2.1 General
n
n
n
n
n
n
n
n
n
n
5 V supply voltage
I2C-bus control over all functions
Four I2C-bus addresses provided; selection by programmable Module Address (MAD)
Three I2C-bus voltage level supported; selection via pin BVS
Separate gain controlled amplifiers with input selector and conversion for incoming IF
[analog Vision IF (VIF) or Sound IF (SIF) or Digital TV (DTV)] allows the use of
different filter shapes and bandwidths
All conventional ATV standards applicable by using DTV bandwidth window (SAW)
filter
Two 4 MHz reference frequency stages; the first one operates as crystal oscillator, the
second one as external signal input
Stabilizer circuit for ripple rejection and to achieve constant output signals
Smallest size, simplest application
ElectroStatic Discharge (ESD) protection for all pins
2.2 Analog TV processing
n Gain controlled wideband VIF amplifier; AC-coupled
n Multistandard true synchronous demodulation with active carrier regeneration: very
linear demodulation, good intermodulation figures, reduced harmonics and excellent
pulse response
n Integrated Nyquist processing, providing additionally image suppression for high
adjacent channel selectivity
n Optional use of conventional Nyquist filter to support a wide range of applications
n Gated phase detector for L and L-accent standards
n Fully integrated VIF Voltage-Controlled Oscillator (VCO), alignment-free, frequencies
switchable for all negative and positive modulated standards via I2C-bus
n VIF Automatic Gain Control (AGC) detector for gain control; operating as a peak sync
detector for negative modulated signals and as a peak white detector for positive
modulated signals
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
n Optimized AGC modes for negative modulation; e.g. very fast reaction time for VIF and
SIF
n Precise fully digital Automatic Frequency Control (AFC) detector with 4-bit
Digital-to-Analog Converter (DAC); AFC bits can be read-out via I2C-bus
n High precise Tuner AGC (TAGC) TakeOver Point (TOP) for negative modulated
standards; TOP adjust via I2C-bus
n TAGC TOP for positive standards and Received Signal Strength Indication (RSSI);
adjustable via I2C-bus or alternatively by potentiometer
n Fully integrated Sound Carrier (SC) trap for any ATV standard (SC at 4.5 MHz,
5.5 MHz, 6.0 MHz and 6.5 MHz)
n SIF AGC for gain controlled SIF amplifier and high-performance single-reference
Quasi Split Sound (QSS) mixer
n Fully integrated sound BP filter supporting any ATV standard
n Optional use of external FM or AM sound BP filter
n AM sound demodulation for L and L-accent standard
n Alignment-free selective FM Phase-Locked Loop (PLL) demodulator with high linearity
and low noise; external FM input
n Port function
n VIF AGC voltage monitor output or port function
n TAGC voltage monitor output or port function
n VIF AFC current or tuner, VIF, SIF or FM AGC voltage monitor output
n 2nd SIF output, gain controlled by internal SIF AGC or by internal FM carrier AGC for
Digital Signal Processor (DSP)
n Fully integrated BP filter for 2nd SIF at 4.5 MHz, 5.5 MHz, 6.0 MHz or 6.5 MHz
2.3 Digital TV processing
n
n
n
n
n
n
n
n
n
n
n
n
Applicable for terrestrial and cable TV reception
70 dB variable gain wideband IF amplifier (AC-coupled)
Gain control via external control voltage (0 V to 3 V)
2 V (p-p) differential low IF (downconverted) output or 1 V (p-p) 1st IF output for direct
Analog-to-Digital Converter (ADC) interfacing
DVB downconversion with integrated selectivity for Low IF (LIF)
Integrated anti-aliasing tracking low-pass filter
Fully integrated synthesizer controlled oscillator with excellent phase noise
performance
Synthesizer frequencies for a wide range of world wide DVB standards (for IF center
frequencies of e.g. 34.5 MHz, 36 MHz, 44 MHz and 57 MHz)
TAGC detector for independent tuner gain control loop applications
TAGC operating as peak detector, fast reaction time due to additional speed-up
detector
Port function
TAGC voltage monitor output
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
2 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
2.4 FM radio mode
n
n
n
n
n
n
n
n
Gain controlled wideband Radio IF (RIF) amplifier; AC-coupled
Buffered RIF amplifier wideband output, gain controlled by internal RIF AGC
Use of external FM sound BP filter
2nd RIF output, gain controlled by internal RIF AGC or by internal FM carrier AGC for
DSP
Alignment-free selective FM PLL demodulator with high linearity and low noise
Precise fully digital AFC detector with 4-bit DAC; AFC bits read-out via I2C-bus
Port function
Radio AFC or tuner, RIF or FM AGC voltage monitor output
3. Applications
n Analog and digital TV front-end applications for TV sets, recording applications and
personal computer cards
4. Quick reference data
Table 1.
Quick reference data
VP = 5 V; Tamb = 25 °C.
Symbol
Parameter
VP
supply voltage
IP
supply current
Conditions
Min
Typ
Max
Unit
4.5
5.0
5.5
V
ATV QSS; B/G standard;
sound carrier trap on;
sound BP on
-
-
175
mA
lower limit at −1 dB video
output signal
-
60
100
µV
60
66
-
dB
-
-
-
MHz
[1]
Analog TV signal processing
Video part
Vi(IF)(RMS)
RMS IF input voltage
GVIF(cr)
control range VIF gain
fVIF
VIF frequency
see Table 24
∆fVIF(dah)
digital acquisition help VIF
frequency window
related to fVIF
all standards except M/N
-
±2.3
-
MHz
M/N standard
-
±1.8
-
MHz
1.7
2.0
2.3
V
Vo(video)(p-p)
peak-to-peak video output voltage
positive or negative
modulation; normal mode
and sound carrier on;
W6[1] = 0; W4[7] = 0;
W7[4] = 0; see Figure 10
Gdif
differential gain
“ITU-T J.63 line 330”
ϕdif
differential phase
B/G standard
-
-
5
%
L standard
-
-
7
%
B/G standard
-
2
4
deg
L standard
-
2
4
deg
“ITU-T J.63 line 330”
TDA9897_TDA9898_4
Product data sheet
[2][3]
[2][3]
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
3 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 1.
Quick reference data …continued
VP = 5 V; Tamb = 25 °C.
Symbol
Parameter
Bvideo(−3dB)
−3 dB video bandwidth
αSC1
first sound carrier attenuation
Conditions
Min
Typ
Max
Unit
trap bypass mode and
sound carrier off; AC load:
CL < 20 pF, RL > 1 kΩ
[4]
6
8
-
MHz
M/N standard;
f = fSC1 = 4.5 MHz;
see Figure 21
[4]
38
-
-
dB
B/G standard;
f = fSC1 = 5.5 MHz;
see Figure 23
[4]
35
-
-
dB
[2][5]
53
57
-
dB
(S/N)w
weighted signal-to-noise ratio
normal mode and sound
carrier on; B/G standard;
50 % grey video signal;
unified weighting filter
(“ITU-T J.61”);
see Figure 20
PSRRCVBS
power supply ripple rejection on
pin CVBS
normal mode and sound
carrier on; fripple = 70 Hz;
video signal; grey level;
positive and negative
modulation; see Figure 11
[2]
14
20
-
dB
∆IAFC/∆fVIF
change of AFC current with VIF
frequency
AFC TV mode
[6]
0.85
1.05
1.25
µA/kHz
Vo(AF)(RMS)
RMS AF output voltage
FM: QSS mode;
27 kHz FM deviation;
50 µs de-emphasis
430
540
650
mV
AM: 54 % modulation
400
500
600
mV
THD
total harmonic distortion
FM: 50 µs de-emphasis;
FM deviation: for TV mode
27 kHz and for radio mode
22.5 kHz
-
0.15
0.50
%
AM: 54 % modulation;
BP on; see Figure 33
-
0.5
1.0
%
80
100
-
kHz
FM: 27 kHz FM deviation;
50 µs de-emphasis; vision
carrier unmodulated;
FM PLL only
48
56
-
dB
AM: BP off
44
50
-
dB
14
20
-
dB
Audio part
f−3dB(AF)
AF cut-off frequency
W3[2] = 0; W3[4] = 0;
without de-emphasis;
FM window
width = 237.5 kHz
(S/N)w(AF)
AF weighted signal-to-noise ratio
“ITU-R BS.468-4”
PSRR
power supply ripple rejection
fripple = 70 Hz; see Figure 11
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
4 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 1.
Quick reference data …continued
VP = 5 V; Tamb = 25 °C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vo(RMS)
RMS output voltage
IF intercarrier single-ended
to GND; see Figure 9 and
Table 21
B/G standard;
SC1 on; SC2 off;
internal BP via FM AGC
90
140
180
mV
L standard; without
modulation; W7[5] = 0;
internal BP + 6 dB
90
140
180
mV
2
-
300
mV
0.85
1.05
1.25
µA/kHz
35
46
-
dB
-
1.0
1.1
V
FM sound part
Vi(FM)(RMS)
RMS FM input voltage
gain controlled operation;
W1[1:0] = 10 or
W1[1:0] = 11 or
W1[1:0] = 01; see Figure 9
∆IAFC/∆fRIF
change of AFC current with RIF
frequency
AFC radio mode
αAM
AM suppression
referenced to 27 kHz
FM deviation;
50 µs de-emphasis;
AM: f = 1 kHz; m = 54 %
[6]
Digital TV signal processing
Digital direct IF
Vo(dif)(p-p)
peak-to-peak differential output
voltage
between pin OUT2A and
pin OUT2B
[7]
W4[7] = 0
W4[7] = 1
-
0.50
0.55
V
[8]
-
83
-
dB
60
66
-
dB
fripple = 70 Hz
-
60
-
dB
fripple = 20 kHz
-
60
-
dB
GIF(max)
maximum IF gain
GIF(cr)
control range IF gain
[8]
power supply ripple rejection
[8]
PSRR
output peak-to-peak level to
input RMS level ratio
residual spurious at nominal
differential output voltage
dependent on power supply
ripple
Digital low IF
Vo(dif)(p-p)
peak-to-peak differential output
voltage
between pin OUT1A and
pin OUT1B; W4[7] = 0
[7]
-
2
-
V
GIF(max)
maximum IF gain
output peak-to-peak level to
input RMS level ratio
[8]
-
89
-
dB
GIF(cr)
control range IF gain
[8]
60
66
-
dB
fsynth
synthesizer frequency
-
-
-
MHz
see Table 34 and Table 35
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
5 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 1.
Quick reference data …continued
VP = 5 V; Tamb = 25 °C.
Symbol
Parameter
Conditions
ϕn(synth)
synthesizer phase noise
with 4 MHz crystal oscillator
reference; fsynth = 31 MHz;
fIF = 36 MHz
αripple(pb)LIF
low IF pass-band ripple
Min
Typ
Max
Unit
at 1 kHz
[8]
89
99
-
dBc/Hz
at 10 kHz
[8]
89
99
-
dBc/Hz
at 100 kHz
[8]
98
102
-
dBc/Hz
at 1.4 MHz
[8]
115
119
-
dBc/Hz
6 MHz bandwidth
-
-
2.7
dB
7 MHz bandwidth
-
-
2.7
dB
8 MHz bandwidth
-
-
2.7
dB
αstpb
stop-band attenuation
8 MHz band; f = 15.75 MHz
30
40
-
dB
αimage
image rejection
−10 MHz to 0 MHz; BP on
30
34
-
dB
C/N
carrier-to-noise ratio
at fo = 4.9 MHz;
Vi(IF) = 10 mV (RMS);
see Figure 37
112
118
-
dBc/Hz
-
4
-
MHz
15
150
500
mV
[8][9][10]
Reference frequency input from external source
fref
reference frequency
W7[7] = 0
Vref(RMS)
RMS reference voltage
W7[7] = 0; see Figure 34
and Figure 46
[11]
[1]
Values of video and sound parameters can be decreased at VP = 4.5 V.
[2]
AC load; CL < 20 pF and RL > 1 kΩ. The sound carrier frequencies (depending on TV standard) are attenuated by the integrated sound
carrier traps.
[3]
Condition: luminance range (5 steps) from 0 % to 100 %. Measurement value is based on 4 of 5 steps.
[4]
The sound carrier trap can be bypassed by setting the I2C-bus bit W2[0] to logic 0; see Table 23. In this way the full composite video
spectrum appears at pin CVBS. The video amplitude is reduced to 1.1 V (p-p).
[5]
Measurement using 200 kHz high-pass filter, 5 MHz low-pass filter and subcarrier notch filter (“ITU-T J.64”).
[6]
To match the AFC output signal to different tuning systems a current output is provided. The test circuit is given in Figure 19. The
AFC steepness can be changed by resistors R1 and R2.
[7]
With single-ended load for fIF < 45 MHz RL ≥ 1 kΩ and CL ≤ 5 pF to ground and for fIF = 45 MHz to 60 MHz RL = 1 kΩ and CL ≤ 3 pF to
ground.
[8]
This parameter is not tested during production and is only given as application information.
[9]
Noise level is measured without input signal but AGC adjusted corresponding to the given input level.
[10] Set with AGC nominal output voltage as reference. For C/N measurement switch input signal off.
[11] The tolerance of the reference frequency determines the accuracy of VIF AFC, RIF AFC, FM demodulator center frequency, maximum
FM deviation, sound trap frequency, LIF band-pass cut-off frequency, as well as the accuracy of the synthesizer.
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
6 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
5. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
TDA9897HL/V3
LQFP48
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm
SOT313-2
TDA9897HN/V3
HVQFN48
plastic thermal enhanced very thin quad flat package; no leads;
48 terminals; body 7 × 7 × 0.85 mm
SOT619-1
TDA9898HL/V3
LQFP48
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm
SOT313-2
TDA9898HN/V3
HVQFN48
plastic thermal enhanced very thin quad flat package; no leads;
48 terminals; body 7 × 7 × 0.85 mm
SOT619-1
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
7 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
6. Block diagram
SDA
SCL
23
24
i.c.
ADRSEL BVS
14
25
GNDD
32
22
I2C-BUS
TDA9898
AGCDIN
FM peak
36
SIF AGC
A
AM average
B
sideband
IF3A
IF3B
IF1A
IF1B
SYNTHESIZER
3
Q
4
I
IF2B
CIFAGC
i.c.
D
VCO
6
Q
7
NYQUIST
FILTER
I
VIF PLL
IF2A
C
SIDEBAND
FILTER
E
sideband (L-accent)
9
10
VIF AGC
5
VIF AFC
45
ACQUISITION
HELP
I2C-BUS
TOPNEG
DECODER
SOUND
CARRIER
TRAP
GROUP
DELAY
EQUALIZER
F
standard
TOP1
TAGC
trap reference
TOP2
PEAK
AGC
TUNER
RSSI
DETECTOR
AND
L STANDARD
TUNER
AGC
47
SYNTHESIZER
AND VCO
standard
G
I2C-BUS TOPPOS
AND RSSI
H
J
48
2, 18, 37
GND
n.c.
Fig 1.
8
11
13
1
38
34
CTAGC
TOP2
optional tuner
AGC TOP for
positive
modulation and
radio signal
strength detector
onset
LFVIF
LFSYN2
LFSYN1
GDS
001aai732
Block diagram of TDA9898 (continued in Figure 2)
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
8 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
4 MHz reference
input
R(2)
R(2)
EXTERNAL SOUND
BAND-PASS FILTER(1)
VP
43, 44
GNDA
40, 41
SUPPLY
EXTFILO EXTFILI
15
17
FREF
46
OPTXTAL
39
4 MHz FREQUENCY
REFERENCE
+3 dB
29
A
B
30
TDA9898
OUTPUT
SWITCH
26
27
C
BP on/off
BAND-PASS
FILTER
D
OUT2A
OUT2B
OUT1A
OUT1B
FM
AGC
21
FM
SWITCH
EXTFMI
20 CDEEM
31
FM
NB PLL
AUD
28 CAF
AM
DEMODULATOR
E
AM
SWITCH
33
VIF AGC
TAGC
SIF AGC
FM AGC
AFC
F
G
H
16
VIF
AGC
port
12
35
port
TAGC
J
I2C-bus
42
CVBS
MPP
PORT1
PORT2
PORT3
port
19
LFFM
001aai733
(1) Optional.
(2) Connect resistor if input or crystal is not used.
Fig 2.
Block diagram of TDA9898 (continued from Figure 1)
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
9 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
SDA
SCL
23
i.c.
24
ADRSEL BVS
14
25
GNDD
32
22
I2C-BUS
TDA9897
AGCDIN
FM peak
36
SIF AGC
A
AM average
B
sideband
IF3A
IF3B
IF1A
IF1B
SYNTHESIZER
3
Q
4
I
IF2B
D
VCO
6
Q
7
NYQUIST
FILTER
I
VIF PLL
IF2A
C
SIDEBAND
FILTER
E
sideband
9
10
VIF AGC
VIF AFC
i.c.
45
ACQUISITION
HELP
I2C-BUS
TOPNEG
DECODER
SOUND
CARRIER
TRAP
GROUP
DELAY
EQUALIZER
F
standard
TOP1
TAGC
trap reference
TOP2
PEAK
AGC
TUNER
RSSI
DETECTOR
AND
L STANDARD
TUNER
AGC
47
SYNTHESIZER
AND VCO
standard
G
I2C-BUS TOPPOS
AND RSSI
H
J
48
2, 5, 18, 37
GND
n.c.
Fig 3.
8
11
13
1
38
34
CTAGC
TOP2
optional tuner
AGC TOP for
positive
modulation and
radio signal
strength detector
onset
LFVIF
LFSYN2
LFSYN1
GDS
001aai734
Block diagram of TDA9897 (continued in Figure 4)
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
10 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
4 MHz reference
input
R(2)
R(2)
EXTERNAL SOUND
BAND-PASS FILTER(1)
VP
43, 44
GNDA
40, 41
SUPPLY
EXTFILO EXTFILI
15
17
FREF
46
OPTXTAL
39
4 MHz FREQUENCY
REFERENCE
+3 dB
29
A
B
30
TDA9897
OUTPUT
SWITCH
26
27
C
BP on/off
BAND-PASS
FILTER
D
OUT2A
OUT2B
OUT1A
OUT1B
FM
AGC
21
FM
SWITCH
EXTFMI
20 CDEEM
31
FM
NB PLL
AUD
28 CAF
AM
DEMODULATOR
E
AM
SWITCH
33
VIF AGC
TAGC
SIF AGC
FM AGC
AFC
F
G
H
16
VIF
AGC
port
12
35
port
TAGC
J
I2C-bus
42
CVBS
MPP
PORT1
PORT2
PORT3
port
19
LFFM
001aai735
(1) Optional.
(2) Connect resistor if input or crystal is not used.
Fig 4.
Block diagram of TDA9897 (continued from Figure 3)
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
11 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
7. Pinning information
37 n.c.
38 LFSYN1
39 OPTXTAL
40 GNDA
41 GNDA
42 PORT3
44 VP
43 VP
45 i.c.
46 FREF
47 TAGC
48 GND
7.1 Pinning
LFSYN2
1
36 AGCDIN
n.c.
2
35 PORT2
IF3A
3
34 GDS
IF3B
4
33 CVBS
CIFAGC(1)
5
32 BVS
IF1A
6
IF1B
7
CTAGC
8
29 OUT2A
IF2A
9
28 CAF
31 AUD
TDA9897HL
TDA9898HL
30 OUT2B
IF2B 10
27 OUT1B
TOP2 11
26 OUT1A
PORT1 12
SCL 24
SDA 23
GNDD 22
EXTFMI 21
LFFM 19
CDEEM 20
n.c. 18
EXTFILI 17
MPP 16
EXTFILO 15
i.c. 14
LFVIF 13
25 ADRSEL
008aaa150
(1) Not connected for TDA9897HL.
Fig 5.
Pin configuration for LQFP48
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
12 of 103
TDA9897; TDA9898
NXP Semiconductors
37 n.c.
38 LFSYN1
39 OPTXTAL
40 GNDA
41 GNDA
42 PORT3
43 VP
44 VP
45 i.c.
46 FREF
terminal 1
index area
47 TAGC
48 GND
Multistandard hybrid IF processing
LFSYN2
1
36 AGCDIN
n.c.
2
35 PORT2
IF3A
3
34 GDS
IF3B
4
33 CVBS
CIFAGC(1)
5
32 BVS
IF1A
6
IF1B
7
CTAGC
8
29 OUT2A
IF2A
9
28 CAF
31 AUD
TDA9897HN
TDA9898HN
30 OUT2B
IF2B 10
27 OUT1B
TOP2 11
26 OUT1A
SCL 24
SDA 23
GNDD 22
EXTFMI 21
CDEEM 20
LFFM 19
n.c. 18
EXTFILI 17
MPP 16
EXTFILO 15
i.c. 14
25 ADRSEL
LFVIF 13
PORT1 12
008aaa151
Transparent top view
(1) Not connected for TDA9897HN.
Fig 6.
Pin configuration for HVQFN48
7.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
LFSYN2
1
loop filter synthesizer 2 (conversion synthesizer)
n.c.
2
not connected
IF3A
3
IF symmetrical input 3 for sound
IF3B
4
CIFAGC
5
TDA9898: IF AGC capacitor; L standard
TDA9897: not connected
IF1A
6
IF symmetrical input 1 for vision or digital
IF1B
7
CTAGC
8
TAGC capacitor
IF2A
9
IF symmetrical input 2 for vision or digital
IF2B
10
TOP2
11
TOP potentiometer for positive modulated standards and RSSI reference
PORT1
12
digital port function 1 or VIF AGC monitor output
LFVIF
13
loop filter VIF PLL
i.c.
14
internally connected; connect to ground
EXTFILO
15
output to external filter
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 3.
Pin description …continued
Symbol
Pin
Description
MPP
16
multipurpose pin: VIF AGC or SIF AGC or FM AGC or TAGC or VIF AFC or
FM AFC monitor output
EXTFILI
17
input from external filter
n.c.
18
not connected
LFFM
19
loop filter FM PLL
CDEEM
20
de-emphasis capacitor
EXTFMI
21
external FM input
GNDD
22
digital ground
SDA
23
I2C-bus data input and output
SCL
24
I2C-bus clock input
ADRSEL
25
address select
OUT1A
26
low IF or 2nd sound intercarrier symmetrical output
OUT1B
27
CAF
28
Direct Current (DC) decoupling capacitor
OUT2A
29
1st Digital IF (DIF) symmetrical output
OUT2B
30
AUD
31
audio signal output
BVS
32
I2C-bus voltage select
CVBS
33
composite video signal output
GDS
34
additional video group delay select; leave open for default operation[1]
PORT2
35
digital port function 2
AGCDIN
36
AGC input for DIF amplifier for e.g. input from channel decoder AGC
n.c.
37
not connected
LFSYN1
38
loop filter synthesizer 1 (filter control synthesizer)
OPTXTAL
39
optional quartz input
GNDA
40
analog ground
GNDA
41
analog ground
PORT3
42
digital port function 3 or TAGC monitor output
VP
43
supply voltage
VP
44
supply voltage
i.c.
45
internally connected; connect to ground
FREF
46
4 MHz reference input
TAGC
47
TAGC output
GND
48
ground; plateau connection
[1]
Recommendation: Leave this pin open or use a capacitor to GND, as shown in the application diagrams in
Figure 47, Figure 48 and Figure 49.
TDA9897_TDA9898_4
Product data sheet
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
8. Functional description
8.1 IF input switch
Different signal bandwidth can be handled by using two signal processing chains with
individual gain control.
Switch configuration allows independent selection of filter for analog VIF and for analog
SIF (used at same time) or DIF.
The switch takes into account correct signal selection for TAGC in the event of VIF and
DIF signal processing.
8.2 VIF demodulator
ATV demodulation using 6 MHz DVB window (band-pass) filter (for 6 MHz, 7 MHz or
8 MHz channel width).
IF frequencies adapted to enable the use of different filter configurations. The Nyquist
processing is integrated. The integrated Nyquist processing provides also adjacent
channel suppression. Sideband switch supplies selection of lower or upper sideband (e.g.
for L-accent).
For optional use of standard Nyquist filter the integrated Nyquist processing can be
switched off.
Equalizer provides optimum pulse response at different standards [e.g. to cope with
higher demands for Liquid Crystal Display (LCD) TV].
Integrated sound traps.
Sound trap reference independent from received 2nd sound IF (reference taken from
integrated reference synthesizer).
IF level selection provides an optimum adaptation of the demodulator to high linearity or
low noise.
8.3 VIF AGC and tuner AGC
8.3.1 Mode selection of VIF AGC
Peak white AGC for positive modulation mode with adaptation for speed up and black level
AGC (using proven system from TDA9886).
For negative modulation mode equal response times for increasing or decreasing input
level (optimum for amplitude fading) or normal peak AGC or ultra fast peak AGC.
8.3.2 VIF AGC monitor
VIF AGC DC voltage monitor output (with expanded internal characteristic).
VIF AGC read out via I2C-bus (for IF level indication) with zero-calibration via TOP setting
(TOP setting either via I2C-bus or via TOP potentiometer).
TDA9897_TDA9898_4
Product data sheet
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
8.3.3 Tuner AGC
Independent integral tuner gain control loop (not nested with VIF AGC). Integral
characteristic provides high control accuracy.
Accurate setting of tuner control onset (TOP) for integral tuner gain control loop via
I2C-bus.
For L standard, TAGC remains VIF AGC nested, as from field experience in the past this
narrowband TAGC gives best performance.
Thus two switchable TAGC systems for negative/DIF and positive modulation
implemented.
L standard tuner time constant switching integrated (= speed up function in the event of
step into high input levels), to speed up settling time.
For TOP setting at L standard, additional adjustment via optional potentiometer or I2C-bus
is provided.
Tuner AGC status bit provided.
8.4 DIF/SIF FM and AM sound AGC
External AGC control input for DIF. DIF includes direct IF and low IF.
Integrated gain control loop for SIF.
AGC control for FM SIF related to used SAW bandwidth.
Peak AGC control in the event of FM SIF.
Ultra fast SIF AGC time constant when VIF AGC set to ultra fast mode.
Slow average AGC control in the event of AM sound.
AM sound AGC related to AM sound carrier level.
Fast AM sound AGC in the event of fast VIF AGC (speed up).
SIF/FM AGC DC voltage monitor output with expanded internal characteristic.
8.5 Frequency phase-locked loop for VIF
Basic function as previous TDA9887 design.
PLL gating mode for positive and negative modulation, optional.
PLL optimized for either overmodulation or strong multipath.
TDA9897_TDA9898_4
Product data sheet
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
8.6 DIF/SIF converter stage
Frequency conversion with sideband suppression.
Selection mode of upper or lower sideband for pass or suppression.
Suppression around zero for frequency conversion.
Conversion mode selection via synthesizer for DIF and radio mode or via VIF Frequency
Phase-Locked Loop (FPLL) for TV QSS sound (FM/AM).
External BP filter (e.g. for 4.5 MHz) for additional filtering, optional.
Bypass mode selection for use of external filter.
Integrated SIF BP tracking filter for chroma suppression.
Integrated tracking filters for LIF.
Symmetrical output stages for direct IF, LIF and 2nd SIF (intercarrier signal).
Second narrowband gain control loop for 2nd SIF via FM PLL.
8.7 Mono sound demodulator
8.7.1 FM PLL narrowband demodulation
Additional external input for either TV or radio intercarrier signal.
FM carrier selection independent from VIF trap, because VIF trap uses reference via
synthesizer.
FM wide and ultra wide mode with adapted loop bandwidth and different selectable
FM acquisition window widths to cope with FM overmodulation conditions.
8.7.2 AM sound demodulation
AM sound envelope detector.
L and L-accent standard without SAW switching (done by sideband selection of SIF
converter).
8.8 Audio amplifier
Different gain settings for FM sound to adapt to different FM deviation.
Switchable de-emphasis for FM sound.
Automatic mute function when FM PLL is unlocked.
Forced mute function.
Output amplifier for AM sound.
TDA9897_TDA9898_4
Product data sheet
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
8.9 Synthesizer
The synthesizer supports SIF/DIF frequency conversion. A large set of synthesizer
frequencies in steps of 0.5 MHz enables flexible combination of SAW filter and required
conversion frequency.
Synthesizer loop internally adapted to divider ratio range for optimum phase noise
requirement (loop bandwidth).
Synthesizer reference either via 4 MHz crystal or via an external source. Individual pins
for crystal and external reference allows optimum interface definition and supports use of
custom reference frequency offset.
8.10 I2C-bus transceiver and slave address
Four different I2C-bus device addresses to enable application with multi-IC use.
I2C-bus transceiver input ports can handle three different I2C-bus voltages.
Read-out functions as TDA9887 plus additional read out of VIF AGC and VIFLOCK,
BLCKLEV and TAGC status.
Table 4.
Slave address detection
Slave address
Selectable address bit
Pin ADRSEL
A3
A0
MAD1
0
1
GND
MAD2
0
0
VP
MAD3
1
1
resistor to GND
MAD4
1
0
resistor to VP
9. I2C-bus control
Table 5.
Slave addresses
For MAD activation via pin ADRSEL: see Table 4.
Slave address
Bit
Name
Value
A6
A5
A4
A3
A2
A1
A0
MAD1
43h
1
0
0
0
0
1
1
MAD2
42h
1
0
0
0
0
1
0
MAD3
4Bh
1
0
0
1
0
1
1
MAD4
4Ah
1
0
0
1
0
1
0
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Product data sheet
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
9.1 Read format
S
BYTE 1
A
BYTE 2
A
A6 to A0
R/W
D7 to D0
D7 to D0
slave address
1
data (R1)
data (R2)
from master to slave
Table 6.
NA
S = START condition
A = acknowledge
NA = not acknowledge
P = STOP condition
from slave to master
Fig 7.
BYTE 3
P
001aad167
I2C-bus read format (slave transmits data)
R1 - data read register 1 bit allocation
7
6
5
4
3
2
1
0
AFCWIN
BLCKLEV
CARRDET
AFC4
AFC3
AFC2
AFC1
PONR
Table 7.
R1 - data read register 1 bit description
Bit
Symbol
Description
7
AFCWIN
AFC window[1]
1 = VCO in ±1.6 MHz AFC window[2]
1 = VCO in ±0.8 MHz AFC window[3]
0 = VCO out of ±1.6 MHz AFC window[2]
0 = VCO out of ±0.8 MHz AFC window[3]
6
BLCKLEV
black level detection
1 = black level detected
0 = no black level detected
CARRDET FM carrier detection[4]
5
1 = detection (FM PLL is locked and level is less than 6 dB below gain
controlled range of FM AGC)
0 = no detection
4 to 1
AFC[4:1]
automatic frequency control; see Table 8
0
PONR
power-on reset
1 = after power-on reset or after supply breakdown
0 = after a successful reading of the status register
[1]
If no IF input is applied, then bit AFCWIN can be logic 1 due to the fact that the VCO is forced to the AFC
window border for fast lock-in behavior.
[2]
All standards except M/N standard.
[3]
M/N standard.
[4]
Typical time constant of FM carrier detection is 50 ms. The minimal recommended wait time for read out is
80 ms.
TDA9897_TDA9898_4
Product data sheet
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 8.
Automatic frequency control bits
fnom is the nominal frequency.
f[1]
Bit
AFC4
AFC3
AFC2
AFC1
R1[4]
R1[3]
R1[2]
R1[1]
0
1
1
1
≤ (fnom − 187.5 kHz)
0
1
1
0
fnom − 162.5 kHz
0
1
0
1
fnom − 137.5 kHz
0
1
0
0
fnom − 112.5 kHz
0
0
1
1
fnom − 87.5 kHz
0
0
1
0
fnom − 62.5 kHz
0
0
0
1
fnom − 37.5 kHz
0
0
0
0
fnom − 12.5 kHz
1
1
1
1
fnom + 12.5 kHz
1
1
1
0
fnom + 37.5 kHz
1
1
0
1
fnom + 62.5 kHz
1
1
0
0
fnom + 87.5 kHz
1
0
1
1
fnom + 112.5 kHz
1
0
1
0
fnom + 137.5 kHz
1
0
0
1
fnom + 162.5 kHz
1
0
0
0
≥ (fnom + 187.5 kHz)
[1]
In ATV mode f means vision intermediate frequency; in radio mode f means radio intermediate frequency.
Table 9.
R2 - data read register 2 bit allocation
7
6
5
4
3
2
1
0
VIFLOCK
TAGC
VAGC5
VAGC4
VAGC3
VAGC2
VAGC1
VAGC0
Table 10.
R2 - data read register 2 bit description
Bit
Symbol
Description
7
VIFLOCK
VIF PLL lock-in detection
1 = VIF PLL is locked
0 = VIF PLL is not locked
6
TAGC
tuner AGC
1 = active
0 = inactive
5 to 0
VAGC[5:0] AGC level detector; VIF AGC in ATV mode, SIF AGC in radio mode and
DIF AGC in DTV mode; see Table 11
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Product data sheet
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 11.
AGC bits
Bit
VAGC5
VAGC4
VAGC3
VAGC2
VAGC1
VAGC0
R2[5]
R2[4]
R2[3]
R2[2]
R2[1]
R2[0]
1
1
1
1
1
1
0 (TOP)[1]
1
1
1
1
1
0
−0.04
1
1
1
1
0
1
−0.08
1
1
1
1
0
0
−0.12
1
1
1
0
1
1
−0.16
1
1
1
0
1
0
−0.20
1
1
1
0
0
1
−0.24
1
1
1
0
0
0
−0.28
1
1
0
1
1
1
−0.32
1
1
0
1
1
0
−0.36
1
1
0
1
0
1
−0.40
1
1
0
1
0
0
−0.44
1
1
0
0
1
1
−0.48
1
1
0
0
1
0
−0.52
1
1
0
0
0
1
−0.56
1
1
0
0
0
0
−0.60
1
0
1
1
1
1
−0.64
1
0
1
1
1
0
−0.68
1
0
1
1
0
1
−0.72
1
0
1
1
0
0
−0.76
1
0
1
0
1
1
−0.80
1
0
1
0
1
0
−0.84
1
0
1
0
0
1
−0.88
1
0
1
0
0
0
−0.92
1
0
0
1
1
1
−0.96
1
0
0
1
1
0
−1.00
1
0
0
1
0
1
−1.04
1
0
0
1
0
0
−1.08
1
0
0
0
1
1
−1.12
1
0
0
0
1
0
−1.16
1
0
0
0
0
1
−1.20
1
0
0
0
0
0
−1.24
0
1
1
1
1
1
−1.28
0
1
1
1
1
0
−1.32
0
1
1
1
0
1
−1.36
0
1
1
1
0
0
−1.40
0
1
1
0
1
1
−1.44
0
1
1
0
1
0
−1.48
0
1
1
0
0
1
−1.52
TDA9897_TDA9898_4
Product data sheet
Typical
∆VAGC(VIF)
(V)
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 11.
AGC bits …continued
Bit
VAGC4
VAGC3
VAGC2
VAGC1
VAGC0
R2[5]
R2[4]
R2[3]
R2[2]
R2[1]
R2[0]
0
1
1
0
0
0
−1.56
0
1
0
1
1
1
−1.60
0
1
0
1
1
0
−1.64
0
1
0
1
0
1
−1.68
0
1
0
1
0
0
−1.72
0
1
0
0
1
1
−1.76
0
1
0
0
1
0
−1.80
0
1
0
0
0
1
−1.84
0
1
0
0
0
0
−1.88
0
0
1
1
1
1
−1.92
0
0
1
1
1
0
−1.96
0
0
1
1
0
1
−2.00
0
0
1
1
0
0
−2.04
0
0
1
0
1
1
−2.08
0
0
1
0
1
0
−2.12
0
0
1
0
0
1
−2.16
0
0
1
0
0
0
−2.20
0
0
0
1
1
1
−2.24
0
0
0
1
1
0
−2.28
0
0
0
1
0
1
−2.32
0
0
0
1
0
0
−2.36
0
0
0
0
1
1
−2.40
0
0
0
0
1
0
−2.44
0
0
0
0
0
1
−2.48
0
0
0
0
0
0
−2.52
[1]
The reference of 0 (TOP) can be adjusted via TOPPOS[4:0] (register W10; see Table 47 and Table 45) or
via potentiometer at pin TOP2.
TDA9897_TDA9898_4
Product data sheet
Typical
∆VAGC(VIF)
(V)
VAGC5
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
9.2 Write format
S
BYTE 1
A
BYTE 2
A
BYTE 3
A
BYTE n
A6 to A0
R/W
A7 to A0
bits 7 to 0
bits 7 to 0
slave address
0
subaddress
data 1
data n
from master to slave
A
S = START condition
A = acknowledge
P = STOP condition
from slave to master
Fig 8.
P
001aad166
I2C-bus write format (slave receives data)
9.2.1 Subaddress
Table 12.
W0 - subaddress register bit allocation
7
6
5
4
3
2
1
0
A7
A6
A5
A4
A3
A2
A1
A0
Table 13.
W0 - subaddress register bit description
Bit
Symbol
Description
7 to 4
A[7:4]
has to be set to logic 0
3 to 0
A[3:0]
subaddress; see Table 14
Table 14.
Subaddress control bits
Bit
Mode
A3
A2
A1
A0
0
0
0
0
subaddress for register W1
0
0
0
1
subaddress for register W2
0
0
1
0
subaddress for register W3
0
0
1
1
subaddress for register W4
0
1
0
0
subaddress for register W5
0
1
0
1
subaddress for register W6
0
1
1
0
subaddress for register W7
0
1
1
1
subaddress for register W8
1
0
0
0
subaddress for register W9
1
0
0
1
subaddress for register W10
1
0
1
0
subaddress for register W11
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 15. I2C-bus write register overview
The register setting after power-on is not specified.
Register 7
6
5
4
3
W1[1]
RADIO
STD1
STD0
TV
0
0
FM
EXTFIL
W2[2]
MOD
STD4
STD3
STD2
SB
PLL
GATE
TRAP
W3[3]
RESCAR
AMUTE
FMUTE
FMWIDE0
DEEMT
DEEM
AGAIN1
AGAIN0
W4[4]
VIFLEVEL
BP
MPPS1
MPPS0
AMMODE
IFIN1
IFIN0
VIFIN
W5[5]
FSFREQ1
FSFREQ0
SFREQ5
SFREQ4
SFREQ3
SFREQ2
SFREQ1
SFREQ0
W6[6]
TAGC1
TAGC0
AGC2
AGC1
FMWIDE1
TWOFLO
VIDEO1V7
DIRECT
W7[7]
EXTFILO
VAGC
SIFLEVEL
VIDLEVEL
PORT1
MODEP1
FILOUTBP
NYQOFF
W8[8]
FEATURE
AVIDRED
MODEP3
TAGCIN3
FORCESP
PORT3
PORT2
0
W9[9]
DAGCSLOPE TAGCIS
TAGCTC
TOPNEG4
TOPNEG3
TOPNEG2
TOPNEG1
TOPNEG0
W10[10]
0
READTAGC XPOTPOS
TOPPOS4
TOPPOS3
TOPPOS2
TOPPOS1
TOPPOS0
W11[11]
0
0
OFFSETP
BLACKAGC GDEQ
VIFIN3
VIF31875
OFFSETN
[1]
See Table 17 for detailed description of W1.
[2]
See Table 23 for detailed description of W2.
[3]
See Table 27 for detailed description of W3.
[4]
See Table 29 for detailed description of W4.
[5]
See Table 33 for detailed description of W5.
[6]
See Table 37 for detailed description of W6.
[7]
See Table 40 for detailed description of W7.
[8]
See Table 42 for detailed description of W8.
[9]
See Table 44 for detailed description of W9.
2
1
0
[10] See Table 47 for detailed description of W10.
[11] See Table 50 for detailed description of W11.
9.2.2 Description of data bytes
Table 16.
W1 - data write register bit allocation
7
6
5
4
3
2
1
0
RADIO
STD1
STD0
TV
0
0
FM
EXTFIL
Table 17.
W1 - data write register bit description
Bit
Symbol
Description
7
RADIO
FM mode
1 = radio
0 = ATV/DTV
6 and 5
STD[1:0]
2nd sound IF; see Table 18 and Table 19
4
TV
TV mode
1 = ATV QSS
0 = DTV; direct IF or LIF; depends on setting of TV mode (W6[0])
3 and 2
-
0 = fixed value
1 and 0
FM and EXTFIL FM and output switching; see Table 21
TDA9897_TDA9898_4
Product data sheet
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Rev. 04 — 25 May 2009
24 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 18. Intercarrier sound BP and FM PLL frequency select for ATV, QSS mode
For description of bit MOD refer to Table 23 and bits FSFREQ[1:0] are described in Table 33.
Bit
fFMPLL
(MHz)
Sound BP
RADIO
MOD
STD1
STD0
FSFREQ1
FSFREQ0
W1[7]
W2[7]
W1[6]
W1[5]
W5[7]
W5[6]
0
1
0
0
X
X
4.5
M/N standard
0
1
0
1
X
X
5.5
B/G standard
0
1
1
0
X
X
6.0
I standard
0
1
1
1
X
X
6.5
D/K standard
0
0
1
1
X
X
off
L/L-accent standard
fFMPLL
(MHz)
Sound BP
Table 19. Intercarrier sound BP and FM PLL frequency select for radio
For description of bit MOD refer to Table 23 and bits FSFREQ[1:0] are described in Table 33.
Bit
RADIO
MOD
STD1
STD0
FSFREQ1
FSFREQ0
W1[7]
W2[7]
W1[6]
W1[5]
W5[7]
W5[6]
1
1
X
X
0
0
4.5
M/N standard
1
1
X
X
0
1
5.5
B/G standard
1
1
X
X
1
0
6.0
I standard
1
1
X
X
1
1
6.5
D/K standard
Table 20. Intercarrier sound FM PLL frequency select for radio 10.7 MHz
For description of bit MOD refer to Table 23 and for BP refer to Table 29.
Bit
fFMPLL (MHz)
BP
MOD
RADIO
W4[6]
W2[7]
W1[7]
0
0
1
TDA9897_TDA9898_4
Product data sheet
10.7
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 21. 2nd intercarrier and sound I/O switching
Switch input numbering in accordance with Figure 9.
AMMODE MOD
FM
EXTFIL Audio
mode
Input signal selection
Signal at OUT1A and OUT1B
Mono sound
Input switch
Output switch
FM
AM
Signal
input input path
Input Signal path
Demodulation
via
1
X
internal
6
internal BP
W4[3]
W2[7] W1[1] W1[0]
X
1
0
0
X
1
0
1
2
X
EXTFILI 7
internal BP
external BP
X
1
1
0
3
X
EXTFMI 7
internal BP
external input
X
1
1
1
2
X
EXTFILI 6
external BP via FM AGC external BP
0
0
0
0
5
internal
6
internal BP + 6 dB
internal BP
0
0
0
1
AM
1
sound 1 X
5
internal
7
internal BP
internal BP
0
0
1
0
X
5
internal
7
internal BP
internal BP
0
0
1
1
2
5
EXTFILI 6
external BP
internal BP
1
0
0
0
4
EXTFILI 7
internal BP
external BP
1
0
0
1
AM
2
sound 2 X
5
internal
7
internal BP
internal BP
1
0
1
0
X
5
internal
7
internal BP
internal BP
1
0
1
1
2
4
EXTFILI 6
external BP
external BP
FM
sound
internal BP via FM AGC
BYPASS
output
switch
7
6
internal
BAND-PASS
W7.1 = 0
W7.1 = 1
3 dB
external filter output
external filter input
external FM input
FM:
input
AGC
switch
amplifier
1
2
3
AM:
fixed-gain
amplifier
OUT1A
OUT1B
FM PLL
input
switch
4
5
AM
DEMODULATOR
EXTFILI
EXTFILO
Fig 9.
EXTFMI
008aaa145
Signal path for intercarrier (2nd SIF) processing
TDA9897_TDA9898_4
Product data sheet
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26 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 22.
W2 - data write register bit allocation
7
6
5
4
3
2
1
0
MOD
STD4
STD3
STD2
SB
PLL
GATE
TRAP
Table 23.
W2 - data write register bit description
Bit
Symbol
Description
7
MOD
modulation
1 = negative; FM mono sound at ATV
0 = positive; AM mono sound at ATV
6 to 4
STD[4:2]
vision IF; see Table 24
3
SB
sideband for sound IF and digital low IF
1 = upper
0 = lower
2
PLL
operating modes; see Table 25
1
GATE
PLL gating
1 = on; fPC = fVIF ± 175 kHz
0 = off
0
TRAP
sound trap
1 = on
0 = bypass
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
27 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 24.
Vision IF
Bit
VIF31875
NYQOFF
MOD
STD4
STD3
STD2
W11[0][1]
W7[0]
W2[7]
W2[6]
W2[5]
W2[4]
fVIF (MHz) Sideband
in case of
TV = 1
W7[0] = 0
(QSS)
X
X
X
0
0
0
38.0
low
X
X
X
0
0
1
38.375
low
X
X
X
0
1
0
38.875
low
X
X
X
0
1
1
39.875
low
X
X
1
1
0
0
45.75
low
X
X
1
1
0
1
58.75
low
X
X
1
1
1
0
46.25
low
X
X
1
1
1
1
59.25
low
0
0
0
1
0
0
32.25
high
0
0
0
1
0
1
32.625
high
0
0
0
1
1
0
33.125
high
0
0
0
1
1
1
33.625
high
1
X
0
1
0
0
31.875
high
X
1
0
1
0
1
33.9
-
1
0
0
1
0
1
33.9
high
1
X
0
1
1
0
35.0
high
1
X
0
1
1
1
36.0
high
[1]
Register W11 is logical AND protected by bit W8[7]. Therefore it is required to set W8[7] = 1 to enable pass
of any W11 bit.
Table 25.
VIF PLL gating and detector mode
Bit
Gating and detector mode
MOD
PLL
W2[7]
W2[2]
0
0
0 % gating in positive modulation mode (W2[1] = 1)
0
1
36 % gating in positive modulation mode (W2[1] = 1)
1
0
π mode on; optimized for overmodulation in negative modulation mode;
fPC = fVIF ± 175 kHz
1
1
π mode off; optimized for multipath in negative modulation mode;
fPC = fVIF ± 175 kHz
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
28 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 26.
W3 - data write register bit allocation
7
6
5
4
3
2
1
0
RESCAR
AMUTE
FMUTE
FMWIDE0
DEEMT
DEEM
AGAIN1
AGAIN0
Table 27.
W3 - data write register bit description
Bit
Symbol
Description
7
RESCAR
video gain correction for residual carrier
1 = 20 % residual carrier
0 = 10 % residual carrier
6
AMUTE
auto mute
1 = on
0 = off
5
FMUTE
forced mute
1 = on
0 = off
4
FMWIDE0
FM window (W6[3] = 0)
1 = 475 kHz; normal FM phase detector steepness
0 = 237.5 kHz; high FM phase detector steepness
3
DEEMT
de-emphasis time
1 = 50 µs
0 = 75 µs
2
DEEM
de-emphasis
1 = on
0 = off
1 and 0
AGAIN[1:0] audio gain
00 = 0 dB
01 = −6 dB
10 = −12 dB (only for FM mode)
11 = −18 dB (only for FM mode)
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
29 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 28.
W4 - data write register bit allocation
7
6
5
4
3
2
1
0
VIFLEVEL
BP
MPPS1
MPPS0
AMMODE
IFIN1
IFIN0
VIFIN
Table 29.
W4 - data write register bit description
Bit
Symbol
Description
7
VIFLEVEL control of internal VIF mixer input level (W1[4] = 1) and OUT1/OUT2
output level; see Table 30
1 = reduced[1]
0 = normal
6
BP
SIF/DIF BP
1 = on (bit W6[0] = 0; see Table 37)
0 = bypass
5 and 4
MPPS[1:0] AGC or AFC output; see Table 31
3
AMMODE
AM mode extension; see Table 21
1 = second selection set
0 = first selection set
2 and 1
IFIN[1:0]
DIF/SIF input
00 = IF1A/B input
01 = IF3A/B input
10 = not used
11 = IF2A/B input
0
VIFIN
VIF input (W11[1] = 0)
1 = IF1A/B input
0 = IF2A/B input
[1]
Not recommended in combination with internal video level set to reduced (W7[4] = 1).
Table 30.
List of output signals at OUT1 and OUT2
Bit
Output signal at
TV
W1[4]
W6[0]
W1[1]
W1[0]
OUT1A,
OUT1B
0
0
X
X
low IF
off
0
1
X
X
off
direct IF
0
intercarrier[1]
off
off
1
DIRECT
X
FM
0
OUT2A,
OUT2B
1
X
0
1
intercarrier[2]
1
X
1
0
intercarrier[2]
off
1
intercarrier[1]
off
1
X
1
[1]
Intercarrier output level based on wideband AGC of SIF amplifier.
[2]
Intercarrier output level based on narrowband AGC of FM amplifier.
TDA9897_TDA9898_4
Product data sheet
EXTFIL
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
30 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 31.
Output mode at pin MPP for ATV or radio mode
Bit
Pin MPP output mode
VAGC
RADIO
MPPS1
MPPS0
W7[6]
W1[7]
W4[5]
W4[4]
0
X
0
0
gain control voltage of FM PLL
0
X
0
1
gain control voltage of SIF amplifier
0
X
1
0
TAGC monitor voltage
0
0
1
1
AFC current output, VIF PLL
0
1
1
1
AFC current output, radio mode
1
X
0
0
gain control voltage of VIF amplifier
Table 32.
W5 - data write register bit allocation
7
6
5
4
3
2
1
0
FSFREQ1
FSFREQ0
SFREQ5
SFREQ4
SFREQ3
SFREQ2
SFREQ1
SFREQ0
Table 33.
W5 - data write register bit description
Bit
Symbol
Description
7 and 6
FSFREQ[1:0] DTV filter or sound trap selection for video
ATV; sound trap; TV = 1; see Table 16 and Table 17
00 = M/N standard (4.5 MHz)
01 = B/G standard (5.5 MHz)
10 = I standard (6.0 MHz)
11 = D/K and L/L-accent standard (6.5 MHz)
DTV (low IF); upper BP cut-off frequency; TV = 0; see Table 16 and
Table 17
00 = 7.0 MHz
01 = 8.0 MHz
10 = 9.0 MHz
11 = recommended mode for direct IF; W6[0] = 1
5 to 0
SFREQ[5:0]
synthesizer frequencies; see Table 34 and Table 35
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
31 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 34.
DIF/SIF synthesizer frequencies (using bit TWOFLO = 0)
Bit
SFREQ5
fsynth (MHz)
SFREQ4
SFREQ3
SFREQ2
SFREQ1
SFREQ0
W5[5]
W5[4]
W5[3]
W5[2]
W5[1]
W5[0]
1
1
1
1
1
1
22.0
1
1
1
1
1
0
22.5
1
1
1
1
0
1
23.0
1
1
1
1
0
0
23.5
1
1
1
0
1
1
24.0
1
1
1
0
1
0
24.5
1
1
1
0
0
1
25.0
1
1
1
0
0
0
25.5
1
1
0
1
1
1
26.0
1
1
0
1
1
0
26.5
1
1
0
1
0
1
27.0
1
1
0
1
0
0
27.5
1
1
0
0
1
1
28.0
1
1
0
0
1
0
28.5
1
1
0
0
0
1
29.0
1
1
0
0
0
0
29.5
1
0
1
1
1
1
30.0
1
0
1
1
1
0
30.5
1
0
1
1
0
1
31.0
1
0
1
1
0
0
31.5
1
0
1
0
1
1
32.0
1
0
1
0
1
0
32.5
1
0
1
0
0
1
33.0
1
0
1
0
0
0
33.5
1
0
0
1
1
1
34.0
1
0
0
1
1
0
34.5
1
0
0
1
0
1
35.0
1
0
0
1
0
0
35.5
1
0
0
0
1
1
36.0
1
0
0
0
1
0
36.5
1
0
0
0
0
1
37.0
1
0
0
0
0
0
37.5
0
1
1
1
1
1
38.0
0
1
1
1
1
0
38.5
0
1
1
1
0
1
39.0
0
1
1
1
0
0
39.5
0
1
1
0
1
1
40.0
0
1
1
0
1
0
40.5
0
1
1
0
0
1
41.0
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
32 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 34.
DIF/SIF synthesizer frequencies (using bit TWOFLO = 0) …continued
Bit
fsynth (MHz)
SFREQ5
SFREQ4
SFREQ3
SFREQ2
SFREQ1
SFREQ0
W5[5]
W5[4]
W5[3]
W5[2]
W5[1]
W5[0]
0
1
1
0
0
0
41.5
0
1
0
1
1
1
42.0
0
1
0
1
1
0
42.5
0
1
0
1
0
1
43.0
0
1
0
1
0
0
43.5
0
1
0
0
1
1
44.0
0
1
0
0
1
0
44.5
0
1
0
0
0
1
45.0
0
1
0
0
0
0
45.5
0
0
1
1
1
1
46.0
0
0
1
1
1
0
46.5
0
0
1
1
0
1
47.0
0
0
1
1
0
0
47.5
0
0
1
0
1
1
48.0
0
0
1
0
1
0
48.5
0
0
1
0
0
1
49.0
0
0
1
0
0
0
49.5
0
0
0
1
1
1
50.0
0
0
0
1
1
0
50.5
0
0
0
1
0
1
51.0
0
0
0
1
0
0
51.5
0
0
0
0
1
1
52.0
0
0
0
0
1
0
52.5
0
0
0
0
0
1
53.0
0
0
0
0
0
0
53.5
Table 35.
DIF/SIF synthesizer frequency for Japan (using bit TWOFLO = 1)
Bit
fsynth (MHz)
SFREQ5
SFREQ4
SFREQ3
SFREQ2
SFREQ1
SFREQ0
W5[5]
W5[4]
W5[3]
W5[2]
W5[1]
W5[0]
1
1
0
0
1
0
TDA9897_TDA9898_4
Product data sheet
57
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
33 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 36.
W6 - data write register bit allocation
7
6
5
4
3
2
1
0
TAGC1
TAGC0
AGC2
AGC1
FMWIDE1
TWOFLO
VIDEO1V7
DIRECT
Table 37.
Bit
W6 - data write register bit description
Symbol
7 and 6 TAGC[1:0]
Description
tuner AGC mode[1]
00 = TAGC integral loop mode; all currents off
01 = TAGC integral loop mode; source current off
10 = TAGC integral loop mode
11 = TAGC derived from IF AGC; recommended for positive modulated
signals
5 and 4 AGC[2:1]
AGC mode and behavior; see Table 38
3
FM window
FMWIDE1
1 = 1 MHz
0 = see Table 27 bit FMWIDE0
2
TWOFLO
synthesizer frequency selection
1 = Japan mode (57 MHz)
0 = synthesizer mode
1
VIDEO1V7 video output level selection; sound carrier trap set to on (W2[0] = 1);
see Table 22 and Table 23
1 = 1.7 V at CVBS
0 = 2.0 V at CVBS
0
DIRECT
direct IF at DTV mode; TV set to DTV (W1[4] = 0); see Table 16 and
Table 17
1 = direct IF output
0 = low IF output
[1]
In TAGC integral loop mode the pin TAGC provides sink and source currents for control. TakeOver Point
(TOP) is set via register TOPNEG W9[4:0].
Table 38.
AGC mode and behavior
Bit
MOD
FORCESP
AGC2
SIF AGC
mode
W2[7]
W8[3]
W6[5]
W6[4]
0
0
0
0
normal
normal
0
0
0
1
minimum gain
minimum gain
0
0
1
0
normal
normal
0
0
1
1
normal
fast
0
1
X
X
fast
fast
1
X
0
0
normal
normal
1
X
0
1
minimum gain
minimum gain
1
X
1
0
2nd
normal
1
X
1
1
2nd fast
fast
TDA9897_TDA9898_4
Product data sheet
AGC1
VIF AGC
mode
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
34 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 39.
W7 - data write register bit allocation
7
6
EXTFILO
VAGC
5
4
SIFLEVEL VIDLEVEL
3
2
1
0
PORT1
MODEP1
FILOUTBP
NYQOFF
Table 40.
W7 - data write register bit description
Bit
Symbol
Description
7
EXTFILO
mute of output buffer of pin EXTFILO
1 = mute
0 = normal
gain control voltage of VIF amplifier at pin MPP; see Table 31
6
VAGC
5
SIFLEVEL SIF level reduction
1 = internal SIF level is reduced by 6 dB (only for AM sound)
0 = internal SIF level is normal
4
VIDLEVEL video level reduction
1 = internal video level is reduced by 6 dB[1]
0 = internal video level is normal
3
PORT1
output state; port 1 mode selection set to logic output port (W7[2] = 1)
1 = output port is HIGH (external pull-up resistor needed)
0 = output port is LOW
2
MODEP1
port 1 mode selection; pin PORT1
1 = logic output port; level controlled by bit PORT1 (W7[3])
0 = monitor output of VIF AGC voltage
1
FILOUTBP external filter output signal source; see Figure 9
1 = signal for external filter is obtained behind internal BP filter
0 = signal for external filter is obtained behind SIF mixer
0
NYQOFF
internal Nyquist processing; see Table 24
1 = internal Nyquist processing off[2]
0 = internal Nyquist processing on
[1]
Not recommended in combination with internal IF level set to reduced (W4[7] = 1).
[2]
At internal Nyquist processing off (W7[0] = 1) it is mandatory to set the internal video level to normal
(W7[4] = 0).
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
35 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 41.
W8 - data write register bit allocation
7
6
5
4
3
2
1
0
FEATURE
AVIDRED
MODEP3
TAGCIN3
FORCESP
PORT3
PORT2
0
Table 42.
W8 - data write register bit description
Bit
Symbol
Description
7
FEATURE
feature enable
1 = feature PORT2; PORT3 monitor output of TAGC voltage and data
write register W11[7:0] enabled
0 = feature disabled; pin PORT2 and pin PORT3 set to high-ohmic;
data write register W11[7:0] = 0000 0000
6
AVIDRED
automatic reduction of internal video level for PC / SC < 11.0 dB
1 = enabled
0 = disabled
5
MODEP3
port 3 mode selection; pin PORT3
1 = logic output port; level controlled by bit PORT3 (W8[2])
0 = monitor output of TAGC voltage
4
TAGCIN3
TAGC IF input selection; feature enable set to enable (W8[7] = 1)
1 = IF3A and IF3B input
0 = IF1A and IF1B input or IF2A and IF2B input depends on VIF input
selection (W4[0])
3
FORCESP VIF AGC and SIF AGC fast mode activation; modulation setting
(W2[7] = 0)
1 = forced
0 = automatic; dependent on video level
2
PORT3
output state; feature enable set to enable (W8[7] = 1); port 3 mode
selection set to logic output port (W8[5] = 1)
1 = output port is HIGH (external pull-up resistor needed)
0 = output port is LOW
1
PORT2
output state; feature enable set to enable (W8[7] = 1)
1 = output port is HIGH (external pull-up resistor needed)
0 = output port is LOW
0
-
0 = fixed value
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
36 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 43.
W9 - data write register bit allocation
7
6
5
4
3
2
1
0
DAGCSLOPE
TAGCIS
TAGCTC
TOPNEG4
TOPNEG3
TOPNEG2
TOPNEG1
TOPNEG0
Table 44.
W9 - data write register bit description
Bit
Symbol
Description
7
DAGCSLOPE AGCDIN input characteristic; see Figure 44
1 = high voltage for high gain
0 = low voltage for high gain
6
TAGCIS
tuner AGC IF input (TOP1)
1 = inverse to VIF input
0 = aligned to VIF input
5
TAGCTC
tuner AGC charge current (TOP1)
1 = high
0 = normal
4 to 0
TOPNEG[4:0] TOP adjustment for integral loop mode (TOP1); recommended for negative modulation;
see Table 45
Table 45.
Tuner takeover point adjustment bits W9[4:0]
Bit
TOPNEG4
TOPNEG3
TOPNEG2
TOPNEG1
TOPNEG0
TOP adjustment
(dBµV)[1]
W9[4]
W9[3]
W9[2]
W9[1]
W9[0]
1
1
1
1
1
98.5 typical
:
:
:
:
:
see Figure 13
1
0
0
0
0
79.3[2]
:
:
:
:
:
see Figure 13
0
0
0
0
0
59.6 typical
[1]
Average step size is 1.255 dB typical.
[2]
See Table 53 for parameter tuner takeover point accuracy (αacc(set)TOP).
Table 46.
W10 - data write register bit allocation
7
6
5
4
3
2
1
0
0
READTAGC
XPOTPOS
TOPPOS4
TOPPOS3
TOPPOS2
TOPPOS1
TOPPOS0
Table 47.
W10 - data write register bit description
Bit
Symbol
Description
7
-
0 = fixed value
6
READTAGC
signal source for TAGC read-out on R2[6]
1 = inverse to used TAGC detector (integral or IF based)
0 = aligned to used TAGC detector (integral or IF based)
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
37 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 47.
W10 - data write register bit description …continued
Bit
Symbol
Description
5
XPOTPOS
TOP derived from IF AGC via I2C-bus or potentiometer (TOP2)
1 = TOP adjustment by external potentiometer at pin TOP2
0 = see Table 48
4 to 0
TOPPOS[4:0]
Table 48.
TOP adjustment for TAGC derived from IF AGC (TOP2); recommended for positive
modulation; see Table 48
Tuner takeover point adjustment bits W10[4:0]
Bit
TOP adjustment
(dBµV)
TOPPOS4
TOPPOS3
TOPPOS2
TOPPOS1
TOPPOS0
W10[4]
W10[3]
W10[2]
W10[1]
W10[0]
1
1
1
1
1
99.0 typical
:
:
:
:
:
see Figure 13
1
0
0
0
0
78.5[1]
:
:
:
:
:
see Figure 13
0
0
0
0
0
56.9 typical
[1]
See Table 53 for parameter tuner takeover point accuracy (αacc(set)TOP2).
Table 49.
W11 - data write register bit allocation
7
6
5
4
3
2
1
0
0
0
OFFSETN
OFFSETP
BLACKAGC
GDEQ
VIFIN3
VIF31875
Table 50.
W11 - data write register bit description[1]
Bit
Symbol
Description
7 and 6
-
0 = fixed value
5
OFFSETN
VIF PLL offset sink current (approximately 0.6 µA)
1 = enabled (requires W11[4] = 0)
0 = disabled
4
OFFSETP
VIF PLL offset source current (approximately 0.6 µA)
1 = enabled (requires W11[5] = 0)
0 = disabled
3
BLACKAGC
black level AGC
1 = disabled
0 = enabled
2
GDEQ
activate group delay equalizer
1 = on (if pin 34 is open-circuit)
1 = off (if pin 34 is connected to ground)
0 = off (if pin 34 is open-circuit)
0 = on (if pin 34 is connected to ground)
1
VIFIN3
VIF input selection
1 = IF3A and IF3B input
0 = IF1A and IF1B input or IF2A and IF2B input depends on VIF input selection (W4[0])
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
38 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 50.
W11 - data write register bit description[1] …continued
Bit
Symbol
Description
0
VIF31875
VIF frequency selection for global ATV application inclusive DVB-T; see Table 24
1 = 31.875 MHz
0 = 32.250 MHz
[1]
Register W11 is logical AND protected by bit W8[7]. Therefore it is required to set W8[7] = 1 to enable pass of any W11 bit.
10. Limiting values
Table 51. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VP
supply voltage
Vn
voltage on any other pin
tsc
short-circuit time
Tstg
Tamb
Tcase
case temperature
Vesd
Conditions
Min
Max
Unit
-
5.5
V
all pins except ground
0
VP
V
to ground or VP
-
10
s
storage temperature
−40
+150
°C
ambient temperature
−20
+70
°C
TDA9898HL (LQFP48)
-
105
°C
TDA9898HN (HVQFN48)
-
115
°C
TDA9897HL (LQFP48)
-
105
°C
TDA9897HN (HVQFN48)
-
115
°C
human body model
[1]
-
±3000
V
machine model
[2]
-
±300
V
electrostatic discharge voltage
[1]
Class 2 according to JESD22-A114.
[2]
Class B according to EIA/JESD22-A115.
11. Thermal characteristics
Table 52.
Thermal characteristics
Symbol
Parameter
Conditions
Rth(j-a)
thermal resistance from junction to ambient
in free air; 2 layer board
Typ
Unit
67
K/W
TDA9898HN (HVQFN48)
48
K/W
TDA9897HL (LQFP48)
67
K/W
TDA9897HN (HVQFN48)
48
K/W
TDA9898HL (LQFP48)
19
K/W
TDA9898HN (HVQFN48)
10
K/W
TDA9897HL (LQFP48)
19
K/W
TDA9897HN (HVQFN48)
10
K/W
TDA9898HL (LQFP48)
Rth(j-c)
thermal resistance from junction to case
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
39 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
12. Characteristics
12.1 Analog TV signal processing
Table 53. Characteristics
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
4.5
5.0
5.5
V
-
-
175
mA
Supply; pin VP
[1]
VP
supply voltage
IP
supply current
ATV QSS; B/G standard;
sound carrier trap on;
sound BP on
power-on reset supply
voltage
for start of reset at
decreasing supply voltage
[2]
2.5
3.0
3.5
V
for end of reset at
increasing supply voltage;
I2C-bus transmission
enable
[2]
-
3.3
4.4
V
Power-on reset
VP(POR)
VIF amplifier; pins IF1A and IF1B or pins IF2A and IF2B or pins IF3A and IF3B
VI
-
1.95
-
V
differential input resistance
[3]
-
2
-
kΩ
Ci(dif)
differential input
capacitance
[3]
-
3
-
pF
Vi(IF)(RMS)
RMS IF input voltage
lower limit at −1 dB video
output signal
-
60
100
µV
upper limit at +1 dB video
output signal
150
190
-
mV
-
-
320
mV
-
0.7
-
dB
Ri(dif)
input voltage
permissible overload
[4]
∆GIF
IF gain variation
GVIF(cr)
control range VIF gain
60
66
-
dB
f−3dB(VIF)l
lower VIF cut-off frequency
-
15
-
MHz
f−3dB(VIF)u
upper VIF cut-off frequency
-
80
-
MHz
0.9
-
3.6
V
VIF PLL and true synchronous video
difference between picture
and sound carrier; within
AGC range; ∆f = 5.5 MHz
demodulator[5]
VLFVIF
voltage on pin LFVIF (DC)
fVCO(max)
maximum VCO frequency
fVCO = 2fPC
120
140
-
MHz
fVIF
VIF frequency
see Table 24
-
-
-
MHz
∆fVIF(dah)
digital acquisition help VIF
frequency window
related to fVIF
all standards except
M/N
-
±2.3
-
MHz
M/N standard
-
±1.8
-
MHz
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
40 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
[6]
Min
Typ
Max
Unit
-
-
30
ms
-
30
70
µV
tacq
acquisition time
Vlock(min)(RMS)
RMS minimum lock-in
voltage
Tcy(dah)
digital acquisition help
cycle time
-
64
-
µs
tw(dah)
digital acquisition help
pulse width
64
-
-
µs
Ipul(acq)VIF
VIF acquisition pulse
current
sink or source
21
-
33
µA
KO(VIF)
VIF VCO steepness
∆fVIF / ∆VLFVIF
-
26
-
MHz/V
KD(VIF)
VIF phase detector
steepness
∆IVPLL / ∆ϕVCO(VIF)
-
33
-
µA/rad
Ioffset(VIF)
VIF offset current
−1
0
+1
µA
W4[7] = 0; W7[4] = 0
1.7
2.0
2.3
V
W4[7] = 1; W7[4] = 0
1.7
2.0
2.3
V
W4[7] = 0; W7[4] = 1
1.7
2.0
2.3
V
W4[7] = 0; W7[4] = 0
−240
-
+240
mV
W4[7] = 1; W7[4] = 0
−240
-
+240
mV
W4[7] = 0; W7[4] = 1
−240
-
+240
mV
W4[7] = 0; W7[4] = 0
−100
-
+100
mV
W4[7] = 1; W7[4] = 0
−100
-
+100
mV
W4[7] = 0; W7[4] = 1
−100
-
+100
mV
2.0
2.33
2.75
Video output 2 V; pin
measured on active IF
input pins;
maximum IF gain;
negative modulation mode
W2[7] = 1 and PLL set to
overmodulation mode
W2[2] = 0 and W2[1] = 0
CVBS[7]
Normal mode (sound carrier trap active) and sound carrier on
Vo(video)(p-p)
∆Vo(CVBS)
peak-to-peak video output
voltage
CVBS output voltage
difference
positive or negative
modulation; W6[1] = 0;
see Figure 10
difference between
L and B/G standard;
W3[7] = 0
difference between
I and B/G standard;
20 % residual carrier at
I standard; W3[7] = 1
Vvideo/Vsync
video voltage to sync
voltage ratio
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
41 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vsyncl
sync level voltage
W4[7] = 0; W7[4] = 0
1.0
1.2
1.4
V
W4[7] = 1; W7[4] = 0
0.9
1.2
1.5
V
W4[7] = 0; W7[4] = 1
0.9
1.2
Vclip(video)u
upper video clipping
voltage
Vclip(video)l
lower video clipping voltage
1.5
V
VP − 1.2 VP − 1
-
V
-
0.4
0.9
V
RO
output resistance
-
-
30
Ω
Ibias(int)
internal bias current (DC)
for emitter-follower
1.5
2.0
-
mA
Isink(o)(max)
maximum output sink
current
AC and DC
1
-
-
mA
Isource(o)(max)
maximum output source
current
AC and DC
3.9
-
-
mA
∆Vo(CVBS)
CVBS output voltage
difference
50 dB gain control
-
-
0.5
dB
30 dB gain control
-
-
0.1
dB
∆Vblt/VCVBS
black level tilt to CVBS
voltage ratio
negative modulation
-
-
1
%
∆Vblt(v)/VCVBS
vertical black level tilt to
CVBS voltage ratio
worst case in L standard;
vision carrier modulated
by test line [Vertical
Interval Test Signal
(VITS)] only
-
-
3
%
Gdif
differential gain
“ITU-T J.63 line 330”
B/G standard
-
-
5
%
L standard
-
-
7
%
-
2
4
deg
ϕdif
differential phase
[3]
“ITU-T J.63 line 330”
[8]
[8]
B/G standard
L standard
-
2
4
deg
53
57
-
dB
M/N standard; 50 IRE grey
video signal;
see Figure 20
47
51
-
dB
fundamental wave and
harmonics
-
2
5
mV
-
-
12
kHz
(S/N)w
weighted signal-to-noise
ratio
B/G standard; 50 % grey
video signal; unified
weighting filter
(“ITU-T J.61”);
see Figure 20
(S/N)unw
unweighted signal-to-noise
ratio
VPC(rsd)(RMS)
RMS residual picture
carrier voltage
∆fPC(p-p)
peak-to-peak picture carrier 3 % residual carrier;
frequency variation
50 % serration pulses;
L standard
TDA9897_TDA9898_4
Product data sheet
[9]
[3]
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
42 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
-
-
3
%
[10]
35
40
-
dB
[11]
40
-
-
dB
fripple = 70 Hz;
video signal; grey level;
positive and negative
modulation; see Figure 11
14
20
-
dB
0.5 MHz to 2.5 MHz
−1.5
-
+1
dB
2.5 MHz to 3.6 MHz
−2
-
+1
dB
3.6 MHz to 3.8 MHz
−3
-
+1
dB
∆ϕ
phase difference
0 % residual carrier;
50 % serration pulses;
L standard; L-gating = 0 %
αH(video)
video harmonics
suppression
AC load: CL < 20 pF,
RL > 1 kΩ
αsp
spurious suppression
PSRRCVBS
power supply ripple
rejection on pin CVBS
[3]
M/N standard inclusive Korea; see Figure 21[12]
αripple(resp)f
frequency response ripple
3.8 MHz to 4.2 MHz
−16
-
+1
dB
first sound carrier
attenuation
f = fSC1 = 4.5 MHz
38
-
-
dB
f = fSC1 ± 60 kHz
29
-
-
dB
αSC2
second sound carrier
attenuation
f = fSC2 = 4.724 MHz
25
-
-
dB
td(grp)CC
color carrier group delay
time
f = 3.58 MHz; including
transmitter pre-correction;
see Figure 22
αSC1
f = fSC2 ± 60 kHz
16
-
-
dB
−75
−50
+75
ns
0.5 MHz to 3.2 MHz
−1.5
-
+1
dB
3.2 MHz to 4.5 MHz
−3
-
+1
dB
4.5 MHz to 4.8 MHz
−5
-
+1
dB
[13]
B/G standard; see Figure 23[12]
αripple(resp)f
frequency response ripple
4.8 MHz to 5 MHz
−12
-
+1
dB
first sound carrier
attenuation
f = fSC1 = 5.5 MHz
35
-
-
dB
f = fSC1 ± 60 kHz
26
-
-
dB
αSC2
second sound carrier
attenuation
f = fSC2 = 5.742 MHz
25
-
-
dB
f = fSC2 ± 60 kHz
16
-
-
dB
αSC(NICAM)
NICAM sound carrier
attenuation
fcar(NICAM) = 5.85 MHz;
f = fcar(NICAM) ± 250 kHz
12
-
-
dB
α
attenuation
f = f(N+1)ch = 7 MHz
21
-
-
dB
td(grp)CC
color carrier group delay
time
f = 4.43 MHz; including
transmitter pre-correction;
see Figure 24
αSC1
f = f(N+1)ch ± 750 kHz
TDA9897_TDA9898_4
Product data sheet
[13]
5
-
-
dB
−75
−10
+75
ns
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
43 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
I standard; see Figure
αripple(resp)f
Conditions
Min
Typ
Max
Unit
0.5 MHz to 3.2 MHz
−1.5
-
+1
dB
3.2 MHz to 4.5 MHz
−2
-
+1
dB
4.5 MHz to 5 MHz
−4
-
+1
dB
5 MHz to 5.5 MHz
−12
-
+1
dB
35
-
-
dB
25[12]
frequency response ripple
αSC1
first sound carrier
attenuation
f = fSC1 = 6.0 MHz
f = fSC1 ± 60 kHz
26
-
-
dB
αSC(NICAM)
NICAM sound carrier
attenuation
fcar(NICAM) = 6.55 MHz;
f = fcar(NICAM) ± 250 kHz
12
-
-
dB
td(grp)CC
color carrier group delay
time
f = 4.43 MHz;
see Figure 26
−75
−15
+75
ns
0.5 MHz to 3.1 MHz
−1.5
-
+1
dB
3.1 MHz to 4.5 MHz
−2
-
+1
dB
4.5 MHz to 4.8 MHz
−4
-
+1
dB
4.8 MHz to 5.1 MHz
−6
-
+1
dB
first sound carrier
attenuation
f = fSC1 = 6.5 MHz
35
-
-
dB
f = fSC1 ± 60 kHz
26
-
-
dB
second sound carrier
attenuation (upper side)
f = fSC2 = 6.742 MHz
25
-
-
dB
f = fSC2 ± 60 kHz
16
-
-
dB
second sound carrier
attenuation (lower side)
f = fSC2 = 6.258 MHz
25
-
-
dB
f = fSC2 ± 60 kHz
16
-
-
dB
αSC(NICAM)
NICAM sound carrier
attenuation
fcar(NICAM) = 5.85 MHz;
f = fcar(NICAM) ± 250 kHz
6
-
-
dB
td(grp)CC
color carrier group delay
time
f = 4.28 MHz; including
transmitter pre-correction;
see Figure 28
−50
0
+100
ns
0.5 MHz to 3.2 MHz
−1.5
-
+1
dB
3.2 MHz to 4.5 MHz
−2
-
+1
dB
4.5 MHz to 4.8 MHz
−4
-
+1
dB
4.8 MHz to 5.3 MHz
−12
-
+1
dB
fcar(NICAM) = 5.85 MHz;
f = fcar(NICAM) ± 250 kHz
5
-
-
dB
[13]
D/K standard; see Figure 27[12]
αripple(resp)f
αSC1
αSC2(us)
αSC2(ls)
frequency response ripple
[13]
L standard; see Figure 29[12]
αripple(resp)f
frequency response ripple
αSC(NICAM)
NICAM sound carrier
attenuation
αSC(AM)
AM sound carrier
attenuation
td(grp)CC
color carrier group delay
time
f = fSC(AM) = 6.5 MHz
38
-
-
dB
f = fSC(AM) ± 30 kHz
29
-
-
dB
f = 4.28 MHz; including
transmitter pre-correction;
see Figure 30
−75
−5
+75
ns
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
44 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Video output 1.7 V; pin CVBS; see Figure 50, optional CVBS buffer at setting W6[1] = 1
Normal mode (sound carrier trap active) and sound carrier on
Vo(video)(p-p)
Vsyncl
peak-to-peak video output
voltage
sync level voltage
positive or negative
modulation; W6[1] = 1;
see Figure 10
W4[7] = 0; W7[4] = 0
1.44
1.7
1.96
V
W4[7] = 1; W7[4] = 0
1.44
1.7
1.96
V
W4[7] = 0; W7[4] = 1
1.44
1.7
1.96
V
W4[7] = 0; W7[4] = 0
1.0
1.2
1.4
V
W4[7] = 1; W7[4] = 0
0.9
1.2
1.5
V
W4[7] = 0; W7[4] = 1
0.9
1.2
1.5
V
see Figure 10
-
1.1
-
V
1.5
-
V
-
V
Video output 1.1 V; pin CVBS
Trap bypass mode and sound carrier off[12]
Vo(video)(p-p)
peak-to-peak video output
voltage
Vsyncl
sync level voltage
-
Vclip(video)u
upper video clipping
voltage
VP − 1.2 VP − 1
Vclip(video)l
lower video clipping voltage
Bvideo(−3dB)
−3 dB video bandwidth
AC load: CL < 20 pF,
RL > 1 kΩ
-
0.4
0.9
V
6
8
-
MHz
(S/N)w
weighted signal-to-noise
ratio
B/G standard; 50 % grey
video signal; unified
weighting filter
(“ITU-T J.61”);
see Figure 20
[9]
54
-
-
dB
(S/N)unw
unweighted signal-to-noise
ratio
M/N standard; 50 IRE grey
video signal;
see Figure 20
[9]
47
51
-
dB
[3]
0.5
-
4.5
V
1 mV (60 dBµV)
2.0
-
2.5
V
10 mV (80 dBµV)
2.4
-
3.0
V
200 mV (106 dBµV)
3.0
-
VP
V
VIF AGC
Pin MPP
Vmonitor(VIFAGC)
VIF AGC monitor voltage
VAGC
AGC voltage
see Figure 12; Vi(IF) set to
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
45 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
tresp
Parameter
response time
Conditions
increasing VIF step;
negative modulation
Min
Typ
Max
Unit
[14]
normal mode
-
100
-
µs/dB
2nd mode
-
9
-
µs/dB
-
3
-
µs/dB
-
100
-
µs/dB
-
5
-
µs/dB
-
70
-
µs/dB
-
250
-
µs/dB
-
20
-
µs/dB
-
80
-
µs/dB
-
6
-
µs/dB
20 dB
-
900
-
ms
normal mode
-
180
-
ms/dB
-
3
-
ms/dB
-
24
-
ms/dB
−10
−6
−2
dB
fast 2nd mode
increasing VIF step;
positive modulation
[14]
normal mode
fast mode
decreasing VIF step;
negative modulation
[14]
normal mode
2nd mode
2nd mode (speed-up)
[15]
fast 2nd mode
fast 2nd mode
(speed-up)
decreasing VIF step;
positive modulation
[15]
[14]
fast mode; W8[3] = 1
fast mode (speed-up)
[16]
αth(fast)VIF
VIF fast mode threshold
∆VVAGC(step)
VIF AGC voltage difference see Table 11
(step)
-
40
-
mV/bit
maximum charge current
L standard; normal mode;
W8[3] = 0
75
100
125
µA
L standard; fast mode;
W8[3] = 1
-
2.0
-
mA
L standard
Pin CIFAGC
Ich(max)
Ich(add)
additional charge current
L standard: in the event of
missing VITS pulses and
no white video content
-
100
-
nA
Idch
discharge current
L standard; normal mode;
W8[3] = 0
-
35
-
nA
L standard; fast mode;
W8[3] = 1 or speed-up
-
1.4
-
µA
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
46 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tuner AGC; pin TAGC
TAGC integral loop mode (W6[7:6] = 10); TAGC is current output; applicable for negative modulation only; unmodulated VIF;
see Table 44 and Figure 13
Vi(IF)(RMS)
RMS IF input voltage
αacc(set)TOP1
TOP1 setting accuracy
Isource
source current
Isink
sink current
∆αacc(set)TOP1/∆T TOP1 setting accuracy
variation with temperature
for TOP1; at starting point
of tuner AGC takeover;
Isink(TAGC) = 100 µA
W9[4:0] = 0 0000
-
59.6
-
dBµV
W9[4:0] = 1 0000
-
78.3
-
dBµV
W9[4:0] = 1 1111
-
98.5
-
dBµV
−2
-
+2
dB
W9[5] = 0
0.20
0.33
0.45
µA
W9[5] = 1
1.6
2.5
3.4
µA
fast mode activated by
internal level detector;
W9[5] = 0
7
11
15
µA
fast mode activated by
internal level detector;
W9[5] = 1
60
90
120
µA
TAGC discharge current;
VTAGC = 1 V
375
500
625
µA
W9[4:0] = 1 0000
-
0.006
0.02
dB/K
50
-
-
MΩ
TAGC charge current
[3]
RL
load resistance
Vsat(u)
upper saturation voltage
pin operating as current
output
VP − 0.3 -
-
V
Vsat(l)
lower saturation voltage
pin operating as current
output
-
-
0.3
V
αth(fast)AGC
AGC fast mode threshold
activated by internal fast
AGC detector; I2C-bus
setting corresponds to
W9[4:0] = 1 0000
6
8
10
dB
td
delay time
before activating; Vi(IF)
below αth(fast)AGC
40
60
80
ms
TDA9897_TDA9898_4
Product data sheet
[3]
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
47 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
TAGC loop based on VIF AGC (W6[7:6] = 11); TAGC is voltage output; applicable for TV mode: positive modulation and
optional for negative modulation); see Table 47, Figure 13 and Figure 14
Vi(IF)(RMS)
RMS IF input voltage
for TOP2; at starting point
of tuner AGC takeover;
VTAGC = 3.5 V
RTOP2 = 22 kΩ or
W10[5:0] = 00 0000
-
56.9
-
dBµV
RTOP2 = 10 kΩ or
W10[5:0] = 01 0000
-
78.5
-
dBµV
RTOP2 = 0 kΩ
-
98
-
dBµV
W10[5:0] = 01 1111
αacc(set)TOP2
TOP2 setting accuracy
∆αacc(set)TOP2/∆T TOP2 setting accuracy
variation with temperature
VO
∆Gslip(TAGC)
output voltage
TAGC slip gain offset
VTAGC = 3.5 V
-
99
-
dBµV
−8
-
+8
dB
-
0.03
0.07
dB/K
no tuner gain reduction
4.5
-
VP
V
maximum tuner gain
reduction
0.2
-
0.6
V
tuner gain voltage from
0.6 V to 3.5 V
3
5
8
dB
-
3.5
-
V
-
27
-
kΩ
W10[5] = 1; external
resistor operation
0
-
22
kΩ
W10[5] = 0; forced
I2C-bus operation
100
-
-
kΩ
-
0.55VP
V
TOP adjust 2; pin TOP2; IF based TAGC loop mode; see Figure 14
VTOP2
voltage on pin TOP2 (DC)
RI
input resistance
RTOP2
resistance on pin TOP2
pin open-circuit
adjustment of VIF AGC
based TAGC loop
Pin CTAGC
voltage on pin CTAGC
[3]
0.2
IL
leakage current
sink or source
[3]
-
-
10
nA
RO
output resistance
equivalent time constant
resistance
[3]
-
10
-
MΩ
VP − 0.8 VP − 0.5
-
V
VCTAGC
Pin MPP output characteristic
General
Vsat(u)
upper saturation voltage
Vsat(l)
lower saturation voltage
Io(max)
RO
maximum output current
sink or source
output resistance
TDA9897_TDA9898_4
Product data sheet
-
0.5
0.8
V
[3]
350
-
-
µA
[3]
-
1.3
3
kΩ
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
48 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIF AGC; see Figure 12
-
6
-
dB
SIF AGC; see Figure 16
-
6
-
dB
FM AGC; see Figure 15
-
6
-
dB
TAGC; see Figure 12
-
0
-
dB
100 kHz VIF deviation
80
-
160
µA
200 kHz VIF deviation
160
200
240
µA
1.5 MHz VIF deviation
160
-
240
µA
[19]
0.85
1.05
1.25
µA/kHz
AGC monitor (voltage output)
Gv
voltage gain
voltage on pin MPP to
internal control voltage;
see Table 31
[17]
AFC monitor (current output)
Io
output current
sink or source;
see Figure 17 and
Figure 18
[18][19]
AFC TV mode
∆IAFC/∆fVIF
change of AFC current with
VIF frequency
fVIFacc(dig)
digital accuracy of VIF
frequency
read-out via I2C-bus;
R1[4:1] = f0; fref = 4 MHz
[20]
−20
-
+20
kHz
fVIFacc(a)
analog accuracy of VIF
frequency
IAFC = 0 A; fref = 4 MHz
[20]
−20
-
+20
kHz
[19]
0.85
1.05
1.25
µA/kHz
AFC radio mode
∆IAFC/∆fRIF
change of AFC current with
RIF frequency
fRIFacc(dig)
digital accuracy of RIF
frequency
read-out via I2C-bus;
R1[4:1] = f0; fref = 4 MHz
[20]
−10
-
+10
kHz
fRIFacc(a)
analog accuracy of RIF
frequency
IAFC = 0 A; fref = 4 MHz
[20]
−10
-
+10
kHz
Pin PORT1 or pin PORT3 operating as voltage monitor
Vsat(u)
upper saturation voltage
VP − 0.8 VP − 0.5
-
V
Vsat(l)
lower saturation voltage
-
0.5
0.8
V
Io(max)
maximum output current
[3]
10
-
-
µA
[3]
-
1.3
3
kΩ
voltage ratio: pin PORT1
to internal VIF AGC
voltage
[3][17]
-
6
-
dB
voltage ratio: pin PORT3
to internal TAGC voltage
[3][17]
-
0
-
dB
-
1.95
-
V
RO
Gv
sink or source
output resistance
voltage gain
SIF amplifier; pins IF1A and IF1B or pins IF2A and IF2B or pins IF3A and IF3B
VI
input voltage
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
49 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Ri(dif)
Conditions
Min
Typ
Max
Unit
differential input resistance
-
2
-
kΩ
Ci(dif)
differential input
capacitance
-
3
-
pF
Vi(SIF)(RMS)
RMS SIF input voltage
FM mode; −3 dB at
intercarrier output
pins OUT1A and OUT1B;
without FM AGC;
see Table 21
-
60
100
µV
AM mode; −3 dB at
AF output pin AUD
-
40
70
µV
FM mode; +1 dB at
intercarrier output
pins OUT1A and OUT1B;
without FM AGC;
see Table 21
150
190
-
mV
AM mode; +1 dB at
AF output pin AUD
70
140
-
mV
permissible overload
-
-
320
mV
FM and AM mode
GSIF(cr)
control range SIF gain
60
66
-
dB
f−3dB(SIF)l
lower SIF cut-off frequency
-
7
-
MHz
f−3dB(SIF)u
upper SIF cut-off frequency
-
80
-
MHz
increasing
-
8
-
ms
decreasing
-
10
-
ms
increasing
-
65
-
ms
decreasing
-
125
-
ms
increasing
-
0.09
-
ms
decreasing
-
28
-
ms
increasing
-
0.03
-
ms
decreasing
-
4
-
ms
SIF AGC detector; pin MPP; see Figure 16
tresp
response time
increasing or decreasing
SIF step of 20 dB;
AM mode; fast AGC
increasing or decreasing
SIF step of 20 dB;
AM mode; slow AGC
increasing or decreasing
SIF step of 20 dB;
FM mode; normal AGC
increasing or decreasing
SIF step of 20 dB;
FM mode; fast AGC
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
50 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VAGC(SIF)
SIF AGC voltage
FM mode
VSIF = 100 µV
1.2
-
2.1
V
VSIF = 10 mV
2.4
-
3.2
V
VSIF = 140 mV
3.1
-
VP
V
VSIF = 100 µV
1.4
-
2.3
V
VSIF = 10 mV
2.6
-
3.4
V
VSIF = 70 mV
3.2
-
VP
V
1
-
3
V
-
31
-
MHz/V
AM mode
Conversion synthesizer PLL; pin LFSYN2 (radio mode)
VLFSYN2
voltage on pin LFSYN2
KO
VCO steepness
∆fVCO / ∆VLFSYN2
KD
phase detector steepness
∆ILFSYN2 / ∆ϕVCO;
see Table 57;
fVCO selection:
Io(PD)
phase detector output
current
22 MHz to 29.5 MHz
-
32
-
µA/rad
30 MHz to 37.5 MHz
-
38
-
µA/rad
38 MHz to 45.5 MHz
-
47
-
µA/rad
46 MHz to 53.5 MHz
-
61
-
µA/rad
57 MHz
-
61
-
µA/rad
-
200
-
µA
sink or source;
fVCO selection:
22 MHz to 29.5 MHz
ϕn(synth)
synthesizer phase noise
30 MHz to 37.5 MHz
-
238
-
µA
38 MHz to 45.5 MHz
-
294
-
µA
46 MHz to 53.5 MHz
-
384
-
µA
57 MHz
-
384
-
µA
with 4 MHz crystal
oscillator reference;
fsynth = 31 MHz;
fIF = 36 MHz
at 1 kHz
[3]
89
99
-
dBc/Hz
at 10 kHz
[3]
89
99
-
dBc/Hz
at 100 kHz
[3]
98
102
-
dBc/Hz
at 1.4 MHz
[3]
115
119
-
dBc/Hz
50
-
-
dBc
-
-
10
nA
αsp
spurious suppression
multiple of ∆f = 500 kHz
[3]
IL
leakage current
synthesizer spurious
performance > 50 dBc
[3]
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
51 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
PSRR
power supply ripple
rejection
residual spurious at
nominal differential output
voltage dependent on
power supply ripple at
70 Hz; see Figure 11
-
50
-
dB
Single reference QSS intercarrier mixer; pins OUT1A and OUT1B
VOUT1A
voltage on pin OUT1A (DC)
1.8
2.0
2.2
V
VOUT1B
voltage on pin OUT1B (DC)
1.8
2.0
2.2
V
Ibias(int)
internal bias current (DC)
for emitter-follower
2.0
2.5
-
mA
Isink(o)(max)
maximum output sink
current
DC and AC
1.4
1.7
-
mA
Isource(o)(max)
maximum output source
current
DC and AC; with external
resistor to GND
3.0
-
-
mA
RO
output resistance
output active;
single-ended to GND
-
-
25
Ω
output inactive; internal
resistance to GND
-
800
-
Ω
Vo(RMS)
RMS output voltage
IF intercarrier
single-ended to GND;
B/G standard;
SC1 on; SC2 off;
see Figure 9 and Table 21
internal BP via FM AGC
90
140
180
mV
internal BP
90
170
230
mV
W7[5] = 0;
internal BP + 6 dB
90
140
180
mV
W7[5] = 1;
internal BP + 6 dB
45
70
90
mV
W7[5] = 0; internal BP
45
70
90
mV
IF intercarrier
single-ended to GND;
L standard;
without modulation;
see Figure 9 and Table 21
W7[5] = 1; internal BP
20
35
45
mV
f−3dB(ic)u
upper intercarrier cut-off
frequency
internal sound band-pass
off
11
15
-
MHz
αimage
image rejection
band-pass off;
−8 MHz to 0 MHz
24
28
-
dB
Vinterf(RMS)
RMS interference voltage
fundamental wave and
harmonics
-
2
5
mV
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
52 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
-
5
-
dB
M/N
-
4.7
-
MHz
B/G
-
5.75
-
MHz
I
-
6.25
-
MHz
D/K
-
6.25
-
MHz
L/L-accent
-
6.05
-
MHz
M/N
-
4.7
-
MHz
B/G
-
5.75
-
MHz
I
-
6.25
-
MHz
D/K
-
6.25
-
MHz
fc + 0.5
fc + 0.65
fc + 0.8
MHz
AM intercarrier from pin EXTFILI to pins OUT1A and OUT1B
G
gain
IF intercarrier; L standard;
without modulation
Band-pass mode
fc
center frequency
QSS mode;
BP selection for standard
radio mode;
BP selection for standard
f−3dB(BP)u
upper BP cut-off frequency
f−3dB(BP)l
lower BP cut-off frequency
fc − 0.5
fc − 0.65
fc − 0.8
MHz
αstpb
stop-band attenuation
20
30
-
dB
αCC
color carrier attenuation
QSS mode;
BP selection for standard
M/N; fCC = 3.58 MHz
15
23
-
dB
B/G; fCC = 4.43 MHz
22
30
-
dB
I; fCC = 4.43 MHz
20
28
-
dB
D/K; fCC = 4.28 MHz
20
28
-
dB
L/L-accent;
fCC = 4.28 MHz
20
28
-
dB
1.8
2.0
2.2
V
420
620
820
mV
W7[5] = 0
210
310
410
mV
W7[5] = 1
105
155
205
mV
1
-
-
mA
External filter output; pin EXTFILO
VEXTFILO
voltage on pin EXTFILO
(DC)
VEXTFILO(p-p)
peak-to-peak voltage on
pin EXTFILO
IF intercarrier; SC1 on;
SC2 off
IF intercarrier; L standard;
without modulation
Io(max)
maximum output current
AC and DC
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
53 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
see Table 18 and Table 20
-
4.5
-
MHz
-
5.5
-
MHz
-
6.0
-
MHz
-
6.5
-
MHz
-
10.7
-
MHz
fFMPLL = 4.5 MHz
1.5
1.9
3.3
V
fFMPLL = 5.5 MHz
1.5
2.2
3.3
V
fFMPLL = 6.0 MHz
1.5
2.35
3.3
V
fFMPLL = 6.5 MHz
1.5
2.5
3.3
V
fFMPLL = 10.7 MHz
1.5
2.3
3.3
V
FM PLL demodulator
fFMPLL
FM PLL frequency
FM PLL filter; pin LFFM
VLFFM
voltage on pin LFFM
Tcy(dah)
digital acquisition help
cycle time
-
64
-
µs
tw(dah)
digital acquisition help
pulse width
-
16
-
µs
Io(dah)
digital acquisition help
output current
W3[4] = 0; W6[3] = 0;
FM window
width = 237.5 kHz
14
18
22
µA
W3[4] = 1; W6[3] = 0;
FM window
width = 475 kHz
28
36
44
µA
W3[4] = 0; W6[3] = 1;
FM window
width = 1 MHz
14
18
22
µA
W3[4] = 1; W6[3] = 1;
FM window
width = 1 MHz
28
36
44
µA
W3[4] = 0; W6[3] = 0;
FM window
width = 237.5 kHz
-
5.5
-
µA/rad
W3[4] = 1; W6[3] = 0;
FM window
width = 475 kHz
-
14.5
-
µA/rad
W3[4] = 0; W6[3] = 1;
FM window
width = 1 MHz
-
5.5
-
µA/rad
W3[4] = 1; W6[3] = 1;
FM window
width = 1 MHz
-
14.5
-
µA/rad
KD(FM)
FM phase detector
steepness
sink or source
∆IFMPLL / ∆ϕVCO(FM)
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
54 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
KO(FM)
FM VCO steepness
∆fFMPLL / ∆VLFFM
f < 10 MHz
f = 10.7 MHz
Ioffset(FM)
FM offset current
Min
Typ
Max
Unit
-
3.3
-
MHz/V
-
5.9
-
MHz/V
W6[3] = 0; W3[4] = 0
−1.5
0
+1.5
µA
W6[3] = 0; W3[4] = 1
−2.5
0
+2.5
µA
FM intercarrier input; pins EXTFMI and EXTFILI; see Figure 9
|Zi|
input impedance
AC-coupled via 4 pF
-
20
-
kΩ
Vi(FM)(RMS)
RMS FM input voltage
gain controlled operation;
W1[1:0] = 10 or
W1[1:0] = 11 or
W1[1:0] = 01
2
-
300
mV
Vlock(min)(RMS)
RMS minimum lock-in
voltage
W1[1:0] = 10 or
W1[1:0] = 11 or
W1[1:0] = 01
-
-
1.5
mV
Vdet(FM)min(RMS)
RMS minimum FM carrier
detection voltage
W1[1:0] = 10 or
W1[1:0] = 11 or
W1[1:0] = 01
-
-
1.8
mV
QSS mode;
25 kHz FM deviation;
75 µs de-emphasis
400
500
600
mV
QSS mode;
27 kHz FM deviation;
50 µs de-emphasis
430
540
650
mV
QSS mode;
55 kHz FM deviation;
50 µs de-emphasis
900
-
1300
mV
radio mode;
22.5 kHz FM deviation;
75 µs de-emphasis
360
450
540
mV
-
1.1 × 10−3 7 × 10−3 dB/K
-
0.15
FM demodulator part; audio output; pin AUD
Vo(AF)(RMS)
RMS AF output voltage
∆Vo(AF)/∆T
AF output voltage variation
with temperature
THD
total harmonic distortion
50 µs de-emphasis;
FM deviation: for
TV mode 27 kHz and for
radio mode 22.5 kHz
TDA9897_TDA9898_4
Product data sheet
0.50
%
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
55 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
∆fAF(max)
fAF(max)
Parameter
maximum AF frequency
deviation
maximum AF frequency
Conditions
Min
Typ
Max
Unit
W3[1:0] = 00 (audio
gain = 0 dB)
±55
-
-
kHz
W3[1:0] = 01 (audio
gain = −6 dB)
±110
-
-
kHz
W3[1:0] = 10 (audio
gain = −12 dB)
±170
-
-
kHz
W3[1:0] = 11 (audio
gain = −18 dB) and
W3[4] = 1 (FM window
width = 475 kHz)
±380
-
-
kHz
FM window
width = 237.5 kHz;
−6 dB audio gain;
FM deviation 100 kHz
15
-
-
kHz
FM window
width = 475 kHz;
−18 dB audio gain;
FM deviation 300 kHz
15
-
-
kHz
THD < 2 %; pre-emphasis
off; fAF = 400 Hz
THD < 2 %;
pre-emphasis off
[21]
[3]
f−3dB(AF)
AF cut-off frequency
W3[2] = 0; W3[4] = 0;
without de-emphasis;
FM window
width = 237.5 kHz
80
100
-
kHz
(S/N)w(AF)
AF weighted
signal-to-noise ratio
27 kHz FM deviation;
50 µs de-emphasis; vision
carrier unmodulated;
FM PLL only;
“ITU-R BS.468-4”
48
56
-
dB
(S/N)unw(AF)
AF unweighted
signal-to-noise ratio
radio mode (10.7 MHz);
22.5 kHz FM deviation;
75 µs de-emphasis
-
58
-
dB
VSC(rsd)(RMS)
RMS residual sound carrier fundamental wave and
voltage
harmonics; without
de-emphasis
-
-
2
mV
αAM
AM suppression
referenced to 27 kHz
FM deviation;
50 µs de-emphasis;
AM: f = 1 kHz; m = 54 %
35
46
-
dB
PSRR
power supply ripple
rejection
fripple = 70 Hz;
see Figure 11
14
20
-
dB
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
56 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
-
-
300
Ω
2.0
2.4
2.7
V
Audio amplifier
Audio output; pin AUD
RO
output resistance
VO
output voltage
RL
load resistance
CL
load capacitance
Vo(AF)(RMS)
RMS AF output voltage
[3]
AC-coupled
[3]
10
-
-
kΩ
DC-coupled
[3]
100
-
-
kΩ
[3]
-
-
1
nF
25 kHz FM deviation;
75 µs de-emphasis;
see Table 27
0 dB
400
500
600
mV
−6 dB
-
250
-
mV
−12 dB
-
125
-
mV
−18 dB
-
62.5
-
mV
400
500
600
mV
AM; m = 54 %;
see Table 27
0 dB
−6 dB
f−3dB(AF)u
upper AF cut-off frequency
W3[2] = 0 (without
de-emphasis)
[22]
f−3dB(AF)l
lower AF cut-off frequency
W3[2] = 0 (without
de-emphasis)
[23]
-
250
-
mV
-
150
-
kHz
-
20
-
Hz
αmute
mute attenuation
of AF signal
70
-
-
dB
∆Vjmp
jump voltage difference
(DC)
switching AF output to
mute state or vice versa;
activated by digital
acquisition help W3[6] = 1
or via W3[5]
-
±50
±150
mV
PSRR
power supply ripple
rejection
fripple = 70 Hz;
see Figure 11
14
20
-
dB
-
2.4
-
V
W3[3:2] = 11 (50 µs
de-emphasis)
8.5
-
14
kΩ
W3[3:2] = 01 (75 µs
de-emphasis)
13
-
21
kΩ
fAF = 400 Hz;
Vo(AF) = 500 mV (RMS);
0 dB attenuation
-
170
-
mV
De-emphasis network; pin CDEEM
VO
output voltage
RO
output resistance
VAF(RMS)
RMS AF voltage
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
57 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
AF decoupling
Pin CAF
Vdec
IL
Io(max)
FM
decoupling voltage (DC)
fFMPLL = 4.5 MHz
1.5
1.9
3.3
V
fFMPLL = 5.5 MHz
1.5
2.2
3.3
V
fFMPLL = 6.0 MHz
1.5
2.35
3.3
V
fFMPLL = 6.5 MHz
1.5
2.5
3.3
V
fFMPLL = 10.7 MHz
1.5
2.3
3.3
V
leakage current
∆VAUD < ±50 mV (p-p);
0 dB attenuation
-
-
±25
nA
maximum output current
sink or source
1.15
1.5
1.85
µA
45
50
-
dB
operation[24][25]
Single reference QSS AF performance; pin AUD[26]
(S/N)w(SC1)
first sound carrier weighted PC / SC1 > 40 dB at
signal-to-noise ratio
pins IF1A and IF1B or
IF2A and IF2B; 27 kHz FM
deviation; BP off;
“ITU-R BS.468-4”
black picture
white picture
45
50
-
dB
6 kHz sine wave
(black-to-white
modulation)
43
47
-
dB
250 kHz square wave
(black-to-white
modulation)
45
50
-
dB
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
58 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Single reference QSS AF performance with external FM demodulator connected to OUT1A and
(S/N)w(SC1)
(S/N)w(SC2)
Max
Unit
OUT1B[27]
first sound carrier weighted PC / SC1 > 40 dB at
signal-to-noise ratio
pins IF1A and IF1B or
IF2A and IF2B; 27 kHz
FM deviation; BP off;
“ITU-R BS.468-4”
second sound carrier
weighted signal-to-noise
ratio
black picture
53
58
-
dB
white picture
50
53
-
dB
6 kHz sine wave
(black-to-white
modulation)
44
48
-
dB
250 kHz square wave
(black-to-white
modulation)
40
45
-
dB
sound carrier
subharmonics;
f = 2.75 MHz ± 3 kHz
45
51
-
dB
sound carrier
subharmonics;
f = 2.87 MHz ± 3 kHz
46
52
-
dB
black picture
48
55
-
dB
white picture
46
51
-
dB
6 kHz sine wave
(black-to-white
modulation)
42
46
-
dB
250 kHz square wave
(black-to-white
modulation)
29
34
-
dB
sound carrier
subharmonics;
f = 2.75 MHz ± 3 kHz
44
50
-
dB
sound carrier
subharmonics;
f = 2.87 MHz ± 3 kHz
45
51
-
dB
400
500
600
mV
with external reference
FM demodulator;
PC / SC2 > 40 dB at
pins IF1A and IF1B or
IF2A and IF2B; 27 kHz
(54 % FM deviation);
BP off; “ITU-R BS.468-4”
AM operation
L standard; pin AUD
Vo(AF)(RMS)
RMS AF output voltage
54 % modulation
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
59 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
THD
total harmonic distortion
54 % modulation; BP on;
see Figure 33
-
0.5
1.0
%
BAF(−3dB)
−3 dB AF bandwidth
12
18
-
kHz
(S/N)w(AF)
AF weighted
signal-to-noise ratio
BP on
38
42
-
dB
BP off
44
50
-
dB
-
40
-
dB
-
4
-
MHz
2.3
2.6
2.9
V
-
2
-
kΩ
-
-
200
Ω
-
-
-
pF
0.22
-
4.7
kΩ
“ITU-R BS.468-4”
composite IF;
PC / SC = 10 dB; VIF
modulation = color bar;
“ITU-R BS.468-4”;
SAW filter application
see Figure 47; BP on
Reference frequency
General
fref
[28]
reference frequency
Reference frequency generation with crystal; pin OPTXTAL
VOPTXTAL
voltage on pin OPTXTAL
(DC)
pin open-circuit
Ri
input resistance
Rrsn(xtal)
crystal resonance
resistance
Cpull
pull capacitance
Rswoff(OPTXTAL)
switch-off resistance on pin to switch off crystal input
OPTXTAL
by external resistor wired
between pin OPTXTAL
and GND
Iswoff
switch-off current
[3]
[29]
Rswoff(OPTXTAL) = 0.22 kΩ
-
-
5000
µA
Rswoff(OPTXTAL) = 3.3 kΩ
-
500
-
µA
2.3
2.6
2.9
V
-
2
-
kΩ
Reference frequency input from external source; pin OPTXTAL
VOPTXTAL
voltage on pin OPTXTAL
(DC)
Ri
input resistance
Vref(RMS)
RMS reference voltage
pin open-circuit
[3]
80
-
400
mV
-
2
4.7
kΩ
100
-
pF
RO
output resistance
of external reference
signal source
[3]
Cdec
decoupling capacitance
to external reference
signal source
[3]
22
2.2
2.5
2.8
V
[3]
50
-
-
kΩ
-
4
-
MHz
Reference frequency input from external source; pin FREF
VFREF
voltage on pin FREF (DC)
Ri
input resistance
fref
reference frequency
pin open-circuit
[28]
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
60 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vref(RMS)
RMS reference voltage
see Figure 34
15
150
500
mV
RO
output resistance
of external reference
signal source; AC-coupled
-
-
4.7
kΩ
Cdec
decoupling capacitance
to external reference
signal source
22
100
-
pF
Rswoff(FREF)
switch-off resistance on
pin FREF
to switch off reference
signal input by external
resistor wired between
pin FREF and GND
3.9
-
27
kΩ
Iswoff
switch-off current
Rswoff(FREF) = 3.9 kΩ
-
-
100
µA
Rswoff(FREF) = 22 kΩ
-
25
-
µA
Group delay select; pin GDS; see Figure 24 and Table 50
VGDS
voltage on pin GDS
pin open-circuit
-
VP
-
V
Isink(I)
input sink current
pin connected to VP
-
-
1
µA
Isource(I)
input source current
pin connected to GND
-
-
72
µA
VI
input voltage
GDEQ on; W11[2] = 0;
pin connected to GND
0
-
0.46VP
V
GDEQ on; W11[2] = 1;
pin open-circuit
0.58VP
-
VP
V
GDEQ off; W11[2] = 1;
pin connected to GND
0
-
0.46VP
V
GDEQ off; W11[2] = 0;
pin open-circuit
0.58VP
-
VP
V
pin open-circuit
-
0.5VP
-
V
MAD1; pin connected to
GND
0
-
0.04VP
V
MAD3; pin connected to
GND via RADRSEL
0.20VP
-
0.34VP
V
MAD4; pin connected to
VP via RADRSEL
0.66VP
-
0.80VP
V
MAD2; pin connected to
VP
0.96VP
-
VP
V
-
31
-
kΩ
42.3
47
51.7
kΩ
I2C-bus transceiver[30]
Address select; pin ADRSEL
VADRSEL
voltage on pin ADRSEL
(DC)
Ri
input resistance
RADRSEL
resistance on pin ADRSEL
I2C-bus
for address select
[3]
voltage select; pin BVS
VBVS
voltage on pin BVS (DC)
pin open-circuit
-
0.52VP
-
V
Isink(I)
input sink current
pin connected to VP
-
-
10
µA
Isource(I)
input source current
pin connected to GND
-
-
60
µA
TDA9897_TDA9898_4
Product data sheet
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VI
input voltage
VCC(I2C-bus) = 5.0 V;
pin connected to VP
0.88VP
-
VP
V
VCC(I2C-bus) = 3.3 V;
pin open-circuit
0.46VP
-
0.58VP
V
VCC(I2C-bus) = 2.5 V;
pin connected to GND
0
-
0.12VP
V
I2C-bus transceiver; pins SCL and SDA[31]
VIH
HIGH-level input voltage
LOW-level input voltage
VIL
IIH
HIGH-level input current
IIL
LOW-level input current
VOL
LOW-level output voltage
fSCL
SCL clock frequency
VCC(I2C-bus) = 5.0 V
[32]
0.6VP
-
VP
V
VCC(I2C-bus) = 3.3 V
[33]
2.3
-
VP
V
VCC(I2C-bus) = 2.5 V
[33]
1.75
-
VP
V
VCC(I2C-bus) = 5.0 V
[32]
−0.3
-
+0.3VP
V
VCC(I2C-bus) = 3.3 V
[33]
−0.3
-
+1.0
V
VCC(I2C-bus) = 2.5 V
[33]
−0.3
-
+0.75
V
−10
-
+10
µA
−10
-
+10
µA
-
-
0.4
V
0
-
400
kHz
-
-
0.4
V
W7[3] = 0
-
-
3
mA
W7[3] = 1
-
-
10
µA
W8[1] = 0
-
-
3
mA
W8[1] = 1
-
-
10
µA
W8[2] = 0
-
-
3
mA
W8[2] = 1
-
-
10
µA
-
-
VP + 0.5 V
IOL = 3 mA; for data
transmission (SDA)
Pins PORT1 or PORT2 or PORT3 operating as open-collector output port
VOL
LOW-level output voltage
I = 2 mA (sink)
Isink(o)
output sink current
PORT1
PORT2; W8[7] = 1
PORT3; W8[7] = 1
VOH
HIGH-level output voltage
[1]
Values of video and sound parameters can be decreased at VP = 4.5 V.
[2]
Condition for secure POR is a rise or fall time greater than 2 µs.
[3]
This parameter is not tested during the production and is only given as application information for designing the receiver circuit.
[4]
Level headroom for input level jumps during gain control setting.
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Product data sheet
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NXP Semiconductors
Multistandard hybrid IF processing
[5]
BLF(−3dB) = 100 kHz (damping factor d = 1.7; calculated with sync level within gain control range). Calculation of the VIF PLL filter by
using the following formulae:
B LF ( –3dB ) = K O K D R , valid for d ≥ 1.2
1
d = --- R 2πK O K D C
2
with the following parameters:
KO = VCO steepness (Hz/V),
KD = phase detector steepness (A/rad),
R = loop filter serial resistor (Ω),
C = loop filter serial capacitor (F),
BLF(−3dB) = −3 dB LF bandwidth (Hz),
d = damping factor.
[6]
The VCO frequency offset related to the PC frequency is set to 1 MHz with white picture video modulation.
[7]
AC load; CL < 20 pF and RL > 1 kΩ. The sound carrier frequencies (depending on TV standard) are attenuated by the integrated sound
carrier traps.
[8]
Condition: luminance range (5 steps) from 0 % to 100 %. Measurement value is based on 4 of 5 steps.
[9]
Measurement using 200 kHz high-pass filter, 5 MHz low-pass filter and subcarrier notch filter (“ITU-T J.64”).
[10] Modulation VSB; sound carrier off; fvideo > 0.5 MHz.
[11] Sound carrier on; fvideo = 10 kHz to 10 MHz.
[12] The sound carrier trap can be bypassed by setting the I2C-bus bit W2[0] to logic 0; see Table 23. In this way the full composite video
spectrum appears at pin CVBS. The video amplitude is reduced to 1.1 V (p-p).
[13] Measurement condition: with transformer, transmitter pre-correction on; reference is at 1 MHz.
[14] The response time is valid for a VIF input level range from 200 µV to 70 mV.
[15] AGC response time increased if no AGC event occurs during two lines at minimum.
[16] AGC response time increased if video level falls below half of selected level.
RL
[17] Load applied to output pin causes signal loss. The resulting gain can be calculated by using G v(load) = G v + 20 log  -------------------- .
R + R 
O
L
[18] See Figure 19 to smooth current pulses.
[19] To match the AFC output signal to different tuning systems a current output is provided. The test circuit is given in Figure 19. The
AFC steepness can be changed by different applications of resistors R1 and R2.
[20] The AFC value of the VIF and RIF frequency is generated by using digital counting methods. The used counter resolution is provided
with an uncertainty of ±1 bit corresponding to ±25 kHz. This uncertainty of ±25 kHz has to be added to the frequency accuracy
parameter.
[21] Measured with an FM deviation of 25 kHz and the typical AF output voltage of 500 mV (RMS). The audio signal processing stage
provides headroom of 6 dB with THD < 1.5 %. The I2C-bus bits W3[0] and W3[1] control the AF output signal amplitude from
0 dB to −18 dB in steps of −6 dB. Reducing the audio gain for handling a frequency deviation of more than 55 kHz avoids AF output
signal clipping.
[22] Amplitude response depends on dimensioning of FM PLL loop filter.
[23] The lower AF cut-off frequency depends on the value of the capacitor at pin CAF. A value of CAF1 = 470 nF leads to f−3dB(AF)l ≈ 20 Hz
and CAF1 = 220 nF leads to f−3dB(AF)l ≈ 40 Hz.
[24] For all signal-to-noise measurements the used VIF modulator has to meet the following specifications:
a) Incidental phase modulation for black-to-white jump less than 0.5 degrees.
b) QSS AF performance, measured with the television demodulator AMF2 (audio output, weighted signal-to-noise ratio) better than
60 dB (at deviation 27 kHz) for 6 kHz sine wave black-to-white video modulation.
c) Picture-to-sound carrier ratio PC / SC1 = 13 dB (transmitter).
[25] The PC / SC ratio is calculated as the addition of TV transmitter PC / SC1 ratio and SAW filter PC / SC1 ratio. This PC / SC ratio is
necessary to achieve the weighted signal-to-noise values as noted. A different PC / SC ratio will change these values.
[26] Measurement condition is SC1 / SC2 ≥ 7 dB.
[27] The differential QSS signal output on pins OUT1A and OUT1B is analyzed by a test demodulator TDA9820. The signal-to-noise ratio of
this device is better than 60 dB. The measurement is related to an FM deviation of ±27 kHz and in accordance with “ITU-R BS.468-4”.
TDA9897_TDA9898_4
Product data sheet
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63 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
[28] The tolerance of the reference frequency determines the accuracy of VIF AFC, RIF AFC, FM demodulator center frequency, maximum
FM deviation, sound trap frequency, LIF band-pass cut-off frequency, as well as the accuracy of the synthesizer.
[29] The value of Cpull determines the accuracy of the resonance frequency of the crystal. It depends on the used type of crystal.
[30] The AC characteristics are in accordance with the I2C-bus specification for fast mode (maximum clock frequency is 400 kHz).
Information about the I2C-bus can be found in the brochure “The I2C-bus and how to use it” (order number 9398 393 40011).
[31] The SDA and SCL lines will not be pulled down if VP is switched off.
[32] The threshold is dependent on VP.
[33] The threshold is independent of VP.
Table 54.
Examples to the FM PLL filter
BLF(−3dB) (kHz)
Cs (nF)
Cpar (pF)
Rs (kΩ)
Comment
200
2.2
100
8.2
recommended for single-carrier-sound, FM narrow
410
2.2
47
5.6
recommended for single-carrier-sound, FM wide
110
2.2
470
5.6
recommended for two-carrier-sound, FM narrow
210
2.2
47
8.2
used for test circuit
Table 55.
Input frequencies and carrier ratios (examples)
Symbol
Parameter
B/G standard M/N standard L standard L-accent standard
Unit
fPC
picture carrier frequency
38.375
38.375
38.375
33.625
MHz
fSC1
sound carrier frequency 1
32.825
33.825
31.825
40.125
MHz
fSC2
sound carrier frequency 2
32.583
-
-
-
MHz
PC / SC1 picture to first sound carrier ratio
13
7
10
10
dB
PC / SC2 picture to second sound carrier ratio
20
-
-
-
dB
trap bypass mode
normal mode 1.7 V
normal mode 2.0 V
2.72 V
2.6 V
3.08 V
2.9 V
3.41 V
3.20 V
zero carrier level
white level
1.83 V
1.71 V
1.80 V
black level
1.5 V
1.2 V
1.20 V
sync level
001aaj651
Fig 10. Typical video signal levels on output pin CVBS (sound carrier off)
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Product data sheet
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
V = VP + Vripple
TDA9897
TDA9898
VP (V)
5.050
5.000
4.950
t (s)
001aae391
Fig 11. Ripple rejection condition
001aaj590
5
Vmonitor(VIFAGC)
(V)
4
5
VTAGC
(V)
4
3
3
2
2
(1)
(2)
(3)
1
(4)
1
0
30
50
70
90
0
110
130
Vi(VIF) (dBµV)
(1) VIF AGC.
(2) TAGC; W10 = 00h.
(3) TAGC; W10 = 10h.
(4) TAGC; W10 = 1Fh.
Fig 12. Typical VIF monitor and TAGC characteristic
TDA9897_TDA9898_4
Product data sheet
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
001aaj591
100
Vi(IF)
(dBµV)
90
80
70
50
0 0000
0 0001
0 0010
0 0011
0 0100
0 0101
0 0110
0 0111
0 1000
0 1001
0 1010
0 1011
0 1100
0 1101
0 1110
0 1111
1 0000
1 0001
1 0010
1 0011
1 0100
1 0101
1 0110
1 0111
1 1000
1 1001
1 1010
1 1011
1 1100
1 1101
1 1110
1 1111
60
Integral TAGC (W9); step width: 1.255 dB typical.
IF based TAGC (W10).
bit pattern W9[4:0] or W10[4:0]
Fig 13. Typical tuner takeover point as a function of I2C-bus register W9 or W10
001aaj592
100
Vi(IF)
(dBµV)
90
80
(1)
70
60
50
0
5
10
15
20
25
RTOP2 (kΩ)
(1) IF based TAGC (TOP2).
Fig 14. Typical tuner takeover point as a function of resistor RTOP2
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
001aaj593
5
001aaj594
5
VAGC(SIF)
(V)
VAGC(FM)
(V)
4
4
3
3
2
2
(1)
(2)
1
1
0
0
40
60
80
100
120
Vi(EXTFMI) (dBµV)
20
40
60
80
100
120
Vi(SIF) (dBµV)
(1) AM.
(2) FM.
Fig 15. Typical FM AGC characteristic measured at
pin MPP
Fig 16. Typical SIF AGC characteristic measured at
pin MPP
TDA9897_TDA9898_4
Product data sheet
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67 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
008aaa035
250
∆fAFC(VIF)(5)
(kHz)
250
IAFC(6)
(µA)
(1)
150
150
50
50
(2)
bit AFCWIN (R1[7]) = 1
0
0
(3)
−50
−50
−150
−150
(4)
−250
36.375
36.875
37.375
37.875
38.375
38.875
−250
39.875
40.375
fVIF (MHz)
39.375
(1) VIF AFC via I2C-bus; accuracy is ±1 digit.
(2) Bit AFCWIN via I2C-bus (VCO is in ±1.6 MHz window) for all standards except M/N standard.
(3) Bit AFCWIN via I2C-bus (VCO is in ±0.8 MHz window) for M/N standard.
(4) VIF AFC average current.
(5) Reading via I2C-bus.
(6) Average; RC network at pin MPP.
Fig 17. Typical analog and digital AFC characteristic for VIF
001aad443
250
∆fAFC(RIF)(4)
(kHz)
250
IAFC(5)
(µA)
(1)
150
150
(2)
50
50
0
0
−50
−50
−150
−150
(3)
−250
5.0
AFC undefined
5.2
bit CARRDET (R1[5]) = 1
5.4
5.6
AFC undefined
5.8
−250
6.0
fRIF (MHz)
Characteristics of digital and analog radio AFC is mirrored with respect to center frequency when lower sideband is used
(W2[3] = 0).
(1) RIF AFC via I2C-bus.
(2) FM carrier detection via I2C-bus.
(3) RIF AFC average current.
(4) Reading via I2C-bus.
(5) Average; RC network at pin MPP.
Fig 18. Typical analog and digital AFC characteristic for RIF
TDA9897_TDA9898_4
Product data sheet
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
VP
R1
22 kΩ
IAFC
MPP
TDA9897
TDA9898
R2
22 kΩ
100 nF
008aaa152
Fig 19. RC network for measurement of analog AFC characteristic
001aaj595
60
S/N
(dB)
(1)
50
(2)
40
30
20
50
60
70
80
90
100
Vi(VIF) (dBµV)
(1) B/G standard; weighted video S/N; using 50 % grey picture.
(2) M/N standard; unweighted video S/N; using 50 IRE grey picture.
Fig 20. Typical signal-to-noise ratio as a function of VIF input voltage
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
001aaj556
5
αresp(f)
0
(dB)
(1)
−5
(2)
(3)
−10
−15
−20
−25
−30
−35
−40
−45
0
1
2
3
4
5
6
f (MHz)
(1) Minimum requirements upper limit.
(2) Minimum requirements lower limit.
(3) Typical trap amplitude frequency response.
Fig 21. Typical amplitude frequency response for sound trap at M/N standard (including
Korea)
001aaj555
250
200
td(grp)
(ns) 150
100
(1)
50
0
(3)
−50
(2)
−100
−150
−200
−250
0
1
2
3
4
5
6
f (MHz)
(1) Minimum requirements upper limit.
(2) Minimum requirements lower limit.
(3) Typical trap group delay response.
Fig 22. Typical group delay response for sound trap at M/N standard
TDA9897_TDA9898_4
Product data sheet
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70 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
001aaj557
5
αresp(f)
0
(dB)
(1)
−5
(2)
(3)
−10
−15
−20
−25
−30
−35
−40
−45
0
1
2
3
4
5
6
7
8
f (MHz)
(1) Minimum requirements upper limit.
(2) Minimum requirements lower limit.
(3) Typical trap amplitude frequency response.
Fig 23. Typical amplitude frequency response for sound trap at B/G standard
001aaj554
250
200
td(grp)
(ns) 150
100
(1)
50
(3)
(4)
0
−50
(5)
(2)
−100
−150
−200
−250
0
1
2
3
4
5
6
f (MHz)
(1) Minimum requirements upper limit (valid for GDEQ off).
(2) Minimum requirements lower limit (valid for GDEQ off).
(3) Typical trap group delay response; GDEQ off.
(4) Typical trap group delay response; GDEQ on.
(5) Typical group delay response of additional group delay equalizer (difference of curves 3 and 4).
Fig 24. Typical group delay response for sound trap at B/G standard
TDA9897_TDA9898_4
Product data sheet
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71 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
001aaj553
5
αresp(f)
0
(dB)
(1)
−5
(2)
(3)
−10
−15
−20
−25
−30
−35
−40
−45
0
1
2
3
4
5
6
7
8
f (MHz)
(1) Minimum requirements upper limit.
(2) Minimum requirements lower limit.
(3) Typical trap amplitude frequency response.
Fig 25. Typical amplitude frequency response for sound trap at I standard
001aaj552
250
200
td(grp)
(ns) 150
100
(1)
50
(3)
0
−50
(2)
−100
−150
−200
−250
0
1
2
3
4
5
6
7
8
f (MHz)
(1) Minimum requirements upper limit.
(2) Minimum requirements lower limit.
(3) Typical trap group delay response.
Fig 26. Typical group delay response for sound trap at I standard
TDA9897_TDA9898_4
Product data sheet
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72 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
001aaj551
5
(1)
αresp(f)
0
(dB)
(2)
−5
−10
−15
(3)
−20
−25
−30
−35
−40
−45
0
1
2
3
4
5
6
7
8
f (MHz)
(1) Minimum requirements upper limit.
(2) Minimum requirements lower limit.
(3) Typical trap amplitude frequency response.
Fig 27. Typical amplitude frequency response for sound trap at D/K standard
001aaj550
250
200
td(grp)
(ns) 150
100
(1)
50
(3)
0
−50
(2)
−100
−150
−200
−250
0
1
2
3
4
5
6
7
8
f (MHz)
(1) Minimum requirements upper limit.
(2) Minimum requirements lower limit.
(3) Typical trap group delay response.
Fig 28. Typical group delay response for sound trap at D/K standard
TDA9897_TDA9898_4
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73 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
001aaj549
5
(1)
αresp(f)
0
(dB)
(3)
(2)
−5
−10
−15
−20
−25
−30
−35
−40
−45
0
1
2
3
4
5
6
7
8
f (MHz)
(1) Minimum requirements upper limit.
(2) Minimum requirements lower limit.
(3) Typical trap amplitude frequency response.
Fig 29. Typical amplitude frequency response for sound trap at L standard
001aaj548
250
200
td(grp)
(ns) 150
100
(1)
50
(3)
0
−50
(2)
−100
−150
−200
−250
0
1
2
3
4
5
6
7
8
f (MHz)
(1) Minimum requirements upper limit.
(2) Minimum requirements lower limit.
(3) Typical trap group delay response.
Fig 30. Typical group delay response for sound trap at L standard
TDA9897_TDA9898_4
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74 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
001aaf579
10
αresp(f)
(dB)
0
(1)
(5)
(4)
(3)
(2)
−10
(7)
−20
(6)
−30
−40
−50
−3.0
−2.0
−1.0
0
1.0
2.0
f − fc (MHz)
3.0
(1) Center frequency.
(2) Minimum upper cut-off frequency.
(3) Minimum lower cut-off frequency.
(4) Maximum upper cut-off frequency.
(5) Maximum lower cut-off frequency.
(6) Minimum upper stop-band attenuation.
(7) Minimum lower stop-band attenuation.
Fig 31. Typical sound BP amplitude frequency response at TV mode, normalized to BP
center frequency
001aaj633
10
Vo(AF)
(dB)
(1)
(2)
0
(1)
(2) (3)
−10
(3)
−20
−30
102
10
103
104
105
fAF (kHz)
(1) FM; transmitter pre-correction off and receiver de-emphasis off; FM PLL filter: Rs = 5.6 kΩ and
Cpar = 47 pF.
(2) AM and AGC normal.
(3) AM and AGC fast.
Fig 32. Typical AM and FM audio frequency response
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
75 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
001aaj596
2.0
THD
(%)
1.5
1.0
0.5
0
102
10
103
104
105
fAF (kHz)
Fig 33. Typical total harmonic distortion as a function of audio frequency at AM standard
001aaj597
60
(S/N)unw
(dB)
50
40
30
0
50
100
150
200
Vi(FREF)(RMS) (mV)
Reference frequency input signal taken from external quartz circuit.
Fig 34. Unweighted FM audio S/N versus reference frequency input level using radio
mode
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
76 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
001aaf639
120
antenna
input
level
(dBµV)
(5)
1
IF signal
RMS
values
(V)
(2)
(4)
10−1
100
(6)
(3)
RF
gain
control
range
80
10−2
IF gain
control
range limited
by TOP
adjustment
60
IF gain
control
range
10−3
10−4
40
(1)
10−5
20
tuner
band-pass
TD1716
X3450L
VIF
amplifier
output
input
output
input
output
input
output
input
input
0
output
(7)
demodulator
10−6
video
amplifier
IF demodulator, TDA989x
Video signal related peak-to-peak levels are divided by factor 2√2 in order to conform with the RMS
value scale of the secondary y-axis, but disregarding the none sine wave signal content.
(1) Signal levels for −1 dB video output level using maximum RF gain and maximum IF gain.
(2) Signal levels for +1 dB video output level using minimum IF gain.
(3) Signal levels for TOP-adjusted tuner output level using maximum RF gain and adjustment-related
minimum IF gain.
(4) Signal levels for TOP-adjusted tuner output level using minimum RF gain and adjustment-related
minimum IF gain.
(5) TOP-adjusted tuner output level.
(6) TOP-adjusted VIF amplifier input level.
(7) Minimum antenna input level at −1 dB video level.
Fig 35. Front-end level diagram
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
77 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
12.2 Digital TV signal processing
Table 56. Characteristics
VP = 5 V[1]; Tamb = 25 °C; 8 MHz system; see Table 33 and Table 34; CW test input signal is used for specification;
Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 Ω via broadband transformer 1 : 1;
gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of Figure 51 with 4 MHz
crystal oscillator reference; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IF amplifier; IF1A and IF1B or IF2A and IF2B or pins IF3A and IF3B
VI
input voltage
1.8
1.93
2.2
V
-
2
-
kΩ
Ri(dif)
differential input
resistance
[2]
Ci(dif)
differential input
capacitance
[2]
-
3
-
pF
GIF(cr)
control range IF gain
[2]
60
66
-
dB
DTV differential output; pins OUT1A, OUT1B, OUT2A and OUT2B
VO
output voltage
pin open-circuit
1.8
2.0
2.2
V
Ibias(int)
internal bias current
(DC)
for emitter-follower
2.0
2.5
-
mA
Isink(o)(max)
maximum output sink
current
DC and AC; see Figure 36
[3]
1.4
1.7
-
mA
Isource(o)(max)
maximum output
source current
DC and AC; see Figure 36
[3]
6.0
-
-
mA
RO
output resistance
differential; output active
[2]
-
-
50
Ω
output inactive; internal
resistance to GND
[2]
-
800
-
Ω
minimum input sine wave
level for nominal output level
-
70
100
µV
maximum input sine wave
level for nominal output level
130
170
-
mV
Vi(IF)(RMS)
RMS IF input voltage
permissible overload
[2]
-
-
320
mV
-
83
-
dB
-
1.0
1.1
V
-
0.50
0.55
V
115
124
-
dBc/Hz
90
104
-
dBc/Hz
W4[7] = 0
40
-
-
dB
W4[7] = 1
40
-
-
dB
Direct IF; pins OUT2A and OUT2B
GIF(max)
maximum IF gain
output peak-to-peak level to
input RMS level ratio
[2]
Vo(dif)(p-p)
peak-to-peak
differential output
voltage
between pin OUT2A and
pin OUT2B
[4]
W4[7] = 0
W4[7] = 1
C/N
carrier-to-noise ratio
at fo = 33.4 MHz;
see Figure 37
[2][5][6]
Vi(IF) = 10 mV (RMS)
Vi(IF) = 0.5 mV (RMS)
αIM
intermodulation
suppression
input signals: fi = 47.0 MHz
and 57.5 MHz; output
signals: fo = 36.5 MHz or
68.0 MHz; see Figure 38
TDA9897_TDA9898_4
Product data sheet
[2]
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
78 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 56. Characteristics …continued
VP = 5 V[1]; Tamb = 25 °C; 8 MHz system; see Table 33 and Table 34; CW test input signal is used for specification;
Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 Ω via broadband transformer 1 : 1;
gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of Figure 51 with 4 MHz
crystal oscillator reference; unless otherwise specified.
Symbol
Parameter
fIF(−1dB)l
lower −1 dB IF cut-off
frequency
f−3dB(IF)u
upper IF cut-off
frequency
power supply ripple
rejection
PSRR
Conditions
Min
Typ
Max
Unit
[2]
-
7
-
MHz
W4[7] = 0
[4]
60
-
-
MHz
W4[7] = 1
[7]
60
-
-
MHz
residual spurious at nominal
differential output voltage
dependent on power supply
ripple
[2]
fripple = 70 Hz
-
60
-
dB
fripple = 20 kHz
-
60
-
dB
-
89
-
dB
Low IF output signal; pins OUT1A and OUT1B; differential
GIF(max)
maximum IF gain
fsynth
synthesizer frequency see Table 34 and Table 35
Vo(dif)(p-p)
PSRR
αripple(pb)LIF
output peak-to-peak level to
input RMS level ratio
[2]
-
-
-
MHz
-
2
-
V
-
1
-
V
fripple = 70 Hz
-
50
-
dB
fripple = 20 kHz
-
30
-
dB
6 MHz bandwidth
-
-
2.7
dB
7 MHz bandwidth
-
-
2.7
dB
peak-to-peak
differential output
voltage
W4[7] = 0
[4]
W4[7] = 1
[4]
power supply ripple
rejection
residual spurious at nominal
differential output voltage
dependent on power supply
ripple
[2]
low IF pass-band
ripple
8 MHz bandwidth
B−3dB
αstpb
−3 dB bandwidth
-
-
2.7
dB
BP off
[4]
11
15
-
MHz
6 MHz bandwidth
[4]
-
7.8
-
MHz
7 MHz bandwidth
[4]
-
8.8
-
MHz
8 MHz bandwidth
[4]
-
9.8
-
MHz
30
40
-
dB
6 MHz band; f = 20 MHz
28
35
-
dB
7 MHz band; f = 13.75 MHz
30
40
-
dB
7 MHz band; f = 20 MHz
28
35
-
dB
8 MHz band; f = 15.75 MHz
30
40
-
dB
8 MHz band; f = 20 MHz
28
35
-
dB
stop-band attenuation 6 MHz band; f = 11.75 MHz
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
79 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 56. Characteristics …continued
VP = 5 V[1]; Tamb = 25 °C; 8 MHz system; see Table 33 and Table 34; CW test input signal is used for specification;
Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 Ω via broadband transformer 1 : 1;
gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of Figure 51 with 4 MHz
crystal oscillator reference; unless otherwise specified.
Symbol
Parameter
Conditions
∆td(grp)
group delay time
variation
from 1 MHz to 2 MHz
[2]
from 2 MHz to end of band
with a bandwidth of
[2]
αimage
C/N
αH(ib)
image rejection
carrier-to-noise ratio
in-band harmonics
suppression
Min
Typ
Max
Unit
-
90
200
ns
6 MHz
-
90
160
ns
7 MHz
-
90
160
ns
8 MHz
-
90
160
ns
BP on
30
34
-
dB
BP off
24
28
-
dB
Vi(IF) = 10 mV (RMS)
112
118
-
dBc/Hz
Vi(IF) = 0.5 mV (RMS)
90
104
-
dBc/Hz
40
-
-
dB
40
-
-
dB
40
-
-
dB
−10 MHz to 0 MHz
at fo = 4.9 MHz;
see Figure 37
[2][5][6]
low IF = multiple of
1.31 MHz;
fi = fsynth + 1.31 MHz;
see Figure 40
[2]
W4[7] = 0
W4[7] = 1
αIM
intermodulation
suppression
input signals:
fi = fsynth + 4.7 MHz and
fsynth + 5.3 MHz; output
signals: fo = 4.1 MHz or
5.9 MHz; see Figure 39
[2]
W4[7] = 0
W4[7] = 1
40
-
-
dB
50
-
-
dB
αsp(ib)
in-band spurious
suppression
single-ended AC load;
RL = 1 kΩ; CL = 5 pF;
1 MHz to end of band;
BP on
[2]
αsp(ob)
out-band spurious
suppression
single-ended AC load;
RL = 1 kΩ; CL = 5 pF; BP on
[2]
50
-
-
dB
IF AGC control; pin AGCDIN
Isink(i)(max)
maximum input sink
current
[2]
-
-
2
µA
Vi(max)
maximum input
voltage
[2]
-
-
VP
V
VAGCDIN
voltage on pin
AGCDIN
[2]
0
-
3
V
∆GIF/∆VAGCDIN
change of IF gain with VAGCDIN = 0.8 V to 2.2 V
voltage on
pin AGCDIN
-
−45
-
dB/V
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
80 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 56. Characteristics …continued
VP = 5 V[1]; Tamb = 25 °C; 8 MHz system; see Table 33 and Table 34; CW test input signal is used for specification;
Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 Ω via broadband transformer 1 : 1;
gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of Figure 51 with 4 MHz
crystal oscillator reference; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tuner AGC; pin TAGC
TAGC integral loop mode (W6[7:6] = 10); TAGC is current output; unmodulated IF; see Table 44 and Figure 13
Vi(IF)(RMS)
RMS IF input voltage
αacc(set)TOP
TOP setting accuracy
Isource
source current
at starting point of tuner
AGC takeover;
Isink(TAGC) = 100 µA
W9[4:0] = 0 0000
-
59.6
-
dBµV
W9[4:0] = 1 0000
-
78.3
-
dBµV
W9[4:0] = 1 1111
-
98.5
-
dBµV
−2
-
+2
dB
0.20
0.33
0.45
µA
TAGC charge current
normal mode; W9[5] = 0
Isink
sink current
∆αacc(set)TOP/∆T TOP setting accuracy
variation with
temperature
normal mode; W9[5] = 1
1.6
2.5
3.4
µA
fast mode activated by
internal level detector;
W9[5] = 0
7
11
15
µA
fast mode activated by
internal level detector;
W9[5] = 1
60
90
120
µA
375
500
625
µA
[2]
-
0.006
0.02
dB/K
[2]
TAGC discharge current;
VTAGC = 1 V
Isink(TAGC) = 100 µA;
W9[4:0] = 1 0000
RL
load resistance
50
-
-
MΩ
Vsat(u)
upper saturation
voltage
pin operating as current
output
[2]
VP − 0.3
-
-
V
Vsat(l)
lower saturation
voltage
pin operating as current
output
[2]
-
-
0.3
V
αth(fast)AGC
AGC fast mode
threshold
activated by internal fast
AGC detector; I2C-bus
setting corresponds to
W9[4:0] = 1 0000
[2]
6
8
10
dB
td
delay time
before activating; Vi(IF)
below αth(fast)AGC
[2]
40
60
80
ms
1.0
-
3.5
V
Filter synthesizer PLL; pin LFSYN1
VLFSYN1
voltage on pin
LFSYN1
KO
VCO steepness
∆fVCO / ∆VLFSYN1
-
3.75
-
MHz/V
KD
phase detector
steepness
∆ILFSYN1 / ∆ϕVCO
-
9
-
µA/rad
Isink(o)PD(max)
maximum phase
detector output sink
current
-
-
65
µA
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
81 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 56. Characteristics …continued
VP = 5 V[1]; Tamb = 25 °C; 8 MHz system; see Table 33 and Table 34; CW test input signal is used for specification;
Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 Ω via broadband transformer 1 : 1;
gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of Figure 51 with 4 MHz
crystal oscillator reference; unless otherwise specified.
Symbol
Parameter
Isource(o)PD(max)
maximum phase
detector output
source current
Conditions
Min
Typ
Max
Unit
-
-
65
µA
1
-
3
V
-
31
-
MHz/V
22 MHz to 29.5 MHz
-
32
-
µA/rad
30 MHz to 37.5 MHz
-
38
-
µA/rad
38 MHz to 45.5 MHz
-
47
-
µA/rad
46 MHz to 53.5 MHz
-
61
-
µA/rad
57 MHz
-
61
-
µA/rad
22 MHz to 29.5 MHz
-
200
-
µA
30 MHz to 37.5 MHz
-
238
-
µA
38 MHz to 45.5 MHz
-
294
-
µA
46 MHz to 53.5 MHz
-
384
-
µA
57 MHz
-
384
-
µA
Conversion synthesizer PLL; pin LFSYN2
VLFSYN2
voltage on pin
LFSYN2
KO
VCO steepness
∆fVCO / ∆VLFSYN2
KD
phase detector
steepness
∆ILFSYN2 / ∆ϕVCO;
see Table 57;
fVCO selection:
Io(PD)
ϕn(synth)
phase detector output sink or source;
current
fVCO selection:
synthesizer phase
noise
fsynth = 31 MHz;
fIF = 36 MHz
at 1 kHz
[2]
89
99
-
dBc/Hz
at 10 kHz
[2]
89
99
-
dBc/Hz
at 100 kHz
[2]
98
102
-
dBc/Hz
at 1.4 MHz
[2]
115
119
-
dBc/Hz
at 1 kHz
[2]
89
96
-
dBc/Hz
at 10 kHz
[2]
89
100
-
dBc/Hz
at 100 kHz
[2]
96
100
-
dBc/Hz
at 1.4 MHz
[2]
115
118
-
dBc/Hz
multiple of ∆f = 500 kHz
[2]
50
-
-
dBc
synthesizer spurious
performance > 50 dBc
[2]
-
-
10
nA
fsynth = 40 MHz;
fIF = 44 MHz; external
4 MHz reference signal of
265 mV (RMS) and phase
noise better than
120 dBc/Hz; see Figure 46
αsp
IL
spurious suppression
leakage current
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
82 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 56. Characteristics …continued
VP = 5 V[1]; Tamb = 25 °C; 8 MHz system; see Table 33 and Table 34; CW test input signal is used for specification;
Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 Ω via broadband transformer 1 : 1;
gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of Figure 51 with 4 MHz
crystal oscillator reference; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
-
4
-
MHz
2.3
2.6
2.9
V
-
2
-
kΩ
-
-
200
Ω
-
-
-
pF
Reference frequency
General
fref
[8]
reference frequency
Reference frequency generation with crystal; pin OPTXTAL
VOPTXTAL
voltage on pin
OPTXTAL (DC)
pin open-circuit
Ri
input resistance
Rrsn(xtal)
crystal resonance
resistance
Cpull
pull capacitance
Rswoff(OPTXTAL)
switch-off resistance
on pin OPTXTAL
to switch off crystal input by
external resistor wired
between pin OPTXTAL and
GND
0.22
-
4.7
kΩ
Iswoff
switch-off current
Rswoff(OPTXTAL) = 0.22 kΩ
-
-
5000
µA
Rswoff(OPTXTAL) = 3.3 kΩ
-
500
-
µA
2.3
2.6
2.9
V
[2]
[9]
Reference frequency input from external source; pin OPTXTAL
VOPTXTAL
voltage on pin
OPTXTAL (DC)
pin open-circuit
Ri
input resistance
Vref(RMS)
RMS reference
voltage
RO
output resistance
of external reference signal
source
Cdec
decoupling
capacitance
to external reference signal
source
[2]
-
2
-
kΩ
80
-
400
mV
[2]
-
2
4.7
kΩ
[2]
22
100
-
pF
2.2
2.5
2.8
V
Reference frequency input from external source; pin FREF
VFREF
voltage on pin FREF
(DC)
pin open-circuit
Ri
input resistance
[2]
50
-
-
kΩ
fref
reference frequency
[8]
-
4
-
MHz
Vref(RMS)
RMS reference
voltage
see Figure 46
15
150
500
mV
RO
output resistance
of external reference signal
source; AC-coupled
-
-
4.7
kΩ
Cdec
decoupling
capacitance
to external reference signal
source
22
100
-
pF
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
83 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 56. Characteristics …continued
VP = 5 V[1]; Tamb = 25 °C; 8 MHz system; see Table 33 and Table 34; CW test input signal is used for specification;
Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 Ω via broadband transformer 1 : 1;
gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of Figure 51 with 4 MHz
crystal oscillator reference; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rswoff(FREF)
switch-off resistance
on pin FREF
to switch off reference signal
input by external resistor
wired between pin FREF
and GND
3.9
-
27
kΩ
Iswoff
switch-off current
Rswoff(FREF) = 3.9 kΩ
-
-
100
µA
Rswoff(FREF) = 22 kΩ
-
25
-
µA
[1]
Some parameters can be decreased at VP = 4.5 V.
[2]
This parameter is not tested during production and is only given as application information.
[3]
Output current can be increased by application of single-ended resistor from each output pin to GND. Recommended resistor value is
minimum 1 kΩ.
[4]
With single-ended load for fIF < 45 MHz RL ≥ 1 kΩ and CL ≤ 5 pF to ground and for fIF = 45 MHz to 60 MHz RL = 1 kΩ and CL ≤ 3 pF to
ground.
[5]
Noise level is measured without input signal but AGC adjusted corresponding to the given input level.
[6]
Set with AGC nominal output voltage as reference. For C/N measurement switch input signal off.
[7]
With single-ended load RL ≥ 1 kΩ and CL ≤ 5 pF to ground.
[8]
The tolerance of the reference frequency determines the accuracy of VIF AFC, RIF AFC, FM demodulator center frequency, maximum
FM deviation, sound trap frequency, LIF band-pass cut-off frequency, as well as the accuracy of the synthesizer.
[9]
The value of Cpull determines the accuracy of the resonance frequency of the crystal. It depends on the used type of crystal.
Table 57.
Conversion synthesizer PLL; loop filter dimensions[1]
fVCO (MHz)
RLFSYN2 (kΩ)[2]
CLFSYN2 (nF)
22 to 29.5
1.5
4.7
30 to 37.5
1.8
4.7
38 to 45.5
2.2
4.7
46 to 53.5
2.7
4.7
57
3.3
4.7
[1]
Calculation of the PLL loop filter by using the following formulae:
KO
B LF ( –3dB ) = -------K D R LFSYN2 , valid for d ≥ 1.2
N
KO
1
d = --- R LFSYN2 2π -------K D C LFSYN2
2
N
with the following parameters:
KO = VCO steepness (Hz/V),
f VCO
0.5 MHz
N = divider ratio: N = -------------------- ,
KD = phase detector steepness (A/rad),
RLFSYN2 = synthesizer loop filter serial resistor (Ω),
CLFSYN2 = synthesizer loop filter serial capacitor (F),
BLF(−3dB) = −3 dB LF bandwidth (Hz),
d = damping factor.
[2]
If more than one frequency range is used in the application, then the smallest resistor value should be applied.
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
84 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
008aaa153
30
CL(dif)
(pF)
20
(2)
10
(1)
0
0
1
2
3
RL(dif) (kΩ)
W4[7] = 0; nominal output level
(1) Direct IF, fmax = 40 MHz, with single-ended resistors of 1 kΩ to GND.
(2) Low IF, fmax = 9 MHz.
Fig 36. Maximum differential load figures at OUT1/OUT2
001aaj598
130
(3)
C/N
(dBc/Hz)
(1)
120
(2)
110
100
90
80
30
50
70
90
110
Vi(IF)(RMS) (dBµV)
(1) Direct IF.
(2) Low IF.
(3) Noise level of measurement setup.
Fig 37. Typical C/N ratio as a function of IF input voltage
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
85 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Vi(IF)(RMS)
(dBµV)
Vo(dif)(p-p)
(V)
74
0.5
(1)
0
0
47
57.5
input signal
0
fi
(MHz)
αIM
0
36.5
47
57.5
68
output signal
fo
(MHz)
008aaa051
(1) 0.25 V for W4[7] = 1.
Fig 38. Direct IF signal conditions for measurement of intermodulation at OUT2
Vi(IF)(RMS)
(dBµV)
Vo(dif)(p-p)
(V)
74
0.5
(1)
0
36
fsynth
40.7
41.3
input signal
0
fi
(MHz)
αIM
0
4.1
4.7
5.3
5.9
output signal
fo
(MHz)
008aaa053
(1) 0.25 V for W4[7] = 1.
Fig 39. Low IF signal conditions for measurement of intermodulation at OUT1
Vi(IF)(RMS)
(dBµV)
Vo(dif)(p-p)
(V)
80
2.0
(1)
0
36
fsynth
37.31
input signal
0
fi
(MHz)
αH(ib)
0
1.31
2.62
3.93
5.24
7.86
6.55
output signal
fo
(MHz)
008aaa054
(1) 1.0 V for W4[7] = 1.
Fig 40. Low IF signal conditions for measurement of harmonics at OUT1
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Product data sheet
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
001aaj605
2
td(grp)LIF
(ns)
αresp(f)
(dB) 1
0
−1
−2
(1) (2) (3)
−3
−4
−5
100
−6
(1)
(2)
(3)
−7
−8
0
−100
−200
−9
−10
0
2
4
6
8
10
12
f (MHz)
tolerance scheme:
(1)
(2)
(3)
(1) Channel bandwidth = 6 MHz.
(2) Channel bandwidth = 7 MHz.
(3) Channel bandwidth = 8 MHz.
Fig 41. Detailed low IF amplitude and group delay pass-band tolerance scheme
001aaj607
10
αresp(f)
(dB) 0
−10
−20
−30
−40
(1)
(2)
(3)
−50
−60
−70
−30
−25
−20
−15
−10
−5
0
f (MHz)
tolerance scheme:
(1)
(2)
(3)
(1) Channel bandwidth = 6 MHz.
(2) Channel bandwidth = 7 MHz.
(3) Channel bandwidth = 8 MHz.
Fig 42. Low IF amplitude stop-band tolerance scheme
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Product data sheet
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87 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
001aaj606
10
αresp(f)
(dB) 0
−10
−20
−30
(1)
(2)
(3)
−40
−50
−60
−70
0
5
10
15
20
25
30
f (MHz)
tolerance scheme:
(1)
(2)
(3)
(1) Channel bandwidth = 6 MHz.
(2) Channel bandwidth = 7 MHz.
(3) Channel bandwidth = 8 MHz.
Fig 43. Low IF amplitude pass-band tolerance scheme
001aaj599
100
G(7)
(dB)
80
60
(1)
(4)
(2)
(5)
(3)
(6)
40
20
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VAGCDIN (V)
(1) 2.0 V (p-p) differential output voltage (LIF, W9[7] = 0, W4[7] = 0).
(2) 1.0 V (p-p) differential output voltage (LIF, W9[7] = 0, W4[7] = 1; DIF, W9[7] = 0, W4[7] = 0).
(3) 0.5 V (p-p) differential output voltage (DIF, W9[7] = 0, W4[7] = 1).
(4) 2.0 V (p-p) differential output voltage (LIF, W9[7] = 1, W4[7] = 0).
(5) 1.0 V (p-p) differential output voltage (LIF, W9[7] = 1, W4[7] = 1; DIF, W9[7] = 1, W4[7] = 0).
(6) 0.5 V (p-p) differential output voltage (DIF, W9[7] = 1, W4[7] = 1).
(7) Ratio of output peak-to-peak level to input RMS level.
Fig 44. Typical gain characteristic for AGCDIN control voltage
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Product data sheet
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NXP Semiconductors
Multistandard hybrid IF processing
001aaj601
2.5
VLFSYN2
(V)
2.0
1.5
1.0
20
30
40
50
60
fsynth (MHz)
Fig 45. Typical synthesizer loop filter voltage as function of synthesizer frequency
001aaj600
105
(1)
ϕn(synth)
(dBc/Hz)
(2)
95
(3)
85
75
0
100
200
300
400
500
Vi(FREF)(RMS) (mV)
fsynth = 40 MHz; fIF = 44 MHz; sound BP off
(1) ∆f = 100 kHz.
(2) ∆f = 10 kHz.
(3) ∆f = 1 kHz.
Fig 46. Typical synthesizer phase noise at carrier frequency plus ∆f on LIF output versus
input voltage on pin FREF
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
13. Application information
tuner
AGC
output
4 MHz
reference
input
synthesizer
trap control
loop filter
VP = 5 V
100 nF
CTAGC
220 nF
CFREF
100 pF
470 Ω
L(4)
analog
ground
470 nF
synthesizer
downconverter
loop filter(2)
3.3 kΩ
100 nF
n.c.
48
1
37
36
2
35
3
34
4
33
2 V CVBS
output
5
32
BVS
31
AUD
22 pF
RLFSYN2 CLFSYN2
n.c.
47
46
45
44
43
42
41
40
39
38
AGC input for DIF
(from channel decoder)
1.5 nF
CIFAGC(5)
470 nF
6
IF(1)
TDA9897
TDA9898
7 MHz WINDOW
7
SAW
X3450L
30
1st DIF
CCTAGC
8
29
9
28
100 nF
CAF
470 nF
6 MHz WINDOW
10
27
11
26
digital LIF or
analog 2nd
sound IF
25
12
13
14
15
16
17
18
19
20
Cs
220 nF
Cpar
100 Ω
21
Cde-em
4.7 nF
22
FM PLL loop filter(3)
24
digital
ground
ADRSEL
100 Ω
Rs
VIF PLL
loop filter
23
external
FM input
SDA
100 Ω
SCL
001aai815
(1) Optional single-ended IF input possible.
(2) Application depends on synthesizer frequency; see Table 57.
(3) Application of FM PLL loop filter; see Table 54.
(4) EMI suppression filter for DC, e.g. BLM21RK121SN1 (Murata).
(5) Capacitor connected only for TDA9898.
Fig 47. Application diagram of TDA9897 and TDA9898; ATV/DVB-T
TDA9897_TDA9898_4
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90 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
tuner
AGC
output
4 MHz
reference
input
synthesizer
trap control
loop filter
VP = 5 V
100 nF
CTAGC
220 nF
CFREF
100 pF
470 Ω
L(3)
analog
ground
470 nF
3.3 kΩ
100 nF
n.c.
synthesizer
downconverter
loop filter(1)
48
1
37
36
2
35
3
34
22 pF
RLFSYN2 CLFSYN2
n.c.
12
47
46
45
44
43
42
41
40
39
38
AGC input for DIF
(from channel decoder)
PORT2
1.5 nF
SOUND
11
SAW
X3751L
33
2 V CVBS
output
5
32
BVS
31
AUD
470 nF
6
8
6 MHz or 8 MHz
WINDOW
7
3
17
2
4
CIFAGC(4)
TDA9897
TDA9898
7
30
1st DIF
CCTAGC
8
29
9
28
100 nF
CAF
470 nF
10
27
11
26
digital LIF or
analog 2nd
sound IF
PORT2
4.7 kΩ
IF
4.7 kΩ
PORT1
12
25
13
BA277
BA277
4.7 kΩ
14
15
16
17
18
19
20
21
22
23
24
4.7 kΩ
4.7 kΩ
Cs
220 nF
Cpar
VP
100 Ω
Cde-em
4.7 nF
digital
ground
FM PLL loop filter(2)
VIF PLL
loop filter
ADRSEL
100 Ω
Rs
external
FM input
SDA
100 Ω
SCL
001aai816
(1) Application depends on synthesizer frequency; see Table 57.
(2) Application of FM PLL loop filter; see Table 54.
(3) EMI suppression filter for DC, e.g. BLM21RK121SN1 (Murata).
(4) Capacitor connected only for TDA9898.
Fig 48. Application diagram of TDA9897 and TDA9898; ATV/DVB-T/DVB-C
TDA9897_TDA9898_4
Product data sheet
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91 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
tuner
AGC
output
4 MHz
reference
input
synthesizer
trap control
loop filter
VP = 5 V
100 nF
CTAGC
220 nF
CFREF
100 pF
470 Ω
L(3)
analog
ground
470 nF
100 nF
1
n.c.
SAW
SIF
X7550
47
37
36
2
35
3
34
4
33
2 V CVBS
output
5
32
BVS
31
AUD
48
22 pF
RLFSYN2 CLFSYN2
IF
3.3 kΩ
n.c.
synthesizer
downconverter
loop filter(1)
46
45
44
43
42
41
40
39
38
AGC input for DIF
(from channel decoder)
PORT2
1.5 nF
n.c.
SAW
VIF
M1980
NYQUIST SLOPE
6
TDA9897
7
30
8
29
9
28
1st DIF
CCTAGC
100 nF
CAF
(5)
470 nF
(4)
(5)
PORT1
10
27
11
26
digital LIF or
analog 2nd
sound IF
25
12
13
14
15
16
17
18
19
20
Cs
220 nF
Cpar
100 Ω
21
Cde-em
4.7 nF
22
FM PLL loop filter(2)
24
digital
ground
ADRSEL
100 Ω
Rs
VIF PLL
loop filter
23
external
FM input
SDA
100 Ω
SCL
001aai817
(1) Application depends on synthesizer frequency; see Table 57.
(2) Application of FM PLL loop filter; see Table 54.
(3) EMI suppression filter for DC, e.g. BLM21RK121SN1 (Murata).
(4) Optional.
(5) Value depends on application.
Fig 49. Application diagram of TDA9897 using SAW filter with Nyquist slope
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Product data sheet
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92 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
buffered TAGC
control voltage
output
CTAGC
4 MHz
22 kΩ
220 nF
22 pF
46
39
47
TDA9897
TDA9898
42
TDA9897
TDA9898
(1)
VAGC voltage
monitor output
(2)
12
TDA9897
TDA9898
(3)
VP
VP
4.7 kΩ
VP
4.7 kΩ
4.7 kΩ
PORT3
42
PORT1
12
TDA9897
TDA9898
TDA9897 35
TDA9898
(4a)
TDA9897
TDA9898
PORT2
(4b)
(4c)
VP
VP
VP
47 µF
47 µF
22 kΩ
TDA9897 33
TDA9898
68 Ω
(5a)
1 V CVBS (5b)
into 75 Ω
TDA9897 33
TDA9898
220 Ω
220 Ω
R ≥ 1 kΩ
R ≥ 1 kΩ
30
TDA9897
TDA9898
(7a)
43 Ω
1 V CVBS
into 75 Ω
27
R ≥ 1 kΩ
TDA9897
TDA9898
1st DIF
29
(7b)
R ≥ 1 kΩ
26
TDA9897
TDA9898
(6)
100 nF
digital LIF or
analog 2nd
sound IF
(8)
15
TDA9897
TDA9898
AFC
voltage
output
16
22 kΩ
17
560 Ω
BP
560 Ω
001aai818
(1) Optional 4 MHz quartz crystal oscillator.
(2) Alternative buffered TAGC voltage output.
(3) Alternative VIF AGC voltage monitor output.
(4) Optional use of (a) PORT1, (b) PORT2 or (c) PORT3.
(5) Optional CVBS buffer at setting (a) W6[1] = 0, 2 V CVBS or (b) W6[1] = 1, 1.7 V CVBS.
(6) Optional analog AFC voltage output.
(7) Optional output current increase at output (a) 1st DIF respectively (b) digital LIF.
(8) Optional radio application with external BP.
Fig 50. Optional applications
TDA9897_TDA9898_4
Product data sheet
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93 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
14. Test information
tuner
AGC
output
4 MHz
reference
input
+5 V
synthesizer
trap control
loop filter
PORT3
3.3 kΩ(2)
CTAGC
100 nF
CFREF
100 pF
2.7 kΩ(7)
22 kΩ(1)
470 Ω
4 MHz(3)
analog
ground
VP = 5 V
22 pF
100 nF
i.c.
synthesizer
downconverter
loop filter(4)
48
RLFSYN2 CLFSYN2
47
46
45
n.c.
1
37
36
2
35
3
34
22 pF
44
43
42
41
40
39
38
AGC input for DIF
(from channel decoder)
2.7 kΩ(7)
+5 V
n.c.
PORT2
1:1
SIF/DIF
1
5
2
4
1.5 nF
51 Ω
3
4
33
2 V CVBS
output
5
32
BVS
31
AUD
30
(b)
8
29
(a)
9
28
CIFAGC(6)
470 nF
1:1
VIF/SIF/DIF
1
5
6
TDA9897
TDA9898
51 Ω
2
4
3
7
1st DIF
CCTAGC
100 nF
1:1
VIF/SIF/DIF
1
CAF
5
470 nF
51 Ω
2
TOP potentiometer for
RSSI and positive modulation
PORT1
3
4
10
27
(b)
11
26
(a)
25
ADRSEL
22 kΩ
2.7 kΩ(7)
+5 V
12
13
14
15
16
17
18
19
21
20
MPP
Cpar
Cs
FM PLL
loop filter(5)
Rs
220 nF
100 Ω
VIF
loop filter
output to
sound BPF
FM input
from sound BPF
Cde-em
4.7 nF
22
23
digital LIF or
analog 2nd
sound IF
24
digital
ground
100 Ω
external
FM input
SDA
100 Ω
SCL
001aai819
(1) Switch-off resistor connected if external reference signal is not used.
(2) Switch-off resistor connected if crystal is not used.
(3) Use of crystal is optional.
(4) Application depends on synthesizer frequency; see Table 57.
(5) Application of FM PLL loop filter; see Table 54.
(6) Capacitor connected only for TDA9898.
(7) Pull-up resistor connected only for port function.
Fig 51. Test circuit of TDA9897 and TDA9898
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Product data sheet
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94 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
15. Package outline
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
37
24
ZE
e
E HE
A A2
(A 3)
A1
w M
θ
bp
pin 1 index
Lp
L
13
48
1
detail X
12
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
1.6
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
7.1
6.9
7.1
6.9
0.5
9.15
8.85
9.15
8.85
1
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
θ
0.95
0.55
7
o
0
0.95
0.55
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT313-2
136E05
MS-026
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-01-19
03-02-25
Fig 52. Package outline SOT313-2 (LQFP48)
TDA9897_TDA9898_4
Product data sheet
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95 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
HVQFN48: plastic thermal enhanced very thin quad flat package; no leads;
48 terminals; body 7 x 7 x 0.85 mm
A
B
D
SOT619-1
terminal 1
index area
A
E
A1
c
detail X
C
e1
1/2 e
e
24
y
y1 C
v M C A B
w M C
b
13
L
25
12
e
e2
Eh
1/2 e
1
36
terminal 1
index area
48
37
Dh
X
0
2.5
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
1
0.05
0.00
0.30
0.18
mm
5 mm
c
D (1)
Dh
E (1)
Eh
0.2
7.1
6.9
5.25
4.95
7.1
6.9
5.25
4.95
e
e1
5.5
0.5
e2
L
v
5.5
0.5
0.3
0.1
w
0.05
y
y1
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT619-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
01-08-08
02-10-18
Fig 53. Package outline SOT619-1 (HVQFN48)
TDA9897_TDA9898_4
Product data sheet
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96 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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97 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
16.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 54) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 58 and 59
Table 58.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 59.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 54.
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
98 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 54. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
17. Soldering of through-hole mount packages
17.1 Introduction to soldering through-hole mount packages
This text gives a very brief insight into wave, dip and manual soldering.
Wave soldering is the preferred method for mounting of through-hole mount IC packages
on a printed-circuit board.
17.2 Soldering by dipping or by solder wave
Driven by legislation and environmental forces the worldwide use of lead-free solder
pastes is increasing. Typical dwell time of the leads in the wave ranges from
3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb
or Pb-free respectively.
The total contact time of successive solder waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic
body must not exceed the specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling may be necessary immediately
after soldering to keep the temperature within the permissible limit.
17.3 Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the
seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is
less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is
between 300 °C and 400 °C, contact may be up to 5 seconds.
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
99 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
17.4 Package related soldering information
Table 60.
Suitability of through-hole mount IC packages for dipping and wave soldering
Package
Soldering method
Dipping
Wave
CPGA, HCPGA
-
suitable
DBS, DIP, HDIP, RDBS, SDIP, SIL
suitable
suitable[1]
PMFP[2]
-
not suitable
[1]
For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit
board.
[2]
For PMFP packages hot bar soldering or manual soldering is suitable.
18. Abbreviations
Table 61.
Abbreviations
Acronym
Description
ADC
Analog-to-Digital Converter
AFC
Automatic Frequency Control
AGC
Automatic Gain Control
ATV
Analog TV
BP
Band-Pass
CW
Continuous Wave
DAC
Digital-to-Analog Converter
DC
Direct Current
DIF
Digital Intermediate Frequency
DSP
Digital Signal Processor
DTV
Digital TV
DVB
Digital Video Broadcasting
DVB-C
Digital Video Broadcasting-Cable
DVB-T
Digital Video Broadcasting-Terrestrial
EMI
Electro-Magnetic Interference
ESD
ElectroStatic Discharge
FPLL
Frequency Phase-Locked Loop
I/O
Input/Output
IC
Integrated Circuit
IF
Intermediate Frequency
LCD
Liquid Crystal Display
LIF
Low Intermediate Frequency
MAD
Module Address
NB
NarrowBand
NICAM
Near Instantaneous Companded Audio Multiplex
PLL
Phase-Locked Loop
POR
Power-On Reset
QSS
Quasi Split Sound
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
100 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 61.
Abbreviations …continued
Acronym
Description
RIF
Radio Intermediate Frequency
RSSI
Received Signal Strength Indication
SAW
Surface Acoustic Wave
SC
Sound Carrier
SIF
Sound Intermediate Frequency
TAGC
Tuner Automatic Gain Control
TOP
TakeOver Point
VCO
Voltage-Controlled Oscillator
VIF
Vision Intermediate Frequency
VITS
Vertical Interval Test Signal
19. Revision history
Table 62.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
TDA9897_TDA9898_4
20090525
Product data sheet
-
TDA9897_TDA9898_3
Modifications:
•
Specification of features for V3 version
TDA9897_TDA9898_3
20080111
Product data sheet
-
TDA9897_TDA9898_2
TDA9897_TDA9898_2
20070411
Product data sheet
-
TDA9897_TDA9898_1
TDA9897_TDA9898_1
20060922
Product data sheet
-
-
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
101 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
20. Legal information
20.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
20.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
21. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
TDA9897_TDA9898_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 25 May 2009
102 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
22. Contents
1
2
2.1
2.2
2.3
2.4
3
4
5
6
7
7.1
7.2
8
8.1
8.2
8.3
8.3.1
8.3.2
8.3.3
8.4
8.5
8.6
8.7
8.7.1
8.7.2
8.8
8.9
8.10
9
9.1
9.2
9.2.1
9.2.2
10
11
12
12.1
12.2
13
14
15
16
16.1
16.2
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Analog TV processing. . . . . . . . . . . . . . . . . . . . 1
Digital TV processing . . . . . . . . . . . . . . . . . . . . 2
FM radio mode . . . . . . . . . . . . . . . . . . . . . . . . . 3
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Quick reference data . . . . . . . . . . . . . . . . . . . . . 3
Ordering information . . . . . . . . . . . . . . . . . . . . . 7
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pinning information . . . . . . . . . . . . . . . . . . . . . 12
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 13
Functional description . . . . . . . . . . . . . . . . . . 15
IF input switch. . . . . . . . . . . . . . . . . . . . . . . . . 15
VIF demodulator . . . . . . . . . . . . . . . . . . . . . . . 15
VIF AGC and tuner AGC. . . . . . . . . . . . . . . . . 15
Mode selection of VIF AGC . . . . . . . . . . . . . . 15
VIF AGC monitor . . . . . . . . . . . . . . . . . . . . . . 15
Tuner AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DIF/SIF FM and AM sound AGC . . . . . . . . . . 16
Frequency phase-locked loop for VIF . . . . . . . 16
DIF/SIF converter stage . . . . . . . . . . . . . . . . . 17
Mono sound demodulator . . . . . . . . . . . . . . . . 17
FM PLL narrowband demodulation. . . . . . . . . 17
AM sound demodulation . . . . . . . . . . . . . . . . . 17
Audio amplifier . . . . . . . . . . . . . . . . . . . . . . . . 17
Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
I2C-bus transceiver and slave address . . . . . . 18
2
I C-bus control . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read format . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Write format . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Subaddress. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Description of data bytes . . . . . . . . . . . . . . . . 24
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 39
Thermal characteristics. . . . . . . . . . . . . . . . . . 39
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 40
Analog TV signal processing . . . . . . . . . . . . . 40
Digital TV signal processing . . . . . . . . . . . . . . 78
Application information. . . . . . . . . . . . . . . . . . 90
Test information . . . . . . . . . . . . . . . . . . . . . . . . 94
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 95
Soldering of SMD packages . . . . . . . . . . . . . . 97
Introduction to soldering . . . . . . . . . . . . . . . . . 97
Wave and reflow soldering . . . . . . . . . . . . . . . 97
16.3
16.4
17
17.1
17.2
17.3
17.4
18
19
20
20.1
20.2
20.3
20.4
21
22
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 97
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 98
Soldering of through-hole mount packages . 99
Introduction to soldering through-hole mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Soldering by dipping or by solder wave . . . . . 99
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 99
Package related soldering information . . . . . 100
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 100
Revision history . . . . . . . . . . . . . . . . . . . . . . 101
Legal information . . . . . . . . . . . . . . . . . . . . . 102
Data sheet status . . . . . . . . . . . . . . . . . . . . . 102
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . 102
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 102
Contact information . . . . . . . . . . . . . . . . . . . 102
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 25 May 2009
Document identifier: TDA9897_TDA9898_4
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