AND8354/D Designing a HighEfficiency, 300-W, Wide Mains Interleaved PFC Prepared by: Joel Turchi ON Semiconductor http://onsemi.com APPLICATION NOTE Overview as long as they share the same control voltage (to do so, the control pin of the two circuits are shorted). The demagnetization time that only depends on the conduction time and on the line and output voltages is then the same in both branches as well Application note AND8355 presents the main characteristics and merits of an interleaved PFC. This paper proposes the key steps to designing an interleaved PFC driven by two NCP1601. The process is practically illustrated on a 300−W, universal mains application: • Maximum output power: 300 W • Input voltage range: from 90 Vrms to 265 Vrms • Regulation output voltage: 390 V • Clamp frequency: 120 kHz This solution lies on the Frequency Clamped Critical conduction mode (FCCrM) that limits the switching frequency spread and by this means, minimizes the switching losses. For an optimal efficiency over the whole power range, the solution also implements the frequency fold−back function to further reduce the light load losses by lowering the switching frequency. AND8356 reports the performance of this solution. ǒ I in(branch1) I in(branch2) + L branch2 L branch1 Where: • Iin(branch1) and Iin(branch2) are the averaged input current drawn by phase 1 and phase 2 respectively • Lbranch1 and Lbranch2 are the inductance values of phase 1 and phase 2 respectively One drawback of the Critical conduction Mode (CrM) circuits is that the switching frequency tends to become very high at light load (up to hundreds of kHz depending on the PFC design). These characteristics lead to high switching losses, possible noise issues and to the need for relatively big inductors to limit the switching frequency higher levels. The NCP1601 is an 8−pin PFC controller designed to operate in Frequency Clamped Critical conduction (FCCrM). FCCrM clamps the switching frequency to overcome the above difficulty. It is worth noting that FCCrM does not simply clamp the switching frequency but in addition, it modulates the on−time to compensate the possible dead−times. As a matter of fact, it automatically transitions from the CrM and DCM (and vice versa) modes in a very clean manner: the input current keeps properly shaped and there is no discontinuity in the power transfer. One NCP1601 per branch is implemented to drive each phase in FCCrM. As voltage mode controllers, the two circuits force the same MOSFET on−time in both branches December, 2008 − Rev. 0 Ǔ V in . V out * V in Hence if we neglect the tolerance in the timing circuitry that for each circuit, adjusts the on−time in response to the control signal, the current cycle duration is the same in the two branches even if their respective coils do not have the same inductance. Finally, the only source of current unbalancing is the inductor tolerance. One can easily show that the current sharing is governed by the following equation: Introduction © Semiconductor Components Industries, LLC, 2008 t demag + t on @ Practically, if the inductance tolerance is ±5%, the maximum deviation between the current of the branches is 10%. NCP1601 Synchronization The NCP1601 oscillator consists of an external capacitor, the voltage of which swings between the 3.5−V lower threshold and the 5−V upper one. The charge and discharge phases are controlled by internal current sources (about 50 mA are permanently sourced by the pin leading to a 50 mA charge current, 100 mA are sunk for the discharge phase only to obtain a 50−mA discharge current). Each time, the capacitor voltage goes below 3.5 V and hence enters a new charge phase, the circuit sets the PWM latch that keeps set until a new drive turn high occurs. 1 Publication Order Number: AND8354/D AND8354/D 50 μA OSC pin + 100 μA Cosc − 5.0 V / 3.5 V S Q CLOCK Q R DRV Figure 1. NCP1601 Clocks Generation Hence, there are two cases: • The PFC stage operates in fixed frequency. When the oscillator voltage goes below the 3.5−V low threshold, a clock is generated that immediately induces the next drive pulse. The switching frequency is the oscillator one (refer to Figure 2). • The PFC stage operates in critical conduction mode. In this condition, the switching frequency is lower than the oscillator one. When the oscillator voltage goes below 3.5 V, a clock is generated but the driver cannot turn high until the core is reset (refer to Figure 3). 5V Vosc 3.5 V Dead−time ZCD IL(coil) current) CLOCK Figure 2. Generation of the Clock Signals − Fixed Frequency Figure 3. Generation of the Clock Signals − Critical Conduction Mode Synchronization of the Two Stages in the Interleaved Application The oscillator capacitors (C14 for circuit of branch 1, C15 for circuit of branch 2) are then charged to about 6 V. As this voltage exceeds the upper oscillator threshold (5 V), the two circuits enter the discharge phase. Capacitors C14 and C15 are discharged by the internal current source (about 50 mA) and the external resistors R26 and R27 respectively. Resistors R28 and R29 can also speed−up the discharge or at the contrary slow it down according to the VFR voltage. VFR is the voltage that controls the frequency fold−back at light load. As explained in the “frequency fold−back” section, this voltage is near zero at full load (and hence tends to shorten the discharge phase) and is increased at light load (to extend the discharge phase and hence reduce the switching frequency). As portrayed by Figure 4, the two NCP1601 circuits are synchronized to the “DRV2” signal (driver of phase 2). One could have chosen “DRV1” as the triggering signal but in this case, the Ct circuitry for which the two branches are not fully symmetrical, should have to be also reversed. When “DRV2” turns high, the (C20, R31) network generates a positive voltage pulse across R31. The D14 ZENER diode clamps this pulse and guarantees the full C20 discharge when DRV2 is in low state. If C20 is large enough to properly bias the ZENER diode (*), a (0 V, 6.8 V) calibrated pulse is obtained across D14. This signal is applied to the oscillator pin of the two controllers through a diode. * Like proposed here, use “DRV2” that is the driver pin signal, rather than the gate signal which dV/dt may be much lower due the MOSFET capacitances. With the connection to the drive pin, C20 = 2.2 nF should give good results. http://onsemi.com 2 AND8354/D Once a pulse has occurred across the D14 ZENER diode, the next clock for branch 1 is generated when the signal SYNC1 (voltage across C14) drops below 3.5 V that is, after a delay τ that meets the following equation: V oscL + ǒ ǒ V oscH * R osc1 @ Ǔ V FR ) (R osc1 @ I DISCH) R 28 Ǔ @e Where, • VoscH represents the level at which the oscillator pin is charged by the DRV2 pulse • VoscL represents the oscillator low threshold (3.5 V) • Rosc1 is R26 // R28 Hence: t + −R osc1 @ C osc1 ȡV @ Inȧ ȧ ȢV ǒ Ǔ V −t ) R osc1 @ FR * (R osc1 @ I DISCH) R 28 R osc1 @ C osc1 • IDISCH is the NCP1601 internal discharge current (50 mA) • Cosc1 is the oscillator capacitor for the NCP1601 of branch 1 ǒR * ǒR V Ǔ ) (R Ǔ ) (R oscL * FR osc1 @ R 28 oscH FR osc1 @ R 28 V ȣ ȧ ȧ ) Ȥ osc1 @ I DISCH) osc1 @ I DISCH Replacing Rosc1, VoscL, VoscH, R28 and IDISCH by their value, it comes: V ȡ ȡ1 * 16.3 ȣȣ @ȧ0.43 * Inȧ ȧ V ȧ Ȣ1 * 25.0ȤȤ Ȣ FR t ^ 23500 @ C osc1 FR Finally: • At full load, VFR is nearly zero and: t(full_load) ≅ 10100 ⋅ Cosc1 • At light load, VFR is nearly VCC that is 15 V and: t(light_load) ≅ 48000 ⋅ Cosc1 1 U1 NCP1601 8 2 7 3 6 4 5 VCC DRV1 SYNC1 C14 470pF 1 U2 NCP1601 8 2 7 3 6 4 5 D13 1N4148 R26 33k R28 82k VFR VCC DRV2 D12 1N4148 SYNC2 C15 470pF R27 100k R30 100 C20 2. 2nF D14 6.8V R31 1k DRV2 R29 150k VFR Figure 4. Synchronization Circuitry Similarly, one can compute the delay τ2 between the DRV2 turn on and the next clock for branch 2. This delay must meet the following equation: V oscL + ǒ ǒ V oscH * R osc2 @ Ǔ V FR ) (R osc2 @ I DISCH) R 28 Ǔ @e http://onsemi.com 3 ǒ Ǔ V −t ) R osc2 @ FR * (R osc2 @ I DISCH) R 28 R osc2 @ C osc2 AND8354/D Where, • Rosc2 is R27 // R29 (60 kW) • Cosc2 is the oscillator capacitor for the branch 2 NCP1601 Hence: t 2 + −R osc2 @ C osc2 ȡV @ Inȧ ȧ ȢV ǒR * ǒR V Ǔ ) (R Ǔ ) (R oscL * FR osc2 @ R 29 oscH FR osc2 @ R 29 V ȣ ȧ ȧ ) Ȥ osc2 @ I DISCH) osc2 @ I DISCH Replacing Rosc1, VoscL, VoscH, R28 and IDISCH by their value, it comes: V ȡ ȡ1 * 16.25 ȣȣ @ȧ0.325 * Inȧ ȧ V ȧ 1 * Ȣ Ȥ Ȣ 22.50 Ȥ FR t 2 ^ 60000 @ C osc2 FR Finally: At full load, VFR is nearly zero and: At light load, t 2 ^ 109750 @ 470 @ 10 −12 ^ 51.58 ms t 2(full_load) ^ 19500 @ C osc2 ^ 1.93 @ t (full_load) This means that the minimum frequency that can be obtained is 20 kHz per branch with VCC = 15 V. The two following figures illustrate the above analysis. Figure 5 is obtained in a moderate load condition. The system operates in fixed frequency. The frequency is in the range of 50 kHz per branch. As wished for out−of−phase operation, (t2 ≅ 2 ⋅ t). Figure 6 is obtained at heavy load. The system operates in critical conduction mode. The frequency is in the range of 110 kHz per branch. Again an out−of−phase operation is obtained with the help of the “phase shift compensation circuitry” (See “maintaining a 180° Phase Shift” section). At light load, VFR is nearly VCC that is 15 V and: t 2(light_load) ^ 109750 @ C osc2 ^ 2.28 @ t (light_load) We can note that if (Cosc1 = Cosc2), the chosen resistors enable to keep τ2 in the range of (2.τ) even when the frequency reduces (frequency fold−back), as required to obtain an out−of−phase operation. In our case, we select (Cosc1 = Cosc2 = 470 pF) to obtain: At full load, t 2 ^ 19500 @ 470 @ 10 −12 ^ 9.16 ms which leads to 110 kHz per branch SYNC2 2 t DRV2 DRV2 SYNC1 t DRV1 DRV1 Figure 5. Synchronization in Fixed Frequency Operation http://onsemi.com 4 AND8354/D SYNC2 DRV2 DRV2 SYNC1 DRV1 DRV1 Figure 6. Synchronization in Critical Conduction Mode Operation Frequency Fold−back integrated to form a dc voltage (VFR) representative of the MOSFETs loading: • VFR is high when the system is in light load and/or at high line • VFR is low when the system is in heavy load, low line. The voltage is applied to the oscillator pin of the two NCP1601. The injection is performed through resistor R28 for branch 1 and R29 for branch 2. These resistors have values (82 kW and 150 kW, respectively) that enable to maintain the out−of−phase operation in light load (see the “synchronization of the two stages in the interleaved application” section). A very simple circuitry is implemented that lowers the switching frequency when the duty−cycle reduces. A npn transistor is operated to be on when any of the two drives is high. In low line, full load when there is always one of the two drives in high state, the npn transistor is permanently on and its collector voltage is low. On the contrary, the duty−cycle reduces in light load and there are large parts of the interleaved PFC switching periods when the two drives are low. During these intervals of time, the npn transistor is off and its collector rises to VCC. These VCC pulses are SYNC2 SYNC1 VCC DRV1 DRV2 R32 10k R35 2.2k R33 10k R34 2.2k R28 82k R36 10k Q3 2N2222 C19 10nF Figure 7. Circuitry for Frequency Fold−back http://onsemi.com 5 VFR R29 150k AND8354/D Dimensioning the Power Components And: Basically, Two 150−W FCCrM PFC stages are to be designed. This chapter will not detail the dimensioning of the power components in very deep details since their computation is traditional. However, the main selection criteria and equations are reminded. (I L(rms)) MAX + Inductor Selection In CrM and in FCCrM (assuming CrM operation at low line, full load), the (maximum) peak and rms inductor currents within one branch are: 2 Ǹ2 @ (I L(pk)) MAX + ǒ Pout(max) 2 h @ (V in(rms)) LL Ǔ + 2 Ǹ2 @ 150 ^ 5.1 A 0.92 @ 90 h @ (V in(rms)) LL 2 @ Lw Ǹ2 @ V @ out ǒ ǒ Ǔ Vout * (V in(rms)) LL Ǹ2 Ǔ Pout(max) 2 (I L(pk)) MAX Ǹ6 ^ 5.1 + 2.1 A Ǹ6 Where: • Pout(max) is the maximum level of the total output power (300 W) • (Vin(rms))LL is the lowest line rms input voltage (90 V) • h is the PFC stage efficiency (assumed to be 92% to have some margin) As aforementioned, the frequency clamp for the two branches is set to about 110 kHz. The inductor must be large enough so that Critical conduction Mode is obtained at low line, full load where the conditions are the most severe. This constraint leads to the equation below (where fsw(max) is the 110−kHz clamp frequency): + @ f sw(max) ǒ Ǔ 0.92 @ 90 2 @ 390 * 90 Ǹ 2 Ǹ2 @ 390 @ 150 @ 110 k ^ 150 mH Finally, a 150 mH / 6 Apk / 2.5 Arms coil was selected. Power Semiconductors The bridge diode should be selected based on the peak current rating and the power dissipation given by: Assuming a 1−V forward voltage per diode (Vf = 1 V), the bridge approximately dissipates 6.5 W. For each branch, the MOSFET is selected based on the peak voltage stress (Vout(max) + margin) and on the rms current flowing through it (IM(rms)): P out(max) Vf V 4 Ǹ2 P bridge + p ^ 1.8 f 300 ^ 6.5 V f h 90 0.92 (V in(rms)) LL 2@ I M(rms) + ǒ P out(max) 2 Ǔ Ǹ3 @ h @ (V in(rms)) LL @ Ǹ 1* 8 @ Ǹ2 @ (V in(rms)) LL 3 @ p @ V out + 2 @ 150 Ǹ3 @ 0.92 @ 90 Ǹ1 * 38 @@ pǸ2@@38590 ^ 1.8 A case temperature (of the input bridge and MOSFETs applied to it) to about 50° compared to the ambient temperature. Interleaved PFC requires two boost diodes (one per branch). No reverse recovery issues to worry about. Simply, they must meet the correct voltage rating (Vout(max) + margin) and exhibit a low forward voltage drop. Supposing a perfect current sharing, the average diode current is the half of the load one Using a 600−V, 0.4−W FET (SPP11N60), will give conduction losses of (assuming that RDS(on) increases by 80% due to temperature effects): P cond + I M(rms) 2 @ R DS(on) + 1.8 2 @ 0.4 @ 1.8 ^ 2.3 W This computation is valid for one branch. As there are two phases to consider, the total MOSFETs conduction losses are actually twice (4.6 W). Switching losses are extremely hard to predict. They are not computed here. As a rule of the thumb, it is considered that the switching losses are in the same range as the conduction ones. The input bridge that rectifies the line voltage and the MOSFETs of the two branches share the same heat−sink. Based on above computations, the total power to be dissipated is in the range of: (6.5 + 4.6 + 4.6 ≅ 16 W). A 2.9−°C/W heat−sink (ref. 437479 from AAVID THERMALLOY) is implemented. It limits the rise of the ǒ I D1(avg) + I D2(avg) + I D(tot) 2 avg Ǔ I P out + LOAD + ^ 0.39 A 2 2 @ V out So, the losses are about (ILOAD ⋅ Vf / 2 ) per diode, i.e., less than 500 mW per diode using MUR550 rectifiers. For each phase, the peak current seen by the diode will be the same as the corresponding inductor peak current. Two axial MUR550 are selected. http://onsemi.com 6 AND8354/D Bulk Capacitor Design The output voltage ripple is given by: The output capacitor is generally designed considering 3 factors: 1. The maximum permissible low frequency ripple of the output voltage. The input current and voltage being both sinusoidal, PFC stages deliver a squared sinusoidal power that matches the load power demand in average only. As a consequence, the output voltage exhibits a low frequency ripple (e.g., 100 Hz ripple in Europe or 120 Hz in USA) that is inherent to the PFC function 2. The rms magnitude of the current flowing through the bulk capacitor. Based on this computation, one must estimate the maximal permissible ESR not to cause an excessive heating. 3. The hold−up time. It can be specified that the power supply must provide the full power for a short mains interruption that is the so called hold−up time. The hold−up time is generally in the range of 10 or 20 ms. DV out(p−p) + P out 2p @ f line @ C out @ V out The capacitor rms current is given by (assuming a resistive load): I C(rms) + Ǹ ǒ Ǔ P out 16 @ Ǹ2 @ P out 2 * V out 9 @ p @ (V in(rms)) LL @ V out @ h 2 2 Finally the following equation expresses the hold−up time: t hold−up + C out @ (V out 2 * V out(min) 2 2 @ P out Where Vout(min) is the minimal bulk voltage necessary to the downstream converter to keep properly feeding the load. The hold−time being not considered here, a 100−mF capacitor was chosen to satisfy the other above conditions. The peak−peak ripple is 25 V (±3% of Vout) and the rms current is 1.4 A. Regulation Circuitry C8 1nF 1 C10 100nF VCONTROL C11 100nF R21 820k R20 820k U1 NCP1601 8 2 7 3 6 4 5 C9 1nF R23 820k 1 R24 270k VCC DRV1 SYNC1 R22 820k U2 NCP1601 8 2 7 3 6 4 5 VBULK R25 270k VCC DRV2 SYNC2 Figure 8. Regulation Circuitry A global 200−nF capacitor is generally enough. Type−2 compensation can be implemented for better dynamic performance if necessary. The NCP1601 is designed to receive a feedback current that is compared to a 200−mA reference current. For each NCP1601, two or more (for safety reasons) resistors are to be connected between the output voltage rail and the feedback pin (pin1). The resistance must be selected so that The two NCP1601 must force the same MOSFET on−time. To do so, the two IC’s must have the same control voltage. Practically, pin2 of the NCP1601 that controls the first phase is connected to pin2 of the NCP1601 that drives the second phase. For each device, a 100−nF compensation capacitor should be placed between pin2 and ground. Short connections are recommended to optimize the noise immunity. http://onsemi.com 7 AND8354/D pin1 absorbs 200 mA when the output voltage is at the desired level: R FB + In our application, we choose three resistors in series (820 kW + 820 kW + 270 kW) for a global 1910 kW resistance. For each circuit, it is recommended to add a 1−nF capacitor between pin1 and ground to filter the possible surrounding noise. V out(nom) * V pin1 200 @ 10 −6 Where: • Vout(nom) is the desired output voltage • Vpin1 is the pin1 voltage (about 3 V) Ct Capacitor For each controller, the capacitor that is applied to pin3 adjusts the maximum on−time and hence, the maximal power that the branch can deliver. In our case: R FB + 390 * 3−6 + 1.935 MW 200 @ 10 U1 NC P 1 6 0 1 R16 3.9k DRV1 C12 1.2nF R18 100 1 8 VCC 2 7 DRV1 3 6 4 5 SYNC1 DRV2 D11 1N4148 R39 2.2k U2 NC P 1 6 0 1 R17 4.7k R38 2.2k C13 1.2nF C21 470pF R19 100 Circuitry for compensation of possible phase shift 1 8 VCC 2 7 DRV2 3 6 4 5 SYNC2 Figure 9. Timing Capacitor Circuitry Let’s assume that the resistors that are used for the offset can be re−used in any design, the Ct capacitor must now be computed as a function of the power to be delivered. To do so, the maximum available on−time should be computed for branch 1 that has the larger offset. As the normal pin3 swing is 1 V and since the pin3 charge current is 100 mA: In the application, it can be noted that a portion of the drive signal offsets the pin 3 voltage. This offset is to reduce the minimum on−time at light load and to help maintain the 180° phase shift. To the light of Figure 9, we can note that: • Branch 1 has a larger offset than branch 2: − The phase 1 offset is: ǒ Ǔ R 18 100 @ V CC + @ V CC 3900 ) 100 R 18 ) R 16 that is, 375.0 mV with VCC = 15 V. The phase 2 offset is: ǒ t on(max) + C pin3 @ 1 V * 375 mV + 6250 @ C pin3 100 @ 10 −6 In our application, we need to provide about 160 W (input) per branch. The following equation gives the maximum power that can be delivered as a function of the maximum on−time (CrM operation): Ǔ R 19 100 @ V CC + @ V CC 4700 ) 100 R 19 ) R 17 that is, 312.5 mV with VCC = 15 V. • Branch 2 has another source of offset that is provided by the “circuitry for compensation of possible phase shift”. The small imbalance in the offsets is explained in the “Maintaining a 180° Phase Shift” section. (P in(avg)) MAX + (V in(rms)) LL 2 [email protected] @ t on(max) From the above equations, we can deduce: C pin3 + http://onsemi.com 8 2 @ L @ (P in(avg)) MAX 6250 @ (V in(rms)) LL 2 AND8354/D In our application: offset ^ 10 −6 @ 160 ^ 948 pF C pin3 + 2 @ 150 @ 6250 @ 90 2 ǒ t − 100 @ V CC @ 1 * e R38ø[email protected] R 38 ) R 39 Ǔ 1−nF is the closed standard capacitor. However, for a 20% necessary margin, a 1.2−nF capacitor is selected and implemented in the two branches. From the above equation, we can deduce the capacitor that exactly compensates the difference in the phase 1 and phase 2 Ct pin offset (62.5 mV) at the end of the 1.6 ms: Maintaining a 1805 Phase Shift C 21 + The synchronization circuitry tends to force a delay between the two branches. The phase shift is perfectly correct in fixed frequency mode but the operation can be altered when the circuit operates in critical conduction mode. For instance, some distortion can result from a protection triggering that would turn off the MOSFETs of the two branches simultaneously. Also, perturbations like discrepancies in the actual on−time, can lead to a loss of the 180° phase shift and even to an in−phase operation that is also a stable operation point! That is why, the synchronization is not sufficient by itself. The difficulty is overcome by controlling the maximum overlap, that is, the maximum time for each the two drivers must be on simultaneously. More specifically, the drive that synchronizes the system (DRV2 in our application) is truncated when the overlap duration is excessive. We can estimate the maximum overlap time by calculating the on−time and demagnetization time at low line, full load (top of the sinusoid). For any of the two branches, the MOSFET conduction time and the demagnetization duration can be expressed as follows: t on + (R 38||R 39) @ In 1 * R [email protected] Ǔ ^ 7.2 nF VCC and Drivers The VCC voltage biases the two controllers but also the frequency fold−back circuitry. The VCC level slightly influences: • The voltage available to drive the MOSFET gate (as in any PFC stage) • The frequency fold−back circuitry • The Ct pin offsets The VCC voltage must remain below 18 V. The design is optimized for (VCC = 15 V). The VCC voltage should be set preferably in this range. A lower VCC voltage would mainly result in a smaller reduction of the switching frequency in light load (refer to the frequency fold−back section). As there are two circuits to feed, it is recommended to locally decouple the VCC pin of each of them. This is the role of the C19 and C20 ceramic capacitors of Figure 13. In any CrM or FCCrM PFC stage, the MOSFET can be turned on in a relatively slow manner because there is no current stress. On the other hand, the opening must be fast to limit the switching losses. As shown in the application schematic of Figure 13, pnp transistors (“Q1” for phase 1 and “Q2” for phase 2) speed−up the turn off of the MOSFETs. V in L @ I L(pk) V out * V in Hence, if we ignore the short dead−time due the valley switching, the duration of a current cycle (that is the switching period) is: t sw + t on ) t demag + 62.5 mV@(R38)R39) In practice, it appears that a 470−pF capacitor that leads to a more abrupt reaction to overlaps, is also a good (conservative) choice. A 470−pF capacitor is then implemented. L @ I L(pk) t demag + ǒ −1.6 ms L @ I L(pk) @ V out Current Sensing Figure 10 portrays the NCP1601 current sensing method. V in @ (V out * V in) The maximum overlap is the difference between the on−time of one driver and half the period when the other driver is supposed to turn high (out−of−phase operation). Hence: t overlap(max) + t on * In our application, t overlap(max) + ǒ L @ I L(pk) V out t sw + 1* 2 V in 2 @ (V out * V in) ǒ Ǔ Ǔ 150 m @ 5.1 390 * 250 ^ 1.6 ms 125 2 @ (390 * 125) The circuit for compensation of possible phase shift, charges the capacitor C21 of Figure 9 when the two drives are on and the obtained ramp is added to the timing ramp of DRV2, resulting on the following additional offset on the (phase 2) Ct pin: Figure 10. Negative Sensing A current sense resistor RSENSE is placed in the return path so that the coil current that flows through it generates a negative voltage. A resistor ROCP is inserted between the http://onsemi.com 9 AND8354/D We select RSENSE to obtain an optimal compromise between noise immunity and losses. A good choice is generally the value that leads to about 0.25% efficiency losses in it: RSENSE negative terminal and the CS pin (current sense pin – pin 4). The NCP1601 is designed to maintain 0 V on the CS pin. To do so, pin4 sources the current ICS that together with the external resistor ROCP forms an offset voltage that cancels the RSENSE negative voltage. More specifically: R SENSE @ I in(rms) 2 + 0.25% @ P in(avg) If one neglects the high frequency ripple of the input current, one can deduce the following RSENSE expression: * (R SENSE @ I L) ) (R OCP @ I CS) + 0 The precedent equation leads to: R SENSE + 0.25% @ R I CS + SENSE @ I L R OCP P in(avg) V in(rms) 2 I in(rms) P in(avg) + 0.25% @ 2 In our case, Hence, pin4 sources the ICS signal that is proportional to the inductor current. When ICS exceeds the 200−mA internal reference, the circuit detects an over−current and disables the drive. The over−current can then be programmed using two elements ROCP and RSENSE. R SENSE + 0.25% @ 90 ^ 63 mW 320 2 In practice, (RSENSE = 75 mW) is chosen. We have now to select ROCP to set the proper current limit. Permissible Current – ROCP Selection Our interleaved circuit monitors the total current. From the formulae given in AND8355, we can deduce that the maximum total current is: (I L(tot)) MAX + 2 Ǹ2 @ (I L(tot)) MAX + 2 Ǹ2 @ P in(avg) (V in(rms)) LL P in(avg) (V in(rms)) LL ȡ ȧ Ȣ @ 1* @ ǒ ǒ V out ȣ ǓǓȧ Ȥ 4 @ V out * ǒǸ2 @ (V in(rms)) LL 1* Ǔ V out Ǹ 4 2 @ (V in(rms)) LL if (V in(rms)) LL v V out 2 Ǹ2 if (V in(rms)) LL v V out 2 Ǹ2 In our case, V in(rms)LL + 90 v Hence, (I L(tot)) MAX + 2 Ǹ2 @ 326 @ 90 ǒ Important Remark: V out + 385 ^ 136. 2 Ǹ2 2 Ǹ2 1* 390 Ǔ 4 @ ǒ390 * (Ǹ2 @ 90)Ǔ It is recommended to clamp the RSENSE negative voltage to prevent excessive levels during the start−up and possible overload sequences (when huge in−rush currents can take place). Otherwise, the circuit may not be able to properly control the MOSFET during such stressing transients. In the application schematic, a 1N5406 (D12) plays the role of the protecting diode. Actually, this diode does not need to be a high voltage one. It only must be able to sustain the in−rush current and its forward voltage must high enough so that the RSENSE voltage is not clamped until the current largely exceeds its permissible level in normal operation. Otherwise, the clamping diode would prevent the RSENSE voltage from being high enough to trigger the over−current protection. ^ 6.4 A In practice, the OCP protection should not trigger during “normal” transients. Hence, it is recommended to place the limit about 50% higher, that is 10 A in our case. R OCP + R SENSE @ (I L(tot)) MAX I OCP + 75 m @ 10 + 3.75 kW 200 m In practice, one (Rocp = 3.9 kW) resistor is chosen for each branch. http://onsemi.com 10 AND8354/D Zero Current Detection IL1 ID1 1 Ac line 8 2 7 3 Iin(t) 4 NCP1601 Vin(t) IL(tot) 6 5 IL2 EMI Filter ID2 1 8 2 7 3 4 RSENSE NCP1601 ID(tot) Vout 6 5 Cbulk LOAD Figure 11. The Total Current is Sensed − An auxiliary winding is coupled to the PFC inductor to provide a positive voltage when the MOSFET is on. − The network (C6, R2) generates a positive pulse whenever the auxiliary voltage rises up and in particular, at the end of a demagnetization phase. This positive pulse is clamped (and calibrated) by a 5−V ZENER diode (D7). − A diode D5 is to eliminate the negative pulses that take place across R2 (when the circuit enters the demagnetization phase for instance) and that may influence the over−current protection. Another 1 kW (R6) reduces the impedance at the cathode of the diode and ensures a proper biasing of D5. − The voltage obtained across R6 is then applied to the current sense pin to turn it positive. The R4x resistor limits the current injected to pin4. How to dimension these elements in a general manner? 1. D5, D7, R2, R4x and R6 could keep the same value in any applications 2. C6 is to be adapted to the dV/dt across the auxiliary winding. This dV/dt depends on the transition speed, on the input and output voltages and on the turn ratio. The turn ratio (Naux / Nprim) is generally in the range of 0.1. C6 must be high enough so that the D7 ZENER diode trips when the core reset occurs. This circuitry is to be applied to the two phases. The NCP1601 is designed to detect the core reset completion by directly sensing the current. Practically, in a conventional 1−phase PFC stage, the circuit monitors the coil current and when it is nearly zero, a ZCD signal is internally generated. This solution is not valid anymore for an interleaved PFC stage. This is because the current sense resistor that is placed in the current return path, sees the total current absorbed by the two branches (see Figure 11). Hence, the voltage across RSENSE is not representative of the current of any specific phase but of the total one. Therefore, this voltage cannot detect the core reset of a branch. However, the RSENSE voltage is utilized as portrayed by Figure 12. To explain how it works, we have to consider the two following cases: 1. There is no current across RSENSE. That simply means that there is no current flowing through both the two branches. No negative voltage being applied to its current sense pin, each NCP1601 naturally detects the core reset and can turn on the MOSFET of the branch it drives as soon as allowed by the synchronization signal. 2. A negative voltage biases the NCP1601 current sense pin as it occurs when one at least of the two branches conveys some current. However, since both circuits are identically biased, both phases are prevented from initiating a new cycle. A circuitry is then added to cancel the RSENSE biasing of the current sense pin when the core reset occurs. As portrayed by Figure 12, this circuit operates as follows: http://onsemi.com 11 AND8354/D Vbulk Vin 1 GateDrive 10 C6 100pF R2 1k 12 D7 5V D5 1N4148 13 2 U1 NCP1601 R4x 10k R6 1k 7 ROCP 1 8 2 7 3 6 4 5 RSENSE to Current Sense of the other branch Figure 12. Demagnetization Circuit (one per branch is required) Conclusions method, you can refer to AND8356. This application note shows that the efficiency can remain as high as 95% at 90 Vrms from 20% to 100% of the load. We can also refer to AND8355 for more general information regarding interleaved PFC stages. This paper particularly focuses on the main characteristics and merits of such a solution. This application note proposes the key equations and design criteria to build an efficient 2−NCP1601 interleaved PFC stage. The practical implementation of a 300−W, wide mains application illustrates the process. As the proposed approach is systematic and as a large part of the design can be “copied−pasted”, the 2−NCP1601 solution can be easily applied to other applications. For information on the performance of a 300−W interleaved PFC designed according to the proposed http://onsemi.com 12 AND8354/D D3 LP RI M = 150u LS E C = 1.5u D2 X2 R13 1N4148 2.2 D10 Vaux2 U3 KBU6K C3 IN − C2 680nF EMI filter Type = Y1 C5 4.7nF 4.7nF CM1 L1 150mH C4 Type = Y1 Type = X2 N M UR550 M2 S P P 11N60 2N2907 DRV 2 D1 M UR550 V bulk 1N4148 D9 R12 2.2 C6 100pF D7 5V Ci r cui tr y for zer o current detection (br a nc h 1 ) R2 1k D5 1N4148 R6 1k Current s ens ing R1 75m/ 3W R4 10k 3.9k R8 C22 S P P 11N60 100mF / 450V M1 R20 R24 820k 270k Q1 10k R10 R14 R21 C8 47 2N2907 1nF 820k DRV 1 C16 C10 V c ont r ol NCP 1601 vcc 100nF R16 100nF 3. 9k 1.2nF DRV 1 D13 C12 DRV 1 U1 100 R18 SYNC1 1N4148 Vaux2 C7 100pF D8 5V Earth R7 1k 90−265VAC R26 33k R28 82k C14 470pF Circuitry for zero current detection (br a nc h 2 ) D4 1N5406 C1 680nF L Type = X2 680nF R15 10k Q2 R11 47 X1 LP RI M = 150u LS E C = 1.5u + 1N5406 R22 R25 820k 270k V bulk Vfr R3 1k C9 1nF D6 1N4148 R5 10k R17 4. 7k DRV 2 R23 820k vcc C11 100nF V c ont r ol 100nF C13 R19 1. 2nF Circuitry for compensation of possible phase shift C20 DRV 2 R31 1k C18 100mF/ 25V D12 DRV 2 1N4148 SYNC2 U2 R27 R29 100k 150k NCP 1601 C15 470pF 3.9k 2.2nF C17 100 R9 R37 10 V aux R30 100 D14 6. 8V Vfr vcc DRV 2 D11 R39 R38 1N4148 2.2k 2. 2k DRV 1 C21 470pF DRV 1 DRV 2 R32 10k R33 10k R35 2.2k R34 R36 10k Q3 2N2222 C19 10nF 2.2k Circ uitry for Frequenc y Foldbac k Figure 13. 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