AND9364/D How to Select the Frequency Foldback Product Option When Designing a Compact, High-Efficiency PFC Stage Using the NCP1602 APPLICATION NOTE This paper describes how to select one of the frequency foldback product options out of the A, B, C, D, E, F, G, H, I list in order to design a Discontinuous Conduction Mode PFC stage driven by the NCP1602. Introduction Housed in a TSOP−6 package, the NCP1602 is designed to optimize the efficiency of your PFC stage throughout the load range. Incorporating protection features for rugged operation, it is ideal in systems where cost−effectiveness, reliability, low stand−by power and high efficiency are key requirements: • Valley Synchronized Frequency Fold−back (VSFF): The circuit operates in Critical conduction Mode (CrM) when the VCTRL pin voltage is above a preset level. When the VCTRL pin voltage goes lower than the preset level, the controller enters a Discontinuous conduction Mode and starts adding dead−time after the inductor demagnetization phase. The lower the VCTRL pin voltage, the higher the value of the dead time added. As a result, the frequency linearly decays to about 33 kHz. • Skip Mode: SKIP Mode is optional, versions NCP1602−[B**] and NCP1602−[D**] have the SKIP mode feature, but versions NCP1602−[A**] and NCP1602−[C**] have the SKIP mode feature disabled. To optimize the Power Efficiency at low output power, a controller version using a SKIP Mode is available. When VCTRL pin voltage gets lower than the SKIP Mode threshold voltage, the power mosfet drive is disabled. As a result the output voltage of the controller goes down , making in turn the VCTRL voltage go up and eventually above the SKIP mode threshold. VCTRL pin voltage being now above the SKIP mode threshold, the drive of the power mosfet is enabled. • Low Start−up Current and Large VCC Range: The extra low start−up consumption of the NCP1602−[**A]&[**B] versions allows the use of high−impedance resistors for charging the VCC capacitor. The NCP1602−[**C]&[**D] versions are targeted in applications where the circuit is fed by an © Semiconductor Components Industries, LLC, 2016 January, 2016 - Rev. 0 www.onsemi.com • • auxiliary power source. Its start−up level is lower than 11.25 V to allow the circuit to be powering from a 12−V rail. Both versions feature a large VCC operating range (9.5 V to 30 V). Fast Line / Load Transient Compensation (Dynamic Response Enhancer and Soft OVP): Due to the slow loop response of traditional PFC stages, abrupt changes in the load or in the input voltage may cause significant over or under−shoots. This circuit drastically limits these possible deviations from the regulation point. Safety Protections: NCP1602 features make the PFC stage extremely robust. Among them, we can mention the Brown−Out Detection block (see NOTE below) that stops operation when the ac line is too low and the 2−level Current Sensing, that forces a low duty−ratio operation mode in the event that the current exceeds 150% of the current limit which may be caused by the inductor saturation or by a short of the bypass or boost diode. NOTE: The voltage of the Brown−out detection block input pin (CS/ZCD) is also used to detect the line range and reduce the loop gain in high−line conditions (2−step feed−forward) • Eased Manufacturing and Safety Testing: Elements of the PFC stage can be accidently shorted, badly soldered or damaged as a result of manufacturing or handling incidents, excessive operating stress or other troubles. In particular, adjacent pins of controllers can be shorted, a pin, grounded or badly connected. It is often required that such open/short situations do not cause fire, smoke nor loud noise. The NCP1602 integrates enhanced functions that help address requirement, for instance, in case of an improper pin connection (including GND) or of a short of the boost or bypass diode. 1 Publication Order Number: AND9364/D AND9364/D PFC Stage Dimensioning Vin D1 L1 IL V bulk Rfb1 Rcs1 AC line VCTRL Cin EMI Filter GND Rcs0 Rz CS / ZCD 1 6 2 5 3 4 Cbulk FB LOAD VCC DRV Q1 Cp Rfb2 Rcs2 Cz Rsense Figure 1. EVB Schematic with Power and Control Circuitry Step 1: Define the Input Parameters Values P eff + • (Vline,rms)LSL : Lower operating line voltage. This is the • • minimum rms input voltage for which the PFC stage operates in nominal conditions. (Vline,rms)USL : Higher operating line voltage. This is the maximum input rms voltage for which the PFC stage operates in nominal conditions. Peff : Power efficiency defined by 2@ Step 2: Calculate the Maximum Inductor Value Average input power is related to line voltage power inductor value and tON,max by the following and well known equation: 2@L 2 @ t ON,max ǒPout,avgǓ ǒPeffǓ 2 LSL USL @ t ON,max (eq. 3) 1.5 USL tON,max in the above equation will depend on High Line or Low Line condition. Low Line/High Line condition is normally sensed by the controller when the resistor divider ratio of the pin CSZCD is equal to 138 so for example a 110 V line application will be sensed as Low Line (LL) and a 230 V line application will be sensed High Line (HL). Low Line condition can also be forced by using a resistor divider ratio of the pin CSZCD equal to 2 x 138, at the expense of loosing OVP2 functionality and not being able to use a Brown−out option. Forcing Low Line means the controller will internally set Low Line condition even if the mains voltage is equal to 230 V. Because Frequency Foldback options are set based on tON,max value and Low Line / High Line condition, the Lmax value will be calculated using the tON,max values of Table 1. transition occurs L : Power inductor P in,avg + ǒV in,rmsǓ L max + • (Pout,avg)LSL : Lower operating input power • (Pout,avg)USL : Higher operating input power • (Pout,avg)FF : Input power at which the CrM to DCM ǒV in,rmsǓ (eq. 2) Now, if we want to chose an inductor value to be able to provide at least 50 percent more output power than the higher operating input power, it will be a maximum inductor value given by the following equation. P out,avg P eff + P in,avg • P out,avg P in,avg (eq. 1) A more well known equation is the definition of power efficiency (eq.2) www.onsemi.com 2 AND9364/D Table 1. NCP1602 FREQUENCY FOLDBACK OPTIONS NCP1602 Option VREF,DT (V) tON,max,LL (s) tON,max,HL (s) tON,FF,LL (ms) tON,FF,HL (ms) A 0.27 25.00 8.33 1.97 0.658 B 0.45 25.00 8.33 3.29 1.100 C 0.68 25.00 8.33 4.97 1.660 D 0.54 12.50 4.17 1.97 0.658 E 0.90 12.50 4.17 3.29 1.100 F 1.35 12.50 4.17 4.93 1.640 G 0.82 8.33 2.78 2.00 0.666 H 1.35 8.33 2.78 3.29 1.100 I 2.00 8.33 2.78 4.87 1.620 So the maximum of the maximum switching frequency at line zero crossing is given by: For example for 207 V mains minimum operating voltage, 36 W (Pout,avg)USL = 36 W, (Peff)USL = 0.9 and Option G the Lmax value will be given for High Line and Low Line by: 2 L max,G,HL + 207 @ 2.78e*6 + 0.993 mH 36 2 @ 0.9 1.5 L max,G,LL + 207 2 @ 8.33e*6 + 2.98 mH 36 2 @ 0.9 1.5 F sw,max,FF,i + (eq. 4) (eq. 5) F sw,max,FF,E + If we start at maximum power and we reduce this power, the maximum switching frequency, which is obtained close to line zero crossing, increases because we are in CrM mode. The maximum of this maximum switching frequency is obtained just before the PFC controller enters into DCM mode. After entering the DCM mode the switching frequency starts to reduce (Frequency Foldback) because a VCTRL based dead time is added after the end of inductor demagnetization. The controller operates at constant tON, and the CrM−DCM border is reached for a tON value equal to tON,FF which depends on product option depicted in Table 1. Theoretically and using a very simple model not taking into account the ringing frequency of the drain voltage after the end of demagnetization, at line zero crossing the tOFF is almost zero and the maximum switching frequency is given by: 1 t ON,FF,LL,E ) p ǸL @ C drain (eq. 9) with tON,FF,LL,E = 3.29 ms @ Low Line F sw,max,FF,E + 1 t ON,FF,HL,E ) p ǸL @ C drain (eq. 10) with tON,FF,HL,E = 1.10 ms @ High Line Assuming Low Line can be forced, there are 2x9=18 tON,FF values corresponding to the product options of Table 1 so 18 cases will have to be check with respect to line zero crossing frequency criteria. Only a certain number of product option will be acceptable. Step 4: Select the Product Options Compatible with the Input Power at which the Switching Transitions from CrM to DCM The input power at which the transition from CrM to DCM mode occurs (see Figure 2) is given by: (eq. 6) P in,avg,FF,i + However tOFF is not equal to zero at line zero crossing but given by: t OFF,ZC + p ǸL @ C drain (eq. 8) The maximum of Fsw,max named Fsw,max,FF,i is given by the tON value at CrM−DCM border tON,FF,LL,i or tON,FF,HL,i and depends on NCP1602 option i shown in Table 1. For example, using option E, Max(Fsw,max) is given by: Step 3: Select the Product Options Compatible with a Maximum Switching Frequency at Line Zero Crossing F sw,max + 1 t ON 1 t ON,FF,i ) p ǸL @ C drain ǒV line,rmsǓ 2L 2 t ON,FF,i (eq. 11) It can be clearly seen that for a given line voltage and inductor value, the product option i, through the parameter tON,FF , controls the Pin,avg,FF value. (eq. 7) Where L is the boost PFC inductor and Cdrain the total capacitance between powermosfet drain node and ground. www.onsemi.com 3 AND9364/D Fsw,max Fsw,max = (Vline,rms)2 / Pin,avg / 2 / L Fsw,max,FF,i CrM DCM Pin,avg Pin,avg,LSL Pin,avg,FF,i Pin,avg,USL Pin,avg,max Figure 2. Line Zero Crossing Frequency versus Input Power switching frequency Fsw,min which appears at maximum line voltage (see Figure 3) and as it carries more power is worth to check. NOTE: The saw tooth shape of Fsw,max versus Pin,avg in DCM is due to the number of valleys Step 5: Check if Minimum Frequency at Maximum Line Voltage Fulfils Requirements We have been checking so far for the maximum of line zero crossing frequency, but there is also the minimum Vline t Fsw Fsw,max Fsw,min t Figure 3. Switching Frequency versus Line Voltage versus Time www.onsemi.com 4 AND9364/D Step 5: Using the Excel Spreadsheet In CrM the minimum swiching frequency Fsw,min is given by: F sw,min + ǒ Ǔ V line,rms Ǹ2 1* V out @ 1 t ON A special Excel Spreadsheet named AN1602_FFB_OPTIONS.xlsx has been written for helping choosing the inductor value and product option, for a given application. It contains all the formulas given in this document. (eq. 12) The maximum of Fsw,min is reached at the CrM−DCM boundary and is given by: F sw,min,FF,i + ǒ 1* Ǔ V line,rms Ǹ2 V out @ 1 t ON,FF,i (eq. 13) Figure 4. Screenshot of the Excel Spreadsheet for Low Line State Figure 5. Screenshot of the Excel Spreadsheet for High Line State www.onsemi.com 5 AND9364/D ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. 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