AND8282/D Implementing Cost Effective and Robust Power Factor Correction with the NCP1606 http://onsemi.com Prepared by: Jon Kraft ON Semiconductor APPLICATION NOTE Introduction The Need for PFC The NCP1606 is a voltage mode power factor correction (PFC) controller designed to drive cost−effective pre−converters to meet input line harmonic regulations. The device operates in Critical Conduction Mode (CRM) for optimal performance in applications up to about 300 W. Its voltage mode scheme enables it to obtain unity power factor without the need for a line sensing network. The output voltage is accurately controlled with a built in high precision error amplifier. The controller also implements a comprehensive array of safety features for robust designs. This application note describes the design and implementation of a 400 V, 100 W, CRM Boost PFC pre−converter using the NCP1606. The converter exhibits high power factor, low standby power dissipation, good active mode efficiency, and a variety of protection features. Most electronic ballasts and switching power supplies use a diode bridge rectifier and a bulk storage capacitor to produce a dc voltage from the utility ac line. This produces a non−sinusoidal current draw and places a significant demand on the power delivery infrastructure. Increasingly, government regulations and utility requirements often necessitate control over line current harmonic content. Active PFC circuits have become the most popular way to meet these harmonic content requirements. They consist of inserting a PFC pre−regulator between the rectifier bridge and the bulk capacitor (Figure 1). The boost (or step−up) converter is the most popular topology for active power factor correction. With the proper control, it can be made to produce a constant output voltage while drawing a sinusoidal current from the line. PFC Preconverter Rectifiers AC Line + High Frequency Bypass Capacitor Converter + NCP1606 Bulk Storage Capacitor Load Figure 1. Active PFC Stage with the NCP1606 Basic Operation of a CRM Boost Converter operation with the zero current switching of DCM operation. But this control method means that the frequency inherently varies with the line input voltage and the output load. The operation and waveforms in a PFC boost converter are illustrated in Figure 2. For detailed information on the operation of a CRM Boost Converter for PFC applications, please refer to AND8123 at www.onsemi.com. For medium power (<300 W) applications, critical conduction mode (CRM) is the preferred control method. Critical conduction mode occurs at the boundary between discontinuous conduction mode (DCM) and continuous conduction mode (CCM). In CRM, the next driver on time is initiated when the boost inductor current reaches zero. Hence, CRM combines the lower peak currents of CCM © Semiconductor Components Industries, LLC, 2009 May, 2009 − Rev. 3 1 Publication Order Number: AND8282/D AND8282/D Diode Bridge Diode Bridge Icoil + Vin L + IN Vd Icoil Vin + Vd L + IN − + VOUT − The power switch is ON The power switch is OFF The power switch being about zero, the input voltage is applied across the coil. The coil current linearly increases with a (Vin/L) slope. Coil Current Vin/L Vd The coil current flows through the diode. The coil voltage is (VOUT − Vin) and the coil current linearly decays with a (VOUT − Vin)/L slope. (VOUT − Vin)/L Icoil_pk Critical Conduction Mode: Next current cycle starts as soon as the core is reset. VOUT Vin If next cycle does not start then Vd rings towards Vin Figure 2. Schematic and Waveforms of an Ideal CRM Boost Converter Features of the NCP1606 The NCP1606 offers an ideal controller for these medium power CRM boost PFC applications. A simple CRM Boost pre−converter featuring the NCP1606 is shown in Figure 3. LBOOST VOUT DBOOST LOAD (Ballast, SMPS, etc.) RZCD + AC Line EMI Filter Cin ROUT1 NCP1606 FB V 1 Ccomp ROUT2 CC 2 Ctrl DRV 3 Ct 4 GND CS ZCD Ct VCC 8 + CBULK 7 6 5 RSENSE Figure 3. CRM Boost PFC Stage Featuring the NCP1606 CS (pin 4) gives cycle by cycle over current protection. This is accomplished with an internal comparator which compares the voltage generated by the switch current and RSENSE to an internal reference. In the NCP1606A, this reference is 1.7 V (typ). The NCP1606B has a reduced OCP threshold of 0.5 V (typ) for improved RSENSE power dissipation. Pin 5 (ZCD) senses the demagnetization of the boost inductor. The next driver on time begins when the voltage at this pin rises above 2.1 V (typ) and then drops below about 1.6 V (typ). A resistor from the zero current detection (ZCD) Pin 1 (FB) senses the boost output voltage through the resistor divider formed by ROUT1 and ROUT2. This pin is the input to an error amplifier, whose output is pin 2 (Control). A combination of resistors and capacitors between these pins form a compensation network that limits the bandwidth of the converter. For good power factor, this bandwidth is generally below 20 Hz. A capacitor connected to pin 3 (Ct) sets the on time for a given Control voltage. The combination of these three pins provides excellent power factor and an accurately controlled output voltage. http://onsemi.com 2 AND8282/D another controller, such as the NCP1230. This approach can further improve standby power performance in a two stage SMPS system. For detailed information on the operation of the NCP1606, please refer to NCP1606/D at www.onsemi.com. winding limits the current into this pin. Additionally, by pulling this pin to ground, the drive pulses are disabled and the controller is placed in a low current standby mode. The NCP1606 features a powerful output driver on pin 7. This driver is capable of switching the gates of large MOSFETs in an efficient manner. The driver incorporates both active and passive pulldown circuitry to prevent the output from floating high when VCC is off. Pin 8 (VCC) powers the controller. When VCC is below its turn on level (VCC(on), typically 12 V), the current consumption of the part is limited to < 40 mA. This gives excellent startup times and reduces standby power losses. Alternatively, VCC can also be directly supplied from Design Procedure The design of a CRM Boost PFC circuit has been discussed in many ON Semiconductor application notes (see Table 1). This application note will briefly go through the design procedure for a 400 V, 100 W converter using the features of the NCP1606. A design aid, which gives these equations and results, is available at www.onsemi.com. Table 1. AND8123 Power Factor Correction Stages Operating in Critical Conduction Mode AND8016 Design of Power Factor Correction Circuits Using the MC33260 AND8154 NCP1230 90 W, Universal Input Adapter Power Supply with Active PFC HBD853 Power Factor Correction Handbook *Additional resources for the design and understanding of CRM Boost PFC circuits available at www.onsemi.com. DESIGN STEP 1: Define the Required Boost Parameters Minimum AC Line Voltage VacLL Maximum AC Line Voltage VacHL 264 VRMS fLINE 47−63 Hz Boost PFC Output Voltage VOUT 400 V Maximum Output Voltage VOUT(max) 440 V POUT 100 W fSW(min) 50 kHz h 92 % Minimum Switching Frequency Estimated Efficiency DESIGN STEP 2: Calculate the Boost Inductor DESIGN STEP 3: Size the Ct Capacitor The boost inductor is calculated with Equation 1: Vac 2 @ ǒ V OUT Ǹ2 Ǔ The Ct capacitor must be large enough to accommodate the maximum on time at low line and full power. The maximum on time is given by: * Vac @ h (eq. 1) V OUT @ P OUT @ f(min) @ Ǹ2 T ON(max) + To ensure the required minimum switching frequency, the boost inductor must be evaluated at both the minimum and maximum RMS line voltage. This results gives: − L @ 88 Vrms = 491 mH − L @ 264 Vrms = 427 mH A value of 390 mH was selected. Equation 2 can be used to calculate the resultant minimum frequency at full load. f SW + VRMS Line Frequency Boost Output Power L+ 88 ǒ Ǔ Vac 2 @ h Vac @ Ǹ2 @ 1* 2 @ L @ P OUT V OUT 2 @ L @ P OUT + 11.0 ms h @ Vac LL 2 (eq. 3) However, delivering too long an on time allows the application to deliver excessive power and also reduces the control range at high line or light loads. Therefore, the Ct cap is best sized slightly larger then that given by Equation 4: Ct u I charge @ T ON(max) V CT(max) + 2 @ P OUT @ L @ I charge h @ Vac RMS 2 @ V CT(max) (eq. 4) Where Icharge and VCT(MAX) are found in the NCP1606 datasheet. To ensure that the maximum on time can always be delivered, use the maximum Icharge and the minimum VCT(MAX) in the calculations for Ct. From the NCP1606 datasheet: − VCT(MAX) = 2.9 V (min) − Icharge = 297 mA (max) This gives a Ct value of 1.1 nF. A normalized value of 1.2 nF (±10%) gives enough margin. (eq. 2) This gives 63 kHz at 88 Vrms and 55 kHz at 264 Vrms. http://onsemi.com 3 AND8282/D DESIGN STEP 4: Determine the ZCD Turns Ratio A winding taken off of the boost inductor gives the zero current detection (ZCD) information. When the switch is on, the ZCD voltage is equal to: V ZCD(on) + * V in N B : N ZCD DRIVE VOUT Drain (eq. 5) where Vin = the instantaneous AC line voltage When the switch is off, the ZCD voltage is equal to: V ZCD(off) + V OUT * V in N B : N ZCD VZCD(off) Winding (eq. 6) To activate the zero current detection comparators of the NCP1606 (see Figure 5), the ZCD turns ratio must be sized such that at least VZCDH (2.1 V typ) is obtained on the ZCD pin during all operating conditions. This means that: N B : N ZCD v V OUT * Vac HL @ Ǹ2 + 11.6 V ZCDH VZCD(on) 5.7 V 2.1 V 1.6 V ZCD 0.6 V (eq. 7) Figure 4. Voltage Waveforms for Zero Current Detection NB Vin NZCD + − + VDD + − VCL−NEG Active Clamp + RSENSE ZCD VCL−POS Clamp + RZCD 2.1 V DRIVE S Q Reset Dominant Latch R Q Demag 1.6 V − + Shutdown 200 mV Figure 5. ZCD Winding and Internal Logic Arrangement significant delay in detecting the ZCD event. In this case, the controller would operate in discontinuous conduction mode (DCM) and the power factor would suffer. Conversely, if the ZCD resistor is too low, then the next driver pulse would start when the voltage is still high and switching efficiency would suffer. A turns ratio of 10 was selected for this design. A resistor, RZCD, is added between the ZCD winding and pin 5 to limit the current into or out of the pin. This current must be low enough so as to not trigger the ZCD shutdown feature. Therefore, RZCD must be: R ZCD w Vac HL @ Ǹ2 + 14.9 kW I CL_NEG @ (N B : N ZCD) (eq. 8) DESIGN STEP 5: Set the FB, OVP, and UVP Levels Because of the slow bandwidth of the PFC stage, the output can suffer from overshoots during transient loads or at startup. To prevent this, the NCP1606 incorporates an adjustable overvoltage protection (OVP) circuit. The OVP activation level is set by ROUT1. A derivation in the NCP1606 datasheet shows that: where ICL_NEG = 2.5 mA (from the NCP1606 datasheet) However, the value of this resistor and the small parasitic capacitance of the ZCD pin also determines when the ZCD winding information is detected and the next drive pulse begins. Ideally, the ZCD resistor will restart the drive at its valley. This will minimize switching losses by turning the MOSFET back on when its drain voltage is at a minimum. The value of RZCD to accomplish this is best found experimentally. Too high of a value could create a V OUT(max) + V OUT(nom) ) R OUT1 @ I OVP where IOVP = 40 mA (for NCP1606A) http://onsemi.com 4 (eq. 9) AND8282/D or IOVP = 10 mA (for NCP1606B) Therefore, to achieve the desired maximum output voltage with the NCP1606B, ROUT1 is equal to: R OUT1 + V OUT(max) * V OUT(nom) I OVP VCC(on) VCC(off) (eq. 10) VOUT(nom) This gives a value of 4.0 MW for the NCP1606B or 1.0 MW for the NCP1606A. ROUT2 is then sized to maintain 2.5 V on the FB pin when Vout is at its targeted level. 2.5 V @ R OUT1 R OUT2 + V OUT(nom) * 2.5 V FB (eq. 11) VEAH UVP Fault is “Removed” Control VEAL UVP UVP Wait UVP Wait Figure 6. Timing Diagram Showing UVP and Recovery from UVP If the open loop event occurs after startup, then the fault may not be detected immediately. This is because the error amplifiers regulates the control pin to achieve 2.5 V on the FB pin. Therefore, the FB voltage can only drop once the maximum control pin voltage is achieved. When the FB voltage drops below the UVP threshold, then the undervoltage fault will be entered. The situation is depicted in Figure 7. P OUT (eq. 12) C bulk @ 2 @ p @ f LINE @ V OUT where fLINE = 47 Hz (worst case for ripple) A bulk capacitor value of 68 mF gives a peak to peak ripple of 12.5 V. This is well below the peak output overvoltage level (40 V). The NCP1606 also incorporates undervoltage protection (UVP). Under normal conditions, the boost output capacitor will charge to the peak of the ac line. But if it does not charge to some minimum voltage, then the NCP1606 enters undervoltage protection. The minimum output voltage that must be sensed is given by: Vout UVP + VOUT 2.5 V VUVP This gives a value of 25.2 kW for the B version or 6.3 kW for the A version. When determining the maximum output voltage level, care must be exercised so as not to interfere with the natural line frequency ripple on the output capacitor. This ripple is caused by the averaging effect of the PFC stage: the current charging the bulk cap is sinusoidal and in phase with the input line, but the load current is not. The resultant ripple voltage can be calculated as: Vripple (pk*pk) + VCC VCC(on) VCC VCC(off) R OUT1 ) R OUT2 @ V UVP + 48.0 V (eq. 13) R OUT2 VOUT VOUT(nom) ROUT1 is Opened where VUVP = 300 mV (typ) Note that this feature also provides protection against open loop conditions in the feedback path. Consider that if ROUT1 was inadvertently open (perhaps due to a bad solder joint), the boost application would normally see that the FB pin is too low (0 V in this case) and respond by delivering maximum power. This could raise the output voltage well above its maximum, potentially causing catastrophic results. However, the NCP1606 incorporates a novel feature which waits 180 ms at startup prior to issuing the first drive pulse. Since the built in error amplifier would normally pull FB to 2.5 V, the NCP1606 leaves the error amplifier disabled during this time. If the FB pin is less than the UVP level (300 mV), it continues to disable both the driver output and the error amplifier. Thus, an undervoltage or open loop condition can be always be accurately detected at startup (Figure 6). FB 2.5 V VUVP VEAH Control VEAL UVP Figure 7. UVP Operation if ROUT1 is Opened After Startup http://onsemi.com 5 AND8282/D DESIGN STEP 6: Size the Power Components standby power dissipation. The startup time can be approximated with the following equation: The power components must be properly sized for the necessary current and voltages which they will experience. The stresses are greatest at full load and low line. 1. The Boost inductor, L 2 @ Ǹ2 @ P OUT I L(peak) + + 3.49 A h @ Vac LL Icoil RMS + 2 @ P OUT + 1.43 A Ǹ3 @ Vac @ h LL T start + R start (eq. 14) Ǹ2 @pǸ2 @ (eq. 15) h @ ǸVac LL @ V OUT 3. The MOSFET, M1 ǒ Ǔ P OUT I M(rms) + 2 @ @ Ǹ3 h @ Vac LL Ǹƪ 1* (eq. 16) P OUT ǒ + 0.73 A (eq. 17) Ǔƫ 8 @ Ǹ2 @ Vac LL 3 @ p @ V OUT LBOOST RZCD + 1.22 A R1 RSTART + 4. The sense resistor, RSENSE V CS(limit) I peak + 0.14 W (B) or 0.49 W (A) (eq. 18) (eq. 19) VCS(limit) = 0.5 V (typ) for the NCP1606B; VCS(limit) = 1.7 V (typ) for the NCP1606A 3 Ct GND 4 Cs ZCD D2 8 7 6 + CVCC 5 C1 stores the energy for the charge pump. R1 limits the current by reducing the rate of voltage change. D1 supplies current to C1 when its cathode is negative. When its cathode is positive it limits the maximum voltage applied to VCC. When the ZCD winding is switching, the voltage change across C1 over one period is: 5. The bulk capacitor, CBULK Ǹ 2 NCP1606 FB V CC Ctrl DRV 1 Cin D1 Figure 8. The ZCD Winding can Supply VCC through a Charge Pump Circuit P Rsense + I M(rms) 2 @ R SENSE + 0.21 W (B) or 0.73 W (A) I C(rms) + IAUX C1 The MOSFET will see a maximum voltage equal to the VOUT overvoltage level (440 V for this example). If an 80% derating is used for the MOSFET’s BVDSS, then a 550 V FET gives adequate margin. R SENSE + (eq. 21) * I CC(startup) where ICC(startup) = 40 mA (max) When the VCC voltage exceeds the VCC(on) level (12 V typical), the internal references and logic of the NCP1606 turn on. The controller has an undervoltage lockout (UVLO) feature which keeps the part active until VCC drops below about 9.5 V. This hysteresis allows ample time for another supply to take over and provide the necessary power to VCC. The ZCD winding is an excellent candidate, but the voltage generated on the winding can be well below the desired VCC level. Therefore, a small charge pump must be constructed to supply VCC. Such a schematic is illustrated in Figure 8. 2. The Boost Diode, DBOOST I D(rms) + 4 @ 3 C Vcc @ V CC(on) Vac (rms)@Ǹ2 (eq. 20) 32 @ Ǹ2 @ P OUT 2 * (I LOAD(rms)) 2 + 0.69 A 9 @ p @ Vac LL @ V OUT @ h 2 DV C1 + The bulk cap value was calculated in Step 5 to give an acceptable ripple voltage which would not trigger the output over voltage protection. This value may need to be further increased so as to give an RMS current that is within the capacitor’s ratings. The voltage rating of the bulk cap should be greater than the maximum VOUT level. Since this design has an output overvoltage level of 440 V, a 450 V capacitor was selected. V OUT * V CC N : N ZCD (eq. 22) Therefore, the current available for charging VCC is: I AUX +C1 @ f SW @ DV C1 + C1 @ f SW @ V OUT * V CC (eq. 23) N : N ZCD For off line ac−dc applications which require PFC, a 2 stage approach is generally used. The first stage is the CRM boost PFC. This supplies the 2nd stage−−traditionally an isolated flyback or forward converter. This solution can exhibit excellent performance at a low cost. However, during light load operations, the input current is low and the PFC stage is not necessary. In fact, leaving it on only degrades the efficiency of the system. Advanced controllers, such as the NCP1230 and NCP1381, can detect this light load case and instruct the PFC to shut down (Figure 9). The DESIGN STEP 7: Supply VCC Generally, a resistor connected between the ac input and pin 8 charges up the VCC cap to the VCC(on) level. Because of the very low consumption of the NCP1606 during this stage, most of the current goes directly to charging up the VCC cap. This provides faster startup times and reduced http://onsemi.com 6 AND8282/D NCP1606 is compatible with this type of topology, provided that the supplied VCC is initially greater than the NCP1606’s VCC(on) level. Dboost + 8 2 3 4 NCP1606 1 PFC_Vcc 1 8 2 7 6 3 6 5 4 5 7 + Cbulk VCC + + + NCP1230 Figure 9. Using the SMPS Controller to Supply Power to the NCP1606 DESIGN STEP 8: Limit the Inrush Current current. After startup, DBYPASS will be reverse biased and will not interfere with the boost converter. 2. External Inrush Current Limiting Resistor An NTC (negative temperature coefficient) thermistor in series with the boost inductor can limit the inrush current (Figure 11). The resistance value drops from a few ohms to a few milliohms as the device is heated by the I2R power dissipation. Alternatively, this NTC can be placed in series with the boost diode. This improves the active efficiency as the resistor only sees the output current instead of the input current. However, an NTC resistor may not be able to adequately protect the inductor and bulk capacitor against inrush current during a brief interruption of the mains, such as during line drop out and recovery. The sudden application of the mains to the PFC converter can cause the circuit to experience an inrush current and a resonant voltage overshoot that is several times normal values. To resize the power components to handle this is cost prohibitive. Furthermore, the controller cannot do anything to protect against this. Turning on the boost switch would only make the issue worse. There are two primary ways to solve this issue: 1. Startup Bypass Rectifier A rectifier can be added from the input voltage to the output voltage (Figure 10). This bypasses the inductor and diverts the startup current directly to the bulk capacitor. The bulk capacitor is then charged to the peak ac line voltage without resonant overshoot and without excessive inductor DBYPASS Vin NTC Vin + NCP1606 + NCP1606 VOUT Vac Vac Figure 10. Use a Second Diode to Route the Inrush Current Away from the Inductor VOUT Figure 11. Use an NTC to Limit the Inrush Current Through the Inductor http://onsemi.com 7 AND8282/D DESIGN STEP 9: Develop the Compensation Network 150 As stated earlier, due to the natural output voltage ripple, the bandwidth of the PFC feedback loop is generally kept below 20 Hz. For a simple type 1 compensation network, only a capacitor is placed between FB and Control. The gain, G(s), of the feedback network is then given by: (eq. 24) Therefore, the capacitor necessary to attenuate the bulk voltage ripple is given by: C COMP + 10 Gń20 4 @ p @ f LINE @ R OUT1 Phase Shift (deg) 1 s @ R OUT1 @ C COMP Gain (10 dB/div) G(s) + 120 Phase Shift (°) 90 60 Gain (dB) 30 (eq. 25) 1 where G is the attenuation level in dB (commonly 60 dB) and fLINE is the minimum AC line frequency (47 Hz). 0 100 10 f (Hz) Figure 12. Gain and Phase for a Type 1 Feedback Network As shown in Figure 12, a type 1 compensation network provides no phase boost to improve stability. For resistive loads, this may be sufficient (Figure 13). But for constant power loads, such as SMPS stages, the phase margin can suffer (Figure 14). Mag [B/A] (dB) 40 Phase [B/A] (deg) 90 Mag [B/A] (dB) 40 Phase [B/A] (deg) 90 80 32 70 24 16 60 16 60 8 50 8 50 0 40 0 40 −8 30 −8 20 −16 10 −24 0 −32 −10 −40 32 100 W, 115 Vac CCOMP = 1.1 mF 24 Gain −16 Phase Margin = 30° −24 −32 −40 Phase 1 10 f(Hz) 100 Figure 13. Boost demo board with a resistive load. Phase margin = 30 deg. 100 W, 115 Vac CCOMP = 1.1 mF 80 70 30 Gain 20 Phase Margin = 17° 1 10 0 Phase 10 f(Hz) 100 −10 Figure 14. Boost demo board with a constant power load. Phase margin has been reduced to 17 deg. If greater system stability is required, then a type 2 compensation network can be implemented. In this setup, a resistor and capacitor are placed in parallel with CCOMP (Figure 15). VOUT ROUT1 E/A FB − + + ROUT2 CCOMP2 RCOMP2 2.5 V CCOMP VCONTROL Control Figure 15. Type 2 compensation network http://onsemi.com 8 AND8282/D The transfer function for the error amplifier is now: 1 ) s @ R COMP2 @ C COMP2 G(s) + s @ R OUT1 @ (C COMP ) C COMP2) @ (1 ) s @ R COMP2 @ ǒ C @C COMP COMP2 C )C COMP COMP2 This gives a pole at 0 Hz, a zero at fZ (eq 27), and another pole at fP (eq 28). fZ + 1 2 @ p @ R COMP2 @ C COMP2 (eq. 27) fP + fZ @ 120 Phase [B/A] (deg) 90 72 90 60 Gain (dB) 24 54 16 Phase Shift (deg) Gain (10 dB/div) (eq. 28) 32 Phase Shift (°) 36 Phase Phase Margin = 32° 8 18 0 0 −8 −24 −32 0 100 −40 −18 100 W, 115 Vac CCOMP = 0.27 mF CCOMP2 = 0.82 mF RCOMP2 = 20 kW ROUT1 = 1.5 MW −16 30 10 Ǔ C COMP ) C COMP2 C COMP Mag [B/A] (dB) 40 150 1 ǒ (eq. 26) Ǔ) Gain −36 −54 −72 1 10 100 f (Hz) f (Hz) Figure 16. Representative Gain and Phase for a Type 2 Feedback Network. Note the Phase Boost Figure 17. Improved Stability with a Type 2 Compensation Network. Phase Margin = 32 deg. has the gain−phase measured under all operating conditions. This can be accomplished with a simple setup (Figure 18) and a good network analyzer. The poor stability observed with the type 1 compensation in Figure 14 has now been improved (with the same total compensation capacitance) to Figure 17. The phase margin and cross over frequency will change with the line voltage. Therefore, it is critical that any design Ch A Isolation Probe Ch B Isolation Probe Network Analyzer VOUT LBOOST Isolator 1 kW RZCD + AC Line EMI Filter Cin ROUT1 1 2 3 ROUT2 4 Ct −90 FB V CC Ctrl DRV Ct GND Cs ZCD 8 LOAD VCC + COUT 7 6 5 RSENSE Figure 18. Gain−Phase Measurement Setup for Boost PFC Pre−converters http://onsemi.com 9 AND8282/D Simple Improvements for Additional THD Reduction 1. Improve the THD/PF at Full Load by Increasing the On Time at the Zero Crossing: The NCP1606, with its constant on time architecture, gives a good deal of flexibility in optimizing each design. If further power factor performance is necessary, consider the following design guidelines. One issue with CRM control is that at the zero crossing of the AC line, the voltage is not large enough to significantly charge the boost inductor during the fixed on time. Hence, very little energy is processed and some “zero crossover distortion” (Figure 19) may be produced. Vin (50 V/div) Iin (500 mA/div) Figure 19. Zero Crossover Distortion Fortunately, such a method is easy to implement on the NCP1606. If a resistor was tied from pin 3 (Ct) to the input voltage, then a current proportional to the instantaneous line voltage would be injected into the capacitor (Figure 20). This current would be much higher at the peak of the line and have nearly no effect at low input voltages. This lowers the THD and PF of the pre−converter. To meet IEC1000 requirements, this is generally not an issue, as the NCP1606 delivers more than an ample reduction in current distortion. However, if improved THD or PF is required, then this zero crossover distortion can be reduced. The key is to increase the on time when the input voltage is low. This allows more time for the inductor to charge up and reduces the voltage level at which the distortion begins. LBOOST Vin I+ + AC Line Cin V in R CTUP VDD RCTUP VCONTROL PWM + ICHARGE Ct DRV Ct VEAL Figure 20. Add RCTUP to Modify the On Time and Reduce the Zero Crossing Distortion http://onsemi.com 10 TON AND8282/D increased no load power dissipation created by RCTUP. The designer must balance the desired THD and PF performance with the no load power dissipation requirements. Therefore, the Ct capacitor can be increased in size so that the on time is a little longer near the zero crossing (Figure 21). This also reduces the frequency variation over the ac line cycle. The disadvantage to this approach is the Vac(t) with RCTUP TON no RCTUP no RCTUP with RCTUP fSW time Figure 21. On Time and Switching Frequency With and Without RCTUP The effect of this resistor on THD and power factor is illustrated in Figure 22. 25 THD (%) 20 15 Rctup = open 10 Rctup = 1.5 MW 5 0 85 115 145 175 205 235 265 Vac (Vrms) Figure 22. Effect of Rctup on Full Load (100 W) THD 2. Improve the THD/PF at Light Load or High Line: deliver the required on time at full load and low line. However, sizing it too large means that the range of control levels at light power will be reduced. And as the Ct capacitor becomes larger, the minimum on time of the driver will also increase. 2. Compensate for propagation delays. If optimizing the Ct capacitor still does not achieve the desired performance, then it may be necessary to compensate for the propagation delay. When the Ct voltage exceeds the VCONTROL setpoint, the PWM comparator sends a signal to end the on time of the driver (Figure 23). If the required on time at light load or high line is less than the minimum on time, then the controller will deliver too much power. Eventually, this will cause the control voltage to fall to its lowest level (VEAL). The controller will then disable the drive (static OVP) to prevent the output voltage from rising too high. Once the output drops lower, the control voltage will rise and the cycle will repeat. Obviously, this will add to the distortion of the input current and output voltage ripple. However, there are two simple solutions to remedy the problem: 1. Properly size the Ct capacitor. As mentioned above, the capacitor must be large enough to http://onsemi.com 11 AND8282/D VCONTROL Control ISWITCH VDD ICHARGE Ct VCT(off) RCT DRIVER PWM + VGATE DRV RDRIVE DRV RSENSE VEAL Ct Figure 23. Block Diagram of the Propagation Delay Components However, there is some delay before the MOSFET fully turns off. This delay is created by the propagation delay of the PWM comparator and the time to bring the MOSFET’s gate voltage to zero (Figure 24). The total delay, tDELAY, is summarized in eq 29: CT(off) t DELAY + t PWM ) t GATE (eq. 29) This delay adds to the effective on time of the controller. But if a resistor (RCT) is inserted in series with the Ct capacitor, then the total on time is reduced by: CT tPWM Dt + Ct @ VGATE DV RCT + Ct @ R CT DI RCT Therefore, to compensate for the propagation delay, RCT must be: R CT + ISWITCH Figure 24. Driver Turn Off Propagation Delay 50 40 THD (%) Rct = 0 W 30 20 Rct = 300 W 10 25 30 (eq. 30) The NCP1606 datasheet gives a typical tPWM of 100 ns. The tGATE delay is a function of the MOSFET’s gate charge and the resistor “RDRIVE.” For this demo board, the gate delay was measured at about 150 ns. Therefore, a value of RCT = 300 W is sufficient to compensate for the propagation delays. This can improve PF and THD, particularly at light load and high line (Figure 25). tGATE tDELAY 0 t DELAY Ct 35 40 45 Pout (W) Figure 25. Effect of Rct on Light Load THD at 264 Vac / 50 Hz (Rctup = open) http://onsemi.com 12 50 AND8282/D Design Results The completed demo board schematic using the NCP1606B is shown in Figure 26. Rstart1 Bridge 180 mH F1 Fuse L1 C1 0.47 mF Vac Cin 4.7 mH 0.1 mF C2 L2 Rstart2 330 kW LBOOST 390 mH Rctup1 750 kW DBOOST 100 W 22 nF Daux NCP1606B 1 8 Rcomp2 U1 Ccomp 54.9 kW 2 7 0.1 mF 3 6 Rct 5 4 Short Ct2 0.33 nF Ccs Open Ct1 1.2 nF Rcs VOUT CBULK 68 mF 450 V Q1 SPP12N50 Rdrv Cvcc2 100 nF NTC 4.7 W ROUT1A 2 MW ROUT1B 2 MW RZCD 100 kW D2 18 V Ccomp1 0.39 mF 0.47 mF MUR460 R1 C3 Aux 10:1 Rctup2 750 kW 330 kW 10 W ROUT2 24.9 kW Cvcc 47 mF Rs1 0.1 W 1W 510 W Figure 26. 100 W PFC Pre−Converter Using the NCP1606B The bill of materials (BOM) and layout drawings are shown in Appendix 1 and 2, respectively. This pre−converter exhibits excellent THD (Figure 27), PF (Figure 28), and efficiency (Figure 29). 20 1.00 18 0.98 16 12 PF 0.96 10 8 0.94 Pout = 100 W 6 4 2 0 0.92 85 115 145 175 205 235 265 0.90 85 115 145 175 205 235 Vac (Vrms) Vac (Vrms) Figure 27. THD vs. Input Voltage at Full Load and 50% Load Figure 28. PF vs. Input Voltage at Full Load and 50% Load 96 95 EFFICIENCY (%) THD (%) 14 Pout = 100 W Pout = 50 W Pout = 50 W Pout = 100 W 94 93 92 Pout = 50 W 91 90 85 115 145 175 205 235 265 Vac (Vrms) Figure 29. Efficiency vs. Input Voltage at Full Load and 50% Load http://onsemi.com 13 265 AND8282/D The input current and resultant output voltage ripple is shown in Figure 30. The overvoltage protection scheme can be observed by starting up the pre−converter with a light load on the output (Figure 31). The OVP activates at about 440 V and restarts at about 410 V. OVP Activated at 440 V VCC (5 V/div) Vin (100 V/div) Vout (100 V/div) NCP1606 Starts Up Here OVP Recovers at 410 V Vin (100 V/div) Iin (1 A/div) Vout Ripple (10 V/div) Figure 30. Full Load Input Current at 115 Vac/60 Hz Figure 31. Startup Transient Showing OVP Activation and Recovery If the NCP1606A is to be used instead, then changes to ROUT1, ROUT2, RSENSE, and the compensation components are necessary. Figure 32 shows the schematic of the 100 W board for the NCP1606A. The changes are highlighted in red. Rstart1 Bridge 180 mH F1 Fuse Vac 4.7 mH L1 C1 0.47 mF Cin C2 L2 0.1 mF Rstart2 330 kW LBOOST 390 mH Rctup1 750 kW Rctup2 750 kW R1 C3 Aux 10:1 100 W 22 nF Daux 330 kW DBOOST D2 18 V Ccomp1 1 mF 0.47 mF NCP1606A 1 8 Rcomp2 U1 Ccomp 20 kW 2 7 270 nF 3 6 Rct 5 4 Short Ct2 0.33 nF Ct1 1.2 nF Ccs Open MUR460 RZCD 100 kW Rdrv Cvcc2 100 nF Rcs 510 W 10 W Cvcc 47 mF Rs2 0.806 NTC 4.7 W ROUT1A 500 kW ROUT1B 500 kW Q1 SPP12N50 VOUT CBULK 68 mF 450 V ROUT2 6.19 kW Rs1 0.806 1W 1W Figure 32. 100 W PFC Pre−Converter Using the NCP1606A This demo board can be configured in a variety of ways to optimize performance. Table 2 gives some results with a few of these configurations. The data confirms that the addition of Rctup has a beneficial effect on the THD. Additionally, the B version exhibits superior standby power dissipation due to its reduced thresholds on IOVP. It also shows improved active mode efficiency at low line. This is because it uses a smaller VCS(limit) level (0.5 V typical), which decreases the Rsense power dissipation by about 70%. This reduction in power consumption is most noticeable at low line, where peak currents are the highest. Table 2. Summary of key parameters for different variations of the demo board. Efficiency @ 100 W THD @ 100 W Version ROUT1 RCTUP Ct Shutdown (VZCD = 0 V) Pdiss @ 264 Vac 115 Vac 60 Hz A 1.0 MEG open 1.2 nF 321 mW 92.5% 94.9% 8.1% A 1.0 MEG 1.5 MEG 1.5 nF 391 mW 92.5% 94.8% 4.5% 7.4% B 4.0 MEG open 1.2 nF 217 mW 93.0% 94.9% 8.0% 13.3% B 4.0 MEG 1.5 MEG 1.5 nF 288 mW 93.0% 94.8% 3.7% 8.9% http://onsemi.com 14 230 Vac 50 Hz 115 Vac 60 Hz 230 Vac 50 Hz 15.1% AND8282/D Appendix 1: Bill of Materials (BOM) Designator Qty. Description Value Manufacturer Part # U1 1 NCP1606B PDIP ON Semiconductor NCP1606B D1 1 General purpose diode 100 V, SOD123 ON Semiconductor MMSD4148T1G Daux 1 Zener diode 18 V, 5% ON Semiconductor MMSZ4705T1 Dboost 1 Ultrafast diode 4 A, 600 V ON Semiconductor MUR460RLG Bridge 1 Diode Bridge Rectifier 2 A, 600 V Vishay 2KBP06M−E4/1 C1, C2 2 X cap 0.47 mF, 275 Vac EPCOS B81130C1474M Cin 1 X cap 0.1 mF, 305 Vac EPCOS B32921A2104M Cbulk 1 Electrolytic Cap, Radial 68 mF, 450 V Panasonic ESMG451ELL680MN35S Cvcc 1 Electrolytic Cap, Radial 47 mF, 25 V Panasonic EEU−FC1E470 C3 1 SM 1206 capacitor 22 nF, 10%, 25 V Ccomp 1 SM 1206 capacitor 100 nF, 10%, 25 V Ccomp2 1 SM 1206 capacitor 390 nF, 10%, 25 V Ccs − SM 1206 capacitor open Ct1 1 SM 1206 capacitor 1.5 nF, 10%, 25 V Cvcc2 1 SM 1206 capacitor 100 nF, 10%, 25 V L1 1 Input Inductor 180 mH Coilcraft PCV−2−184−05L L2 1 Line Filter 4.7 mH, 2.7 A Panasonic ELF−20N027A Lboost 1 Boost inductor and ZCD winding 390 mH, 10:1 Coilcraft FA2890−AL NTC 1 Inrush current limiter, NTC 4.7 W, 20% EPCOS B57238S479M Q1 1 TO−220AB N−CH Power MOSFET 11.6 A, 560 V Infineon SPP12N50C3X R1 1 SM 1206 resistor 100 W Rcomp2 1 SM 1206 resistor 54.9 kW Rct 1 SM 1206 resistor short, 1% Ro1a, Ro1b 2 SM 1206 resistor 2 MW Rout2 1 SM 1206 resistor 24.9 kW Rdrv 1 SM 1206 resistor 10 W Rs1 1 SM 2512 sense resistor 0.100 W, 1 W, 1% KOA SR733ATTER100F Rcs 1 1/4 W Axial Resistor 510 W, 5% Yageo CFR−25JB−510R Rctup1, Rctup2 2 1/4 W Axial Resistor 750 kW, 5% Yageo CFR−25JB−750K Rstart1, Rstart2 2 1/4 W Axial Resistor 330 kW, 5% Yageo CFR−25JB−330K Rzcd 1 1/4 W Axial Resistor 100 kW, 5% Yageo CFR−25JB−100k F1 1 Fuse 2.5 A, 250 V Littelfuse 37312500430 Connector 2 156 mil 3 pin connector MOLEX 26−60−4030 Socket 1 8 pin PDIP socket Mill Max 110−99−308−41−001000 Mechanical 1 Heatsink Aavid 590302B03600 Mechanical 1 Screw 4−40 1/4 inch screw Building Fasteners PMSSS 440 0025 PH Mechanical 1 Nut 4−40 screw nut Building Fasteners HNSS440 Mechanical 1 Nylon Washer Shoulder washer #4 Keystone 3049 Mechanical 1 TO220 Thermal Pad 9 mil Wakefield 173−9−240P Mechanical 4 Standoffs Hex 4−40, Nylon 0.75” Keystone 4804k Mechanical 4 Nylon Nut Hex 4−40 Building Fasteners NY HN 440 http://onsemi.com 15 AND8282/D Appendix 2: Layout Drawings Figure 34. Top View of 100 W Board Layout Figure 33. Bottom View of 100 W Board Layout http://onsemi.com 16 AND8282/D Appendix 3: Summary of Boost Equations for the NCP1606 RMS Input Current I ac + Maximum Inductor Peak Current I pk(max) + Inductor Value ǒ t on(max) + Boost Turns to ZCD Turns Ratio Resistor from ZCD winding to the ZCD pin (pin 5) Boost Output Voltage Maximum VOUT voltage prior to OVP activation and the necessary ROUT1 and ROUT2. Minimum output voltage necessary to exit undervoltage protection (UVP) Bulk Cap Ripple Inductor RMS Current Boost Diode RMS Current MOSFET RMS Current * Vac Ǔ fSW(min) is the minimum desired switching frequency. The maximum L must be calculated at low line and high line. The off time is greatest at the peak of the AC line voltage and approaches zero at the AC line zero crossings. Theta (q) represents the angle of the AC line voltage. V OUT *1 Vac@Ťsin(q)Ť@Ǹ2 Vac 2 @ h 2 @ L @ P OUT Ct w The maximum on time occurs at the lowest line voltage and maximum output power. t on t off + Pin 3 Capacitor OUT Ǹ2 2 @ L @ P OUT h @ Vac LL 2 Off Time f SW + V V OUT @ Vac @ I pk(max) @ f SW(min) Maximum On Time Frequency Where VacLL is the minimum line input voltage. Ipk(max) occurs at the lowest line voltage. 2 @ Ǹ2 @ P OUT h @ Vac LL 2 @ Vac 2 @ Lv h (the efficiency of only the Boost PFC stage) is generally in the range of 90 − 95% P OUT h @ V ac ǒ @ 1* Ǔ Vac @|sin q| @ Ǹ2 V OUT Icharge and VCTMAX are given in the NCP1606 specification table. 2 @ P OUT @ L @ I charge h@ Vac 2 @ V CTMAX Where VacHL is the maximum line input voltage. The turns ratio must be low enough so as to trigger the ZCD comparators at high line. V * Vac HL @ Ǹ2 N B : N ZCD v OUT V ZCDH R ZCD w Vac HL @ Ǹ2 I CL(NEG) @ (N B : N ZCD) V OUT + 2.5 V @ RZCD must be large enough so that the shutdown comparator is not inadvertently activated. R OUT1 ) R OUT2 R OUT2 IOVP is given in the NCP1606 specification table. IOVP is lower for the NCP1606B, then for the NCP1606A version. V OUT(max) + V OUT(nom) ) R OUT1 @ I OVP R OUT1 + V OUT(max) * V OUT(nom) I OVP 2.5 V @ R OUT1 R OUT2 + V OUT(nom) * 2.5 V VUVP is given in the NCP1606 specification table. R ) R OUT2 V OUT + OUT1 @ V UVP R OUT2 (UVP) Vripple (pk−pk) + Icoil (rms) + Id MAX(rms) + 4 @ 3 Use fline = 47 Hz for worst case at universal lines. The ripple must not exceed the OVP level for VOUT. P OUT C bulk @ 2 @ p @ f line @ V OUT 2 @ P OUT Ǹ3 @ Vac @ h LL Ǹ2 @pǸ2 @ P OUT 2 I M(rms) + @ @ Ǹ3 h @ Vac LL P OUT h @ ǸVac LL @ V OUT Ǹ ǒ 1* 3p @ V OUT http://onsemi.com 17 Ǔ 8 @ Ǹ2 @ Vac LL AND8282/D Appendix 3: Summary of Boost Equations for the NCP1606 MOSFET Sense Resistor R SENSE + V CS(limit) I pk VCS(limit) is given in the NCP1606 specification table. The NCP1606B has a lower VCS(limit) level. P RSENSE + I M(rms) 2 @ R SENSE Bulk Capacitor RMS Current I C(rms) + Type 1 CCOMP Ǹ 32 @ Ǹ2 @ P OUT 2 * (I LOAD(rms)) 2 9 @ p @ Vac LL @ V OUT @ h 2 C COMP + 10 Gń20 4 @ p @ f line @ R OUT1 G is the desired attenuation in decibels (dB). Typically it is 60 dB. The product described herein (NCP1606), may be covered by the following U.S. patents: 5,073,850 and 6,362,067. There may be other patents pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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