Digitally Programmable Potentiometer , NV, 256 taps / 3 wire, w/Buf

Not Recommended for New Design
CAT521
Configured Digitally Programmable Potentiometer (DPP):
Programmable Voltage Applications
FEATURES
DESCRIPTION
„ 8-bit DPP configured as a programmable
voltage source in DAC-like applications
„ Buffered wiper output
„ Non-volatile NVRAM memory wiper storage
„ Output voltage range includes both supply rails
„ 1 LSB accuracy, high resolution
„ Serial Microwire-like interface
„ Single supply operation: 2.7V – 5.5V
„ Setting read-back without effecting outputs
The CAT521 is a 8-bit digitally-programmable potentiometer (DPP) configured for programmable voltage
and DAC-like applications. Intended for final calibration
of products such as camcorders, fax machines and
cellular telephones on automated high volume
production lines, it is also well suited for self-calibrating
systems and for applications where equipment which
requires periodic adjustment is either difficult to access
or in a hazardous environment.
The programmable DPP has an output voltage range
which includes both supply rails. The wiper is buffered
by a rail to rail op amp. The wiper setting, stored in
non-volatile NVRAM memory, is not lost when the
device is powered down and is automatically
reinstated when power is returned. The wiper can be
dithered to test new output values without effecting
the stored settings and stored settings can be read
back without disturbing the DPP’s output.
For Ordering Information details, see page 12.
APPLICATIONS
„ Automated product calibration
„ Remote control adjustment of equipment
„ Offset, gain and zero adjustments in selfcalibrating and adaptive control systems
„ Tamper-proof calibrations
„ DAC (with memory) substitute
The CAT521 is controlled with a simple 3-wire,
Microwire like serial interface. A Chip Select pin
allows several devices to share a common serial
interface. Communication back to the host controller is
via a single serial data line thanks to the CAT521 Tri¯¯¯¯ output working in
Stated Data Output pin. A RDY/BSY
concert with an internal low voltage detector signals
proper operation of the non-volatile NVRAM memory
Erase/Write cycle.
PIN CONFIGURATION
PDIP 14-Lead (L)
SOIC 14-Lead (W)
VDD
1
14
VREFH
CLK
2
13
NC
RDY/¯¯¯¯
BSY
3
12
VOUT
CS
4 CAT521 11
NC
DI
5
10
NC
DO
6
8
VREFL
PROG
7
8
GND
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
The CAT521 is available in 0°C to 70°C commercial
and -40°C to 85°C industrial operating temperature
ranges. Both 14-pin plastic DIP and surface mount
packages are available.
1
Doc. No. MD-2003 Rev. I
CAT521
Not Recommended for New Design
FUNCTIONAL DIAGRAM
PROG
DI
CLK
CS
VREFH
1
14
3
7
PROGRAM
CONTROL
5
2
SERIAL
CONTROL
4
WIPER CONTROL REGISTERS
AND NVRAM
RDY/BSY
VDD
24kΩ
24kΩ
24kΩ
12
–
SERIAL
DATA
OUTPUT
REGISTER
CAT521
6
VOUT
DO
9
8
GND
Doc. No. MD-2003 Rev. I
+
24kΩ
VREFL
2
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
Not Recommended for New Design
CAT521
ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Supply Voltage*
VDD to GND
Inputs
CLK to GND
CS to GND
DI to GND
¯¯¯¯ to GND
RDY/BSY
PROG to GND
VREFH to GND
VREFL to GND
Units
-0.5 to +7
-0.5 to VDD +0.5
-0.5 to VDD +0.5
-0.5 to VDD +0.5
-0.5 to VDD +0.5
-0.5 to VDD +0.5
-0.5 to VDD +0.5
-0.5 to VDD +0.5
V
V
V
V
V
V
V
V
Parameters
Outputs
D0 to GND
VOUT 1– 4 to GND
Operating Ambient Temperature
Commercial
(‘C’ or Blank suffix)
Industrial (‘I’ suffix)
Junction Temperature
Storage Temperature
Lead Soldering (10 sec max)
Ratings
Units
-0.5 to VDD +0.5
V
-0.5 to VDD +0.5
V
0 to +70
°C
-40 to +85
+150
-65 to +150
+300
°C
°C
°C
°C
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Test Method
Min
VZAP(2)
ILTH(2)(3)
Max
Units
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
V
Latch-Up
JEDEC Standard 17
100
mA
POWER SUPPLY
Symbol
Parameter
Conditions
IDD1
Supply Current (Read)
IDD2
Supply Current (Write)
VDD
Min
Typ
Max
Units
Normal Operating
—
400
600
µA
Programming, VDD = 5V
—
1600
2500
µA
VDD = 3V
—
1000
1600
µA
2.7
—
5.5
V
Min
Typ
Max
Units
Operating Voltage Range
LOGIC INPUTS
Symbol
Parameter
Conditions
IIH
Input Leakage Current
VIN = VDD
—
—
10
µA
IIL
Input Leakage Current
VIN = 0V
—
—
-10
µA
VIH
High Level Input Voltage
2
—
VDD
V
VIL
Low Level Input Voltage
0
—
0.8
V
LOGIC OUTPUTS
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VOH
High Level Output Voltage
IOH = -40µA
VDD -0.3
—
—
V
VIL
Low Level Output Voltage
IOL = 1 mA, VDD = +5V
—
—
0.4
V
IOL = 0.4 mA, VDD = +3V
—
—
0.4
V
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V.
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
3
Doc. No. MD-2003 Rev. I
CAT521
Not Recommended for New Design
POTENTIOMETER CHARACTERISTICS
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
Symbol
RPOT
Parameter
Conditions
Potentiometer Resistance
See note 3
Min
Typ
Max
24
RPOT to RPOT Match
—
Units
kΩ
±0.5
Pot Resistance Tolerance
±1
%
±20
%
Voltage on VREFH pin
2.7
VDD
V
Voltage on VREFL pin
0
VDD - 2.7
V
Resolution
0.4
%
INL
Integral Linearity Error
0.5
1
LSB
DNL
Differential Linearity Error
0.25
0.5
LSB
ROUT
Buffer Output Resistance
10
Ω
IOUT
Buffer Output Current
3
mA
TCRPOT
TC of Pot Resistance
300
ppm/ºC
CH/CL
Potentiometer Capacitances
8/8
pF
AC ELECTRICAL CHARACTERISTICS
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Digital
tCSMIN
Minimum CS Low Time
150
—
—
ns
tCSS
CS Setup Time
100
—
—
ns
tCSH
CS Hold Time
0
—
—
ns
tDIS
DI Setup Time
50
—
—
ns
50
—
—
ns
CL = 100pF
(1)
tDIH
DI Hold Time
tDO1
Output Delay to 1
—
—
150
ns
tDO0
Output Delay to 0
—
—
150
ns
tHZ
Output Delay to High-Z
—
400
—
ns
tLZ
Output Delay to Low-Z
—
400
—
ns
tBUSY
Erase/Write Cycle Time
—
4
5
ms
tPS
PROG Setup Time
150
—
—
ns
tPROG
Minimum Pulse Width
700
—
—
ns
tCLKH
Minimum CLK High Time
500
—
—
ns
tCLKL
Minimum CLK Low Time
300
—
—
ns
fC
Clock Frequency
DC
—
1
MHz
CLOAD = 10pF, VDD = +5V
—
3
10
µs
CLOAD = 10pF, VDD = +3V
—
6
10
µs
Analog
tDS
DPP Settling Time to 1 LSB
Notes:
(1) All timing measurements are defined at the point of signal crossing VDD / 2.
(2) These parameters are periodically sampled and are not 100% tested.
(3) The 24kΩ +20% resistors are configured as 4 resistors in parallel which would provide a measured value between VREFH and VREFL of 6kΩ
+20%. The individual 24kΩ resistors are not measurable but guaranteed by design and verification of the 6kΩ +20% value.
Doc. No. MD-2003 Rev. I
4
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
Not Recommended for New Design
CAT521
A.C. TIMING DIAGRAM
to
1
2
3
4
5
tCLK H
CLK
tCSS
tCLK L
t CSH
CS
tCSMIN
tDIS
DI
tDIH
t DO0
tLZ
DO
tHZ
tDO1
PROG
t PS
tPROG
RDY/BSY
tBUSY
to
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
1
2
3
5
4
5
Doc. No. MD-2003 Rev. I
CAT521
Not Recommended for New Design
PIN DESCRIPTION
Pin
Name
Function
1
VDD
Power supply positive
2
CLK
Clock input pin
3
¯¯¯¯
RDY/BSY
4
CS
Chip select
5
DI
Serial data input pin
6
DO
Serial data output pin
7
PROG
8
GND
Power supply ground
9
VREFL
Minimum DAC output voltage
10
NC
No Connect
11
NC
No Connect
12
VOUT
DPP output
13
NC
No Connect
14
VREFH
DPP addressing is as follows:
Ready/Busy output
A0
A1
VOUT
1
0
EEPROM Programming Enable
Input
Maximum DPP 1 output voltage
IC. Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.
DEVICE OPERATION
The CAT521 is a single 8-bit configured digitally
programmable potentiometer (DPP™) whose output
can be programmed to any one of 256 individual
voltage steps. Once programmed, the output setting is
retained in non-volatile memory and will not be lost
when power is removed from the chip. Upon power up
the DPP returns to the setting stored in non-volatile
memory. The DPP can be written to and read from
without effecting the output voltage during the read or
write cycle. The output can also be adjusted without
altering the stored output setting, which is useful for
testing new output settings before storing them in
memory.
CHIP SELECT
Chip Select (CS) enables and disables the CAT521’s
read and write operations. When CS is high data may
be read to or from the chip, and the Data Output (DO)
pin is active. Data loaded into the DPP control register
will remain in effect until CS goes low. Bringing CS to
a logic low returns all DPP outputs to the settings
stored in nonvolatile memory and switches DO to its
high impedance Tri-State mode.
Because CS functions like a reset the CS pin has
been desensitized with a 30ns to 90ns filter circuit to
prevent noise spikes from causing unwanted resets
and the loss of volatile data.
DIGITAL INTERFACE
The CAT521 employs a 3 wire, Microwire-like serial
control interface consisting of Clock (CLK), Chip
Select (CS) and Data In (DI) inputs. For all operations,
address and data are shifted in LSB first. In addition,
all digital data must be preceded by a logic “1” as a
start bit. The DPP address and data are clocked into
the DI pin on the clock’s rising edge. When sending
multiple blocks of information a minimum of two clock
cycles is required between the last block sent and the
next start bit.
CLOCK
The CAT521 clock controls both data flow in and out
of the device and non-volatile memory cell programming. Serial data is shifted into the DI pin and out of
the DO pin on the clock’s rising edge. While it is not
necessary for the clock to be running between data
transfers, the clock must be operating in order to write
to non-volatile memory, even though the data being
saved may already be resident in the DPP wiper
control register.
Multiple devices may share a common input data line
by selectively activating the CS control of the desired
Doc. No. MD-2003 Rev. I
DPP OUTPUT
6
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
Not Recommended for New Design
CAT521
¯¯¯¯ will remain high following the program
RDY/BSY
command indicating a failure to record the desired
data in non-volatile memory.
No clock is necessary upon system power-up. The
CAT521 internal power-on reset circuitry loads data
from non-volatile memory to the DPP without using
the external clock.
As data transfers are edge triggered clean clock
transitions are necessary to avoid falsely clocking
data into the control register. Standard CMOS and
TTL logic families work well in this regard and it is
recommended that any mechanical switches used for
breadboarding or device evaluation purposes be
debounced by a flip-flop or other suitable debouncing
circuit.
DATA OUTPUT
Data is output serially by the CAT521, LSB first, via
the Data Out (DO) pin following the reception of a
start bit and two address bits by the Data Input (DI).
DO becomes active whenever CS goes high and
resumes its high impedance Tri-State mode when CS
returns low. Tri-Stating the DO pin allows several
521s to share a single serial data line and simplifies
interfacing multiple 521s to a microprocessor.
VREF
VREF, the voltage applied between pins VREFH & VREFL,
sets the DPP’s Zero to Full Scale output range where
VREFL = Zero and VREFH = Full Scale. VREF can span
the full power supply range or just a fraction of it. In
typical applications VREFH & VREFL are connected
across the power supply rails. When using less than
the full supply voltage be mindfull of the limits placed
on VREFH and VREFL as specified in the References
section of DC Electrical Characteristics.
WRITING TO MEMORY
Programming the CAT521’s non-volatile memory is
accomplished through the control signals: Chip Select
(CS) and Program (PROG). With CS high, a start bit
followed by a two bit DPP address and eight data bits
are clocked into the DPP wiper control register via the
DI pin. Data enters on the clock’s rising edge. The
DPP output changes to its new setting on the clock
cycle following D7, the last data bit.
Programming is accomplished by bringing PROG high
sometime after the start bit and at least 150ns prior to
the rising edge of the clock cycle immediately
following the D7 bit. Two clock cycles after the D7 bit
the DPP wiper control register will be ready to receive
the next set of address and data bits. The clock must
be kept running throughout the programming cycle.
Internal control circuitry takes care of generating and
ramping up the programming voltage for data transfer
to the non-volatile memory cells. The CAT521 nonvolatile memory cells will endure over 1,000,000 write
cycles and will retain data for a minimum of 100 years
without being refreshed.
¯¯¯¯¯
READY/BUSY
When saving data to non-volatile memory, the
¯¯¯¯) signals the start and
Ready/Busy ouput (RDY/BSY
duration of the erase/write cycle. Upon receiving a
¯¯¯¯
command to store data (PROG goes high) RDY/BSY
goes low and remains low until the programming cycle is
complete. During this time the CAT521 will ignore any
data appearing at DI and no data will be output on DO.
¯¯¯¯ is internally ANDed with a low voltage
RDY/BSY
detector circuit monitoring VDD. If VDD is below the
minimum value required for EEPROM programming,
Figure 1. Writing to Memory
to
1
2
3
4
5
6
A0
A1
D0
D1
7
8
9
10
11
12
N
N+1 N+2
CS
NEW DPP DATA
DI
1
D2
D3
D4
D5
D6
D7
D6
D7
CURRENT DPP DATA
DO
D0
D1
D2
D3
D4
D5
PROG
RDY/BSY
DPP
OUTPUT
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
CURRENT
DPP VALUE
NEW
DPP VALUE
NEW
DPP VALUE
NON-VOL ATILE
VOLATILE
NON-VOL ATILE
7
Doc. No. MD-2003 Rev. I
CAT521
Not Recommended for New Design
READING DATA
Each time data is transferred into the DPP wiper
control register currently held data is shifted out via
the D0 pin, thus in every data transaction a read cycle
occurs. Note, however, that the reading process is
destructive. Data must be removed from the register
in order to be read. Figure 2 depicts a Read Only
cycle in which no change occurs in the DPP’s output.
This feature allows µPs to poll DPPs for their current
setting without disturbing the output voltage but it
assumes that the setting being read is also stored in
non-volatile memory so that it can be restored at the
end of the read cycle. In Figure 2 CS returns low
th
before the 13 clock cycle completes. In doing so the
non-volatile memory's setting is reloaded into the DPP
wiper control register. Since this value is the same as
that which had been there previously no change in the
DPP’s output is noticed. Had the value held in the
control register been different from that stored in nonvolatile memory then a change would occur at the
read cycle’s conclusion.
TEMPORARILY CHANGE OUTPUT
The CAT521 allows temporary changes in the DPP’s
output to be made without disturbing the settings
retained in non-volatile memory. This feature is
particularly useful when testing for a new output
setting and allows for user adjustment of preset or
default values without losing the original factory
settings.
Figure 2. Reading from Memory
Figure 3. Temporary Change in Output
Figure 3 shows the control and data signals needed to
effect a temporary output change. DPP settings may
be changed as many times as required. The
temporary setting remains in effect long as CS
remains high. When CS returns low the DPP will
return to the output value stored in non-volatile
memory.
When it is desired to save a new setting acquired
using this feature, the new value must be reloaded
into the DPP wiper control register prior to programming. This is because the CAT521’s internal control
circuitry discards from the programming register the
new data two clock cycles after receiving it if no
PROG signal is received.
to
to
1
2
3
4
5
6
7
8
9
10
11
1
2
3
4
5
6
A0
A1
D0
D1
7
8
9
10
11
12
N
N+1 N+2
12
CS
CS
NEW DPP DATA
DI
1
A0
DI
A1
1
DO
D0
D1
D2
D3
D4
D5
D2
D3
D4
D5
D6
D7
D6
D7
CURRENT DPP DATA
CURRENT DPP DATA
D6
DO
D7
D0
D1
D2
D3
D4
D5
PROG
PROG
RDY/BSY
RDY/BSY
DPP
OUTPUT
DPP
OUTPUT
CURRENT
DPP VALUE
NON-VOL ATILE
Doc. No. MD-2003 Rev. I
8
CURRENT
DPP VALUE
NEW
DPP VALUE
CURRENT
DPP VALUE
NON-VOL ATILE
VOLATILE
NON-VOL ATILE
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
Not Recommended for New Design
CAT521
APPLICATION CIRCUITS
+5V
VI
RI
DPP INPUT
RF
DPP OUTPUT
VDPP =
+15V
CONTROL
& DATA
MSB
–
VDD
CAT521
VDPP
VOUT
+
OP 07
-15V
VREFL
GND
VOUT =
LSB
VDPP ( RI + RF ) - VI R F
RI
For R I = RF
VOUT = 2VDPP - VI
1111
1111
1000
0000
0111
1111
0000
0001
0000
0000
ANALOG OUTPUT
CODE
x (VFS - VZERO) + VZERO
255
VFS = 0.99VREF
VREF = 5V
VZERO = 0.01VREF
RI = RF
255
× 0.98VREF + 0.01VREF = 0.990 VREF
255
128
× 0.98VREF + 0.01VREF = 0.502VREF
255
127
× 0.98VREF + 0.01VREF = 0.498 VREF
255
1
× 0.98VREF + 0.01VREF = 0.014 VREF
255
0
× 0.98VREF + 0.01VREF = 0.010 VREF
255
Bipolar DPP Output
+5V
RI
VOUT = +4.90V
VOUT = +0.02V
VOUT = -0 .02V
VOUT = -4.86V
VOUT = -4.90V
V+
I > 2mA
RF
+15V
VDD
CONTROL
& DATA
–
VREFH
+
CAT521
GND
VREF = 5.00V
VOUT
VDD
OP 07
CONTROL
& DATA
-15V
VREFL
VREFH
CAT521
VREFL
GND
R
VOUT = (1 + F ) VDPP
RI
Amplified DPP Output
LT 1029
Digitally Trimmed Voltage Reference
28 - 32V
15kΩ
10µF
10kΩ
1N5231B
VDD
CONTROL
& DATA
VREFH
5.1V
CAT521
GND
+
–
VREFL
MPT3055EL
LM 324
OUTPUT
1.00kΩ
4.02kΩ
10µF
35V
0 - 25V
@ 1A
Digitally Controlled Voltage Reference
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
9
Doc. No. MD-2003 Rev. I
CAT521
Not Recommended for New Design
PACKAGE OUTLINE DRAWINGS
PDIP 14-Lead (L)(1)(2)
SYMBOL
MIN
A
3.56
5.33
A1
0.38
2.92
3.30
4.95
b
0.36
0.45
0.55
b1
1.15
1.52
1.77
c
0.21
0.26
0.35
D
18.67
19.05
19.68
E
7.62
7.87
8.25
E1
6.10
6.35
7.11
e
TOP VIEW
MAX
A2
E1
D
NOM
2.54 BSC
eB
7.88
L
2.99
10.92
3.30
3.81
E
A2
A
c
A1
e
L
b
b1
eB
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-001.
Doc. No. MD-2003 Rev. I
10
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
Not Recommended for New Design
CAT521
SOIC 14-Lead (W)(1)(2)
SYMBOL
E1
MIN
NOM
MAX
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
c
0.19
D
8.55
E
E1
E
0.25
8.65
8.75
5.80
6.00
6.20
3.80
3.90
4.00
e
1.27 BSC
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
PIN#1 IDENTIFICATION
TOP VIEW
h
D
θ
A
e
b
c
L
A1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
11
Doc. No. MD-2003 Rev. I
CAT521
Not Recommended for New Design
EXAMPLE OF ORDERING INFORMATION
Prefix
CAT
Device # Suffix
521
W
Optional
Company ID
I
Temperature Range
I = Industrial (-40ºC to 85ºC)
Product
Number
521
-
T2
Tape & Reel
T2: 2000/Reel
Package
L: PDIP
W: SOIC
Notes:
(1)
(2)
(3)
All packages are RoHS compliant (Lead-free, Halogen-free).
Standard lead finish is Matte-Tin.
The device used in the above example is a CAT521WI-T2 (SOIC, Industrial Temperature, Tape & Reel).
ORDERING INFORMATION
CAT521WI
CAT521LI
Doc. No. MD-2003 Rev. I
12
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
Not Recommended for New Design
CAT521
REVISION HISTORY
Date
16-Mar-04
Revision
E
Description
Updated Potentiometer Characteristics
12-Jul-04
F
Updated Functional Diagram
Updated Potentiometer Characteristics
Added Note 3 under Potentiometer/AC Characteristics tables
26-Jul-07
G
Updated Ordering Information
Added MD- to document number
Add Package Outline Drawings
15-Jul-08
H
Add “Not Recommended for New Design” to the top of all pages
21-Nov-08
I
Change logo and fine print to ON Semiconductor
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to
any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
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Doc. No. MD-2003 Rev. I
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