Dual Digitally Programmable Potentiometers with 256 Taps & I 2 C Compatible Interface

CAT5270
Dual Digitally Programmable
Potentiometers (DPP) with
256 Taps & I2C Compatible
Interface
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Description
The CAT5270 is a volatile 256−tap by two channels, digitally
programmable potentiometer (DPP) with an I2C compatible interface.
Each DPP consists of a linear taper series of resistive elements
connected between two externally accessible end points. The tap
points between each resistive element are connected to the wiper
outputs with CMOS switches. On power up the wiper position goes to
mid scale.
The CAT5270 can be used as a potentiometer or as a two terminal,
variable resistor. It is available in a 14−lead TSSOP package operating
over the industrial temperature range (−40°C to 85°C).
1
TSSOP−14
Y SUFFIX
CASE 948AM
PIN CONNECTION
Features
•
•
•
•
•
•
•
•
•
•
1
Two Linear Taper Digitally Programmable Potentiometers
256 Resistor Taps per Potentiometer
End to End Resistance 50 kW, 100 kW
I2C Compatible Interface
Low Wiper Resistance 75 W (typ.)
2.5 V to 5.5 V Operation
Standby Current Less than 1 mA
Power On to Mid Scale
14−lead TSSOP Package
Industrial Temperature Range
TSSOP−14 (Y)
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
RH0 RH1
SDA
SCL
I2C COMPATIBLE
INTERFACE
256−POSITION
DECODE
CONTROL
A3
SCL
GND
RW1
RH1
RL1
A1
A0
VCC
RLO
RHO
RWO
A2
SDA
RW0
RW1
A0
A1
A2
A3
CONTROL
LOGIC
RL0
RL1
Figure 1. Functional Diagram
© Semiconductor Components Industries, LLC, 2012
May, 2012 − Rev. 4
1
Publication Order Number:
CAT5270/D
CAT5270
Pin Description
Table 1. PIN DESCRIPTION
Pin #
TSSOP−14
Name
1
A0
2
VCC
Supply Voltage
3
RL0
Low Reference Terminal for
Potentiometer 0
4
RH0
High Reference Terminal for
Potentiometer 0
5
RW0
Wiper Terminal for Potentiometer 0
These inputs set the device address when addressing
multiple devices. A total of sixteen devices can be addressed
on a single bus. A match in the slave address must be made
with the address input in order to initiate communication
with the CAT5270.
6
A2
7
SDA
8
A1
Device Address
9
RL1
Low Reference Terminal for
Potentiometer 1
RH, RL: Resistor End Points
10
RH1
High Reference Terminal for
Potentiometer 1
11
RW1
Wiper Terminal for Potentiometer 1
12
GND
Ground
13
SCL
Bus Serial Clock
14
A3
Device Address
SCL: Serial Clock
The CAT5270 serial clock input pin is used to clock all
data transfers into or out of the device.
SDA: Serial Data
The CAT5270 bidirectional serial data pin is used to
transfer data into and out of the device. The SDA pin is an
open drain output and can be wire−OR’d with the other open
drain or open collector I/Os.
A0, A1, A2, A3: Device Address Inputs
The two sets of RH and RL pins are equivalent to the
terminal connections on a mechanical potentiometer.
RW: Wiper
The RW pins are equivalent to the wiper terminal of a
mechanical potentiometer.
Device Operation
The CAT5270 is two resistor arrays integrated with an I2C
compatible interface and two 8−bit wiper control registers.
Each resistor array contains 255 separate resistive elements
connected in series. The physical ends of each array are
equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL). The tap positions between and
at the ends of the series resistors are connected to the output
Function
Device Address, LSB
Device Address
Serial Data Input/Output
wiper terminals (RW) by a CMOS transistor switch. Only
one tap point for each potentiometer is connected to its wiper
terminal at a time and is determined by the value of the wiper
control register. Data can be read or written to the wiper
control register via the I2C compatible interface. Also, the
device can be instructed to operate in an “increment/
decrement” mode.
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CAT5270
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Temperature Under Bias
−55 to +125
°C
Storage Temperature
−65 to +150
°C
−2.0 to +VCC + 2.0
V
Voltage on Any Pin with Respect to VSS (Note 1)
VCC with Respect to Ground
−2.0 to +6.0
V
Package Power Dissipation Capability (TA = 25°C)
1.0
W
Lead Soldering Temperature (10 sec)
300
°C
Wiper Current
±6
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is −0.5 V. During transitions, inputs may undershoot to −2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5 V, which may overshoot to VCC +2.0 V for periods of less than 20 ns.
Table 3. RECOMMENDED OPERATING CONDITIONS
Parameters
Ratings
Units
VCC
+2.5 to +5.5
V
Industrial Temperature
−40 to +85
°C
Table 4. POTENTIOMETER CHARACTERISTICS (VCC = +2.5 V to +5.5 V, unless otherwise specified.)
Limits
Test Conditions
Min
Typ
Max
Symbol
Parameter
RPOT
Potentiometer Resistance (100 kW)
100
kW
RPOT
Potentiometer Resistance (50 kW)
50
kW
Potentiometer Resistance Tolerance
RPOT Matching
Power Rating
25°C, each pot
Units
±20
%
1
%
50
mW
±3
mA
IW
Wiper Current
RW
Wiper Resistance
IW = ±3 mA @ VCC = 3 V
200
300
W
RW
Wiper Resistance
IW = ±3 mA @ VCC = 5 V
75
150
W
VCC
V
VTERM
Voltage on any RH or RL Pin
VSS = 0 V
Resolution
VSS
0.4
%
Absolute Linearity (Note 4)
Rw(n)(actual) − R(n)(expected) (Note 7)
±1
LSB
(Note 6)
Relative Linearity (Note 5)
Rw(n+1) – R[w(n)+LSB] (Note 7)
±0.2
LSB
(Note 6)
TCRPOT
Temperature Coefficient of RPOT
(Note 3)
TCRATIO
Ratiometric Temp. Coefficient
(Note 3)
CH/CL/CW
Potentiometer Capacitances
(Note 3)
10/10/25
pF
RPOT = 50 kW (Note 3)
0.4
MHz
fc
Frequency Response
ppm/°C
±100
20
ppm/°C
2. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to VCC +1 V.
3. This parameter is tested initially and after a design or process change that affects the parameter.
4. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
5. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer.
It is a measure of the error in step size.
6. LSB = RTOT / 255 or (RH − RL) / 255, single pot
7. n = 0, 1, 2, ..., 255
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CAT5270
Table 5. DC OPERATING CHARACTERISTICS (VCC = +2.5 V to +5.5 V, unless otherwise specified.)
Parameter
Symbol
Test Conditions
ICC
Power Supply Current
ISB
Standby Current (VCC = 5.0 V)
Min
Max
Units
fSCL = 400 kHz, SDA = Open
VCC = 5.5 V, Inputs = GND
1
mA
VIN = GND or VCC, SDA = Open
5
mA
VIN = GND to VCC
10
mA
VOUT = GND to VCC
10
mA
ILI
Input Leakage Current
ILO
Output Leakage Current
VIL
Input Low Voltage
−1
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 1.0
V
0.4
V
VOL1
Output Low Voltage (VCC = 2.5 V)
IOL = 3 mA
Table 6. CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 5 V)
Symbol
Test
Conditions
Max
Units
CI/O (Note 8)
Input/Output Capacitance (SDA)
VI/O = 0 V
8
pF
CIN (Note 8)
Input Capacitance (A0, A1, A2, A3, SCL, WP)
VIN = 0 V
6
pF
Max
Units
Clock Frequency
400
kHz
Noise Suppression Time Constant at SCL, SDA Inputs
200
ns
1
ms
Table 7. AC CHARACTERISTICS
2.5 V – 5.5 V
Symbol
fSCL
TI (Note 8)
tAA
tBUF (Note 8)
Min
Parameter
SLC Low to SDA Data Out and ACK Out
Time the bus must be free before a new transmission can start
1.2
ms
Start Condition Hold Time
0.6
ms
tLOW
Clock Low Period
1.2
ms
tHIGH
Clock High Period
0.6
ms
tSU:STA
Start Condition Setup Time (for a Repeated Start Condition)
0.6
ms
tHD:DAT
Data in Hold Time
0
ns
tSU:DAT
Data in Setup Time
50
tHD:STA
ns
tR (Note 8)
SDA and SCL Rise Time
0.3
ms
tF (Note 8)
SDA and SCL Fall Time
300
ns
tSU:STO
tDH
Stop Condition Setup Time
0.6
ms
Data Out Hold Time
100
ns
Table 8. POWER UP TIMING (Notes 8 and 9)
Symbol
Parameter
Max
Units
tPUR
Power−up to Read Operation
1
ms
tPUW
Power−up to Write Operation
1
ms
Max
Units
Wiper Response Time After Power Supply Stable
10
ms
Wiper Response Time After Instruction Issued
10
ms
Table 9. WIPER TIMING
Symbol
tWRPO
tWRL
Parameter
8. This parameter is tested initially and after a design or process change that affects the parameter.
9. tPUR and tPUW are delays required from the time VCC is stable until the specified operation can be initiated.
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CAT5270
tHIGH
tF
tR
tLOW
tLOW
SCL
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
SDA IN
tAA
tDH
tBUF
SDA OUT
Figure 2. Bus Timing
Serial Bus Protocol
The following defines the features of the I2C compatible
interface protocol:
1. Data transfer may be initiated only when the bus is
not busy.
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock is high
will be interpreted as a START or STOP condition.
The device controlling the transfer is a master, typically a
processor or controller, and the device being controlled is the
slave. The master will always initiate data transfers and
provide the clock for both transmit and receive operations.
Therefore, the CAT5270 will be considered a slave device
in all applications.
After the Master sends a START condition and the slave
address byte, the CAT5270 monitors the bus and responds
with an acknowledge (on the SDA line) when its address
matches the transmitted slave address.
Slave Address Byte
The most significant four bits of the slave address are a
device type identifier. These bits for the CAT5270 are fixed
at 0101[B] (refer to Figure 5).
The next four bits, A3 − A0, are the internal slave address
and must match the physical device address which is defined
by the state of the A3 − A0 input pins for the CAT5270 to
successfully continue the command sequence. Only the
device which slave address matches the incoming device
address sent by the master executes the instruction. The A3
− A0 inputs can be actively driven by CMOS input signals
or tied to VCC or VSS.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH (see Figure 3). The CAT5270 monitors
the SDA and SCL lines and will not respond until this
condition is met.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data (see Figure 4).
The CAT5270 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8−bit
byte.
When the CAT5270 is in a READ mode it transmits 8 bits
of data, releases the SDA line, and monitors the line for an
acknowledge. Once it receives this acknowledge, the
CAT5270 will continue to transmit data. If no acknowledge
is sent by the Master, the device terminates data transmission
and waits for a STOP condition.
If the device has been selected with an IN/DEC operation
it will no longer responds with acknoleadge as the received
data it is not in a byte format.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition (see Figure 3). All
operations must end with a STOP condition.
Device Addressing
The bus Master begins a transmission by sending a
START condition. The Master then sends the Slave Addres
Byte which contains the address of the particular slave
device it is requesting. The four most significant bits of the
8−bit slave address are fixed as 0101 for the CAT5270. The
next four significant bits (A3, A2, A1, A0) are the device
address bits and define which device the Master is accessing
(see Figure 5). Up to sixteen devices may be individually
addressed by the system. Typically, +5 V (VCC) and ground
are hard−wired to these pins to establish the device’s
address.
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CAT5270
SDA
SCL
START CONDITION
STOP CONDITION
Figure 3. Start/Stop Condition
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACKNOWLEDGE
START
Figure 4. Acknowledge Condition
Device Type
Identifier
CAT5270
ID3
0
Slave Address
ID2
ID1
1
0
ID0
A3
A2
A1
A0
1
(MSB)
(LSB)
Figure 5. Identification Format for Slave Address Byte
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CAT5270
Instruction and Register Description
Increment/Decrement Command
The last command is Increment/Decrement (Figures 9 and
10). The Increment/Decrement command is different from
the other commands. Once the instruction is issued and the
CAT5270 has responded with an acknowledge, the master
can clock the selected wiper up and/or down in one segment
steps; thereby providing a fine tuning capability to the host.
For each SCL clock pulse (tHIGH) while SDA is HIGH, the
selected wiper will move one resistor segment towards the
RH terminal. Similarly, for each SCL clock pulse while SDA
is LOW, the selected wiper will move one resistor segment
towards the RL terminal.
See Instructions format for more details.
Instruction Byte
The next byte sent to the CAT5270 contains the
instruction and register pointer information. The four most
significant bits used provide the instruction opcode I3 − I0.
Instructions
Instructions are three bytes in length. These instructions are:
− Read Wiper Control Register – read the current wiper
position of the selected potentiometer in the WCR
− Write Wiper Control Register – change current wiper
position in the WCR of the selected potentiometer
− Increment/Decrement Wiper Control Register –
change step by step the current wiper position in the
WCR of the selected potentiometer
The basic sequence of the three byte instructions is
illustrated in Figure 8.
Wiper Control Register (WCR)
The CAT5270 contains two 8−bit Wiper Control
Registers, one for each potentiometer. The Wiper Control
Register output is decoded to select one of 256 switches
along its resistor array. The contents of the WCR can be
altered in two ways: it may be written by the host via Write
Wiper Control Register instruction; or it can be modified one
step at a time by the Increment/decrement instruction (see
Instruction section for more details).
Write Operation
In the Write mode, the Master device sends the START
condition and the slave address information to the Slave
device. After the Slave generates an acknowledge, the
Master sends the instruction byte that defines the requested
operation of CAT5270. The instruction byte consists of a
seven−bit opcode followed by pot/register selection bit.
After receiving another acknowledge from the Slave, the
Master device transmits the data to be written into the
selected register. The CAT5270 acknowledges once more
and the Master generates the STOP condition.
P
WCR
0
Set R0 wiper position
1
Set R1 wiper position
The Wiper Control Register is a volatile register that loses
its contents when the CAT5270 is powered−down. Upon
power−up, the wiper is set to midspan and may be
repositioned anytime after the power has become stable.
WCR Pot
Selector
Instruction
Opcode
I3
I2
I1
I0
0
0
0
P0
(LSB)
(MSB)
Figure 6. Instruction Byte Format
Table 10. INSTRUCTION SET
Instruction Set (Note 10)
Instruction
I3
I2
I1
I0
F2
F1
F0
WCR/P
Read Wiper Control Register
1
0
0
1
0
0
0
1/0
Read the contents of the Wiper Control
Register pointed to by P
Write Wiper Control Register
1
0
1
0
0
0
0
1/0
Write new value to the Wiper Control
Register pointed to by P
Increment/Decrement Wiper
Control Register
0
0
1
0
0
0
0
1/0
Enable Increment/decrement of the
Control Latch pointed to by P
10. 1/0 = data is one or zero
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Operation
CAT5270
SDA
0
1
0
1
S ID3I D2 ID1ID0 A3 A2 A1 A0 A
T
C
A
K
Device ID
Internal
R
T
Address
1
0
1
I3
I2
I1 I0 F2 F1 F0 P
0
0
0
0
A
C
K
Fixed Pot/WCR
Instruction
Opcode
D7 D6 D5 D4 D3 D2 D1 D0 A
C
K
WCR[7:0]
S
T
O
P
Figure 7. Write Instruction Sequence
SDA
0
1
0
1
S ID3I D2 ID1ID0 A3 A2 A1 A0 A
T
C
A
K
Device ID
Internal
R
T
Address
1
0
0
1
1
0
0
I3
I2
I1 I0 F2 F1 F0 P
0
A
C
K
Fixed Pot/WCR
Instruction
Opcode
D7 D6 D5 D4 D3 D2 D1 D0 A
C
K
Data Register D[7:0]
S
T
O
P
Figure 8. Read Instruction Sequence
SDA
0
1
0
1
S ID3I D2 ID1ID0 A3
T
A
Device ID
R
T
A2 A1 A0 A
C
K
Internal
Address
0
0
1
0
0
0
0
I3
I2
I1
I0 F2 F1 F0 P
A
C
K
Fixed Pot/WCR
Instruction
Opcode
I
N
C
1
I
N
C
2
Figure 9. Increment/Decrement Instruction Sequence
INC/DEC
Command
Issued
I
N
C
n
D
E
C
1
D
E
C
n
S
T
O
P
No Fixed Length
tWRL
SCL
SDA
Voltage Out
RW
Figure 10. Increment/Decrement Timing Limits
Instruction Format
Read Wiper Control Register (WCR)
S
T
A
R
T
DEVICE ADDRESSES
0
1
0
1
A3
A2
A1
A0
A
C
K
INSTRUCTION
1
0
0
1
0
0
0
P
A
C
K
DATA
7
6
5
4
3
2
1
0
A
C
K
S
T
O
P
A
C
K
S
T
O
P
Write Wiper Control Register (WCR)
S
T
A
R
T
DEVICE ADDRESSES
0
1
0
1
A3
A2
A1
A0
A
C
K
INSTRUCTION
1
0
1
0
0
0
0
P
A
C
K
DATA
7
6
5
4
3
2
1
0
Increment (I)/Decrement (D) Wiper Control Register (WCR)
S
T
A
R
T
DEVICE ADDRESSES
0
1
0
1
A3
A2
A1
A0
A
C
K
INSTRUCTION
0
0
1
0
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0
0
0
P
A
C
K
DATA
I
/
D
I
/
D
..
.
I
/
D
I
/
D
S
T
O
P
CAT5270
ORDERING INFORMATION
Part Number
Resistance
Lead Finish
Package
Shipping†
CAT5270YI−50−GT2
50 kW
NiPdAu
CAT5270YI−00−GT2
100 kW
TSSOP−14
(Pb−Free)
2000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
11. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com.
12. All packages are RoHS−compliant (Pb−Free, Halogen−Free).
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CAT5270
PACKAGE DIMENSIONS
TSSOP14, 4.4x5
CASE 948AM−01
ISSUE O
b
SYMBOL
MIN
NOM
A
E1 E
MAX
1.10
A1
0.05
0.15
A2
0.85
0.95
b
0.19
0.30
c
0.13
0.20
D
4.90
5.10
E
6.30
6.50
E1
4.30
4.50
e
0.65 BSC
L
1.00 REF
L1
0.45
0.75
θ
0º
8º
e
PIN#1
IDENTIFICATION
TOP VIEW
D
A2
A
θ1
L1
A1
SIDE VIEW
END VIEW
L
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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PUBLICATION ORDERING INFORMATION
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CAT5270/D
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