1/4-Inch SOC VGA CMOS Digital Image Sensor

MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Features
1/4-Inch SOC VGA CMOS Digital Image Sensor
MT9V131 Datasheet, Rev. H
For the latest datasheet revision, please visit www.onsemi.com
Features
Table 1:
• System-on-a-Chip (SOC)—Completely integrated
camera system
• Ultra low-power, cost effective CMOS image sensor
• Superior low-light performance
• Up to 30 fps progressive scan at 27 MHz for highquality video at VGA resolution
• On-chip image flow processor (IFP) performs
sophisticated processing: color recovery and
correction, sharpening, gamma, lens shading
correction, on-the-fly defect correction, 2X fixed
zoom
• Image decimation to arbitrary size with smooth,
continuous zoom and pan
• Automatic exposure, white balance and black
compensation, flicker avoidance, color saturation,
and defect identification and correction, auto frame
rate, back light compensation
• Xenon and LED-type flash support
• Two-wire serial programming interface
• Progressive ITU_R BT.656 (YCbCr), YUV, 565RGB,
555RGB, and 444RGB output data formats
Key Performance Parameters
Parameter
Typical Value
Optical Format
1/4-inch (4:3)
3.58 mm (H) x 2.69 mm (V)
Active Imager Size
4.48 mm (Diagonal)
Active Pixels
640H x 480V (VGA)
Pixel Size
5.6 m x 5.6m
Color Filter Array
RGB Bayer Pattern
Shutter Type
Electronic Rolling Shutter (ERS)
Maximum Data Rate Master 1213.5 Mp/s
Clock
2427 MHz
15 fps at 12 MHz (default),
VGA (640 x 480)
programmable up to 30 fps
Frame
at 27 MHz
Rate
CIF (352 x 288)
Programmable up to 60 fps
QVGA (320 x 240) Programmable up to 90 fps
ADC Resolution
10-bit, on-chip
Responsivity
1.9 V/lux-sec (550nm)
Dynamic Range
60 dB
SNRMAX
45 dB
Supply Voltage
2.8 V +0.25 V
Power Consumption
<80 mW at 2.8 V, 15 fps at 12 MHz
Operating Temperature
-20°C to +70°C
Packaging
48-Pin CLCC
Applications
• Security
• Biometrics
• Toys
General Description
The ON Semiconductor MT9V131 is a 1/4-inch VGAformat CMOS active-pixel digital image sensor, the
result of combining the MT9V011 image sensor core
with ON Semiconductor's third-generation digital
image flow processor technology. The MT9V131 has an
active imaging pixel array of 649 x 489, capturing highquality color images at VGA resolution.
The sensor is a complete camera-on-a-chip solution
and is designed specifically to meet the demands of
products such as surveillance cameras. It incorporates
sophisticated camera functions on-chip and is programmable through a simple two-wire serial interface.
MT9V131_DS Rev. H 4/15 EN
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©Semiconductor Components Industries, LLC,2015
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Ordering Information
Ordering Information
Table 2:
Available Part Numbers
Part Number
Product Description
Orderable Product Attribute Description
MT9V131C12STC-DR
VGA 1/4" SOC
Dry Pack without Protective Film
MT9V131C12STC-TR
VGA 1/4" SOC
Tape & Reel without Protective Film
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©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Image Flow Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Output Data Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Sensor Core Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Propagation Delays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Appendix A – Sensor Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Serial Bus Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Two-Wire Serial Interface Sample Write and Read Sequences
(with Saddr = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Appendix B – Overview of Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
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©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
List of Figures
List of Figures
Figure 1:
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Figure 26:
Figure 27:
Chip Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Internal Register Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Typical Configuration (Connection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
48-Pin CLCC Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Image Flow Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Sensor Core Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Pixel Array Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Pixel Color Pattern Detail (Top Right Corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Spatial Illustration of Image Readout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Propagation Delays for PIXCLK and Data Out Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Propagation Delays for FRAME_VALID and LINE_VALID Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Data Output Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Typical Spectral Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Die Center – Image Center Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Chief Ray Angle (CRA) vs. Image Height . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Row Timing and FRAME_VALID/LINE_VALID Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Timing Diagram Showing a Write to R0x09 with Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Timing Diagram Showing a Read from R0x09; Returned Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . .24
Timing Diagram Showing a Bytewise Write to R0x09 with Value 0x0284. . . . . . . . . . . . . . . . . . . . . . . .25
Timing Diagram Showing a Bytewise Read from R0x09; Returned Value 0x0284 . . . . . . . . . . . . . . . .25
Serial Host Interface Start Condition Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Serial Host Interface Stop Condition Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Serial Host Interface Data Timing for Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Serial Host Interface Data Timing for Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Acknowledge Signal Timing After an 8-bit Write to the Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Acknowledge Signal Timing After an 8-bit Read from the Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
48- Pin CLCC Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
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©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
List of Tables
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Key Performance Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Available Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Pin Description for the CLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
YUV/YCbCr Output Data Ordering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
RGB Output Data Ordering in Default Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Byte Ordering in 8 + 2 Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Frame Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Frame Time – Larger than One Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Non-Default Register Settings Optimizing 15 fps at 12 MHz Operation . . . . . . . . . . . . . . . . . . . . . . . .28
Non-Default Register Settings Optimizing 30 fps at 27 MHz Operation . . . . . . . . . . . . . . . . . . . . . . . .28
Relation Between IFP R0x37[9:5] Setting and Frame Rate Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Decimation, Zoom, and Pan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
YCbCr Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
YUV Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
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©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
General Description
General Description
This SOC VGA CMOS image sensor features ON Semiconductor’s breakthrough, lownoise CMOS imaging technology that achieves CCD image quality (based on signal-tonoise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of CMOS.
The MT9V131 is a fully-automatic, single-chip camera, requiring only a power supply,
lens, and clock source for basic operation. Output video is streamed through a parallel 8bit DOUT port, as shown in Figure 1. The output pixel clock is used to latch the data,
while FRAME_VALID (FV) and LINE_VALID (LV) signals indicate the active video. The
sensor can be put in an ultra-low power sleep mode by asserting the STANDBY pin.
Output signals can also be tri-stated by de-asserting the OE_BAR pin. The MT9V131
internal registers can be configured using a two-wire serial interface.
The MT9V131 can be programmed to output progressive scan images up to 30 fps in an
8-bit ITU_R BT.656 (YCbCr) formerly CCIR656, YUV, 565RGB, 555RGB, or 444RGB
formats. 10-bit raw Bayer data output can also be selected. The FV and LV signals are
output on dedicated pins, along with a pixel clock (PIXCLK) that is synchronous with
valid data.
Figure 1:
Chip Block Diagram
SCLK
SDATA
SADDR
CLK
STANDBY
OE_BAR
VDD/DGND
VAA/AGND
VAA_PIX
Communication Bus
Image Flow Processor
Sensor Core
. Based on MT9V011
. 668H x 496V (VGA+ Reference)
. 1/4-inch optical format
. Auto black compensation
. Programmable analog gain
. Programmable exposure
. Low power, 10-bit ADCs
. Color correction, gamma,
DOUT[7:0]:DOUT_LSB[1:0]
lens shading correction
. Auto exposure, white balance
. Interpolation and defect
correction
. Flicker avoidance
PIXCLK
FRAME_VALID
LINE_VALID
FLASH
SRAM Line Buffers
The MT9V131 can accept an input clock of up to 27 MHz, delivering 30 fps. With
power-on defaults (see Appendix B on page 28 for recommended defaults), the camera is
configured to deliver 15 fps at 12 MHz and automatically slows down the frame rate in
low-light conditions to achieve longer exposures and better image quality.
Internally, the MT9V131 consists of a sensor core and an image flow processor (IFP). The
sensor core functions to capture raw Bayer-encoded images that are input into the IFP
as shown in Figure 1. The IFP processes the incoming stream to create interpolated,
color-corrected output and controls the sensor core to maintain the desirable exposure
and color balance.
Sensor core and IFP registers are grouped into two separate address spaces, as shown in
Figure 2 on page 7. The internal registers can be accessed through the two-wire serial
interface. Selecting the desired address space can be accomplished by programming
register R0x01, which remains present in both register sets.
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©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
General Description
Figure 2:
Internal Register Grouping
Note:
R0x00
R0x01
R0x00
R0x01
Sensor Core
Registers
(R0x02..R0xFF)
IFP
Registers
(R0x02..R0xFF)
R0x01 = 0b0100
R0x01 = 0b0001
Program R0x01 to select the desired space (0b0100 = sensor core registers, 0b0001 = IFP/SOC registers).
Figure 3 shows MT9V131 typical connections. For low-noise operation, the MT9V131
requires separate supplies for analog and digital power. Incoming digital and analog
ground conductors can be tied together right next to the die. Both power supply rails
should be decoupled to ground using capacitors. The use of inductance filters is not
recommended.
Figure 3:
Typical Configuration (Connection)
V DD
V DD
V AA
VAA_PIX
ADC_TEST
V AA
1.5KΩ
SADDR
1.5KΩ
1KΩ
RESET_BAR
{
Master
Clock
DOUT[7:0]:DOUT_LSB[1:0]
FRAME_ VALI D
LINE_VALI D
PIXCLK
SDATA
SCLK
{
10μF
Two-wir e
serial bus
To CMO S
camera port
EXTCLK
FLASH
To Xenon flas h
trigger or LED enable
DNU
DGND
Note:
MT9V131_DS Rev. H 4/15 EN
A GND
STANDB Y
D GND
OE_BAR
A GND
ON Semiconductor recommends a 1.5K resistor value, but it may be greater for slower two-wire
speed.
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©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Pin Assignment
Pin Assignment
MT9V131_DS Rev. H 4/15 EN
47
46
DGND
48
DOUT7
1
VDD
2
DOUT6
3
VDD
DOUT5
4
DGND
DOUT2
5
DOUT4
DGND
6
DOUT3
NC
48-Pin CLCC Pinout Diagram
45
44
43
NC
DOUT_LSB1
10
39
DNU
DOUT_LSB0
11
38
DGND
DGND
12
37
VDD
FLASH
13
36
DGND
PIXCLK
14
35
OE_BAR
LINE_VALID
15
34
STANDBY
FRAME_VALID
16
33
RESET_BAR
VDD
17
32
VAA_PIX
NC
18
31
ADC_TEST
21
SCLK
20
EXTCLK
19
22
23
24
25
26
27
28
29
30
NC
VDD
AGND
40
VAA
9
AGND
VDD
DOUT0
VAA
41
VDD
8
DGND
42
DOUT1
SADDR
7
SDATA
VDD
DGND
Figure 4:
8
©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Pin Assignment
Table 3:
Pin Description for the CLCC Package
Pin Number
Pin Name
Type
Description
20
EXTCLK
Input
Master clock into sensor. Default is 12 MHz (27 MHz maximum).
21
SCLK
Input
Serial clock.
23
SADDR
Input
Serial interface address select: R0xB8 when HIGH (default).
R0x90 when LOW.
31
ADC_TEST
Input
Tie to Vaa_PIX (factory use only).
33
RESET_BAR
Input
Asynchronous reset of sensor when LOW. All registers assume factory defaults.
34
STANDBY
Input
When HIGH, puts the imager in ultra-low power standby mode.
35
OE_BAR
Input
Output_Enable pin. When HIGH, tri-state all outputs except SDATA (tie LOW for
normal operation).
39
DNU
Input
22
SDATA
I/O
Tie to digital ground.
Serial data I/O.
13
FLASH
Output
Flash strobe.
14
PIXCLK
Output
Pixel clock out. Pixel data output are valid during rising edge of this clock. IFP
R0x08 [9] inverts polarity.
Frequency = Master clock.
15
LINE_VALID
Output
Active HIGH during line of selectable valid pixel data.
16
FRAME_VALID
Output
Active HIGH during frame of valid pixel data.
45
DOUT7
Output
ITU_R BT.656/RGB data bit 7 (MSB).
46
DOUT6
Output
ITU_R BT.656/RGB data bit 6.
1
DOUT5
Output
ITU_R BT.656/RGB data bit 5.
2
DOUT4
Output
ITU_R BT.656/RGB data bit 4.
3
DOUT3
Output
ITU_R BT.656/RGB data bit 3.
4
DOUT2
Output
ITU_R BT.656/RGB data bit 2.
8
DOUT1
Output
ITU_R BT.656/RGB data bit 1.
9
DOUT0
Output
ITU_R BT.656/RGB data bit 0 (LSB).
10
DOUT_LSB1
Output
Raw Bayer 10-bit output.
Raw Bayer 10-bit output (LSB).
11
DOUT_LSB0
Output
7, 17, 25, 37, 40, 41,
44, 47
26, 28
VDD
Supply
VAA
Supply
Analog power (2.8V).
32
VAA_PIX
Supply
Pixel array power (2.8V).
27, 29
AGND
Supply
Analog ground.
5, 12, 19, 24, 36, 38,
43, 48
6, 18, 30, 42
DGND
Supply
NC
–
MT9V131_DS Rev. H 4/15 EN
Digital power (2.8V).
Digital ground.
No connect.
9
©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Image Flow Processor
Image Flow Processor
Overview of Architecture
The IFP consists of a color processing pipeline and a measurement and control logic
block, as shown in Figure 5 on page 11. The stream of raw data from the sensor enters
the pipeline and undergoes a number of transformations. Image stream processing
starts from conditioning the black level and applying a digital gain. The lens shading
block compensates for signal loss caused by the lens. Next, the data is interpolated to
recover missing color components for each pixel and defective pixels are corrected. The
resulting interpolated RGB data passes through the current color correction matrix
(CCM), gamma, and saturation corrections and is formatted for final output.
The measurement and control logic continuously accumulates statistics about image
brightness and color. Indoor 50/60 Hz flicker is detected and automatically updated
when possible. Based on these measurements, the IFP calculates updated values for
exposure time and sensor analog gains, which are sent to the sensor core through the
communication bus.
Color correction is achieved through a linear transformation of the image with a 3 x 3
color correction matrix. Color saturation can be adjusted in the range from zero (black
and white) to 1.25 (125% of full color saturation).
Gamma correction compensates for nonlinear dependence of the display device output
versus driving signal (monitor brightness versus CRT voltage).
Output and Formatting
Processed video can be output in the form of a progressive ITU_R BT.656 or RGB stream.
The ITU_R BT.656 (default) stream contains 4:2:2 data with optional embedded synchronization codes. This kind of output is typically suitable for subsequent display by standard video equipment. For JPEG/MPEG compression, YUV/ encoding is suitable. RGB
functionality is provided to support LCD devices. The MT9V131 can be configured to
output 16-bit RGB (565RGB) and 15-bit RGB (555RGB), as well as two types of 12-bit RGB
(444RGB). The user can configure internal registers to swap odd and even bytes, chrominance channels, and luminance and chrominance components to facilitate interfacing
to application processors.
MT9V131_DS Rev. H 4/15 EN
10
©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Image Flow Processor
Figure 5:
Image Flow Processor Block Diagram
IMAGE SENSOR
LENS CORRECTION
DEMOSAICING
AE, AWB,
FLICKER AVOIDANCE
COLOR CORRECTION
FLASH CONTROL
GAMMA CORRECTION
OUTPUT FORMATTING
The MT9V131 features smooth, continuous zoom and pan. This functionality is available when the IFP output is downsized in the decimation block. The decimation block
can downsize the original VGA image to any integer size, including QVGA, QQVGA, CIF,
and QCIF with no loss to the field of view. The user can program the desired size of the
output image in terms of horizontal and vertical pixel count. In addition, the user can
program the size of a region for downsizing. Continuous zoom is achieved every time the
region of interest is less than the entire VGA image. The maximum zoom factor is equal
to the ratio of VGA to the size of the region of interest. For example, an image rendered
on a 160 x 120 display can be zoomed by 640/160 = 480/120 = 4 times. Continuous pan is
achieved by adjusting the starting coordinates of the region of interest.
Also, a fixed 2X up-zoom is implemented by means of windowing down the sensor core.
In this mode, the IFP receives a QVGA-sized input data and outputs a VGA-size image.
The sub-window can be panned both vertically and horizontally by programming sensor
core registers.
The MT9V131 supports both LED and xenon-type flash light sources using a dedicated
output pad. For xenon devices, the signal generates a strobe to fire when the imager's
shutter is fully open. For LED, the signal can be asserted or de-asserted asynchronously.
Flash modes are configured and engaged over the two-wire serial interface using IFP
R0x98.
MT9V131_DS Rev. H 4/15 EN
11
©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Output Data Ordering
Output Data Ordering
In YCbCr the first and second bytes can be swapped. Luma/chroma bytes can be
swapped as well. R and B channels are bit-wise swapped when chroma swap is enabled.
See IFP R0x3A for channel swapping configuration.
Table 4:
YUV/YCbCr Output Data Ordering
Mode
1st Byte
2nd Byte
Default (no swap)
Cbi
Swapped CrCb
Cri
Swapped YC
Swapped CrCb, YC
Table 5:
3rd Byte
4th Byte
Yi
Cri
Yi+1
Yi
Cbi
Yi+1
Yi
Cbi
Yi+1
Cri
Yi
Cri
Yi+1
Cbi
RGB Output Data Ordering in Default Mode
Mode (Swap Disabled)
Byte
D7
D6
D5
D4
D3
D2
D1
D0
565RGB
First
Second
First
Second
First
Second
First
Second
R7
G4
0
G4
R7
B7
0
G7
R6
G3
R7
G3
R6
B6
0
G6
R5
G2
R6
G2
R5
B5
0
G5
R4
B7
R5
B7
R4
B4
0
G4
R3
B6
R4
B6
G7
0
R7
B7
G7
B5
R3
B5
G6
0
R6
B6
G6
B4
G7
B4
G5
0
R5
B5
G5
B3
G6
B3
G4
0
R4
B4
555RGB
444xRGB
x444RGB
A bypass mode is available whereby raw Bayer 10-bits data is output as two bytes. See
IFP R0x08[7].
Table 6:
Byte Ordering in 8 + 2 Bypass Mode
Byte Ordering
8+2 Bypass
MT9V131_DS Rev. H 4/15 EN
First
Second
D9
0
D8
0
D7
0
12
D6
0
D5
0
D4
0
D3
D1
D2
D0
©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Sensor Core Overview
Sensor Core Overview
The sensor consists of a pixel array of 668 x 496 total, analog readout chain, 10-bit ADC
with programmable gain and black offset, and timing and control.
Figure 6:
Sensor Core Block Diagram
Control Register
Active Pixel
Sensor Array
Communication
Bus to IFP
Timing and Control
Clock
Sync. Signals
Analog Processing
10-bit Data
to IFP
ADC
The sensor core’s pixel array is configured as 668 columns by 496 rows (shown in
Figure 7). The first 18 columns and the first 6 rows of pixels are optically black and can be
used to monitor the black level. The last column and the last row of pixels are also optically black. The black row data is used internally for the automatic black level adjustment. There are 649 columns by 489 rows of optically active pixels, which provides a
four-pixel boundary around the VGA (640 x 480) image to avoid boundary affects during
color interpolation and correction. The additional active column and additional active
row are used to allow horizontally and vertically mirrored readout to also start on the
same color pixel, as shown in Figure 7.
Figure 7:
Pixel Array Description
(0, 0)
6 black rows
1 black column
VGA (640 x 480)
+ 4 pixel boundary for
color correction
+ additional active column
+ additional active row
= 649 x 489 active pixels
(667,495)
18 black columns
1 black row
The sensor core uses the RGB Bayer color pattern (shown in Figure 8 on page 14). Evennumbered rows contain green and red color pixels, and odd-numbered rows contain
blue and green color pixels. Even-numbered columns contain green and blue color
pixels; odd- numbered columns contain red and green color pixels.
MT9V131_DS Rev. H 4/15 EN
13
©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Sensor Core Overview
Figure 8:
Pixel Color Pattern Detail (Top Right Corner)
column readout direction
..
.
row
readout
direction
...
black pixels
G
R
G
R
G
R
G
B
G
B
G
B
G
B
G
R
G
R
G
R
G
B
G
B
G
B
G
B
G
R
G
R
G
R
G
B
G
B
G
B
G
B
Pixel
(18,6)
(First Optical
clear pixel)
..
.
The sensor core image data is read-out in a progressive scan. Valid image data is
surrounded by horizontal and vertical blanking, as shown in Figure 9. The amount of
horizontal and vertical blanking is programmable through the sensor core registers
R0x05 and R0x06, respectively. LINE_VALID is HIGH during the shaded region of the
figure. See “Appendix A – Sensor Timing” on page 21 for the description of
FRAME_VALID timing.
Figure 9:
Spatial Illustration of Image Readout
P0,0 P0,1 P0,2.....................................P0,n-1 P0,n
P1,0 P1,1 P1,2.....................................P1,n-1 P1,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
HORIZONTAL
BLANKING
VALID IMAGE
Pm-1,0 Pm-1,1.....................................Pm-1,n-1 Pm-1,n
Pm,0 Pm,1.....................................Pm,n-1 Pm,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
VERTICAL/HORIZONTAL
BLANKING
VERTICAL BLANKING
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
Notes:
MT9V131_DS Rev. H 4/15 EN
1. Do not change these registers. Contact ON Semiconductor support for settings different from
defaults.
2. IFP controls these registers when AE, AWB, or flicker avoidance are enabled.
14
©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Electrical Specifications
Electrical Specifications
The recommended operating temperature ranges from –20°C to +70°C. The sensor
image quality may degrade above +40°C.
Table 7:
DC Electrical Characteristics
VDD = VAA = 2.8 ± 0.25V; TA = 25°C
Definition
Symbol
Input high voltage
VIH
Input low voltage
VIL
IIN
Input leakage current
Condition
No pull-up resistor; VIN = VDD or
DGND
Max
Unit
VDD - 0.25
Min
Typ
VDD + 0.25
V
–0.3
0.8
V
–5.0
5.0
A
VDD - 0.2
V
Output high voltage
VOH
Output low voltage
VOL
0.2
V
Output high current
IOH
15.0
mA
Output low current
IOL
20.0
mA
Tri-state output leakage current
IOZ
5.0
A
IAA
Analog standby supply current
IAA Standby
Default settings, CLOAD = 10pF
CLKIN = 12 MHz
CLKIN = 27 MHz
Default settings, CLOAD = 10pF
CLKIN = 12 MHz
CLKIN = 27 MHz
STDBY = VDD
Digital standby supply current
IDD Standby
STDBY = VDD
Analog operating supply current
IDD
Digital operating supply current
Notes:
MT9V131_DS Rev. H 4/15 EN
10.0
10.0
20.0
20.0
25.0
25.0
mA
5.0
10.0
0.0
8.0
15.0
2.5
20.0
20.0
5.0
mA
0.0
2.5
5.0
A
A
1. To place the chip in standby mode, first raise STANDBY to VDD, then wait two master clock cycles
before turning off the master clock. Two master clock cycles are required to place the analog circuitry into standby, low-power mode.
2. When STANDBY is de-asserted, standby mode is exited immediately (within several master clocks),
but the current frame and the next two frames will be invalid. The fourth frame will contain a valid
image.
15
©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Electrical Specifications
Table 8:
AC Electrical Characteristics
VDD = VAA = 2.8 ± 0.25V; TA = 25°C
Definition
Symbol
Input clock frequency
f
Condition
CLKIN
Clock duty cycle
50:50
t
Input clock rise time
t
Input clock fall time
F
CLKIN to PIXCLK propagation delay
PIXCLK to DOUT[7:0] at 27 MHz
PIXCLK to FRAME_VALID and
LINE_VALID propagation delay
LOW-to-HIGH
t
HIGH-to-LOW
t
PLHP
t
Hold time
t
DSETUP
tPLH
HIGH-to-LOW
t
Output fall time
Notes:
Unit
10
12
27
MHz
45
50
55
%
1
2
5
ns
1
2
5
ns
12
14
ns
6
10
14
ns
CLOAD = 10pF
11
18
–
ns
CLOAD = 10pF
F,L
Max
6
DHOLD
LOW-to-HIGH
Typ
CLOAD = 10pF
PHLP
Setup time
PHLF,L
tOUT
R
tOUT
F
Output rise time
MT9V131_DS Rev. H 4/15 EN
R
Min
11
18
–
ns
4
9.0
13
ns
4
7.5
13
ns
CLOAD = 10pF
5
7.0
15
ns
CLOAD = 10pF
5
9.0
15
ns
Notes
1
3
2
1. For 30 fps operation with a 27 MHz clock, the user must have a precise duty cycle equal to 50%.
With a slower frame rate and a slower clock, the clock duty cycle can be relaxed.
2. Typical is 1/2 of CLKIN period.
3. PIXCLK can be programmed to be inverted or non-inverted.
16
©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Propagation Delays
Propagation Delays
Propagation Delays for PIXCLK and Data Out Signals
The output PIXCLK delay, relative to the master clock (CLKIN), is typically 10–12ns. Note
that the data outputs change on the rising edge of the master clock (CLKIN) as shown in
in Figure 10. PIXCLK by default is inverted from CLKIN but can be programmed to be
non-inverted.
Figure 10:
Propagation Delays for PIXCLK and Data Out Signals
tR
tF
CLK_IN
tPLHP
tPLHP
PIXCLK
tOH
DOUT (7:0)
Note:
DOUT (7:0)
DOUT (7:0)
DOUT (7:0)
DOUT (7:0)
Default condition of the IPA register R0x08[9] = 0.
Propagation Delays for FRAME_VALID and LINE_VALID Signals
The LINE_VALID and FRAME_VALID signals change on the same clock edge as the data
output. The LINE_VALID goes HIGH on the same falling master clock edge as the output
of the first valid pixel’s data and returns LOW on the same master clock falling edge as
the end of the output of the last valid pixel’s data. The default timing of PIXCLK with
respect to LINE_VALID and FRAME_VALID is shown in Figure 11.
Figure 11:
Propagation Delays for FRAME_VALID and LINE_VALID Signals
tPLHF,L
MT9V131_DS Rev. H 4/15 EN
tPHLF,L
CLKIN
CLKIN
FRAME_VALID
LINE_VALID
FRAME_VALID
LINE_VALID
17
©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Propagation Delays
Output Data Timing
As shown in Figure 12, FRAME_VALID goes HIGH 6 pixel clocks prior to the time that the
first LINE_VALID goes HIGH. It returns LOW at a time corresponding to 6 pixel clocks
after the last LINE_VALID goes LOW.
Figure 12:
Data Output Timing Diagram
PIXCLK
FRAME_VALID
tLVHOLD
tLVSETUP
LINE_VALID
DOUT(7:0)
tFVHOLD
tFVSETUP
tDSETUP
Cb0
Y0
Cr0
Y1
Ylast
Cb0
Ylast
Cb0
tDHOLD
Notes:
MT9V131_DS Rev. H 4/15 EN
1.
2.
3.
4.
5.
6.
7.
PIXCLK = 27 MHz (MAX)
tFVSETUP = / setup time for FRAME_VALID before falling edge of PIXCLK / = 18ns
tFVHOLD = / hold time for FRAME_VALID after falling edge of PIXCLK / = 18ns
tLVSETUP = / setup time for LINE_VALID before falling edge of PIXCLK / = 18ns
tLVHOLD = / hold time for LINE_VALID after falling edge of PIXCLK / = 18ns
tDSETUP = / setup time for DOUT before falling edge of PIXCLK / = 18ns
tDHOLD = / hold time for DOUT after falling edge of PIXCLK / = 18ns
Frame start: FF00 00A0
Line start: FF00 0080
Line end: FF00 0090
Frame end: FF00 00B0
8. Drawing shown has R0x08[9] = 1
18
©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Propagation Delays
Figure 13:
Typical Spectral Characteristics
50
Quantum Efficiency (%)
45
Blue
40
Green
35
Red
30
25
20
15
10
5
0
350
450
550
650
750
850
950
1050
Wavelength (nm)
Figure 14:
Die Center – Image Center Offset
- Direction
+ Direction
0
11.0um
Die
Center
+ Direction
ARRAY
0
-91.3um
- Direction
Pixel Array Center
Pixel (0, 0)
Note:
MT9V131_DS Rev. H 4/15 EN
Not to scale.
19
©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Propagation Delays
Figure 15:
Chief Ray Angle (CRA) vs. Image Height
Image Height
CRA vs. Image Height Plot
MT9V131 CRA Design
30
28
26
24
22
20
CRA (deg)
18
16
14
12
10
8
6
4
2
0
MT9V131_DS Rev. H 4/15 EN
20
(%)
(mm)
CRA
(Deg)
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
0
0.112
0.224
0.336
0.448
0.560
0.672
0.784
0.896
1.008
1.120
1.232
1.344
1.456
1.568
1.680
1.792
1.904
2.016
2.128
2.240
0
1.46
2.92
4.38
5.84
7.30
8.75
10.21
11.67
13.13
14.59
16.05
17.51
18.97
20.43
21.89
23.34
24.80
26/26
27.72
29.18
©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Appendix A – Sensor Timing
Appendix A – Sensor Timing
Figure 16:
Row Timing and FRAME_VALID/LINE_VALID Signals
...
FRAME_VALID
...
LINE_VALID
...
Number of master clocks
Note:
Table 9:
P1
A
Q
A
Q
A
P2
The signals in Figure 16 are defined in Table 9.
Frame Time
Parameter
Name
Equation (Master Clocks)
Default Timing
At 12 MHz
A
Active data time
(R0x04 - 7) x 2
= 1,280 pixel clocks
= 1,280 master clocks
= 106.7s
P1
Frame start blanking
(R0x05 + 112) x 2
= 300 pixel clocks
= 300 master clocks
= 25.0s
P2
Frame end blanking
14 CLKS
= 14 pixel clocks
= 14 master clocks
= 1.17s
Q
Horizontal blanking
(R0x05 + 121) x 2
(MIN R0x05 value = 9)
= 318 pixel clocks
= 318 master clocks
= 26.5s
A+Q
Row time
(R0x04 + R0x05 +114) x 2
= 1,598 pixel clocks
= 1,598 master clocks
= 133.2s
V
Vertical blanking
(R0x06 + 9) x (A + Q) + (Q - P1 - P2)
= 20,778 pixel clocks
= 20,778 master clocks
= 1.73ms
Nrows x (A + Q)
Frame valid time
(R0x03 - 7) x (A + Q) - (Q - P1 - P2)
= 767,036 pixel clocks
= 767,036 master clocks
= 63.92ms
F
Total frame time
(R0x03 + R0x06 + 2) x (A + Q)
= 787,814 pixel clocks
= 787,814 master clocks
= 65.65ms
Note:
In order to avoid flicker, frame time is 65.65ms.
Sensor timing is shown above in terms of master clock cycle. The vertical blanking and
total frame time equations assume that the number of integration rows (bits 11 through
0 of R0x09) is less than the number of active row plus blanking rows
(R0x03 + 1 + R0x06 + 1). If this is not the case, the number of integration rows must be
used instead to determine the frame time, as shown in Table 10.
Table 10:
Frame Time – Larger than One Frame
Parameter
Name
Equation (Master Clocks)
Default Timing
V’
Vertical blanking (long integration time)
(R0x09 - R0x03) x (A + Q)
F’
Total Frame Time (long integration time)
(R0x09 + 1) x (A + Q)
–
–
MT9V131_DS Rev. H 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Serial Bus Description
Serial Bus Description
Registers are written to and read from the MT9V131 through the two-wire serial interface bus. The sensor is a serial interface slave and is controlled by the serial clock (SCLK),
which is driven by the serial interface master. Data is transferred into and out of the
MT9V131 through the serial data (SDATA) line. The SDATA line is pulled up to 2.8V offchip by a 1.5K resistor. Either the slave or master device can pull the SDATA line down—
the serial interface protocol determines which device is allowed to pull the SDATA line
down at any given time. The registers are 16 bits wide and can be accessed through 16bit or 8-bit two-wire serial bus sequences.
Protocol
The two-wire serial interface defines several different transmission codes, as follows:
• a start bit
• the slave device eight-bit address. SADDR is used to select between two different
addresses in case of conflict with another device. If SADDR is LOW, the slave address is
0x90; if SADDR is HIGH, the slave address is 0xB8.
• an acknowledge or a no-acknowledge bit
• an 8-bit message
• a stop bit
Sequence
A typical read or write sequence begins by the master sending a start bit. After the start
bit, the master sends the slave device's 8-bit address. The last bit of the address determines if the request will be a read or a write, where a “0” indicates a write and a “1” indicates a read. The slave device acknowledges its address by sending an acknowledge bit
back to the master.
If the request was a write, the master then transfers the 8-bit register address to which a
write should take place. The slave sends an acknowledge bit to indicate that the register
address has been received. The master then transfers the data 8 bits at a time, with the
slave sending an acknowledge bit after each 8 bits. The MT9V131 uses 16-bit data for its
internal registers, thus requiring two 8-bit transfers to write to one register. After 16 bits
are transferred, the register address is automatically incremented, so that the next 16 bits
are written to the next register address. The master stops writing by sending a start or
stop bit.
A typical read sequence is executed as follows. First the master sends the write-mode
slave address and 8-bit register address, just as in the write request. The master then
sends a start bit and the read-mode slave address. The master then clocks out the
register data 8 bits at a time. The master sends an acknowledge bit after each 8-bit
transfer. The register address is auto-incremented after every 16 bits is transferred. The
data transfer is stopped when the master sends a no-acknowledge bit.
The MT9V131 allows for 8-bit data transfers through the two-wire serial interface by
writing (or reading) the most significant 8 bits to the register and then writing (or
reading) the least significant 8 bits to R0x7F (127).
Bus Idle State
The bus is idle when both the data and clock lines are HIGH. Control of the bus is initiated with a start bit, and the bus is released with a stop bit. Only the master can generate
the start and stop bits.
MT9V131_DS Rev. H 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Serial Bus Description
Start Bit
The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line
is HIGH.
Stop Bit
The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line
is HIGH.
Slave Address
The 8-bit address of a two-wire serial interface device consists of 7 bits of address and
1 bit of direction. A “0” in the least significant bit (LSB) of the address indicates write
mode, and a “1” indicates read mode. The write address of the sensor is 0xB8, while the
read address is 0xB9; this only applies when SADDR is set HIGH.
Data Bit Transfer
One data bit is transferred during each clock pulse. The serial interface clock pulse is
provided by the master. The data must be stable during the HIGH period of the serial
clock—it can only change when the two-wire serial interface clock is LOW. Data is transferred 8 bits at a time, followed by an acknowledge bit.
Acknowledge Bit
The master generates the acknowledge clock pulse. The transmitter (which is the master
when writing, or the slave when reading) releases the data line, and the receiver indicates an acknowledge bit by pulling the data line LOW during the acknowledge clock
pulse.
No-Acknowledge Bit
The no-acknowledge bit is generated when the data line is not pulled down by the
receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate
a read sequence.
MT9V131_DS Rev. H 4/15 EN
23
©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Two-Wire Serial Interface Sample Write and Read Sequences (with Saddr = 1)
Two-Wire Serial Interface Sample Write and Read Sequences
(with SADDR = 1)
16-Bit Write Sequence
A typical write sequence for writing 16 bits to a register is shown in Figure 17. A start bit
given by the master, followed by the write address, starts the sequence. The image sensor
will then give an acknowledge bit and expects the register address to come first, followed
by the 16-bit data. After each 8-bits, the image sensor will give an acknowledge bit. All 16
bits must be written before the register will be updated. After 16 bits are transferred, the
register address is automatically incremented, so that the next 16 bits are written to the
next register. The master stops writing by sending a start or stop bit.
Figure 17:
Timing Diagram Showing a Write to R0x09 with Value 0x0284
SCLK
SDATA
0xB8 ADDR
R0x09
START
ACK
0xB9 ADDR
ACK
0000 0010
ACK
1000 0100
ACK
STOP
NACK
16-Bit Read Sequence
A typical read sequence is shown in Figure 18. First the master has to write the register
address, as in a write sequence. Then a start bit and the read address specifies that a read
is about to happen from the register. The master then clocks out the register data 8 bits
at a time. The master sends an acknowledge bit after each 8-bit transfer. The register
address is auto-incremented after every 16 bits is transferred. The data transfer is
stopped when the master sends a no-acknowledge bit.
Figure 18:
Timing Diagram Showing a Read from R0x09; Returned Value 0x0284
SCLK
SDATA
0xB8 ADDR
START
MT9V131_DS Rev. H 4/15 EN
R0x09
ACK
0xB9 ADDR
ACK
ACK
24
1000 0100
0000 0010
ACK
STOP
NACK
©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Two-Wire Serial Interface Sample Write and Read Sequences (with Saddr = 1)
8-Bit Write Sequence
All registers in the camera are treated and accessed as 16-bit, even when some registers
do not have all 16-bits used. However, certain hosts only support 8-bit serial communication access. The camera provides a special accommodation for these hosts.
To be able to write one byte at a time to the register a special register address is added.
The 8-bit write is done by first writing the upper 8 bits to the desired register and then
writing the lower 8 bits to the special register address (R0x7F). The register is not
updated until all 16 bits have been written. It is not possible to just update half of a
register. In Figure 19, a typical sequence for 8-bit writing is shown. The second byte is
written to the special register (R0x7F).
Figure 19:
Timing Diagram Showing a Bytewise Write to R0x09 with Value 0x0284
SCLK
SDATA
0xB8 ADDR
0000 0010
R0x09
0xB8 ADDR
1000 0100
R0x7F
STOP
START
START
ACK
ACK
ACK
ACK
ACK
ACK
8-Bit Read Sequence
To read 1 byte at a time, the same special register address is used for the lower byte. The
upper 8 bits are read from the desired register. By following this with a read from the
special register (R0x7F) the lower 8 bits are accessed, as shown in Figure 20 The master
sets the no-acknowledge bits.
Figure 20:
Timing Diagram Showing a Bytewise Read from R0x09; Returned Value 0x0284
SCLK
SDATA
0xB8 ADDR
0xB9 ADDR
R0x09
0000 0010
START
START
ACK
ACK
NACK
ACK
SCLK
SDATA
0xB8 ADDR
0xB9 ADDR
R0x7F
1000 0100
STOP
START
START
MT9V131_DS Rev. H 4/15 EN
ACK
ACK
ACK
25
NACK
©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Two-Wire Serial Interface Sample Write and Read Sequences (with Saddr = 1)
Two-Wire Serial Bus Timing
The two-wire serial interface operation requires a certain minimum of master clock
cycles between transitions. These are specified below in master clock cycles.
Figure 21:
Serial Host Interface Start Condition Timing
4
5
SCLK
SDATA
Figure 22:
Serial Host Interface Stop Condition Timing
4
5
SCLK
SDATA
Note:
Figure 23:
All timing are in units of master clock cycle.
Serial Host Interface Data Timing for Write
4
4
SCLK
SDATA
Note:
Figure 24:
SDATA is driven by an off-chip transmitter.
Serial Host Interface Data Timing for Read
5
SCLK
SDATA
Note:
MT9V131_DS Rev. H 4/15 EN
SDATA is pulled LOW by the sensor, or allowed to be pulled HIGH by a pull-up resistor off-chip.
26
©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Two-Wire Serial Interface Sample Write and Read Sequences (with Saddr = 1)
Figure 25:
Acknowledge Signal Timing After an 8-bit Write to the Sensor
3
6
SCLK
Sensor pulls down
SDATA pin
SDATA
Figure 26:
Acknowledge Signal Timing After an 8-bit Read from the Sensor
6
7
SCLK
SDATA
Note:
MT9V131_DS Rev. H 4/15 EN
Sensor tri-states SDATA pin
(turns off pull down)
After a read, the master receiver must pull down SDATA to acknowledge receipt of data bits. When
read sequence is complete, the master must generate a no acknowledge by leaving SDATA to float
HIGH. On the following cycle, a start or stop bit may be used.
27
©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Appendix B – Overview of Programming
Appendix B – Overview of Programming
Default Sensor Configuration
In its default configuration, the sensor outputs up to 15 fps at 12 MHz master clock
frequency. Auto exposure, automatic white balance, 60Hz flicker avoidance, defect
correction, and automatic noise suppression in low-light conditions are enabled. The
frame rate is controlled by AE and can be slowed down to 5 fps in low light. Lens shading
correction is disabled. Gamma correction uses gamma = 0.6. Image data are output in
progressive YCbCr ITU_R.BT.656 VGA format, with Y, Cb, and Cr values ranging from 16
to 240.
The use of the non-default register settings shown in Table 11 are recommended to optimize sensor performance in the above configuration.
Table 11:
Non-Default Register Settings Optimizing 15 fps at 12 MHz Operation
Core:
R0x5 = 0x2E, R0x7[4] = 0, R0x21 = 0xE401, R0x2F = 0xF7B6
IFP:
R0x33 = 0x1411, R0x38 = 0x878, R0x39 = 0x122, R0x3B = 0x42C, R0x3E = 0xFFF,
R0x40 = 0x0E10, R0x41 = 0x1417, R0x42 = 0x1213,
R0x43 = 0x1112, R0x44 = 0x7110, R0x45 = 0x7473
Note:
Table 12:
Non-default register settings required for an optimal 30 fps, 27 MHz operation are shown in
Table 12.
Non-Default Register Settings Optimizing 30 fps at 27 MHz Operation
Note:
Core:
R0x05 = 0x84, R0x06 = 0xA, R0x07[4] = 0, R0x21 = 0xE401
IFP:
R0x33 = 0x1411, R0x39 = 0x122, R0x3B = 0x42C, R0x3E = 0xFFF, R0x59 = 0x1F8,
R0x5A = 0x25D, R0x 5C = 0x201E, R0x5D = 0x2725, R0x64 = 0x117D
To obtain register settings for other frame rates and clock speeds, contact a ON Semiconductor
FAE.
Auto Exposure
Target image brightness and accuracy of AE are set by IFP R0x2E[7:0] and R0x2E[15:8],
respectively. For example, to overexpose images, set IFP R0x2E[7:0] = 0x78. To change
image brightness on LCD in RGB preview mode, use IFP R0x34[15:8]. AE logic can be
programmed to keep the frame rate constant or vary it within certain range, by writing to
IFP R0x37[9:5] one of the values tabulated in Table 13. Current and time-averaged luma
values can be read in IFP R0x4C and R0x4D, respectively.
Table 13:
Relation Between IFP R0x37[9:5] Setting and Frame Rate Range
Minimum Frame Rate
Maximum Frame Rate = 15 fps
Maximum Frame
Rate = 30 fps
30 fps
15 fps
7.5 fps
5 fps
N/A
8
16
24
4
8
16
24
The speed of AE is set using IFP R0x2F. The speed should be higher for preview modes
and lower for video output to avoid sudden changes in brightness between frames.
MT9V131_DS Rev. H 4/15 EN
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MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Appendix B – Overview of Programming
Auto exposure is disabled by setting IFP R0x06[14] = 0. When AE, AWB, and flicker avoidance are all disabled (IFP R0x06[14] = 0, IFP R0x06[1] = 0, and IFP R8[11] = 0), exposure
and analog gains can be adjusted manually (see core registers R0x09, R0x0C, and R0x2B
through R0x2E).
Automatic White Balance
AWB can be disabled by setting IFP R0x06[1] = 0. Use IFP R0x25[2:0] and R0x25[6:3] to
speed up AWB response. Note that speeding AWB up may result in color oscillation. If
necessary, AWB range can be restricted by changing the upper limit in IFP R0x25[14:8]
and lower limit in IFP R0x25[6:0].
Flicker Avoidance
Use IFP R0x5B to choose automatic/manual, 50Hz/60Hz flicker avoidance and IFP
R0x08[11] = 0 to disable this feature.
Flash
For flash programming, see IFP R0x98 description.
Decimation, Zoom, and Pan
For output decimation programming, see IFP R0xA5 description. Table 14 provides
some examples.
Table 14:
Decimation, Zoom, and Pan
Note:
IFP Registers
CIF Output
(Correct Aspect Ratio)
QVGA Output
2:1 Zoom
QVGA Output
1:1 Zoom
R0xA5
R0xA6
R0xA7
R0xA8
R0xA9
R0xAA
26
586
352
0
480
288
160
320
320
120
240
240
0
640
320
0
480
240
For fixed 2x upsize zoom, set core R0x1E[0] = 1.
Interpolation
Use IFP R0x05[2:0] to adjust image sharpness. By default, sharpness is automatically
reduced in low-light conditions (see IFP R0x5[3]). For 565RGB 16-bit capture, set IFP
R0x06[12] = 0 and IFP R0x05[3] = 0 to avoid contouring.
Special Effects
To switch from color to gray scale output, set IFP R0x08[5] = 1.
Image Mirroring
To mirror images horizontally, set core R0x20[14] = 1 and IFP R0x08[0] = 1. To flip images
vertically, set core R0x20[15] = 1 and IFP R0x08[1] = 1.
MT9V131_DS Rev. H 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Appendix B – Overview of Programming
Test Pattern
See IFP R0x48 and IFP R0x35[5:3] description.
Gamma Correction
See Table 15 and Table 16 for register settings required to setup non-default gamma
correction. Note that these settings determine output signal range. Use YCbCr settings
with ITU_R BTU-compatible devices. Use YUV settings for JPEG capture and RGB
preview; switching to YUV mode requires setting IFP R0x34 = 0 and IFP R0x35 = 0xFF01.
Table 15:
Table 16:
YCbCr Settings
Gamma
0.45
0.5
0.55
0.6
(Default)
0.7
1.0
IFP R0x53
IFP R0x54
IFP R0x55
IFP R0x56
IFP R0x57
0x3224
0x5D44
0x987F
0xC0AE
0xE0D0
0x2A1D
0x543B
0x9277
0xBDA9
0xE0CF
0x2318
0x4C34
0x8C70
0xBAA4
0xE0CD
0x1E14
0x452D
0x8669
0xB7A0
0xE0CC
0x150D
0x3923
0x785D
0xB097
0xE0C9
0x804
0x2010
0x6040
0xA080
0xE0C0
Gamma
0.45
0.5
0.55
0.6
0.7
1.0
IFP R0x53
IFP R0x54
IFP R0x55
IFP R0x56
IFP R0x57
0x3829
0x3021
0xAD90
0xDAC5
0xFEEC
0x3021
0x6043
0xA687
0xD6C0
0xFEEB
0x281B
0x573B
0x9F7F
0xD3BA
0xFEE9
0x2216
0x4F34
0x9877
0xCFB5
0xFEE7
0x180F
0x4128
0x8C69
0xC8AB
0xFEE4
0x0904
0x2412
0x6C48
0xB591
0xFED9
YUV Settings
MT9V131_DS Rev. H 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Appendix B – Overview of Programming
Figure 27:
48- Pin CLCC Package Outline
2.3 ±0.2
D
1.7
Seating
plane
Substrate material: alumina ceramic 0.7 thickness
Wall material: alumina ceramic
A
Lid material: borosilicate glass 0.55 thickness
8.8
47X
1.0 ±0.2
0.8
TYP
4.4
48
48X
0.40 ±0.05
48X R 0.15
H CTR
1.75
Ø0.20 A B C
1
First
clear
pixel
5.215
4.84
4.4
Ø0.20 A B C
5.715
0.8 TYP
4X
10.9 ±0.1
CTR
V CTR
11.43
8.8
Image
sensor die:
0.675 thickness
0.2
5.215
5.715
11.43
Lead finish:
Au plating, 0.50 microns
minimum thickness
over Ni plating, 1.27 microns
minimum thickness
C
Optical
area
A
B
0.05
1.400 ±0.125
0.90
for reference only
0.35
for reference only
0.10 A
10.9 ±0.1
CTR
Optical
center1
Optical area:
Maximum rotation of optical area relative to package edges: 1º
Maximum tilt of optical area relative to
seating plane A : 50 microns
Maximum tilt of optical area relative to
top of cover glass D : 100 microns
Note: 1. Optical center = package center.
MT9V131_DS Rev. H 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Revision History
Revision History
Rev. H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/16/15
• Updated “Ordering Information” on page 2
Rev. G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3/31/15
• Converted to ON Semiconductor template
Rev. F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/4/11
• Updated trademarks
• Applied updated template
Rev. E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/24/10
• Remove iCSP reference from Table 1, “Key Performance Parameters,” on page 1 and
Table 2, “Available Part Numbers,” on page 2
• Remove Figure 4, Figure 27, and Figure 28
• Remove Table 3
• Updated to non-confidential
Rev. D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/6/10
• Updated to Aptina template
Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/1/08
• Changed operating temperature on Table 1 on page 1 from –20°C to +60°C to –20°C to
+70°C.
• Changed register description for registers 48, 49, 50, 76, and 77 in Table 8 (on page 14).
• Added registers R0x1F, R0x20, R0x24, R0x2A, R0x30, R0x31, R0x32, R0x36, R0x37,
r0x39, R0x3C, R0x3D, R0x3E, R0x46, R0x4C, R0x4D, R0x59, R0x5A, R0x5C, R0x5D,
R0x80, R0x81, R0x82, R0x83, R0x84, R0x85, R0x86, R0x87, R0x88, R0x89, R0x8A, R0x8B,
R0x8C, R0x8D, R0x8E, R0x8F, R0x90, R0x91, R0x92, R0x93, R0x94, and R0x95 to
Table 9, IFP Register Description.
• Updated Figure 13: “Typical Spectral Characteristics,” on page 19.
• Added Figure 15: “Chief Ray Angle (CRA) vs. Image Height,” on page 20.
• Added last sentence of first paragraph in “Auto Exposure” on page 28.
• Updated signal names to new standard:
– Changed OE# to OE_BAR
– Changed RESET# to RESET_BAR
– Changed VAAPIX to VAA_PIX
Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3/5/07
• Fixed typos.
• Updated document with hexadecimal format for registers.
• Added Table 3 on page 9 for CLCC package.
• Added Figure on page 32 for CLCC package.
• Updated Figure 10 on page 17, Table 8 on page 16, and Figure 12 on page 18.
• Updated Figure 13 on page 19.
• Updated Figure 17 on page 24.
MT9V131_DS Rev. H 4/15 EN
32
©Semiconductor Components Industries, LLC,2015.
MT9V131: 1/4-Inch SOC VGA CMOS Digital Image Sensor
Revision History
Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/06
• Initial release.
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without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey
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MT9V131_DS Rev. H 4/15 EN
33
©Semiconductor Components Industries, LLC,2015 .
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