1 Mb Ultra-Low Power Asynchronous CMOS SRAM

N01L63W3A
1Mb Ultra-Low Power Asynchronous CMOS SRAM
64K × 16 bit
Features
Overview
• Single Wide Power Supply Range
2.3 to 3.6 Volts
The N01L63W3A is an integrated memory device
containing a 1 Mbit Static Random Access Memory
organized as 65,536 words by 16 bits. The device
is designed and fabricated using ON
Semiconductor’s advanced CMOS technology to
provide both high-speed performance and ultra-low
power. The device operates with a single chip
enable (CE) control and output enable (OE) to
allow for easy memory expansion. Byte controls
(UB and LB) allow the upper and lower bytes to be
accessed independently. The N01L63W3A is
optimal for various applications where low-power is
critical such as battery backup and hand-held
devices. The device can operate over a very wide
temperature range of -40oC to +85oC and is
available in JEDEC standard packages compatible
with other standard 64Kb x 16 SRAMs.
• Very low standby current
2.0µA at 3.0V (Typical)
• Very low operating current
2.0mA at 3.0V and 1µs (Typical)
• Very low Page Mode operating current
0.8mA at 3.0V and 1µs (Typical)
• Simple memory control
Single Chip Enable (CE)
Byte control for independent byte operation
Output Enable (OE) for memory expansion
• Low voltage data retention
Vcc = 1.8V
• Very fast output enable access time
30ns OE access time
• Automatic power down to standby mode
• TTL compatible three-state output driver
• Compact space saving BGA package available
Product Family
Part Number
Package Type
N01L63W3AB
48 - BGA
N01L63W3AT
44 - TSOP II
N01L63W3AB2
48 - BGA Green
N01L63W3AT2
44 - TSOP II Green
Operating
Temperature
Power
Supply
(Vcc)
Speed
55ns @ 2.7V
-40oC to +85oC 2.3V - 3.6V 70ns @ 2.3V
Standby
Operating
Current (ISB), Current (Icc),
Typical
Typical
2 µA
2 mA @ 1MHz
Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
PIN
ONE
N01L63W3A
TSOP
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
©2008 SCILLC. All rights reserved.
July 2008 - Rev. 9
1
2
3
4
5
6
A
LB
OE
A0
A1
A2
NC
B
I/O8
UB
A3
A4
CE
I/O0
C
I/O9
I/O10
A5
A6
I/O1
I/O2
D
VSS
I/O11
NC
A7
I/O3
VCC
E
VCC
I/O12
NC
NC
I/O4
VSS
F
I/O14 I/O13
A14
A15
I/O5
I/O6
G
I/O15
NC
A12
A13
WE
I/O7
H
NC
A8
A9
A10
A11
NC
48 Pin BGA (top)
6 x 8 mm
Pin Descriptions
Pin Name
Pin Function
A0-A15
Address Inputs
WE
CE
OE
LB
UB
I/O0-I/O15
Write Enable Input
Chip Enable Input
Output Enable Input
Lower Byte Enable Input
Upper Byte Enable Input
NC
VCC
Not Connected
VSS
Ground
Data Inputs/Outputs
Power
Publication Order Number:
N01L63W3A/D
N01L63W3A
Functional Block Diagram
Word
Address
Decode
Logic
Address
Inputs
A4 - A15
Page
Address
Decode
Logic
Input/
Output
Mux
and
Buffers
Word Mux
Address
Inputs
A0 - A3
4K Page
x 16 word
x 16 bit
RAM Array
I/O0 - I/O7
I/O8 - I/O15
CE
WE
OE
UB
LB
Control
Logic
Functional Description
CE
WE
OE
UB
LB
I/O0 - I/O151
MODE
POWER
H
X
X
X
X
High Z
Standby2
Standby
L
X
X
H
H
High Z
Active
Active
L
L
X3
1
L
1
L
Data In
Write3
Active
L
H
L
L1
L1
Data Out
Read
Active
L
H
H
L1
L1
High Z
Active
Active
1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - I/O7
are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown.
2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally
isolated from any external influence and disabled from exerting any influence externally.
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
Capacitance1
Item
Symbol
Test Condition
Input Capacitance
CIN
I/O Capacitance
CI/O
Max
Unit
VIN = 0V, f = 1 MHz, TA = 25oC
8
pF
VIN = 0V, f = 1 MHz, TA = 25oC
8
pF
1. These parameters are verified in device characterization and are not 100% tested
Rev. 9 | Page 2 of 10 | www.onsemi.com
Min
N01L63W3A
Absolute Maximum Ratings1
Item
Symbol
Rating
Unit
Voltage on any pin relative to VSS
VIN,OUT
–0.3 to VCC+0.3
V
Voltage on VCC Supply Relative to VSS
VCC
–0.3 to 4.5
V
Power Dissipation
PD
500
mW
Storage Temperature
TSTG
–40 to 125
oC
Operating Temperature
TA
-40 to +85
oC
Soldering Temperature and Time
TSOLDER
260oC, 10sec
oC
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Operating Characteristics (Over Specified Temperature Range)
Test Conditions
Min.
Typ1
Item
Symbol
Supply Voltage
VCC
Data Retention Voltage
VDR
Input High Voltage
VIH
1.8
VCC+0.3
V
Input Low Voltage
VIL
–0.3
0.6
V
Output High Voltage
VOH
IOH = 0.2mA
Output Low Voltage
VOL
IOL = -0.2mA
0.2
V
Input Leakage Current
ILI
VIN = 0 to VCC
0.5
µA
Output Leakage Current
ILO
OE = VIH or Chip Disabled
0.5
µA
Read/Write Operating Supply Current
@ 1 µs Cycle Time2
ICC1
VCC=3.6 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0
2.0
3.0
mA
Read/Write Operating Supply Current
@ 70 ns Cycle Time2
ICC2
VCC=3.6 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0
9.5
14.0
mA
Page Mode Operating Supply Current
@ 70ns Cycle Time3 (Refer to Power
Savings with Page Mode Operation
diagram)
ICC3
VCC=3.6 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0
4.0
Read/Write Quiescent Operating Supply Current3
ICC4
VCC=3.6 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0,
f=0
Maximum Standby Current3
ISB1
VIN = VCC or 0V
Chip Disabled
tA= 85oC, VCC = 3.6 V
Maximum Data Retention Current3
IDR
2.3
Chip Disabled
3
Vcc = 1.8V, VIN = VCC or 0
Chip Disabled, tA= 85oC
Max
Unit
3.6
V
1.8
V
VCC–0.2
V
2.0
mA
3.0
mA
20
µA
10
µA
1. Typical values are measured at Vcc=Vcc Typ., TA=25°C and are not 100% tested.
2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive
output capacitance expected in the actual system.
3. This device assumes a standby mode if the chip is disabled (CE high). In order to achieve low standby current all inputs must be
within 0.2 volts of either VCC or VSS
Rev. 9 | Page 3 of 10 | www.onsemi.com
N01L63W3A
Power Savings with Page Mode Operation (WE = VIH)
Page Address (A4 - A15 )
Word Address (A0 - A3)
Open page
Word 1
Word 2
...
Word 16
CE
OE
LB, UB
Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal
organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power
saving feature.
The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open
and 16-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant
bits and addressing the 16 words within the open page, power is reduced to the page mode value which is
considerably lower than standard operating currents for low power SRAMs.
Rev. 9 | Page 4 of 10 | www.onsemi.com
N01L63W3A
Timing Test Conditions
Item
Input Pulse Level
0.1VCC to 0.9 VCC
Input Rise and Fall Time
5ns
Input and Output Timing Reference Levels
0.5 VCC
Output Load
CL = 30pF
Operating Temperature
-40 to +85 oC
Timing
2.3 - 3.6 V
2.7 - 3.6 V
Item
Symbol
Read Cycle Time
tRC
Address Access Time
tAA
70
55
ns
Chip Enable to Valid Output
tCO
70
55
ns
Output Enable to Valid Output
tOE
35
30
ns
Byte Select to Valid Output
tLB, tUB
35
30
ns
Chip Enable to Low-Z output
tLZ
10
10
ns
Output Enable to Low-Z Output
tOLZ
5
5
ns
Byte Select to Low-Z Output
tLBZ, tUBZ
10
10
ns
Chip Disable to High-Z Output
tHZ
0
20
0
20
ns
Output Disable to High-Z Output
tOHZ
0
20
0
20
ns
Byte Select Disable to High-Z Output
tLBHZ, tUBHZ
0
20
0
20
ns
Output Hold from Address Change
tOH
10
10
ns
Write Cycle Time
tWC
70
55
ns
Chip Enable to End of Write
tCW
50
40
ns
Address Valid to End of Write
tAW
50
40
ns
Byte Select to End of Write
tLBW, tUBW
50
40
ns
Write Pulse Width
tWP
40
40
ns
Address Setup Time
tAS
0
0
ns
Write Recovery Time
tWR
0
0
ns
Write to High-Z Output
tWHZ
Data to Write Time Overlap
tDW
40
35
ns
Data Hold from Write Time
tDH
0
0
ns
End Write to Low-Z Output
tOW
5
10
ns
Min.
Max.
70
Min.
55
20
Rev. 9 | Page 5 of 10 | www.onsemi.com
Max.
Units
ns
20
ns
N01L63W3A
Timing of Read Cycle (CE = OE = VIL, WE = VIH)
tRC
Address
tAA
tOH
Data Out
Previous Data Valid
Data Valid
Timing Waveform of Read Cycle (WE= VIH)
tRC
Address
tAA
tHZ
tCO
CE
tLZ
tOHZ
tOE
OE
tOLZ
tLB, tUB
LB, UB
tLBLZ, tUBLZ
Data Out
High-Z
tLBHZ, tUBHZ
Data Valid
Rev. 9 | Page 6 of 10 | www.onsemi.com
N01L63W3A
Timing Waveform of Write Cycle (WE control)
tWC
Address
tWR(4)
tAW
tCW
CE
tLBW, tUBW
LB, UB
tWP
tAS
WE
tDW
High-Z
tDH
Data Valid
Data In
tWHZ
tOW
High-Z
Data Out
Timing Waveform of Write Cycle (CE Control)
tWC
Address
tAW
tWR
tCW
CE
tAS
tLBW, tUBW
LB, UB
tWP
WE
tDW
Data Valid
Data In
tLZ
Data Out
tDH
tWHZ
High-Z
Rev. 9 | Page 7 of 10 | www.onsemi.com
N01L63W3A
44-Lead TSOP II Package (T44)
18.41±0.13
11.76±0.20
10.16±0.13
0.80mm REF
0.45
0.30
DETAIL B
SEE DETAIL B
1.10±0.15
0o-8o
0.20
0.00
0.80mm REF
Note:
1. All dimensions in inches (Millimeters)
2. Package dimensions exclude molding flash
Rev. 9 | Page 8 of 10 | www.onsemi.com
N01L63W3A
Ball Grid Array Package
0.28±0.05
1.24±0.10
D
A1 BALL PAD
CORNER (3)
1. 0.35±0.05 DIA.
E
2. SEATING PLANE - Z
0.15 Z
0.05
TOP VIEW
SIDE VIEW
1. DIMENSION IS MEASURED AT THE
A1 BALL PAD
MAXIMUM SOLDER BALL DIAMETER.
CORNER
PARALLEL TO PRIMARY Z.
SD
e
SE
2. PRIMARY DATUM Z AND SEATING
PLANE ARE DEFINED BY THE
SPHERICAL CROWNS OF THE
SOLDER BALLS.
3. A1 BALL PAD CORNER I.D. TO BE
MARKED BY INK.
K TYP
J TYP
e
BOTTOM VIEW
Dimensions (mm)
e = 0.75
D
6±0.10
SD
SE
J
K
BALL
MATRIX
TYPE
0.375
0.375
1.125
1.375
FULL
E
8±0.10
Rev. 9 | Page 9 of 10 | www.onsemi.com
Z
N01L63W3A
Ordering Information
Part Number
Package
Shipping Method
N01L63W3AT5I
Leaded 44-TSOP II
Tray
N01L63W3AT25I
Green 44-TSOP II (RoHS Compliant)
Tray
N01L63W3AB5I
Leaded 48-BGA
Tray
N01L63W3AB25I
Green 48-BGA (RoHS Compliant)
Tray
N01L63W3AT5IT
Leaded 44-TSOP II
Tape & Reel
N01L63W3AT25IT
Green 44-TSOP II (RoHS Compliant)
Tape & Reel
N01L63W3AB5IT
Leaded 48-BGA
Tape & Reel
N01L63W3AB25IT
Green 48-BGA (RoHS Compliant)
Tape & Reel
Revision History
Revision #
Date
A
Jan. 2000
Initial advance release
B
Apr. 2001
Access time 55ns @ 3.0V, corrected voltage range, TSOP mechanical package
drawing, misc. errata
C
Sept. 2001
Misc. modifications, preliminary release
D
Dec. 2001
Part number change from EM064L16, modified Overview and Features, added
Page Mode Operation diagam, revised Operating Characteristics table, Functional Description table and Ordering Information diagram
E
Nov. 2002
Replaced Isb and Icc on Product Family table with typical values
F
Oct. 2004
Added Pb-Free and Green Package Option
G
Nov. 2005
Removed Pb-Free Pkg, added Green Pkg and RoHS Compliant
H
9
Change Description
September 2006 Converted to AMI Semiconductor
July 2008
Converted to ON Semiconductor and new part numbers
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without
further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does
SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special,
consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical
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Rev. 9 | Page 10 of 10 | www.onsemi.com
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