1-of-8 Decoder/Demultiplexer

MC74AC151, MC74ACT151
1−of−8
Decoder/Demultiplexer
The MC74AC151/74ACT151 is a high−speed 8−input digital
multiplexer. It provides, in one package, the ability to select one line of
data from up to eight sources. The MC74AC151/74ACT151 can be
used as a universal function generator to generate any logic function of
four variables. Both true and complementary outputs are provided.
• Outputs Source/Sink 24 mA
• ′ACT151 Has TTL Compatible Inputs
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DIP−16
N SUFFIX
CASE 648
16
VCC
I4
I5
I6
I7
S0
S1
S2
16
15
14
13
12
11
10
9
1
16
1
2
I3
3
I2
I1
4
5
I0
6
Z
Z
7
E
8
1
16
GND
1
SO−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
Figure 1. Pinout: 16−Lead Packages Conductors
(Top View)
PIN ASSIGNMENT
16
PIN
FUNCTION
I0−I7
Data Inputs
S0−S2
Select Inputs
ORDERING INFORMATION
Device
E
Enable Input
Z
Data Output
Z
Inverted Data Output
TRUTH TABLE
Inputs
1
EIAJ−16
M SUFFIX
CASE 966
Outputs
E
S2
S1
S0
Z
Z
H
L
L
L
L
L
L
L
L
X
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
H
I0
I1
I2
I3
I4
I5
I6
I7
L
I0
I1
I2
I3
I4
I5
I6
I7
Package
Shipping
MC74AC151N
PDIP−16
25 Units/Rail
MC74ACT151N
PDIP−16
25 Units/Rail
MC74AC151D
SOIC−16
48 Units/Rail
MC74ACT151D
SOIC−16
48 Units/Rail
MC74AC151DR2
SOIC−16
2500 Tape & Reel
MC74ACT151DR2
SOIC−16
2500 Tape & Reel
MC74AC151DT
TSSOP−16
96 Units/Rail
MC74ACT151DT
TSSOP−16
96 Units/Rail
MC74AC151DTR2
TSSOP−16 2500 Tape & Reel
MC74ACT151DTR2 TSSOP−16 2500 Tape & Reel
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
MC74AC151M
EIAJ−16
50 Units/Rail
MC74ACT151M
EIAJ−16
50 Units/Rail
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 6
1
Publication Order Number:
MC74AC151/D
MC74AC151, MC74ACT151
S0 E
I0
I1 I2
I3
I4
I5
I6
I7
S1
S2
Z
Z
Figure 2. Logic Symbol
FUNCTIONAL DESCRIPTION
Z = E•(I0•S0•S1•S2+I1•S0•S1•S2+
I2•S0•S1•S2+I3•S0•S1•S2+
I4•S0•S1•S2+I5•S0•S1•S2+
I6•S0•S1•S2+I7•S0•S1•S2)
The MC74AC151/74ACT151 provides the ability, in one
package, to select from eight sources of data or control
information. By proper manipulation of the inputs, the
MC74AC151/74ACT151 can provide any logic function of
four variables and its complement.
The MC74AC151/74ACT151 is a logic implementation
of a single pole, 8−position switch with the switch position
controlled by the state of three Select inputs, S0, S1, S2. Both
true and complementary outputs are provided. The Enable
input (E) is active LOW. When it is not activated, the
complementary output is HIGH and the true output is LOW
regardless of all other inputs. The logic function provided at
the output is:
I0
I1
I2
I3
I4
I5
S2
S1
S0
E
NOTE:
This diagram is provided only for the
understanding of logic operations and
should not be used to estimate propagation
delays.
Z
Figure 3. Logic Diagram
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2
Z
I6
I7
MC74AC151, MC74ACT151
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
−0.5 to +7.0
V
VIN
DC Input Voltage (Referenced to GND)
−0.5 to VCC +0.5
V
VOUT
DC Output Voltage (Referenced to GND)
−0.5 to VCC +0.5
V
IIN
DC Input Current, per Pin
±20
mA
IOUT
DC Output Sink/Source Current, per Pin
±50
mA
ICC
DC VCC or GND Current per Output Pin
±50
mA
Tstg
Storage Temperature
−65 to +150
°C
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
Supply Voltage
VIN, VOUT
DC Input Voltage, Output Voltage (Ref. to GND)
tr, tf
Input Rise and Fall Time (Note 1)
′AC Devices except Schmitt Inputs
tr, tf
Input Rise and Fall Time (Note 2)
′ACT Devices except Schmitt Inputs
TJ
Junction Temperature (PDIP)
TA
Operating Ambient Temperature Range
IOH
IOL
Min
Typ
Max
′AC
2.0
5.0
6.0
′ACT
4.5
5.0
5.5
0
−
VCC
VCC @ 3.0 V
−
150
−
VCC @ 4.5 V
−
40
−
VCC @ 5.5 V
−
25
−
VCC @ 4.5 V
−
10
−
VCC @ 5.5 V
−
8.0
−
Unit
V
V
ns/V
ns/V
−
−
140
°C
−40
25
85
°C
Output Current − High
−
−
−24
mA
Output Current − Low
−
−
24
mA
1. VIN from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. VIN from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
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3
MC74AC151, MC74ACT151
DC CHARACTERISTICS
Symbol
Parameter
VCC
(V)
74AC
74AC
TA = +25°C
TA =
−40°C to
+85°C
Typ
Unit
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1 V
or VCC − 0.1 V
VIL
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1 V
or VCC − 0.1 V
VOH
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
V
3.0
4.5
5.5
−
−
−
2.56
3.86
4.86
2.46
3.76
4.76
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
5.5
−
−
−
0.36
0.36
0.36
0.44
0.44
0.44
5.5
−
±0.1
±1.0
μA
VI = VCC, GND
5.5
−
−
75
mA
VOLD = 1.65 V Max
5.5
−
−
−75
mA
VOHD = 3.85 V Min
5.5
−
8.0
80
μA
VIN = VCC or GND
VOL
Maximum Low Level
Output Voltage
IIN
Maximum Input
Leakage Current
IOLD
†Minimum Dynamic
Output Current
IOHD
ICC
Maximum Quiescent
Supply Current
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
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4
V
V
V
IOUT = −50 μA
*VIN = VIL or VIH
−12 mA
IOH
−24 mA
−24 mA
IOUT = 50 μA
*VIN = VIL or VIH
12 mA
IOL
24 mA
24 mA
MC74AC151, MC74ACT151
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
Symbol
VCC*
(V)
Parameter
74AC
74AC
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Min
Typ
Max
Min
Max
Unit
Fig.
No.
tPLH
Propagation Delay
Sn to Z or Z
3.3
5.0
3.0
2.5
11.5
8.5
18.0
13.0
3.0
2.0
20.0
15.0
ns
3−6
tPHL
Propagation Delay
Sn to Z or Z
3.3
5.0
2.5
2.0
12
8.5
18.0
13.0
2.5
1.5
20.0
15.0
ns
3−6
tPLH
Propagation Delay
E to Z or Z
3.3
5.0
2.5
2.0
8.0
6.0
13.0
10.0
2.0
1.5
14.0
11.0
ns
3−6
tPHL
Propagation Delay
E to Z or Z
3.3
5.0
1.5
1.5
8.5
6.5
13.0
10.0
1.5
1.5
14.0
11.0
ns
3−6
tPLH
Propagation Delay
In to Z or Z
3.3
5.0
2.5
1.5
9.5
7.0
14.0
10.5
2.0
1.5
15.5
11.0
ns
3−5
tPHL
Propagation Delay
In to Z or Z
3.3
5.0
2.5
1.5
9.5
7.0
15.0
11.0
2.0
1.5
16.0
12.0
ns
3−5
*Voltage Range 3.3 V is 3.3 V ± 0.3 V
*Voltage Range 5.0 V is 5.0 V ± 0.5 V
DC CHARACTERISTICS
Symbol
Parameter
VCC
(V)
74ACT
74ACT
TA = +25°C
TA =
−40°C to
+85°C
Typ
Guaranteed Limits
Unit
Conditions
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
V
VOUT = 0.1 V
or VCC − 0.1 V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
V
VOUT = 0.1 V
or VCC − 0.1 V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
V
4.5
5.5
−
−
3.86
4.86
3.76
4.76
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
4.5
5.5
−
−
0.36
0.36
0.44
0.44
V
VOL
Maximum Low Level
Output Voltage
V
V
IOUT = −50 μA
*VIN = VIL or VIH
IOH
−24 mA
−24 mA
IOUT = 50 μA
*VIN = VIL or VIH
IOL
24 mA
24 mA
IIN
Maximum Input
Leakage Current
5.5
−
±0.1
±1.0
μA
VI = VCC, GND
DICCT
Additional Max. ICC/Input
5.5
0.6
−
1.5
mA
VI = VCC − 2.1 V
IOLD
†Minimum Dynamic
Output Current
5.5
−
−
75
mA
VOLD = 1.65 V Max
5.5
−
−
−75
mA
VOHD = 3.85 V Min
5.5
−
8.0
80
μA
VIN = VCC or GND
IOHD
ICC
Maximum Quiescent
Supply Current
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
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MC74AC151, MC74ACT151
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
Symbol
Parameter
VCC*
(V)
74ACT
74ACT
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Min
Typ
Max
Min
Max
Unit
Fig.
No.
tPLH
Propagation Delay
Sn to Z
5.0
3.5
−
15.5
3.0
17.0
ns
3−6
tPHL
Propagation Delay
Sn to Z
5.0
3.5
−
15.5
3.0
16.5
ns
3−6
tPLH
Propagation Delay
Sn to Z
5.0
3.5
−
15
3.0
16.5
ns
3−6
tPHL
Propagation Delay
Sn to Z
5.0
4.0
−
16.5
3.5
18.5
ns
3−6
tPLH
Propagation Delay
E to Z
5.0
2.5
−
9.5
2.5
10.0
ns
3−6
tPHL
Propagation Delay
E to Z
5.0
2.5
−
9.0
2.5
10.0
ns
3−6
tPLH
Propagation Delay
E to Z
5.0
2.5
−
8.5
2.5
9.5
ns
3−6
tPHL
Propagation Delay
E to Z
5.0
3.0
−
10.0
2.5
10.5
ns
3−6
tPLH
Propagation Delay
In to Z
5.0
3.5
−
11.5
3.0
12.5
ns
3−6
tPHL
Propagation Delay
In to Z
5.0
3.5
−
12.0
3.0
13.5
ns
3−6
tPLH
Propagation Delay
In to Z
5.0
3.5
−
12.0
3.0
13.0
ns
3−6
tPHL
Propagation Delay
In to Z
5.0
4.0
−
12.5
3.0
14.0
ns
3−6
*Voltage Range 5.0 V is 5.0 V ± 0.5 V
CAPACITANCE
Symbol
Parameter
Value
Typ
Unit
Test Conditions
CIN
Input Capacitance
4.5
pF
VCC = 5.0 V
CPD
Power Dissipation Capacitance
70
pF
VCC = 5.0 V
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6
MC74AC151, MC74ACT151
MARKING DIAGRAMS
DIP−16
SO−16
MC74AC151N
AWLYYWW
AC151
AWLYWW
MC74ACT151N
AWLYYWW
ACT151
AWLYWW
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
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7
TSSOP−16
EIAJ−16
AC
151
ALYW
74AC151
ALYW
ACT
151
ALYW
74ACT151
ALYW
MC74AC151, MC74ACT151
PACKAGE DIMENSIONS
PDIP−16
N SUFFIX
16 PIN PLASTIC DIP PACKAGE
CASE 648−08
ISSUE R
−A−
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
F
C
DIM
A
B
C
D
F
G
H
J
K
L
M
S
L
S
SEATING
PLANE
−T−
K
H
G
D
M
J
16 PL
0.25 (0.010)
M
T A
M
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
SO−16
D SUFFIX
16 PIN PLASTIC SOIC PACKAGE
CASE 751B−05
ISSUE J
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
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8
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
MC74AC151, MC74ACT151
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
16 PIN PLASTIC TSSOP PACKAGE
CASE948F−01
ISSUE O
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
K
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
8
1
N
0.15 (0.006) T U
S
0.25 (0.010)
A
−V−
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
DETAIL E
H
G
EIAJ−16
M SUFFIX
16 PIN PLASTIC EIAJ PACKAGE
CASE966−01
ISSUE O
16
LE
9
Q1
E HE
1
M_
L
8
Z
DETAIL P
D
e
VIEW P
A
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
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9
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
−−− 0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
−−−
0.78
INCHES
MIN
MAX
−−− 0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
−−− 0.031
MC74AC151, MC74ACT151
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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