LV5122T CMOS IC 2-Cell Lithium-Ion Secondary Battery Protection IC www.onsemi.com Overview The LV5122T is a protection IC for 2-cell lithium-ion secondary batteries. Feature Monitoring function for each cell: Detects overcharge and over-discharge conditions and controls the charging and discharging operation of each cell. High detection voltage accuracy: Over-charge detection accuracy ±25mV MSOP8 (150mil) Over-discharge detection accuracy ±100mV Hysteresis cancel function: The hysteresis of over-discharge detection voltage is canceled by sensing the connection of a load after overcharging has been detected. Discharge current monitoring function: Detects over-currents and load shorting, and an excessive discharge current is controlled. Low current consumption: Normal operation mode typ. 6.0A Stand by mode max. 0.2A 0V cell charging function: Charging is enabled even when the cell voltage is 0V by giving a potential difference between the VDD pin and V- pin. Specifications Absolute Maximum Ratings at Ta = 25C Parameter Power supply voltage Sym Conditions bol VDD V- Input voltage Ratings Unit -0.3 to +12 V VDD-28 to VDD+0.3 V Charger minus voltage Output voltage Cout pin voltage Vcout VDD-28 to VDD+0.3 V Dout pin voltage Vdout VSS-0.3 to VDD+0.3 V Allowable power dissipation Pd Independent IC 170 mW max Operating ambient temperature Topr -30 to +80 C Storage temperature Tstg -40 to +125 C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ORDERING INFORMATION See detailed ordering and shipping information on page 12 of this data sheet. © Semiconductor Components Industries, LLC, 2015 March 2015 - Rev. 1 1 Publication Order Number : LV5122T/D LV5122T Electrical Characteristics 1 at Ta = 25C, unless especially specified. Parameter Operation input voltage 0V cell charging minimum operation Symbol Conditions Vcell Between VDD and VSS Vmin Between VDD-VSS =0 and VDD-V- Ratings min typ Unit max 1.5 10 V 1.5 V voltage Over-charge detection voltage Vd1 Over-charge reset voltage Vh1 Over-charge detection delay time td1 VDD-Vc=3.5V4.5V, Vc-VSS=3.5V Over-charge reset delay time tr1 VDD-Vc=4.5V3.5V, Vc-VSS=3.5V 4.325 4.350 4.375 V 4.100 4.150 4.200 V 0.5 1.0 1.5 s 20.0 40.0 60.0 ms 2.20 2.30 2.40 V Over-discharge detection voltage Vd2 Over-discharge reset hysteresis voltage Vh2 10.0 20.0 40.0 mV Over-discharge detection delay time td2 VDD-Vc=3.5V2.2V, Vc-VSS=3.5V 50 100 150 ms Over-discharge reset delay time tr2 VDD-Vc=2.2V3.5V, Vc-VSS=3.5V 0.5 1.0 1.5 ms Over-current detection voltage Vd3 VDD-Vc=3.5V, Vc-VSS=3.5V 0.28 0.30 0.32 V Over-current reset hysteresis voltage Vh3 VDD-Vc=3.5V, Vc-VSS=3.5V 5.0 10.0 20.0 mV Over-current detection delay time td3 VDD-Vc=3.5V, Vc-VSS=3.5V 2.5 5.0 7.5 ms ms Over-current reset delay time tr3 VDD-Vc=3.5V, Vc-VSS=3.5V 0.5 1.0 1.5 Short circuit detection voltage Vd4 VDD-Vc=3.5V, Vc-VSS=3.5V 1.0 1.3 1.6 V Short circuit detection delay time td4 VDD-Vc=3.5V, Vc-VSS=3.5V 0.2 0.5 0.8 ms VDD0.4 VDD0.5 VDD0.6 Standby reset voltage Vstb Between VDD-Vc=2.0V, Vc-VSS=2.0V (V-)-VSS Reset resistance (connected to VDD) RDD 100 200 400 k Reset resistance (connected to VSS) RSS 0.5 1.0 1.5 M Cout Nch ON voltage VOL1 0.5 V Cout Pch ON voltage VOH1 IOL=50A, VDD-Vc=3.9V, Vc-VSS=3.9V Dout Nch ON voltage VOL2 IOL=50A, VDD-Vc=Vd2(min), 0.5 V Dout Pch ON voltage VOH2 IOL=50A, VDD-Vc=3.9V, Vc-VSS=3.9V IOL=50A, VDD-Vc=4.4V, Vc-VSS=4.4V VDD-0.5 V V Vc-VSS=Vd2(min) VDD-0.5 V Vc input current Ivc VDD-Vc=3.5V, Vc-VSS=3.5V 0.0 1.0 A Current drain IDD VDD-Vc=3.5V, Vc-VSS=3.5V 6.0 13.0 A Standby current Istb VDD-Vc=2.2V, Vc-VSS=3.5V 0.2 A Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. No.A0728-2/10 LV5122T Electrical Characteristics 2 at Ta = -20 to 70C, unless especially specified. Parameter Symbol Conditions Operation input voltage Vcell Between VDD and VSS 0V cell charging minimum operation Vmin Between VDD-VSS =0 and VDD-V- Ratings min typ Unit max 1.65 10 V 1.65 V voltage Over-charge detection voltage Vd1 4.305 4.350 4.390 V Over-charge reset voltage Vh1 4.080 4.150 4.215 V Over-charge detection delay time td1 VDD-Vc=3.5V4.5V, Vc-VSS=3.5V 0.350 1.000 1.950 s Over-charge reset delay time tr1 VDD-Vc=4.5V3.5V, Vc-VSS=3.5V 14.0 40.0 78.0 ms Over-discharge detection voltage Vd2 2.18 2.30 2.42 V Over-discharge reset hysteresis voltage Vh2 8.0 20.0 42.0 mV Over-discharge detection delay time td2 VDD-Vc=3.5V2.2V, Vc-VSS=3.5V 35 100 195 ms Over-discharge reset delay time tr2 VDD-Vc=2.2V3.5V, Vc-VSS=3.5V 0.35 1.0 1.95 ms 0.271 0.300 0.329 V Over-current detection voltage Vd3 VDD-Vc=3.5V, Vc-VSS=3.5V Over-current reset hysteresis voltage Vh3 VDD-Vc=3.5V, Vc-VSS=3.5V 3.5 10.0 23.0 mV Over-current detection delay time td3 VDD-Vc=3.5V, Vc-VSS=3.5V 1.75 5.00 9.75 ms Over-current reset delay time tr3 VDD-Vc=3.5V, Vc-VSS=3.5V 0.35 1.00 1.95 ms Short circuit detection voltage Vd4 VDD-Vc=3.5V, Vc-VSS=3.5V 0.9 1.3 1.7 V Short circuit detection delay time td4 VDD-Vc=3.5V, Vc-VSS=3.5V 0.14 0.5 1.04 ms VDD0.4 VDD0.5 VDD0.6 70 200 520 k 0.35 1.0 1.95 M Standby reset voltage Vstb Reset resistance (connected to VDD) RDD Between VDD-Vc=2.0V, Vc-VSS=2.0V (V-)-VSS Reset resistance (connected to VSS) RSS Cout Nch ON voltage VOL1 IOL=50A, VDD-Vc=4.4V, Vc-VSS=4.4V Cout Pch ON voltage VOH1 IOL=50A, VDD-Vc=3.9V, Vc-VSS=3.9V Dout Nch ON voltage VOL2 IOL=50A, VDD-Vc=Vd2(min), 0.5 VDD-0.5 V V V 0.5 V Vc-VSS=Vd2(min) Dout Pch ON voltage VOH2 IOL=50A, VDD-Vc=3.9V, Vc-VSS=3.9V VDD-0.5 V Vc input current Ivc VDD-Vc=3.5V, Vc-VSS=3.5V 0.0 1.0 A Current drain IDD VDD-Vc=3.5V, Vc-VSS=3.5V 6.0 16.9 A Standby current Istb VDD-Vc=2.2V, Vc-VSS=3.5V 0.2 A The Ratings of the table above is a design guarantees and are not measured. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. No.A0728-3/10 LV5122T Electrical Characteristics 3 at Ta = -30 to 85C, unless especially specified. Parameter Symbol Conditions Operation input voltage Vcell Between VDD and VSS 0V cell charging minimum operation Vmin Between VDD-VSS =0 and VDD-V- Ratings min typ Unit max 1.73 10 V 1.73 V voltage Over-charge detection voltage Vd1 Over-charge reset voltage Vh1 Over-charge detection delay time td1 VDD-Vc=3.5V4.5V, Vc-VSS=3.5V Over-charge reset delay time tr1 VDD-Vc=4.5V3.5V, Vc-VSS=3.5V 4.295 4.350 4.395 V 4.070 4.150 4.220 V 0.3 1.0 2.1 s 12.0 40.0 84.0 ms Over-discharge detection voltage Vd2 2.17 2.30 2.43 V Over-discharge reset hysteresis voltage Vh2 6.0 20.0 42.0 mV Over-discharge detection delay time td2 VDD-Vc=3.5V2.2V, Vc-VSS=3.5V 30 100 210 ms tr2 VDD-Vc=2.2V3.5V, Vc-VSS=3.5V ms Over-discharge reset delay time 0.3 1.0 2.1 Over-current detection voltage Vd3 VDD-Vc=3.5V, Vc-VSS=3.5V 0.267 0.300 0.333 Over-current reset hysteresis voltage Vh3 VDD-Vc=3.5V, Vc-VSS=3.5V 2.5 10.0 240 Over-current detection delay time td3 VDD-Vc=3.5V, Vc-VSS=3.5V 1.5 5.0 10.5 ms Over-current reset delay time tr3 VDD-Vc=3.5V, Vc-VSS=3.5V 0.3 1.0 2.1 ms Short circuit detection voltage Vd4 VDD-Vc=3.5V, Vc-VSS=3.5V 0.8 1.3 1.8 V td4 VDD-Vc=3.5V, Vc-VSS=3.5V ms Short circuit detection delay time V mV 0.12 0.5 1.12 VDD0.4 VDD0.5 VDD0.6 RDD 60 200 560 k RSS 0.3 1.0 2.1 M 0.5 V 0.5 V Standby reset voltage Vstb Between VDD-Vc=2.0V, Vc-VSS=2.0V (V-)-VSS Reset resistance (connected to VDD) Reset resistance (connected to VSS) Cout Nch ON voltage VOL1 Cout Pch ON voltage VOH1 IOL=50A, VDD-Vc=3.9V, Vc-VSS=3.9V Dout Nch ON voltage VOL2 IOL=50A, VDD-Vc=Vd2(min), Dout Pch ON voltage VOH2 IOL=50A, VDD-Vc=3.9V, Vc-VSS=3.9V IOL=50A, VDD-Vc=4.4V, Vc-VSS=4.4V VDD-0.5 V V Vc-VSS=Vd2(min) VDD-0.5 V Vc input current Ivc VDD-Vc=3.5V, Vc-VSS=3.5V 0.0 1.0 A Current drain IDD VDD-Vc=3.5V, Vc-VSS=3.5V 6.0 18.2 A Standby current Istb 0.2 A VDD-Vc=2.2V, Vc-VSS=3.5V The Ratings of the table above is a design guarantees and are not measured. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. No.A0728-4/10 LV5122T Package Dimensions unit : mm Micro8 / MSOP8 (150 mil) CASE 846AH ISSUE A SOLDERING FOOTPRINT* GENERIC MARKING DIAGRAM* 4.30 1.0 (Unit: mm) 0.35 XXX YMD 0.65 XXX = Specific Device Code Y = Year M = Month D = Additional Traceability Data NOTE: The measurements are not to guarantee but for reference only. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. No.A0728-5/10 LV5122T Pd max -- Ta Allowable power dissipation, Pd max -- mW 200 170 Independent IC 150 100 68 50 0 -30 -20 0 20 40 60 80 100 Ambient temperature, Ta -- °C Pin Assignment Dout T 8 7 1 2 VDD Cout Vc Sense 6 5 3 V- 4 VSS Top view Pin Functions Pin No. Symbol Description 1 VDD VDD pin 2 Cout Overcharge detection output pin 3 V- Charger minus voltage input pin 4 VSS VSS pin 5 Sense Sense pin 6 Vc Intermediate voltage input pin 7 T Pin to shorten detection time (open under normal condition) 8 Dout Overdischarge detection output pin No.A0728-6/10 LV5122T Block Diagram Sence 5 VDD 1 + + - Vc 6 2 Cout td1,tr1 Delay conrol logic + - td2,tr2 8 Dout + + - td3,tr3 + - 4 VSS 3 V- td4 7 T No.A0728-7/10 LV5122T Functional Description Over-charge detection If either of the cell voltage is equal to or more than the over-charge detection voltage, stop further charging by turning “L” the Cout pin and turning off external Nch MOS FET after the over-charge detection delay time. This delay time is set by the internal counter. The over-charge detection comparator has the hysteresis function. Note that this hysteresis can be cancelled by connecting the load after detection of over-charge detection. Once over-charge detection is made, over-current detection is not made to prevent malfunction. Note that short-circuit can be detected. Over-charge return If charger is connected and both cell voltages become equal to or lower than the over-charge recovery voltage or over-charge detection voltage when load is connected, the Cout pin returns to “H” after the over-charge recovery delay time set by the internal counter. When load is connected and either cell or both cell voltages are equal to or more than the over-charge detection voltage, the Cout pin does not return to “H.” When the load current is passed through the external Cout pin parasite diode of Nch MOS FET after the over-charge recovery delay time and each cell voltage becomes equal to or below over-charge detection voltage, the Cout returns to “H.” Over-discharge detection When either cell voltage is equal to or below over-discharge voltage, stop further discharge by turning “L” the Dout pin and turning off external Nch MOS FET after the over-charge detection delay time. The IC becomes standby state after detecting over-discharge and its consumption current is kept at about 0A. After detection, the V- pin will be connected to VDD pin via 200kΩ. Over-discharge return Return from over-discharge is made by connecting charger. If the V- pin voltage becomes equal to or lower than the standby return voltage by connecting charger after detecting over-discharge, it returns from the standby state to start cell voltage monitoring. If both voltages become equal to or more than the over-discharge detection voltage by charging, the Dout pin returns to “H” after the over-discharge return. Over-current detection When high current is passed through the battery, the V potential rises by the ON resister of external MOS FET and becomes equal to or more than the over-current detection voltage, that will be deemed over-current state. Turn “L” the Dout pin after the over-current detection delay time and turn off the external Nch MOS FET to prevent high current in the circuit. The delay time is set by the internal counter. After detection, the V- pin will be connected to VSS via 1MΩ. It will not go into standby state after detecting over-current. Short circuit detection If greater discharge current is passed and the V- pin voltage becomes equal to or more than the short-circuit detection voltage, it will go into short-circuit detection state after the short circuit delay time shorter than the over-current detection delay time. When short-circuit is detected, just like the time of over-current detection, turn Dout pin “L” and turn off external Nch MOS FET to prevent high current in the circuit. The V- pin will be connected to VSS after detection via 30kΩ. It will not go into standby state after detecting short-circuit. Over-current/short-detection return After detecting over-current or short circuit, the return resistor (typ.1MΩ) between V- pin and VSS pin becomes effective and if the resistor is opened the V- pin voltage will be pulled by the VSS pin voltage. Thereafter, the IC will return from the over-current/short-circuit detection state when the V- pin voltage becomes equal to or below the over-current detection voltage and the Dout pin returns to “H” after over-current return delay time set by the internal counter. 0V cell charge If the cell voltage is 0V but a potential difference between VDD and V becomes equal to or greater than the 0V cell charging lowest operation voltage, the Cout pin will output “H” and enable charging. No.A0728-8/10 LV5122T Test time reduction function By turning T pin to the VDD potential, the delay times set by the counter can be cut. Normal time settings if T pin is open. Delay time not set by the counter cannot be controlled by this pin. Operation in case of detection overlap Operation in case of detection overlap Overlap state State after detection When, during Over-discharge Over-charge detection is preferred. If When over-charge detection is made first, V- is over-charge detection, detection is made, over-discharge state continues even after released. When over-discharge is detected after over-charge detection, over-discharge detection is resumed. over-charge detection, the standby state is not effectuated. Note that V- is connected to VDD via 200kΩ. Over-current detection (*1) Both detections’ can be made in parallel. (*2) When over-current is detected first, V- is is made, Over-charge detection continues even when the connected to VSS via 1MΩ. When over-charge detection is made first, V- is released. over-current state occurs. If the over-charge state occurs first, over-current detection is interrupted. When, during Over-charge detection Over-discharge detection is interrupted and The standby state is not effectuated when over-discharge is made, over-charge detection is preferred. When over-discharge state continues even after over-discharge detection is made after over-charge detection. Note that V- is connected over-charge detection, over-discharge detection to VDD via 200kΩ. detection, is resumed. When, during over-current detection, Over-current detection (*3) Both detections can be made in parallel. (*4) If over-current is detected in advance, V will is made, Over-discharge detection continues even when be connected to VSS via 1MΩ. After detecting the over-current state is effectuated first. over-discharge, V will be connected to VDD via Over-current detection is interrupted when the 200kΩ to get into standby state. If over-discharge over-discharge state is effectuated first, is detected in advance, V will be connected to (*1) VDD via 200kΩ to get into standby state. (*2) (*3) (*4) Over-charge detection is made, Over-discharge detection is made, (Note) Short-circuit detection can be made independently. No.A0728-9/10 LV5122T Timing Chart [Cout Output System] Hysteresis cancellation by load connection Charger connection Load connection Charger connection Load connection Charger connection Vd1 Vr1 VDD Vd2 VDD Discharging via FETparasite Di Vd4 V- Vd3 VSS Vd5 VDD td1 Cout tr1 td1 tr1 VOver-charge detection state Over-charge detection state [Dout Output System] Load connection Charger connection Load connection Charger Load connection connection Over-current occurrence Charger connection Load connection Load short-circuit occurrence Vd1 Vr1 VDD Vd2 To standby To standby VDD Vd4 V- Vd3 VSS Vd5 Charging via FETparasite Di Charging via FETparasite Di VDD Dout td2 tr2 td3 tr3 td4 tr3 td2 VSS Over-discharge detection state Over-current detection state Short-circuit detection state Charge return Charge return VDD Cout V- No.A0728-10/10 LV5122T Application Circuit Example + R4 R1 C1 VDD Sense C3 VSS R2 C2 Vc LV5122T V- VSS Dout Cout R3 − Components Recommended value max unit R1, R2 100 1k R3 2k 4k R4 100 10k C1, C2, C3 0.1 1 F * These numbers don't mean to guarantee the characteristic of the IC. * In addition to the components in the upper diagram, it is necessary to insert a capacitor with enough capacity between VDD and VSS of the IC as near as possible to stabilize the power supply voltage to the IC. www.onsemi.com 11 LV5122T ORDERING INFORMATION Device LV5122T-TLM-E Package MSOP8 (150mil) (Pb-Free) Shipping (Qty / Packing) 2000 / Tape & Reel † For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. 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