2.5 V / 3.3 V Differential and LVTTL/LVCMOS 2:1 MUX Input Clock Buffer with 1:12 LVCMOS Fanout

NB3L83948C
2.5 V / 3.3 V Differential and
LVTTL/LVCMOS 2:1 MUX to
1:12 LVCMOS Fanout
Description
The NB3L83948C is a pure 2.5 V / 3.3 V (VDD = VDDO) or mixed
mode 3.3 V Core (VDD) / 2.5 V Output (VDDO) clock distribution
buffer with the capability to select either a differential LVPECL /
LVDS / LVHSTL / SSTL / HCSL or single ended LVCMOS / LVTTL
compatible input clock, such as a Primary or a Test Clock. All other
control inputs (CLK_SEL, CLK_EN, and OE) are LVTTL/LVCMOS
level compatible.
The NB3L83948C provides an enable input, CLK_EN pin, which
synchronously enables or disables the clock outputs while in the LOW
state. Since this input is internally synchronized to the input clock,
changing only when the input is LOW, potential output glitching or
runt pulse generation is eliminated.
The 12 LVCMOS output pins drive 50 W series or parallel
terminated transmission lines. The outputs can also be disabled to a
high impedance (tri−stated) via the OE input, or enabled when High.
Fit, Form, and Function compatible with ICS83948I−147,
ICS83948I−01, CY29948AXI, and MPC9448/9448L
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MARKING
DIAGRAMS*
NB3L
83948C
AWLYYWWG
LQFP−32
FA SUFFIX
CASE 873A
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
(*Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Features
• 2.5 V / 3.3V (VDD = VDDO) or
•
•
•
•
•
•
•
•
•
•
VDDO
3.3 V VDD / 2.5 V VDDO Operation:
2.5 $5%, 2.375 to 2.625 V
3.3 $5%; 3.135 to 3.465 V
350 MHz Clock Support
Accepts LVPECL, LVDS, LVHSTL, SSTL, HCSL, or LVCMOS
Clock Inputs
LVCMOS Compatible Control Inputs
12 LVCMOS Clock Outputs
Synchronous Clock Select
Output Enable to High Z State Control
100 ps Max. Skew Between Outputs
Industrial Temp. Range −40°C to +85°C
32−pin LQFP Package
These are Pb−Free Devices
VDD
Q0
GND
Q1
CLK_EN
Q2
D
Q
LVCMOS_CLK
1
CLK
CLK
2
Q3
Q4
Q5
CLK_SEL
Q6
VDDO
Q7
Q8
Q9
Q10
Q11
OE
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information on page 6 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
November, 2014 − Rev. 2
1
Publication Order Number:
NB3L83948C/D
NB3L83948C
Q0
VDDO
Q1
GND
Q2
VDDO
Q3
31
30
29
28
27
26
25
Q4
22
VDDO
21
Q5
20
GND
19
Q6
18
VDDO
17
8
GND
23
7
24
6
GND
5
VDD
4
OE
3
CLK_EN
2
CLK
1
CLK
32
LVCMOS_CLK
GND
CLK_SEL
Q7
13
14
GND
Q9
VDDO
GND
12
Q10
16
11
VDDO
Q8
10
Q11
15
9
Figure 2. Pinout Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Open
Default
1
CLK_SEL
LVTTL/LVCMOS Input
Pullup
Clock Select Input. When LOW, the CLK/CLK differential
inputs are selected. When HIGH, LVCMOS_CLK is selected.
2
LVCMOS_CLK
LVTTL/LVCMOS Input
Pullup
Single ended Test Clock Input
3
CLK
LVPECL, LVDS,
LVHSTL, SSTL,
HCSL, or LVCMOS
Pullup
True Clock Input (internal)
4
CLK
LVPECL, LVDS,
LVHSTL, SSTL,
HCSL, or LVCMOS
Pulldown
5
CLK_EN
LVTTL/LVCMOS Input
Pullup
Synchronous Clock Enable Input. When HIGH, outputs are
enabled. When LOW, outputs are disabled (LOW).
6
OE
LVTTL/LVCMOS Input
Pullup
Output High Z State control. When HIGH, the outputs are
active and enabled. When LOW, the outputs are high impedance disabled.
7
VDD
POWER
8, 12, 16, 20,
24, 28, 32
GND
GND
9, 11, 13, 15,
17, 19, 21,
23, 25, 27,
29, 31
Q[11:0]
LVCMOS Output
10, 14, 18,
22, 26, 30
VDDO
POWER
Description
Invert Clock Input
VDD Positive Supply pin for core logic. All VDD, VDDO, and
GND pins must be externally connected to a power supply
to guarantee proper operation. Bypass with 0.01 mF cap to
GND.
GND Supply Ground. All VDD, VDDO and GND pins must
be externally connected to power supply to guarantee
proper operation.
Clock Output Pins
VDDO Positive Supply pins. All VDD, VDDO, and GND pins
must be externally connected to a power supply to guarantee proper operation. Bypass each supply pin with 0.01 mF
to GND.
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NB3L83948C
Table 2. CLOCK SELECT FUNCTION TABLE
Control Input
Clock
CLK_SEL
CLK, CLK
LVCMOS_CLK
0
Selected
De−Selected
1
De−Selected
Selected
CLK
CLK_EN
Q
Figure 3. CLK_EN Control Timing Diagram
The CLK_EN control input synchronously enables or disables the outputs as shown in Figure 3. This control latches on the
falling edge of the selected input CLK. When CLK_EN is LOW, the outputs are disabled in a LOW state. When CLK_EN is
HIGH, the outputs are enabled as shown. CLK_EN to CLK Set up and Hold times must be satisfied.
Table 3. ATTRIBUTES (Note 1)
Characteristics
Value
Internal Input Pullup and Pulldown Resistor
ESD Protection
50 kW
Human Body Model
Machine Model
> 1.5 kV
> 200 V
Moisture Sensitivity (Note 1)
Level 2
Flammability Rating
Oxygen Index
UL−94 code V−0 A 1/8”
28 to 34
Transistor Count
275 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS (Note 2)
Symbol
VDD/VDDO
Parameter
Positive Power Supply
Condition
Rating
Unit
GND = 0 V
4.6
V
−0.3 v VI v VDD + 0.3
V
−40 to v +85
°C
−65 to +150
°C
VI
Input Voltage
TA
Operating Temperature Range, Industrial
Tstg
Storage Temperature Range
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
80
55
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
(Note 3)
12−17
°C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If
stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
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NB3L83948C
Table 5. DC CHARACTERISTICS VDD = VDDO = 3.3 $5% (3.135 to 3.465 V) or 2.5 $5% (2.375 to 2.625 V); VDD = 3.3 $5%
(3.135 to 3.465 V) and VDDO = 2.5 $5% (2.375 to 2.625 V) GND = 0 V, TA = −40°C to +85°C; (Note 4)
Characteristic
Symbol
IDD
Min
Typ
Quiescent Power Supply Current
Unit
mA
3.3V VDD = VDDO or 3.3 V VDD, 2.5 VDDO
2.5 V VDD = VDDO
VIH
Max
55
52
V
Input HIGH Voltage at 3.465 V VDD
CLK_SEL; LVCMOS_CLK, CLK_EN, OE
2.0
VDD+0.3
CLK_SEL; LVCMOS_CLK, CLK_EN, OE
1.7
VDD+0.3
CLK_SEL; LVCMOS_CLK, CLK_EN, OE
−0.3
0.8
CLK_SEL; LVCMOS_CLK, CLK_EN, OE
−0.3
0.7
Input HIGH Voltage 2.625 VDD
VIL
V
Input LOW Voltage 3.465 V VDD
Input LOW Voltage 2.625 V VDD
IIN
VOH
VOL
Input Current (VIN = VDD)
300
mA
V
Output HIGH Voltage IOH = −24 mA
3.3 V ±5% = VDD = VDDO
2.4
Output HIGH Voltage IOH = −15 mA
3.3 V ±5% or 2.5 V ±5% = VDD; 2.5 V +5% = VDDO
1.8
V
Output LOW Voltage IOL = 24 mA
3.3 V ±5% = VDD = VDDO
0.55
3.3 V ±5% = VDD = VDDO
0.3
Output LOW Voltage IOL = 12 mA
Output LOW Voltage IOL = 15 mA
0.6
0.3 V ±5% = VDD; 2.5 V ±5% = VDDO
VCMR
VPP
Common Mode Voltage Range (CLK/CLK)
V
3.3 V ±5% or 2.5 V ±5% = VDD
GND+0.5
VDD−0.85
3.3 V ±5% or 2.5 V ±5% = VDD
0.15
1.3
Input Voltage (Peak−to−Peak) CLK/CLK
ZO
Output Impedance
CIN
Input Capacitance
CPD
Power Dissipation Capacitance (per Output)
V
5
7
25
12
W
4
pF
pF
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Parallel terminated 50 W to VDDO/2. See Figure 5.
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NB3L83948C
Table 6. AC CHARACTERISTICS VDD = VDDO = 3.3 $5% (3.135 to 3.465 V) or 2.5 $5% (2.375 to 2.625 V); VDD = 3.3 $5%
(3.135 to 3.465 V) and VDDO = 2.5 $5% (2.375 to 2.625 V) GND = 0 V, TA = −40°C to +85°C; (Note 5)
Characteristic
Symbol
Fmax
tPLH/tPHL
Min
Maximum Operating Frequency
Typ
Max
350
Unit
MHz
Propagation Delay, (crosspoint to VDDO/2) f ≤ 350 MHz
ns
3.3 V VDD = VDDO or 3.3 V VDD, 2.5 V VDDO; CLK/CLK to Qx
1.6
3.6
3.3 V VDD = VDDO or 3.3 V VDD, 2.5 V VDDO; 3.3 V LVCMOS_CLK to Qx
1.0
3.0
2.5 V VDD = VDDO CLK/CLK to Qx
1.6
3.6
2.5 V VDD = VDDO LVCMOS_CLK to Qx
1.0
3.0
ns
tPZL/tPZH
Output Enable Time OE to Qx
5
ns
tPLZ/tPHZ
Output Disable Time OE to Qx
5
ns
tSKEWDC
Duty Cycle Skew at VDD / 2
%
At 150 MHz; 3.3 V VDD = VDDO
At 200 MHz; 2.5 V VDD = VDDO
At 150 MHz; 2.5 V VDD = VDDO
tSKEWD−D
45
45
40
55
55
60
Device to Device Skew (similar condition)
ns
CLK/CLK to Qx; CLK to Qx
tSKEWO−O
tS
tH
tr/tf
1.0
Output to Output Skew Within A Device
25
100
Set−up Time to CLK tf
ps
ns
CLK_EN to CLK/CLK
CLK_EN to CLK
1.0
0.0
CLK/CLK to CLK_EN
CLK to CLK_EN
0.0
1.0
Hold Time to CLK tf
ns
Output rise and fall times
ns
(0.8 V and 2.0 V) 3.3 V VDD = VDDO
(0.6 V and 1.8 V) or 3.3 V VDD, 2.5 VDDO
(0.6 V and 1.8 V) 2.5 V VDD = VDDO
1.0
1.0
1.3
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Outputs loaded with 50 W to VTT (VDDO/2); see Figure 5. CLOCK input with 50% duty cycle. Measured at CLK/CLK crosspoint to Qx VDDO/2,
CLK VDDO/2 to Qx VDDO/2; see Figure 4.
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NB3L83948C
VPP = VIH − VIL
CLK
V DDO
V DDO
2
2
VIHCMR
CLK
GND
LVCMOS_CLK
V DDO
V DDO
2
2
V DDO
V DDO
Qx
2
2
tPHL
tPHL
V DDO
tPW
V DDO
V DDO
2
2
2
Qx
tP
t SKEWDC % + ǒt PWńt PǓ
100
Figure 4. AC Reference Measurement
ZO = 50 W
NB3L83948C
Qx
D
Receiver /
Scope
50 W
DUT
GND
Figure 5. Typical Termination for Output Driver and Device Evaluation. Supplies may be centered on GND
($1.65 V or $1.25 V) to permit direct connection into 50 W to GND Scope modules
ORDERING INFORMATION
Package
Shipping†
NB3L83948CFAG
LQFP−32
(Pb−Free)
250 Units / Tray
NB3L83948CFAR2G
LQFP−32
(Pb−Free)
2000 Units / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NB3L83948C
PACKAGE DIMENSIONS
25
0.20 (0.008) AB T-U Z
BASE
METAL
1
−U−
−T−
B
B1
P
F
DETAIL Y
17
8
ÉÉ
ÉÉ
ÉÉ
N
AE
V
V1
AE
J
DETAIL Y
9
−Z−
9
AC T-U Z
32
M
4X
A1
D
0.20 (0.008)
A
−T−, −U−, −Z−
32 LEAD LQFP
CASE 873A−02
ISSUE C
4X
0.20 (0.008) AC T-U Z
S1
8X
S
SECTION AE−AE
M_
R
DETAIL AD
G
C E
−AB−
0.10 (0.004) AC
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DATUM PLANE −AB− IS LOCATED AT
BOTTOM OF LEAD AND IS COINCIDENT
WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE
DETERMINED AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE
DETERMINED AT SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE
MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL NOT CAUSE THE
D DIMENSION TO EXCEED 0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY
VARY FROM DEPICTION.
H
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.450
0.750
12_ REF
0.090
0.160
0.400 BSC
1_
5_
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.018
0.030
12_ REF
0.004
0.006
0.016 BSC
1_
5_
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
W
K
X
DETAIL AD
Q_
0.250 (0.010)
−AC−
GAUGE PLANE
SEATING
PLANE
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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Sales Representative
NB3L83948C/D
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