2.5V/3.3V/5V ECL Differential Receiver/Driver with Oscillator Gain Stage and Enabled High Gain Outputs

NBLVEP16VR
2.5V/3.3V/5VECL
Differential Receiver/Driver
with Oscillator Gain Stage
and Enabled High Gain
Outputs
The NBLVEP16VR is an ECL/LVPECL oscillator gain stage with
high−gain output buffers, selectable output enable and a feedback
buffer. The NBLVEP16VR is a solution for crystal oscillators and
SAW−based voltage−controlled oscillators.
• Q and Q Outputs have Selectable 4 mA or 8 mA, Self Bias Current
Sources
• QHG and QHG have Selectable 10 mA, Self Bias Current Sources
• Synchronous Output Enable of the High−Gain Outputs with
Selectable Disabled State
• Selectable LVCMOS/LVTTL or LVPECL Level Input of the Output
Enable Pin
• Maximum Frequency > 2.5 GHz Typical
• (LV)PECL Mode Operating Range: VCC = 2.375 V to 5.5 V with
VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with
VEE = −2.375 V to −5.5 V
• Temperature Compensated Outputs
• 50 mV Clock Input Sensitivity
• VBB Output Supports Current Source/Sink Capability up to a
Robust 1.5 mA
4 mA ea. (opt.)
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MARKING DIAGRAM
XXXX
XXXX
ALYW
Bottom View
QFN−16
MN SUFFIX
CASE 485G
XXXX
A
L
Y
W
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Package
Shipping†
NBLVEP16VRMN
QFN−16
123 / Rail
NBLVEP16VRMNR2
QFN−16
3000/ Tape &
Reel
Device
NBWLVEP16VR
Wafer
Refer to
Note 1.
1. Contact Sales Representative.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
4 mA ea.
CS_SEL
VEE
Q
Q
D
D
470 1
Q
Q
QHG
QHG
10 mA ea. (opt.)
470 VBB
0
VEEP
VBB
VBB_ADJ
OD_MODE
EN
LEN Q
LATCH
D
LVCMOS/LVTTL
Threshold
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 4
Figure 1. Logic Diagram
1
EN_SEL
Publication Order Number:
NBLVEP16VR/D
NBLVEP16VR
4 mA ea.
4 mA ea. (opt.)
CS_SEL
VEE
Q
Q
D
D
Q
Q
1
QHG
QHG
10 mA ea. (opt.)
470 470 0
VEEP
VBB
VBB
VBB_ADJ
OD_MODE
LEN Q
LATCH
EN
D
EN_SEL
LVCMOS/LVTTL
Threshold
Figure 2. Logic Diagram
Table 1. Q AND Q INTERNAL CURRENT SOURCE
SELECTOR
Table 2. QHG AND QHG INTERNAL CURRENT
SOURCE SELECTOR
CS_SEL
Q
Q
See Figure
VEEP
QHG
QHG
See Figure
OPEN
4 mA Typical
4 mA Typical
13, 13
OPEN
0 mA
0 mA
8, 11
VEE
8 mA Typical
8 mA Typical
10, 13
VEE
10 mA Typical
10 mA Typical
9, 12
VCC
0 mA
4 mA Typical
13, 13
Table 3. OUTPUT ENABLE AND OUTPUT DISABLED STATE TRUTH TABLE
EN_SEL†
OD−MODE*
EN*
Q and Q
QHG
QHG
VCC or OPEN
Low or OPEN
LVPECL Low, VEE or OPEN
Data
Data
Data
VCC or OPEN
Low or OPEN
LVPECL High or VCC
Data
Low
High
VEE
Low or OPEN
LVCMOS Low, VEE, or OPEN
Data
Low
High
VEE
Low or OPEN
LVCMOS High or VCC
Data
Data
Data
VCC or OPEN
High
LVPECL Low, VEE or OPEN
Data
Data
Data
VCC or OPEN
High
LVPECL High or VCC
Data
High
Low
VEE
High
LVCMOS Low, VEE, or OPEN
Data
High
Low
VEE
High
LVCMOS High or VCC
Data
Data
Data
*Pins will default LOW when left open.
†Pin will default HIGH when left open.
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NBLVEP16VR
OD_MODE
Q
Q
NC
VCC
16
15
14
13
Exposed Pad
(EP)
NC
12
D
3
10
QHG
VBB
VBB
4
9
EN_SEL
VBB
NBLVEP16VR
EN
6
7
Die: 1.16 x 1.19 mm
(x)
(y)
D
QHG
5
VCC
NBLVEP16VR
OD_MODE
CS_SEL
11
2
Q VCC
NC
1
D
Q
D
Bond Pad: 84 m Diameter
Die Thickness: 11 mil, $1 mil
CS_SEL
QHG
QHG
EN_SEL
VEEP
8
EN VBB_ADJ VEE VEE
VBB_ADJ VEE VEEP
Figure 4. Die Map
Figure 3. Pinout Diagram (Top View)
Table 4. PIN DESCRIPTION
Pin No
Name
1
OD_MODE*
I/O
2
Description
LVCMOS/LVTTL Input (See Table 3)
Selectable Mode of Output Disabled Level
D
ECL / LVPECL Input
Clock / Data Input
3
D
ECL / LVPECL Input
Inverted Clock / Data Input
4
VBB
Reference Voltage Output
Reference Voltage Output
5
EN*
ECL / LVPECL or LVCMOS/LVTTL Input
(see Table 3)
Output Enable Synchronous with D and D
6
VBB_ADJ
7
VEE
8
VEEP
9
EN_SEL†
10
Adjust Standard VBB Levels Upward When Tied to VCC for
2.5 V Power Supply. Open for 3.3 V and 5 V Power Supply.
Negative Power Supply
Negative Power Supply
Open or Tied to VEE (See Table 1) Optional 10mA Current
Source For QHG and QHG
LVCMOS / LVTTL Input (See Table 3)
Input Level Selector Pin for EN
QHG
ECL / LVPECL Output
Inverted High−Gain Output, Gain > 200
11
QHG
ECL / LVPECL Output
High−Gain Output, Gain > 200
12
CS_SEL
13
VCC
Positive Power Supply
Positive Power Supply
14
NC
No Connect
No Connect
15
Q
ECL / LVPECL Output
ECL/LVPECL Output for Feedback Loop
16
Q
ECL / LVPECL Output
Inverted ECL/LVPECL Output for Feedback Loop
Power Supply (OPT)
Exposed Pad on Package Bottom Should Only Be Connected to VEE or Left Open
EP
Selects Q and Q Current Source Magnitude (see Table 1),
Open or Tied to VEE or VCC
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
*Pins will default LOW when left open.
†Pin will default HIGH when left open.
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NBLVEP16VR
APPLICATIONS INFORMATION
The output disable mode state pin, OD_MODE, adds
functional flexibility by giving the designer a choice of the
QHG outputs’ polarity when these high−gain outputs are
disabled. For example, with OD_MODE LOW and
EN LOW (LVPECL), the input is passed to the outputs and
the data output equals the data input. If the D input is LOW
when the EN goes HIGH, the next data transition to a HIGH
is ignored and QHG remains LOW and QHG remains
HIGH. The next positive transition of the data input is not
passed on to the QHG outputs under these conditions. The
QHG and QHG outputs remain in their disabled state as long
as the EN input is held HIGH. The EN input has no influence
on the Q or Q outputs and the data inputs are passed on to
these outputs whether EN is HIGH or LOW. When the data
input is HIGH and EN goes HIGH, it will force QHG LOW
and QHG HIGH on the next negative transition of the D
input. This configuration is ideal for crystal oscillator
applications where the oscillator can be free−running and
QHG/QHG gate on and off synchronously without adding
extra counts to the output. See truth table and timing diagram
for detailed ENable functions and options.
The NBLVEP16VR provides a VBB and internal 470 bias resistors from D to VBB and D to VBB for ac coupled
single−ended or differential input signal(s). The VBB_ADJ
pin is used for 2.5 V single−ended operation when it is
connected to VCC. The VBB output current source/sink
capability can support a robust 1.5 mA.
For single−ended input conditions, the unused differential
input is internally connected to VBB as a switching reference
voltage. Decouple VBB and VCC with a 0.01 F capacitor.
This internal VBB will rebias AC coupled input(s). Inputs D
or D must be signal driven or auto oscillation may result.
The NBLVEP16VR is an ECL/LVPECL oscillator gain
stage with high−gain output buffers, selectable output
enable and a feedback buffer. The NBLVEP16VR is a
solution for crystal oscillators and SAW−based
voltage−controlled oscillators. Design versatility is
enhanced with EN, a synchronous output enable pin to
eliminate runt pulses; EN_SEL, an input state selector pin
offering LVCMOS/LVTTL or ECL/LVPECL level control
of EN; and OD_MODE, an output disable mode state pin
which selects the polarity of the high−gain output’s disabled
state.
The NBLVEP16VR Q and Q outputs are ideal for
feedback applications common in crystal oscillator gain
blocks. They each have a selectable on−chip pull−down
current source. External resistors may be used to increase the
pull−down current to a maximum of 25 mA. The QHG and
QHG outputs each have an optional on−chip pull−down
current source of 10 mA. When VEEP is left open, the 10 mA
output current sources are disabled and the QHG and QHG
outputs operate as standard ECL/LVPECL. When VEEP is
connected to VEE, the 10 mA current sources are activated.
The QHG and QHG pull−down current can be decreased by
using a resistor connect from VEEP to VEE. See current
source truth table for functions and options.
The output enable input pin, EN, is synchronized with the
D and D data input signals in a way that furnishes glitchless
gating of the QHG and QHG outputs and allows continuous
oscillator operation. For applications that require output
enable control, the NBLVEP16VR provides expanded
output enable selectability. The logic level of the input state
selector pin, EN_SEL, will determine whether the EN pin
accepts ECL/LVPECL or LVCMOS/LVTTL logic levels.
D
D
(PECL) EN_SEL HIGH (OPEN)
EN
EN_SEL LOW
(CMOS) (SHORTED TO VEE)
OD_MODE
Q
Q
QHG
QHG
Figure 5. Timing Diagram
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NBLVEP16VR
ATTRIBUTES
Characteristics
ESD Protection
Value
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 150 V
> 1 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Level 1
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
388
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS
Symbol
Rating
Unit
VCC
LVPECL Mode Power Supply
Parameter
VEE = 0 V
Condition 1
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
−6
V
VI
LVPECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
−6
V
V
IBB
VBB Current Sink/Source
$1.5
mA
IIN
Input Current (VIN − VBB) B 470 $5
mA
Iout
Output Current
50
100
mA
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
JA
Thermal Resistance (Junction−to−Ambient)
0 LFPM
500 LFPM
41.6
35.2
°C/W
°C/W
JC
Thermal Resistance (Junction−to−Case)
Standard Board (2S2P)
4.0
°C/W
D, D
Continuous
Surge
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
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NBLVEP16VR
DC CHARACTERISTICS, LVPECL VCC = 2.5 V, VEE = 0 V (Note 2, 6)
−40°C
25°C
85°C
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Negative Power Supply Current (Note 3)
30
35
48
30
38
48
35
40
54
mA
VOH
Output HIGH Voltage (Note 4)
1340
1670
1340
1670
1340
1670
mV
VOL
Output LOW Voltage (Note 4)
620
950
620
950
620
950
mV
VIH
Input High Voltage (Single−Ended)
(D, D, EN) (Notes 5, 6)
1655
2000
1655
2000
1655
2000
mV
VIL
Input Low Voltage (Single−Ended)
(D, D, EN) (Notes 5, 6)
1050
1395
1050
1395
1050
1395
mV
VBB
Output Voltage Reference (Note 6)
1420
1630
1420
1630
1420
1630
mV
VIHCMR
Input High Voltage Common Mode Range
(Differential Configuration)
2.5
1.2
2.5
1.2
2.5
V
IIH
Input HIGH Current (Note 5)
EN
150
A
IIL
Input LOW Current (Note 5)
EN
Symbol
1525
1.2
1525
150
0.5
1525
150
0.5
0.5
A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with VCC.
3. VEEP and CS_SEL open.
4. QHG/QHG outputs loaded with 50 to VCC − 2.0 V (VEEP = OPEN) Figure 11 or with optional current source (VEEP = VEE) Figure 12.
Q/Q outputs loaded with 8 mA current source (CS_SEL = VEE).
5. EN_SEL Open.
6. VBB_ADJ tied to VCC for 2.5 V single−ended input operation.
DC CHARACTERISTICS, LVPECL VCC = 3.3 V, VEE = 0 V (Note 7)
−40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
30
38
48
30
40
48
35
42
54
mA
2140
2470
2140
2470
2140
2470
mV
1420
1750
1420
1750
1420
1750
mV
Input High Voltage (Single−Ended)
(D, D, EN) (Note 10)
2075
2420
2075
2420
2075
2420
mV
VIL
Input Low Voltage (Single−Ended)
(D, D, EN) (Note 10)
1355
1675
1355
1675
1355
1675
mV
VBB
Output Voltage Reference
1790
2030
1790
2030
1790
2030
mV
VIHCMR
Input High Voltage Common Mode Range
(Differential Configuration)
3.3
1.2
3.3
1.2
3.3
V
IIH
Input HIGH Current (Note 10)
EN
150
A
IIL
Input LOW Current (Note 10)
EN
Symbol
Characteristic
IEE
Negative Power Supply Current (Note 8)
VOH
Output High Voltage (Note 9)
VOL
Output Low Voltage (Note 9)
VIH
1900
1.2
150
0.5
1900
150
0.5
0.5
1900
A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
7. Input and output parameters vary 1:1 with VCC.
8. VEEP and CS_SEL open.
9. QHG/QHG outputs loaded with 50 to VCC − 2.0 V (VEEP = OPEN) Figure 11 or with optional current source (VEEP = VEE) Figure 12.
Q/Q outputs loaded with 8 mA current source (CS_SEL = VEE).
10. EN_SEL Open.
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NBLVEP16VR
DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 11)
−40°C
25°C
85°C
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Negative Power Supply Current (Note 12)
30
41
48
30
43
48
35
45
54
mA
VOH
Output High Voltage (Note 13)
3840
4170
3840
4170
3840
4170
mV
VOL
Output Low Voltage (Note 13)
3120
3450
3120
3450
3120
3450
mV
VIH
Input High Voltage (Single−Ended)
(D, D, EN) (Note 14)
3775
4120
3775
4120
3775
4120
mV
VIL
Input Low Voltage (Single−Ended)
(D, D, EN) (Note 14)
3055
3375
3055
3375
3055
3375
mV
VBB
Output Voltage Reference
3490
3730
3490
3730
3490
3730
mV
VIHCMR
Input High Voltage Common Mode Range
(Differential Configuration)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current (Note 14)
EN
150
A
IIL
Input LOW Current (Note 14)
EN
Symbol
3600
2.0
3600
150
3600
150
0.5
0.5
0.5
A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
11. Input and output parameters vary 1:1 with VCC.
12. VEEP and CS_SEL open.
13. QHG/QHG outputs loaded with 50 to VCC − 2.0 V (VEEP = OPEN) Figure 11 or with optional current source (VEEP = VEE) Figure 12.
Q/Q outputs loaded with 8 mA current source (CS_SEL = VEE).
14. EN_SEL Open.
DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5V to −2.375 V (Note 15)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
38
48
30
40
48
35
42
54
mA
IEE
Negative Power Supply Current
(Note 16)
30
VOH
Output High Voltage (Note 17)
−1160
−830
−1160
−830
−1160
−830
mV
VOL
Output Low Voltage (Note 17)
−1880
−1550
−1880
−1550
−1880
−1550
mV
VIH
Input High Voltage (Single−Ended)
(D, D, EN) (Notes 18, 19)
−3.3 V
VBB_ADJ = OPEN
−2.5 V
VBB_ADJ = VCC
VIL
mV
−1225
−845
Input Low Voltage (Single−Ended)
(D, D, EN) (Notes 18, 19)
−3.3 V
VBB_ADJ = OPEN
−2.5 V
VBB_ADJ = VCC
−1945
−1450
VBB
Output Voltage Reference
−3.3 V or −5.2 V VBB_ADJ = OPEN
−2.5 V (Note 19)
VBB_ADJ = VCC
−1510
−1080
VIHCMR
Input High Voltage Common Mode
Range (Differential Configuration)
VEE v −5 V
IIH
Input HIGH Current (Note 18)
EN
IIL
Input LOW Current (Note 18)
EN
−880
−500
−1225
−845
−880
−500
−1225
−845
−880
−500
mV
−1400
−975
−1625
−1105
−1945
−1450
−1270
−870
−1510
−1080
0
VEE+1.2
VEE+1.2
VEE+2.0
−1400
−975
−1625
−1105
−1945
−1450
−1270
−870
−1510
−1080
0
VEE+1.2
VEE+2.0
150
0.5
−1400
−975
−1270
−870
0.5
mV
0
V
150
A
VEE+2.0
150
0.5
−1625
−1105
V
A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
15. Input and output parameters vary 1:1 with VCC.
16. VEEP and CS_SEL open.
17. QHG/QHG outputs loaded with 50 to VCC − 2.0 V (VEEP = OPEN) Figure 11 or with optional current source (VEEP = VEE) Figure 12.
Q/Q outputs loaded with 8 mA current source (CS_SEL = VEE).
18. EN_SEL Open.
19. VBB_ADJ tied to VCC for −2.5 V single−ended operation.
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NBLVEP16VR
(LVCMOS/LVTTL DC CHARACTERISTICS
VCC = 2.375 V or 5.0 V, VEE = 0 V or VCC = 0 V, VEE = −2.375 V to −5.5 V (Note 20)
−40°C
Min
Characteristic
Symbol
25°C
Typ
Max
Min
85°C
Typ
Max
Min
Typ
Max
Unit
VIH
Input High Voltage
VEE+2.0
VCC
VEE+
2.0
VCC
VEE+2.0
VCC
V
VIL
Input Low Voltage
VEE
VEE+0.8
VEE
VEE+0.8
VEE
VEE+0.8
V
IIH
Input HIGH Current
−150
150
−150
150
−150
150
A
IIL
Input LOW Current
−150
150
−150
150
−150
150
A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
20. EN_SEL = LOW When EN is Used as a LVCMOS/LVTTL Input.
AC CHARACTERISTICS VCC = 2.375 V to 5.5 V; VEE = 0 V or VCC = 0 V VEE = −2.375 V to −5.5 V (Note 21)
−40°C
Characteristic
Symbol
Min
Typ
25°C
Max
Min
Typ
500
310
210
700
500
380
215
165
335
335
300
280
410
415
85°C
Max
Min
Typ
500
280
190
700
450
330
230
205
360
360
315
300
440
450
Max
Unit
VOUTPP
Differential Output (QHG)
Voltage (Peak−to−Peak)
fout < 1 GHz
fout < 2 GHz
fout < 2.5 GHz
500
260
210
660
500
400
tPLH,
tPHL
Propagation Delay (Differential)
Figure 10
D to Q (CS_SEL = OPEN)
Figure 10
D to Q (CS_SEL = VEE)
Figure 8
D to QHG (VEEP Open)
Figure 9
D to QHG (VEEP = VEE)
215
155
315
320
290
270
390
400
tS
Set−Up Time
EN to D
0.5
0.5
0.5
ns
tH
Hold Time
EN to D
1.0
1.0
1.0
ns
tJITTER
Random Clock Jitter (RMS)
tSKEW
Duty Cycle Skew (Note 23)
5
20
5
20
5
20
ps
VINPP
Differential Input Voltage
(Peak−to−Peak) (Note 22)
Single−Ended Configuration
D to QHG
D to Q
D to QHG
D to Q
25
50
50
100
800
800
1200
1200
25
50
50
100
800
800
1200
1200
25
50
50
100
800
800
1200
1200
mV
mV
mV
tr
tf
Output Rise/Fall Times (20% − 80%)
Q, Q (CS_SEL = VEE or OPEN)
QHG, QHG (VEEP = VEE or OPEN)
70
90
120
150
300
210
70
90
120
150
300
210
70
90
120
150
300
210
DCO
Output Duty Cycle (Note 24) (QHG)
45
50
55
45
50
55
45
50
55
385
395
475
490
0.5
385
405
495
505
0.5
mV
mV
400
445
520
530
0.5
ps
ps
ps
%
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously. The device has a DC voltage
gain of [40 for Q/Q outputs and [200 for QHG/QHG outputs.
21. QHG/QHG and Q/Q outputs loaded with AC coupled 50 loads. VEEP and CS_SEL connected to VEE.
22. VINPP is the minimum differential Peak−to−Peak input swing for which AC parameters are guaranteed.
23. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point
of the outputs, (tpLH – tpHL).
24. Assumes 50% Input Duty Cycle.
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8
NBLVEP16VR
9
800
8
700
7
600
6
500
5
400
4
300
3
200
2
100
1
0
0
500
1000
1500
2000
2500
3000
FREQUENCY (MHz)
Figure 6. Fmax/Jitter for QHG, QHG Output
800
700
QHG/QHG VOUTpp (mV)
600
500
400
300
200
100
0
50
40
30
VINPP (mV)
Figure 7. Differential Gain vs. Input Voltage (100 MHz)
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9
20
JITTEROUT ps (RMS)
VOUTpp (mV)
Differential Inputs
900
NBLVEP16VR
Zo = 50 QHG
D
Receiver
Driver
QHG
D
Zo = 50 50 VEEP (OPEN)
50 VTT
VTT = VCC − 2.0 V
Figure 8. Typical Termination for Output Driver
VEEP Open (See Application Note AND8020 − Termination of ECL Logic Devices.)
Zo = 50 QHG
D
*R
Driver
QHG
Receiver
D
Zo = 50 *R = 2 Zo = 100 for 50 Transmission Lines
VEEP
VEE
Figure 9. QHG/QHG Output Loading and Termination, VEEP = VEE.
Zo = 50 Q
D
Receiver
Driver
Q
Zo = 50 *R
D
*R = 2 Zo = 100 for 50 Transmission
Lines
VEE
VEE
CS_SEL (Open or Tied to VEE)
VEE
Figure 10. Q/Q Output Loading and Termination, CS_SEL Open or Tied to VEE or VCC
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10
NBLVEP16VR
Zo = 50 QHG
50 Driver
QHG
Oscilliscope
Zo = 50 50 VEEP (OPEN)
Figure 11. QHG/QHG Device Evaluation Set−up; VEEP = OPEN
Zo = 50 QHG
Driver
50 Oscilliscope
QHG
Zo = 50 50 VEEP
VEE
Figure 12. QHG/QHG Device Evaluation Set−up; VEEP = VEE
Zo = 50 Q
50 Driver
Q
Oscilliscope
Zo = 50 50 VEE
VEE
CS_SEL (Open or Tied to VEE)
VEE
Figure 13. Q/Q Device Evaluation Set−up; CS_SEL = VEE or OPEN
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11
NBLVEP16VR
VR
4.0 mA ea.
Q
CS_SEL
VEE
Q
D
D
1
QHG
QHG
10 mA ea.
470 VBB
Q
Q
0
VBB
VEEP
VBB_ADJ
OD_MODE
LEN Q
LATCH
EN
D
EN_SEL
LVCMOS/LVTTL
Threshold
Figure 14. Typical Application
when a voltage is applied to it. Thus, when a change in the
control voltage is applied to the control pin of the oscillator,
it causes a change in the capacitance seen by the crystal
internal to the oscillator. These changes in the circuit load
capacitance cause changes in the oscillator output frequency
due to crystal loading.
The VCXO, or voltage controlled crystal oscillator, is an
oscillator where the output frequency is controlled by the
crystal and an external control voltage. The VCXO can have
the output frequency change with a change in voltage at a
control pin of the oscillator. Most, if not all, VCXO’s use
varactor diodes to vary the frequency. A varactor diode is a
semiconductor device that behaves as a variable capacitor
Resource Reference of Application Notes
AN1404
−
ECLinPS Circuit Performance at
Non−Standard VIH Levels
AN1406
−
Designing with LVPECL (ECL at
+5.0 V)
AND8002
−
Marking and Date Codes
AND8009
−
ECLinPS Plus Spice I/O Model Kit
AND8020
−
Termination of ECL Logic Devices
For an updated list of Application Notes, please see
our website at http://onsemi.com.
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12
NBLVEP16VR
PACKAGE DIMENSIONS
QFN−16
CASE 485G−01
ISSUE B
D
PIN 1
LOCATION
ÇÇÇ
ÇÇÇ
ÇÇÇ
0.15 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
A
B
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
TOP VIEW
0.15 C
(A3)
0.10 C
A
16 X
0.08 C
SIDE VIEW
SEATING
PLANE
A1
C
D2
16X
L
5
NOTE 5
e
4
16X
9
E2
K
12
1
16
16X
e
13
b
0.10 C A B
0.05 C
EXPOSED PAD
8
BOTTOM VIEW
NOTE 3
SOLDERING FOOTPRINT
0.575
0.022
3.25
0.128
0.30
0.012
EXPOSED PAD
1.50
0.059
3.25
0.128
0.50
0.02
0.30
0.012
SCALE 10:1
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13
mm Ǔ
ǒinches
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.18
0.30
3.00 BSC
1.65
1.85
3.00 BSC
1.65
1.85
0.50 BSC
0.20
−−−
0.30
0.50
NBLVEP16VR
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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