Dual JK Positive Edge-Triggered Flip-Flop

MC74AC109, MC74ACT109
Dual JK Positive
Edge−Triggered Flip−Flop
The MC74AC109/74ACT109 consists of two high−speed
completely independent transition clocked JK flip−flops. The clocking
operation is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D flip−flop (refer to
MC74AC74/74ACT74 data sheet) by connecting the J and K inputs
together.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q HIGH
• Outputs Source/Sink 24 mA
• ′ACT109 Has TTL Compatible Inputs
CD2
J2
K2
CP2
SD2
Q2
Q2
16
15
14
13
12
11
10
9
CD
J
K
CP
SD
Q
CD1
J1
K1
CP1
Q1
Q1
3
K1
4
5
6
7
CP1
SD1
Q1
Q1
1
2
CD1
J1
DIP−16
N SUFFIX
CASE 648
16
1
16
VCC
SD1
http://onsemi.com
1
16
1
Q
8
GND
16
Figure 1. Pinout; 16−Lead Packages Conductors
(Top View)
1
SO−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
EIAJ−16
M SUFFIX
CASE 966
ORDERING INFORMATION
Device
Package
Shipping
PIN ASSIGNMENT
MC74AC109N
PDIP−16
25 Units/Rail
PIN
FUNCTION
MC74ACT109N
PDIP−16
25 Units/Rail
J1, J2, K1, K2
Data Inputs
MC74AC109D
SOIC−16
48 Units/Rail
CP1, CP2
Clock Pulse Inputs
MC74ACT109D
SOIC−16
48 Units/Rail
CD1, CD2
Direct Clear Inputs
MC74AC109DR2
SOIC−16
2500 Tape & Reel
SD1, SD2
Direct Set Inputs
MC74ACT109DR2
SOIC−16
2500 Tape & Reel
Q1, Q2, Q1,
Q2
Outputs
MC74AC109DT
TSSOP−16
96 Units/Rail
MC74ACT109DT
TSSOP−16
96 Units/Rail
MC74AC109DTR2
TSSOP−16 2500 Tape & Reel
MC74ACT109DTR2 TSSOP−16 2500 Tape & Reel
MC74AC109M
EIAJ−16
50 Units/Rail
MC74ACT109M
EIAJ−16
50 Units/Rail
MC74AC109MEL
EIAJ−16
2000 Tape & Reel
MC74ACT109MEL
EIAJ−16
2000 Tape & Reel
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 6
1
Publication Order Number:
MC74AC109/D
MC74AC109, MC74ACT109
TRUTH TABLE
Inputs
SD
CD
CP
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
L
Outputs
J
X
X
X
L
H
L
H
X
K
X
X
X
L
L
H
H
X
Q
SD
Q
Q
J
H
L
H
L
L
H
H
H
Toggle
Q0
Q0−
H
L
Q0
Q0−
SD
CP
Q
J
H = HIGH Voltage Level
L = LOW Voltage Level
= LOW−to−HIGH Clock Transition
X = Immaterial
Q0(Q0) = Previous Q0(Q0) before
LOW−to−HIGH Transition of Clock
Q
Q
CP
CD
K
CD
K
Figure 2. Logic Symbol
SD
K
Q
CP
Q
J
CD
NOTE:
This diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation
delays.
Figure 3. Logic Diagram
(One Half Shown)
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
−0.5 to +7.0
V
DC Input Voltage (Referenced to GND)
−0.5 to VCC +0.5
V
VOUT
DC Output Voltage (Referenced to GND)
−0.5 to VCC +0.5
V
IIN
DC Input Current, per Pin
±20
mA
IOUT
DC Output Sink/Source Current, per Pin
±50
mA
ICC
DC VCC or GND Current per Output Pin
±50
mA
Tstg
Storage Temperature
−65 to +150
°C
VCC
DC Supply Voltage (Referenced to GND)
VIN
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
http://onsemi.com
2
MC74AC109, MC74ACT109
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
Supply Voltage
VIN, VOUT
DC Input Voltage, Output Voltage (Ref. to GND)
tr, tf
Input Rise and Fall Time (Note 1)
′AC Devices except Schmitt Inputs
Min
Typ
Max
Unit
′AC
2.0
5.0
6.0
′ACT
4.5
5.0
5.5
0
−
VCC
VCC @ 3.0 V
−
150
−
VCC @ 4.5 V
−
40
−
VCC @ 5.5 V
−
25
−
VCC @ 4.5 V
−
10
−
VCC @ 5.5 V
−
8.0
−
−
−
140
°C
−40
25
85
°C
V
V
ns/V
tr, tf
Input Rise and Fall Time (Note 2)
′ACT Devices except Schmitt Inputs
TJ
Junction Temperature (PDIP)
TA
Operating Ambient Temperature Range
IOH
Output Current − High
−
−
−24
mA
IOL
Output Current − Low
−
−
24
mA
ns/V
1. VIN from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. VIN from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
DC CHARACTERISTICS
Symbol
Parameter
VCC
(V)
74AC
74AC
TA = +25°C
TA =
−40°C to
+85°C
Typ
Unit
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1 V
or VCC − 0.1 V
VIL
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1 V
or VCC − 0.1 V
VOH
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
V
3.0
4.5
5.5
−
−
−
2.56
3.86
4.86
2.46
3.76
4.76
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
5.5
−
−
−
0.36
0.36
0.36
0.44
0.44
0.44
5.5
−
±0.1
±1.0
μA
VI = VCC, GND
5.5
−
−
75
mA
VOLD = 1.65 V Max
5.5
−
−
−75
mA
VOHD = 3.85 V Min
5.5
−
4.0
40
μA
VIN = VCC or GND
VOL
Maximum Low Level
Output Voltage
IIN
Maximum Input
Leakage Current
IOLD
†Minimum Dynamic
Output Current
IOHD
ICC
Maximum Quiescent
Supply Current
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
http://onsemi.com
3
V
V
V
IOUT = −50 μA
*VIN = VIL or VIH
−12 mA
IOH
−24 mA
−24 mA
IOUT = 50 μA
*VIN = VIL or VIH
12 mA
IOL
24 mA
24 mA
MC74AC109, MC74ACT109
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
Symbol
VCC*
(V)
Parameter
74AC
74AC
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Min
Typ
Max
Min
Max
Unit
Fig.
No.
fmax
Maximum Clock
Frequency
3.3
5.0
125
150
−
−
−
−
100
125
−
−
MHz
3−3
tPLH
Propagation Delay
CPn to Qn or Qn
3.3
5.0
4.0
2.5
−
−
13.5
10.0
3.5
2.0
16.0
10.5
ns
3−6
tPHL
Propagation Delay
CPn to Qn or Qn
3.3
5.0
3.0
2.0
−
−
14.0
10.0
3.0
1.5
14.5
10.5
ns
3−6
tPLH
Propagation Delay
CDn or SDn to Qn or Qn
3.3
5.0
3.0
2.5
−
−
12.0
9.0
2.5
2.0
13.0
10.0
ns
3−6
tPHL
Propagation Delay
CDn or SDn to Qn or Qn
3.3
5.0
3.0
2.0
−
−
12.0
9.5
3.0
2.0
13.5
10.5
ns
3−6
Unit
Fig.
No.
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
AC OPERATING REQUIREMENTS
Symbol
VCC*
(V)
Parameter
Typ
74AC
74AC
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Guaranteed Minimum
ts
Set−up Time, HIGH or LOW
Jn or Kn to CPn
3.3
5.0
−
−
6.5
4.5
7.5
5.0
ns
3−9
th
Hold Time, HIGH or LOW
Jn or Kn to CPn
3.3
5.0
−
−
0
0.5
0
0.5
ns
3−9
tw
Pulse Width
CPn or CDn or SDn
3.3
5.0
−
−
4.0
3.5
4.5
3.5
ns
3−6
trec
Recovery TIme
CDn or SDn to CP
3.3
5.0
−
−
0
0
0
0
ns
3−9
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
DC CHARACTERISTICS
Symbol
Parameter
VCC
(V)
74ACT
74ACT
TA = +25°C
TA =
−40°C to
+85°C
Typ
Guaranteed Limits
Unit
Conditions
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
V
VOUT = 0.1 V
or VCC − 0.1 V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
V
VOUT = 0.1 V
or VCC − 0.1 V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
V
4.5
5.5
−
−
3.86
4.86
3.76
4.76
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
http://onsemi.com
4
V
IOUT = −50 μA
*VIN = VIL or VIH
−24 mA
IOH
−24 mA
MC74AC109, MC74ACT109
DC CHARACTERISTICS (continued)
Symbol
Parameter
VCC
(V)
74ACT
74ACT
TA = +25°C
TA =
−40°C to
+85°C
Typ
VOL
Maximum Low Level
Output Voltage
Unit
Conditions
Guaranteed Limits
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
4.5
5.5
−
−
0.36
0.36
0.44
0.44
V
IOUT = 50 μA
V
*VIN = VIL or VIH
24 mA
IOL
24 mA
IIN
Maximum Input
Leakage Current
5.5
−
±0.1
±1.0
μA
VI = VCC, GND
ΔICCT
Additional Max. ICC/Input
5.5
0.6
−
1.5
mA
VI = VCC − 2.1 V
IOLD
†Minimum Dynamic
Output Current
5.5
−
−
75
mA
VOLD = 1.65 V Max
5.5
−
−
−75
mA
VOHD = 3.85 V Min
5.5
−
4.0
40
μA
VIN = VCC or GND
IOHD
ICC
Maximum Quiescent
Supply Current
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
Symbol
VCC*
(V)
Parameter
74ACT
74ACT
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Min
Typ
Max
Min
Max
Unit
Fig.
No.
fmax
Maximum Clock
Frequency
5.0
145
−
−
125
−
MHz
3−3
tPLH
Propagation Delay
CPn to Qn or Qn
5.0
4.0
−
11.0
3.5
13.0
ns
3−6
tPHL
Propagation Delay
CPn to Qn or Qn
5.0
3.0
−
10.0
2.5
11.5
ns
3−6
tPLH
Propagation Delay
CDn or SDn to Qn or Qn
5.0
2.5
−
9.5
2.0
10.5
ns
3−6
tPHL
Propagation Delay
CDn or SDn to Qn or Qn
5.0
2.5
−
10.0
2.0
11.5
ns
3−6
Unit
Fig.
No.
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
AC OPERATING REQUIREMENTS
Symbol
VCC*
(V)
Parameter
Typ
74ACT
74ACT
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Guaranteed Minimum
ts
Set−up Time, HIGH or LOW
Jn or Kn to CPn
5.0
−
2.0
2.5
ns
3−9
th
Hold Time, HIGH or LOW
Jn or Kn to CPn
5.0
−
2.0
2.0
ns
3−9
tw
Pulse Width
CPn or CDn or SDn
5.0
−
5.0
6.0
ns
3−6
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
http://onsemi.com
5
MC74AC109, MC74ACT109
AC OPERATING REQUIREMENTS (continued)
Symbol
VCC*
(V)
Parameter
74ACT
74ACT
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Typ
Recovery TIme
CDn or SDn to CP
trec
5.0
Unit
Fig.
No.
ns
3−9
Guaranteed Minimum
−
0
0
Value
Typ
Unit
Test Conditions
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
CAPACITANCE
Symbol
Parameter
CIN
Input Capacitance
4.5
pF
VCC = 5.0 V
CPD
Power Dissipation Capacitance
35
pF
VCC = 5.0 V
MARKING DIAGRAMS
DIP−16
SO−16
MC74AC109N
AWLYYWW
AC109
AWLYWW
MC74ACT109N
AWLYYWW
ACT109
AWLYWW
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
http://onsemi.com
6
TSSOP−16
EIAJ−16
AC
109
ALYW
74AC109
ALYW
ACT
109
ALYW
74ACT109
ALYW
MC74AC109, MC74ACT109
PACKAGE DIMENSIONS
PDIP−16
N SUFFIX
16 PIN PLASTIC DIP PACKAGE
CASE 648−08
ISSUE R
−A−
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
F
C
DIM
A
B
C
D
F
G
H
J
K
L
M
S
L
S
SEATING
PLANE
−T−
K
H
G
D
M
J
16 PL
0.25 (0.010)
M
T A
M
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
SO−16
D SUFFIX
16 PIN PLASTIC SOIC PACKAGE
CASE 751B−05
ISSUE J
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
http://onsemi.com
7
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
MC74AC109, MC74ACT109
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
16 PIN PLASTIC TSSOP PACKAGE
CASE948F−01
ISSUE O
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
K
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
8
1
N
0.15 (0.006) T U
S
0.25 (0.010)
A
−V−
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
DETAIL E
H
G
EIAJ−16
M SUFFIX
16 PIN PLASTIC EIAJ PACKAGE
CASE966−01
ISSUE O
16
LE
9
Q1
E HE
1
M_
L
8
Z
DETAIL P
D
e
VIEW P
A
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
http://onsemi.com
8
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
−−− 0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
−−−
0.78
INCHES
MIN
MAX
−−− 0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
−−− 0.031
MC74AC109, MC74ACT109
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
http://onsemi.com
9
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
MC74AC109/D
Similar pages